JP2004282236A - Solid-state imaging apparatus, and driving apparatus for solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus for much more stabilizing a dark level. <P>SOLUTION: The solid-state imaging apparatus is provided with: a plurality of light receiving pixels for outputting a pixel signal in response to a light receiving amount; an OB pixel region comprising a plurality of optical black pixels for outputting a dark signal to decide a reference level of the pixel signal; and a read section for reading the pixel signal and the dark signal and transferring them to a clamp circuit. The read section performs a reference level stabilizing operation to read the dark signal for a plurality of times for a period required for the clamp circuit to pull-in the reference level. After the reference level stabilizing operation, the read section performs reading operations of the pixel signal. Thus, the read section executes the read operation of the pixel signal in a state wherein the pull-in of the reference level (that is, decision of the dark level) is finished. Consequently, a conventional problem of appearance of an amplified and increased deviation in the dark level is eliminated in the case of increasing an amplification factor in an external circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device and a driving device for a solid-state imaging device. Specifically, the present invention relates to a technique for stabilizing a reference level of a pixel signal in a solid-state imaging device.
[0002]
[Prior art]
Solid-state imaging devices used in video cameras and electronic cameras are classified into several types. Among these, the amplification type solid-state imaging device is superior to the CCD type in terms of high functionality and low power consumption, and has attracted attention in recent years.
In the amplification type solid-state imaging device, each pixel arranged in a two-dimensional matrix outputs a photoelectric conversion unit that generates a signal charge according to the amount of received light, and outputs a voltage (hereinafter, referred to as a pixel signal) according to the signal charge. Pixel amplifier. The pixel signal from the pixel amplifier is transferred via a vertical signal line and a horizontal signal line, and is output outside the solid-state imaging device.
[0003]
Since such an amplification type solid-state imaging device uses the XY address system, switching noise is large. In addition, since each pixel has a pixel amplifier, fixed pattern noise is large. In order to remove these noises, the amplification type solid-state imaging device includes a noise removal circuit connected to each vertical signal line, and performs a correlated double sampling process on the pixel signals. The noise removing circuit here is, for example, a clamp capacitor and a clamp transistor connected to each vertical signal line in Patent Document 1.
[0004]
By the way, the solid-state imaging device has pixels that are shielded (or have no photodiode) in order to keep the reference level of the pixel signal constant regardless of the temperature at the time of shooting. In this specification, this pixel (optical black portion or optical black) is abbreviated as an OB pixel. Then, a signal output from the OB pixel (hereinafter, referred to as a dark signal) is used to determine a reference level of the pixel signal.
Specifically, after the dark signal is output from the solid-state imaging device, it is input to the analog signal processing circuit. The analog signal processing circuit determines a reference level of the pixel signal, that is, a signal level corresponding to black (hereinafter, referred to as a dark level) based on the level of the dark signal.
[0005]
The above-described analog signal processing circuit requires a certain amount of time from the time of operation to the time when a stable signal is output. For this reason, even in a state where none of the rows is selected to read the pixel signal, the switches and the noise removal circuit of the vertical signal line and the horizontal signal line are operated. Thereby, the analog signal processing circuit is also operated to output a signal irrelevant to the image data (for example, see Patent Document 2). Hereinafter, this operation is referred to as a blank reading operation.
[0006]
The dark signal may fluctuate due to a change in temperature, and includes high-frequency noise. It is difficult to obtain a stable dark level from a dark signal containing high frequency noise. For this reason, a stable dark level is determined by averaging each dark signal from OB pixels formed over a plurality of rows in an analog signal processing circuit.
[0007]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-77642 (Section 7-8, FIG. 1)
[Patent Document 2]
JP-A-2000-278616 (Section 4-5, FIG. 6-8)
[0008]
[Problems to be solved by the invention]
The amplification type solid-state imaging device is extremely excellent for use in photographing with normal illuminance. However, when used in photographing with extremely low illuminance, it is necessary to greatly increase the amplification factor in an external circuit, so that a slight shift (fluctuation) in the dark level may be amplified and appear large. For this reason, in photographing with extremely low illuminance, it has been particularly desired to stabilize the dark level.
[0009]
Therefore, an object of the present invention is to provide a technique for further stabilizing a dark level in a solid-state imaging device.
[0010]
[Means for Solving the Problems]
The solid-state imaging device according to claim 1 includes a plurality of light receiving pixels, an OB pixel region, and a readout unit. Each light receiving pixel outputs a pixel signal corresponding to the amount of received light. The OB pixel area includes a plurality of optical black pixels that output a dark signal for determining a reference level of a pixel signal. The reading unit reads the pixel signal and the dark signal, and transfers the read signals to the clamp circuit. The reading unit performs a reference level stabilizing operation of reading a dark signal a plurality of times during a period required for the clamp circuit to pull in the reference level. After this reference level stabilizing operation, the reading section performs a pixel signal reading operation.
[0011]
A solid-state imaging device according to a second aspect is the invention according to the first aspect, and is characterized by the following points. First, the reading unit includes a first scanning circuit that inputs a first drive pulse for reading a pixel signal to a plurality of light receiving pixels. Second, the reading unit includes a second scanning circuit that inputs a second drive pulse for reading a dark signal to the OB pixel area. Third, the reading unit includes a timing generator. The timing generator causes the first scanning circuit to perform a pixel signal reading operation by inputting a pulse defining a timing for outputting the first driving pulse to the first scanning circuit. Further, the timing generator causes the second scanning circuit to perform the reference level stabilizing operation by inputting a pulse defining the timing for outputting the second driving pulse to the second scanning circuit.
[0012]
A driving device for a solid-state imaging device according to a third aspect is a driving device for driving a solid-state imaging device including a light receiving pixel, an OB pixel region, and a reading unit. Here, each light receiving pixel outputs a pixel signal corresponding to the amount of received light. The OB pixel area includes a plurality of optical black pixels that output a dark signal for determining a reference level of a pixel signal. The reading unit reads the pixel signal and the dark signal, and transfers the read signals to the clamp circuit. The invention according to the present invention is characterized in that it comprises a stabilizing operation command section and a read command section. The stabilization operation command unit causes the solid-state imaging device to perform a “reference level stabilization operation of reading a dark signal a plurality of times during a period required for the clamp circuit to pull in the reference level”. After the reference level stabilizing operation, the read command unit causes the solid-state imaging device to perform a pixel signal reading operation.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.
<Configuration of First Embodiment>
FIG. 1 is a block diagram of a solid-state imaging device according to the first embodiment of the present invention. This embodiment corresponds to claims 1 and 3. The solid-state imaging device 2 includes a solid-state imaging device 4, a driving pulse generation circuit 6 that inputs a driving pulse voltage to the solid-state imaging device 4 (corresponding to “a solid-state imaging device driving device” according to claim 3), and a solid-state imaging device. And an analog signal processing circuit 8 for processing an output signal of the element 4.
The analog signal processing circuit 8 includes a capacitor C, a DC regeneration circuit (corresponding to a clamp circuit described in the claims) 10, a sample and hold circuit 12, a gain control amplifier 14, and an A / D conversion circuit 16. I have.
[0014]
FIG. 2 is a schematic plan view showing the configuration of the solid-state imaging device 4 described above. Note that VSS in the figure is a ground line. The solid-state imaging device 4 includes constant current sources 20a to 20n, a large number of pixels 24 having m rows and n columns, vertical signal lines 26a to 26n connected to each pixel 24 for each column, and a row of pixels 24. A vertical scanning circuit 28, a column buffer amplifier 30a to 30n, a correlated double sample capacitance Cc1 to Ccn, a correlated double sample transistor Qc1 to Qcn, a column selection transistor Qopt1 to Qoptn, and a horizontal reset transistor QHres. , An output buffer amplifier 34, a horizontal signal line 38, AND gates AG1 to AGn, and a horizontal scanning circuit 42. Note that the last characters “a”, “m”, “n”, etc. of each element indicate which row or column the element is arranged in, and thus are omitted as appropriate.
[0015]
AND gate AG receives horizontal gate pulse voltage φGH at one input terminal.
When the horizontal gate pulse voltage φGH is at a high level, the column selection transistor Qopt receives a horizontal read pulse voltage φHopt from the horizontal scanning circuit 42 via an AND gate AG at its gate. The column selection transistor Qopt connects the vertical signal line 26 to the horizontal signal line 38 according to the horizontal read pulse voltage φHopt.
[0016]
The horizontal reset transistor QHres resets the horizontal signal line 38 to a constant voltage Vref according to the horizontal reset pulse voltage φHres received at the gate.
The pixel 24 includes a photodiode PD, a P-channel transfer transistor Qfw, a P-channel reset transistor Qrsg, and an N-channel junction field-effect transistor JFET (hereinafter abbreviated as JFET). I have. Note that the pixel 24 in the n-th column in each row and all the pixels 24 in the first and second rows are formed as the above-described OB pixels. Further, the pixels 24 other than the OB pixels correspond to the “light receiving pixels” in the claims, and are therefore appropriately distinguished from the “light receiving pixels”.
[0017]
A constant voltage Vrsd is applied to the source of the reset transistor Qrsg, and a constant voltage VD is applied to the drain of the JFET. The drive pulse voltages φTG1 to φTGm are applied to the gate of the transfer transistor Qfw by the vertical scanning circuit 28. The drive pulse voltages φRSG1 to φRSGm are applied to the gates of the reset transistor Qrsg by the vertical scanning circuit 28.
[0018]
<Description of Operation of First Embodiment>
FIG. 3 is a timing chart showing an example of the operation of the solid-state imaging device 2 of the present embodiment. In the figure, the “output signal of the solid-state imaging device” is a pixel signal of each row in one of the columns other than the n-th column (that is, a column having light receiving pixels in the third and subsequent rows; see FIG. 2). “Clamp output” is the waveform of the output signal of the DC regeneration circuit 10 of the analog signal processing circuit 8 (see FIG. 1). The “clamp pulse” is a pulse signal input to the DC regeneration circuit 10, that is, a waveform of a pulse signal that defines a clamp timing. Hereinafter, the operation of the solid-state imaging device 2 will be described with reference to FIGS.
[0019]
First, the drive pulse generation circuit 6 causes the solid-state imaging device 4 to perform the same idle reading operation as in the related art. A period during which the idle reading operation is performed (until a clock signal CLKV2 described later is switched to a high level) is referred to as an “idle reading period TV”.
Next, the drive pulse generation circuit 6 inputs a start pulse STV to the vertical scanning circuit 28 to drive a vertical shift register (not shown) in the vertical scanning circuit 28. In substantially synchronization with this, the drive pulse generation circuit 6 sequentially inputs the clock signals CLKV1 and CLKV2 to the vertical scanning circuit 28. Thereby, one row of the solid-state imaging device 4 (the first row in FIG. 2 in this example) is selected. However, the row selected here is a row composed of only OB pixels. Further, a period from when the clock signal CLKV2 is switched to the high level to when the second row is selected is referred to as a “first row selection period T1”.
[0020]
Immediately after the clock signal CLKV2 is switched to the high level, the drive pulse generation circuit 6 sets the pulse voltage RSG to be input to the vertical scanning circuit 28 to the low level so that the drive pulse voltages φRSG1 to φRSGm of all rows are changed. Low level. Therefore, immediately after the first row is selected, the reset transistors Qrsg are turned on, so that the gate voltages of the JFETs in all rows are reset to Vrsd.
[0021]
Next, the drive pulse generation circuit 6 switches the pulse voltage RSG to a high level. As a result, the drive pulse voltage φRSG1 output to each pixel 24 in the first row selected by the vertical shift register switches to a high level. Therefore, each reset transistor Qrsg in the first row is turned off, and the gate of each JFET in the first row is switched to a floating state. As a result, each JFET in the first row is ready to output a voltage or signal voltage corresponding to a fixed pattern noise component from its source to the vertical signal line 26.
[0022]
Next, the drive pulse generation circuit 6 switches the noise component accumulation pulse φC to a high level to turn on the correlated double sample transistors Qc1 to Qcn. As a result, the fixed pattern noise component of each pixel 24 in the first row is accumulated in the correlated double sample capacitors Cc1 to Ccn. Thereafter, the drive pulse generation circuit 6 switches the noise component accumulation pulse φC to a low level.
[0023]
Next, the drive pulse generation circuit 6 switches the pulse voltage TG input to the vertical scanning circuit 28 to a low level. As a result, the drive pulse voltage φTG1 output to each pixel 24 in the first row selected by the vertical shift register switches to a low level. Therefore, each transfer transistor Qfw in the first row is turned on. Therefore, the signal charge of the photodiode PD is transferred to the gate of the JFET. Thereafter, each JFET in the first row outputs a signal voltage (including a fixed pattern noise component) corresponding to the amount of the transferred signal charge from the source to the vertical signal gland 26.
[0024]
Note that the signal voltage here is a dark signal because it is for the first row of OB pixels. The fixed pattern noise component included in the dark signal is canceled by the fixed pattern noise component accumulated in the correlated double sample capacitors Cc1 to Ccn during the period when φC is at a high level (correlated double sampling processing).
Thereafter, the drive pulse generation circuit 6 returns the pulse voltage TG to the high level, and causes the vertical scanning circuit 28 to switch the drive pulse voltage φTG1 to the high level.
[0025]
Next, the drive pulse generation circuit 6 sets the horizontal gate pulse voltage φGH and the horizontal read pulse voltage φHopt to a high level. Thereby, the horizontal shift registers (not shown) in the horizontal scanning circuit 42 are sequentially turned on one by one. Therefore, high-level voltages are sequentially input to one of the input terminals of the AND gates AG1 to AGn one by one. Therefore, the column selection transistors Qopt1 to Qoptn are sequentially turned on one by one (however, two or more are not turned on at the same time). As a result, signals obtained by removing each fixed pattern noise component from each dark signal in the first row are sequentially output from the output buffer amplifier 34.
[0026]
The horizontal signal line 38 is reset to a constant voltage Vref for each pixel signal by the horizontal reset transistor QHres and the horizontal reset pulse voltage φHres.
Next, the drive pulse generation circuit 6 keeps the first row selected (by not inputting the clock signals CLKV1 and CLKV2 and preventing the vertical shift register from proceeding forward) while keeping the first row selected. The signal reading operation is repeated. The operation repeated here (hereinafter referred to as a repetition operation) is “an operation from the time when the driving pulse voltage φRSG is set to a low level to the time when the dark signal of the first row is output from the output buffer amplifier 34”, that is, “the operation in FIG. Operation during a period separated by a vertical broken line ”. This repetitive operation corresponds to the reference level stabilizing operation described in the claims.
[0027]
The repetitive operation is performed until the DC reproduction circuit 10 stably determines the reference level (dark level) based on the dark signal in the first row. That is, in FIG. 3, this is a period until the clamp output during a period when the clamp pulse is at a high level matches the reference level indicated by the broken line.
Then, after the repetition operation, an operation of reading a pixel signal for generating image data is performed. That is, in the example of FIG. 3, in the first row selection period T1 in which three readings are performed, the first two operations are repetitive operations, and the last one is a dark signal reading operation. After the first row selection period T1, the second and subsequent rows are sequentially selected, and pixel signals are read from the light receiving pixels of each row.
[0028]
The number of times the repetitive operation is performed may be set in advance, for example. The number of times may be determined based on a measurement result or may be determined by calculation. Specifically, the range in which the level of the dark signal can be estimated is estimated, and the period required for the pull-in of the DC regeneration circuit 10 (based on the level of the dark signal after starting to receive the dark signal) is determined from the circuit configuration of the DC regeneration circuit 10. (A period until the dark level is determined) may be calculated.
Alternatively, a detection circuit for detecting that the pull-in operation of the DC regeneration circuit 10 is stabilized may be provided in the analog signal processing circuit 8, and the repetition operation may be terminated when the pull-in is completed.
[0029]
<Cause analysis of conventional issues>
The inventor has clarified the cause of the dark level shift in the conventional solid-state imaging device. Before describing the operation and effect of the present embodiment, this cause analysis will be described with reference to FIGS. 4 and 5.
[0030]
Here, FIG. 4 is a circuit diagram showing a path until signal charges in the pixels 24 in the solid-state imaging device 4 are output to the outside of the solid-state imaging device 4. In the figure, VSS indicates a ground line, and VCC indicates a power supply line (each power supply line is not necessarily the same voltage).
FIG. 5 is an example of a timing chart in the case where the solid-state imaging device 4 is operated by the conventional driving pulse generation circuit. In the figure, TV is a period during which a blank reading operation is performed. T1, T2, T3, T4, and T5 are the first row (rows containing only OB pixels), the second row (rows containing only OB pixels), the third row, the fourth row, and the fifth row, respectively. It is a period that is.
[0031]
If the idle reading operation is sufficiently performed, the DC reproduction circuit 10 of the analog signal processing circuit 8 operates in a stable state. Therefore, the “clamp output” during the period of TV and the period of T1 should be at the same level.
[0032]
However, in the conventional driving method, as shown in FIG. 5, a difference occurs in the clamp output between the period of TV and the period of T1. As a result, the present inventor has found that even when a pixel signal is output from a light receiving pixel (after the third row), a difference occurs in the dark level and affects the output image. The following are considered as causes of this difference.
[0033]
During the idle reading operation, the drive pulse voltages φRSG1 to φRSGm are always at a low level, and thus the gate of each JFET is kept at a constant voltage Vrsd. At this time, the source voltages of all the JFETs output to the vertical signal line 26 are lower than in “normal operation (when the drive pulse voltages φRSG1 to φRSGm are sequentially set to a high level)”. Therefore, the voltage at the positive terminal of the current source 20 connected to the vertical signal line 26 has dropped to a value near the limit at which the current source 20 can operate. Therefore, since the column buffer amplifier 30 has a low input voltage, the output voltage is also very low. That is, it is considered that the output impedance of the column buffer amplifier 30 during the idle reading operation is higher than that during the "normal operation".
[0034]
In “normal operation”, when the noise component accumulation pulse φC is switched to a high level to turn on the correlated double sample transistor Qc, the charging voltage of the electrode on the column buffer amplifier 30 side in the correlated double sample capacitance Cc becomes
(Fixed pattern noise component-Vref)
It becomes. Next, the noise component accumulation pulse φC switches to a low level. At this time, since the output impedance of the column buffer amplifier 30 is sufficiently low, the correlated double sample transistor Qc switches off quickly. After switching off, the signal voltage is read. At this time, the charging voltage of the electrode on the column selection transistor Qopt side in the correlated double sample capacitance Cc is:
[Signal voltage- (fixed pattern noise component-Vref)]
It becomes.
[0035]
However, if the output impedance of the column buffer amplifier 30 is high, even if the noise component accumulation pulse φC is switched to a high level, the correlated double sample transistor Qc discharges the electric charge accumulated in the parasitic capacitance between its gate and drain. Takes time. For this reason, it is considered that the correlated double sample transistor Qc does not switch from ON to OFF sufficiently quickly during the idle reading operation.
[0036]
Therefore, during the idle reading operation, before the correlated double sample transistor Qc is completely turned off, the correlated double sample capacitance Cc is further charged a little by the voltage read later. That is, at the time of the idle reading operation, the voltage charged in the correlated double sample capacitance Cc in advance to cancel the fixed pattern noise component included in the signal voltage is higher than that in the “normal operation”. As a result, the inventor has clarified that the output signal at the time of the idle reading operation has a slightly lower level than the dark signal read directly from the OB pixel.
[0037]
The level difference between the output signal and the dark signal at the time of the idle reading operation is amplified and increases as the imaging sensitivity increases, that is, as the gain of the gain control amplifier 14 increases. Furthermore, the present inventor has found that the above-mentioned problem is reduced by reading out a normal pixel signal after selecting and reading out a row of OB pixels more times than before.
[0038]
<Effects of First Embodiment>
The main difference between the present embodiment and the conventional driving method is that, in the present embodiment, by setting the selection period of the first row longer than the selection period of the other rows, the period required for pulling in the DC regeneration circuit 10 is reduced. Among them, a “repeat operation” for repeatedly reading the first line has been added ”. In this case, during the selection period of the first row, the potential of the vertical signal line 26 becomes the read potential of the dark signal, so that the output impedance of the column buffer amplifier 30 does not change from that at the time of normal scanning.
[0039]
For this reason, after the determination of the dark level by the DC reproduction circuit 10 is completed, the second and subsequent rows are sequentially selected, and the pixel signals for generating the image data are read. Therefore, the dark level can be sufficiently stabilized before the reading of the pixel signal is started.
That is, since the dark level does not fluctuate during the reading of the pixel signal, even if the amplification factor in the external circuit (the gain control amplifier 14 in this example) is greatly increased, the deviation of the dark level is amplified. It does not appear large. As a result, a good image signal can be obtained even when shooting with extremely low illuminance.
[0040]
<Supplementary items of the first embodiment>
[1] In the first embodiment, an example has been described in which the operation is repeatedly performed on the first row to stabilize the dark level. The present invention is not limited to such an embodiment. The row to be subjected to the repetitive operation may be a row other than the first row as long as it has only OB pixels.
However, it is desirable that the row to be subjected to the repetitive operation is the row in which the temporal order of scanning is the first row as in the first row used in the present embodiment.
Also, only one row need not be the target of the repeated operation. For example, the first row and the second row may be alternately selected, and the operation may be repeatedly performed on the first row and the second row. However, the condition is that the row to be subjected to the repetitive operation has only OB pixels.
[0041]
[2] The vertical shift register may be a static shift register or a dynamic shift register.
In the case of using a dynamic shift register, the period of the repetitive operation for one row needs to be shorter than the holding period of the register. In this case, the stabilization time of the DC regeneration circuit 10 (the time required for the DC regeneration circuit 10 to pull in) may be obtained by repeatedly performing the operation on a plurality of rows as described above.
[0042]
Specifically, when a predetermined time shorter than the register holding time has elapsed after the start of the repetitive operation for one row, the clock signals CLKV1 and CLKV2 are input to select another row, and a new row is selected. What is necessary is just to perform repetitive operation | movement with respect to it.
Such a mode of repeatedly performing the operation on a plurality of rows is effective when the stabilization time of the DC regeneration circuit 10 is long.
[0043]
[3] When a static element is used for the vertical shift register, the operation can be repeated almost indefinitely after selecting one row. In this case, if the time of the repetitive operation is made long enough to stabilize the output signal of the analog signal processing circuit 8, the idle reading operation may be omitted. Also in this case, it is not necessary to set only one row as a target of the repetition operation, and the repetition operation may be performed by always selecting one of a plurality of rows including only OB pixels.
[0044]
[4] The example has been described in which the pixel 24 in the n-th column in each row and all the pixels 24 in the first and second rows are formed as OB pixels. The present invention is not limited to such an embodiment. The area to be the OB pixel may be another part. However, for the above-described reason, it is desirable that all the first rows be OB pixels and be subjected to the repetitive operation.
[0045]
[5] The example in which the solid-state imaging device 2, the driving pulse generation circuit 6, and the analog signal processing circuit 8 constitute the solid-state imaging device 2 has been described. The present invention is not limited to such an embodiment. A solid-state imaging device may be configured with only the solid-state imaging device 4 and the driving pulse generation circuit 6. In this case, an external analog signal processing circuit is connected to the solid-state imaging device. That is, the clamp circuit described in the claims may be external or internal to the solid-state imaging device.
[0046]
[6] Finally, the correspondence between the claims and the present embodiment will be described. Note that the correspondence shown below is an interpretation for reference, and does not limit the present invention.
The optical black pixels described in the claims correspond to OB pixels.
The OB pixel region described in the claims corresponds to the pixels 24 in the first row.
The stabilizing operation command section described in claims corresponds to “the function of the drive pulse generating circuit 6 that causes the solid-state imaging device 4 to perform the repetitive operation (reference level stabilizing operation)”.
[0047]
The read command unit described in claims corresponds to “the function of the drive pulse generation circuit 6 that causes the solid-state imaging device 4 to perform a read operation of a pixel signal for generating image data after the repetition operation”.
The reading unit described in claims corresponds to “the function of the drive pulse generation circuit 6 that causes the solid-state imaging device 4 to perform the above-described repetitive operation and the pixel signal readout operation”.
[0048]
<Second embodiment>
FIG. 6 is a schematic plan view illustrating the configuration of the solid-state imaging device according to the second embodiment of the present invention. This embodiment corresponds to claims 1 to 3. The configuration of the present embodiment is the same as that of the first embodiment except for the following two points, and duplicate description (a configuration diagram corresponding to FIG. 1, a pixel signal reading operation, and the like) is omitted.
[0049]
First, the solid-state imaging device further includes a dedicated OB pixel row (only the 0th row) composed of only OB pixels, and a dedicated scanning circuit 60 that scans only the dedicated OB pixel row. Each OB pixel in the dedicated OB pixel row is the same as the OB pixel of the first embodiment except that it is not connected to the vertical scanning circuit 28 but is connected to the dedicated scanning circuit 60. The dedicated scanning circuit 60 outputs the drive pulse voltages φRSG0 and φTG0, and reads a dark signal from the dedicated OB pixel row to the vertical signal line 26.
[0050]
Second, the drive pulse generation circuit further drives the dedicated scanning circuit 60, and therefore has a different function from the first embodiment as described later.
For this reason, in the present embodiment, the solid-state imaging device is denoted by 62, the solid-state imaging device is denoted by 64, and the drive pulse generation circuit is denoted by 66.
[0051]
<Description of Operation of Second Embodiment>
FIG. 7 is a timing chart showing an example of the operation of the solid-state imaging device 62 of the present embodiment. Hereinafter, the operation of the solid-state imaging device 62 will be described with reference to FIGS.
First, the drive pulse generation circuit 60 causes the solid-state imaging device 64 to perform the same idle reading operation as in the first embodiment. As in the first embodiment, this period is referred to as an “idle reading period TV”.
[0052]
Next, the drive pulse generation circuit 66 switches the dedicated row selection pulse OPT input to the dedicated scanning circuit 60 to a high level, and causes the dedicated scanning circuit 60 to start scanning the 0th row. Further, the drive pulse generating circuit 66 inputs the clock signals CLKV1 and CLKV2 to the vertical scanning circuit 28. At this point, since the start pulse STV has not been input yet, the vertical scanning circuit 28 does not select any row. The period from when the clock signal CLKV2 is switched to the high level until the first row is selected is referred to as a “0th row selection period T0”.
[0053]
Further, as in the first embodiment, immediately after the clock signal CLKV2 is switched to the high level, the gate voltages of the JFETs in all rows are reset to Vrsd.
Next, the dedicated scanning circuit 60 sets the drive pulse voltage φRSG0 to a high level, and switches the gate of the JFET of the OB pixel on the 0th row to a floating state.
Next, the drive pulse generation circuit 66 switches the noise component accumulation pulse φC to a high level, and accumulates the fixed pattern noise component of the OB pixel in the 0th row in the correlated double sample capacitance Cc. Thereafter, the drive pulse generation circuit 66 returns the noise component accumulation pulse φC to a low level.
[0054]
Next, the dedicated scanning circuit 60 switches the drive pulse voltage φTG0 to a low level. As a result, the JFET of each OB pixel on the 0th row outputs a dark signal. Thereafter, a signal obtained by removing the fixed pattern noise component from the signal voltage is sequentially output from the output buffer amplifier 34. After that, the dedicated scanning circuit 60 returns the drive pulse voltage φTG0 to the high level.
[0055]
Next, while the dedicated row selection pulse OPT is at a high level, the operation of reading the dark signal from the 0th row is repeated (hereinafter, the repeated operation is referred to as a repetitive operation as in the first embodiment). . At this time, the clock signals CLKV1 and CLKV2 are also input, but the vertical scanning circuit 28 does not select any row. The repetitive operation is performed during a period required for pull-in of the DC regeneration circuit 10 (until the dark level is determined by the dark signal in the 0th row).
[0056]
Then, after the repetition operation, the drive pulse generation circuit 66 switches the dedicated row selection pulse OPT to a low level, and stops reading from the 0th row.
Next, the drive pulse generation circuit 66 inputs the start pulse STV to the vertical scanning circuit 28. Thereafter, the vertical scanning circuit 28 sequentially selects the first and subsequent rows, and sequentially reads the pixel signals of the first and subsequent rows.
[0057]
<Effect of Second Embodiment>
As described above, also in the second embodiment, the same effects as in the first embodiment can be obtained. Further, in the present embodiment, the dedicated OB pixel row for stabilizing the dark level and the dedicated scanning circuit 60 for scanning the dedicated OB pixel row are provided. Since the dedicated scanning circuit 60 selects only the dedicated OB pixel row and does not need to be a shift register, the dedicated scanning circuit 60 can be easily configured with static elements. Therefore, even if the stabilization time of the DC reproduction circuit 10 is long, the dark level can be stabilized without performing special scanning such as selecting another row of OB pixels and continuing the repetitive operation.
[0058]
<Supplementary items of the second embodiment>
[1] In the second embodiment, the example in which the drive pulse generation circuit 66 scans the dedicated OB pixel row by inputting the dedicated row selection pulse OPT to the dedicated scanning circuit 60 has been described. The present invention is not limited to such an embodiment. For example, the dedicated scanning circuit 60 and the vertical scanning circuit 28 may be linked so that the driving pulse generation circuit 66 does not directly drive the dedicated scanning circuit 60.
[0059]
Specifically, the dedicated scanning circuit 60 scans the dedicated OB pixel row during a period when the vertical shift register is not operating, that is, a period from when the vertical shift register selects the last row to when the start pulse STV is input. Thus, the dedicated row selection pulse OPT may be omitted.
[0060]
[2] The example of performing the blank reading operation has been described. The present invention is not limited to such an embodiment. For example, if the time of the repetitive operation is set long enough to stabilize the output signal of the analog signal processing circuit 8, the idle reading operation can be omitted.
[0061]
[3] Finally, the correspondence between the claims and the present embodiment will be described. Note that the correspondence shown below is an interpretation for reference, and does not limit the present invention.
The OB pixel area described in the claims corresponds to a dedicated OB pixel row (0th row).
The “timing generator” and “solid-state imaging device driving device” described in claims correspond to the driving pulse generation circuit 66.
The first driving pulse described in the claims corresponds to the driving pulse voltages φRSG3 to φRSGm, the driving pulse voltages φTG3 to φTGm, and the voltage input to the AND gate by the horizontal scanning circuit 42 according to the horizontal read pulse voltage φHopt. Note that a part of the operation description corresponding to this overlaps, and is described only in the first embodiment.
[0062]
The first scanning circuit described in claims corresponds to the vertical scanning circuit 28 and the horizontal scanning circuit 42.
The second driving pulse described in the claims corresponds to the driving pulse voltage φRSG0 and the driving pulse voltage φTG0.
The second scanning circuit described in the claims corresponds to the dedicated scanning circuit 60.
[0063]
The “pulse defining the timing for outputting the first drive pulse” in the claims is “a pulse voltage RSG, a pulse voltage TG, a start pulse STV, a clock signal CLKV1, which are input to the vertical scanning circuit 28 by the drive pulse generation circuit 66, CLKV2 ”. Note that a part of the operation description corresponding to this overlaps, and is described only in the first embodiment.
[0064]
The “pulse that defines the timing of outputting the second drive pulse” in the claims corresponds to “the dedicated row selection pulse OPT and the clock signals CLKV1 and CLKV2 input to the dedicated scan circuit 60 by the drive pulse generation circuit 66”.
[0065]
【The invention's effect】
In the present invention, the operation of reading the dark signal from the OB pixel region a plurality of times is performed during the period required for the clamp circuit to pull in the reference level, and after this period, the operation of reading the pixel signal is performed. For this reason, the pixel signal readout operation can be executed in a state where the reference level is pulled in (that is, the dark level is determined). Therefore, when the amplification factor in the external circuit is increased, the conventional problem that the deviation of the dark level is amplified and greatly appears can be solved.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a schematic plan view illustrating a configuration of a solid-state imaging device in FIG. 1;
FIG. 3 is a timing chart illustrating an example of an operation of the solid-state imaging device according to the first embodiment.
4 is a circuit diagram showing a path until signal charges in a pixel in the solid-state imaging device in FIG. 2 are output as a pixel signal.
FIG. 5 is an example of a timing chart when a solid-state imaging device is operated by a conventional driving pulse generation circuit.
FIG. 6 is a schematic plan view illustrating a configuration of a solid-state imaging device according to a second embodiment of the present invention.
FIG. 7 is a timing chart illustrating an example of an operation of the solid-state imaging device according to the second embodiment.
[Explanation of symbols]
2 Solid-state imaging device
4 Solid-state imaging device
6. Drive pulse generation circuit
8 Analog signal processing circuit
10 DC regeneration circuit
12 Sample hold circuit
14 Gain control amplifier
16 A / D conversion circuit
20 constant current source
24 pixels
26a-26n vertical signal line
28 vertical scanning circuit
30a-30n column buffer amplifier
34 output buffer amplifier
38 horizontal signal line
42 horizontal scanning circuit
60 Dedicated scanning circuit
62 Solid-state imaging device
64 solid-state image sensor
66 Drive pulse generation circuit
AG1 to AGn AND gate
C capacitor
Cc1-Ccn Correlated double sample capacity
QHres horizontal reset transistor
Qc1-Qcn Correlated double sample transistor
Qopt1 to Qoptn column select transistor

Claims (3)

A plurality of light-receiving pixels that output pixel signals according to the amount of received light,
An OB pixel area including a plurality of optical black pixels that output a dark signal for determining a reference level of the pixel signal;
A solid-state imaging device comprising: a read unit that reads the pixel signal and the dark signal and transfers the read signals toward a clamp circuit;
The reading unit,
During the period required for the clamp circuit to pull in the reference level, a reference level stabilizing operation for reading the dark signal a plurality of times is performed.
After the reference level stabilizing operation, the pixel signal reading operation is performed. The solid-state imaging device according to claim 1,
The reading unit,
A first scanning circuit for inputting a first drive pulse for reading the pixel signal to the plurality of light receiving pixels;
A second scanning circuit for inputting a second driving pulse for reading the dark signal to the OB pixel area;
A timing for outputting the pixel signal by causing the first scanning circuit to perform a read operation of the pixel signal by inputting a pulse defining a timing for outputting the first driving pulse to the first scanning circuit. A timing generator that causes the second scanning circuit to perform the reference level stabilizing operation by inputting a pulse defining the following to the second scanning circuit: A plurality of light-receiving pixels that output pixel signals according to the amount of received light,
An OB pixel area including a plurality of optical black pixels that output a dark signal for determining a reference level of the pixel signal;
A drive device for reading the pixel signal and the dark signal, and for driving a solid-state imaging device including a readout unit that transfers the readout signal to a clamp circuit,
A stabilizing operation command unit that causes the solid-state imaging device to perform a “reference level stabilizing operation of reading the dark signal a plurality of times during a period required for the clamp circuit to pull in the reference level”;
A driving unit for driving the solid-state imaging device, comprising: a read-out instruction unit that causes the solid-state imaging device to perform the pixel signal reading operation after the reference level stabilizing operation.

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