JP2004281987A - Complementary type semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a complementary type semiconductor device capable of suppressing a kink current due to substrate flotation and to provide its manufacturing method. <P>SOLUTION: The complementary type semiconductor device is provided with a 1st semiconductor layer 4 provided on an insulating substrate 3, a 1st gate insulating film 8 provided on the 1st semiconductor layer 4, a 1st gate electrode 9 provided on the 1st gate insulating layer 8, and an n channel type MOS transistor 21 having a source area 5S and a drain area 5D which are in contact with a 1st channel area 7 in the 1st semiconductor layer 4 below the 1st gate electrode 9 and formed of a silicide layer 14. Further, a 2nd semiconductor layer 4 provided on the insulating substrate 3, a 2nd gate insulating layer 8 provided on the 2nd semiconductor layer 4, a 2nd gate electrode 9 provided on the 2nd gate insulating layer 8, and a p channel type MOS transistor 22 having a 2nd source area 6S and a drain area 6D including an impurity introduced layer in contact with a 2nd channel area 7 in the 2nd semiconductor layer 4 below the 2nd gate electrode 9 are provided on the same substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a complementary semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
[Non-Patent Document] Tanemasa Asano et al., IEICE Technical Report of IEICE, ED2001-12 SDM2001-12 (2001-04).
[0003]
A so-called thin film transistor (TFT) is one in which an insulated gate field effect transistor is formed by forming a semiconductor thin film on an insulating substrate and providing a channel region in the thin film. For example, a liquid crystal display device using a TFT as a switching element can have a thin display portion and is used for office equipment, computers, and the like. As a semiconductor device using this TFT, an active matrix liquid crystal display device is known.
The active matrix type liquid crystal display device includes a pixel matrix circuit for performing image display, a control circuit for performing pixel display, and the like. The control circuit includes a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like, and all of them are configured based on a CMOS (Complementary Metal-Oxide Semiconductor).
[0004]
FIG. 9 is a sectional view of a CMOS using a conventional thin film transistor. As shown in FIG. 9, a semiconductor layer 54 made of a polycrystalline silicon layer or the like is formed on a surface of an insulating substrate 53 in which an insulating layer 52 is formed on a surface of an insulating substrate 51 made of, for example, glass. On the surface of the semiconductor layer 54, a gate insulating layer 58 made of an oxide film or the like is formed. Further, a gate electrode 59 is formed on the surface of the gate insulating layer 58. In the semiconductor layer 54, a pair of an n-type source region 55S and an n-type drain region 55D, and a p-type source region 56S and a p-type drain region 56D are respectively formed.
Channel regions 57 are formed between the n-type source region 55S and the n-type drain region 55D, and between the p-type source region 56S and the p-type drain region 56D. A device in which the gate electrode 59 is formed on the channel region 57 in this manner is called a top-gate thin film transistor. The surfaces of the semiconductor layer 54 and the gate electrode 59 are covered with an interlayer insulating layer 60.
The wiring layer 62 is connected to each of the n-type source region 55S, the n-type drain region 55D, and the p-type source region 56S and the p-type drain region 56D through the contact hole 61 formed in the interlayer insulating layer 60. . Source region 55S and source region 56S of two MOS transistors having different polarities of source region 55S, drain region 55D and channel region 57, in the figure, n-channel MOS transistor 71 and p-channel MOS transistor 72 are connected. Thus, the CMOS 70 is formed.
[0005]
The outline of the manufacturing process of the CMOS 70 shown in FIG. 9 will be described below. FIGS. 10A to 10G and FIGS. 11H to 11L are cross-sectional structural views sequentially showing the manufacturing steps of the CMOS 70 shown in FIG.
First, an insulating layer 52 made of, for example, an oxide film is formed on the entire surface of an insulating substrate 51 made of glass. For example, such a substrate is referred to as an insulating substrate 53. Next, an amorphous semiconductor layer 540 made of amorphous silicon is formed on the surface of the insulating layer 52 (FIG. 10A). Next, the amorphous semiconductor layer 540 is changed to a semiconductor layer 54 made of polycrystalline silicon by a known method (FIG. 10B).
Next, a resist film 810 is selectively formed on the surface of the semiconductor layer 54 to define the shape of the active region by using a photolithography method (FIG. 10C). Next, after the semiconductor layer 54 is etched using the resist film 810 as a mask, the resist film 810 is removed (FIG. 10D). Next, a gate insulating layer 58 is formed on the surfaces of the insulating substrate 53 and the semiconductor layer 54 (FIG. 10E). Next, a conductive layer 590 for forming a gate electrode is formed over the gate insulating layer 58 (FIG. 10F).
Next, a resist film 820 is selectively formed on the surface of the conductive layer 590 using a photolithography method to define the shape of the gate electrode (FIG. 10G). Next, using the resist film 820 as a mask, the conductive layer 590 is etched to form the gate electrode 59, and then the resist film 820 is removed (FIG. 11H). Next, a resist film 830 serving as a mask for impurity introduction is selectively formed in the formation region of the p-channel MOS transistor. Next, using this resist film 830 as a mask, n-type impurities 550 are introduced only into the regions that become the source / drain regions in the semiconductor layer 54 that becomes the n-channel MOS transistor, and the n-type source region 55S and the n-type drain region 55D is formed (FIG. 11 (i)). Note that the gate electrode 59 is used as a mask and no impurity is introduced into the semiconductor layer 54 serving as a channel region located below the gate electrode 59. Next, the resist film 830 is removed.
Next, a resist film 840 serving as a mask for introducing impurities is selectively formed in a region where the n-channel MOS transistor is to be formed. Next, using this resist film 840 as a mask, a p-type impurity 560 is introduced only into the semiconductor layer 54 to be a p-channel MOS transistor to form a p-type source region 56S and a p-type drain region 56D (FIG. 11 (j)). )). Note that the gate electrode 59 is used as a mask and no impurity is introduced into the semiconductor layer 54 serving as a channel region located below the gate electrode 59. Next, the resist film 840 is removed. Next, an interlayer insulating film 60 is formed on the entire surface of the insulating substrate 53 (FIG. 11 (k)). Next, a heat treatment step for activating the impurity atoms added to the semiconductor layer 54 is performed.
Next, a resist film (not shown) for forming a contact hole is selectively formed on the surface of the interlayer insulating film 60. Thereafter, the interlayer insulating film 60 is etched using the resist film as a mask to form contact holes 61 reaching the gate electrode 59, the drain region 55D, the source region 55S, the drain region 56D, and the source region 56S, respectively. Next, after removing the resist film, a conductive layer serving as a wiring layer is formed inside the contact hole 61 and on the surface of the interlayer insulating film 60, and is patterned into a predetermined wiring pattern to form a wiring layer 62. Through the above steps, the CMOS 70 shown in FIG. 9 is completed (FIG. 11 (l)).
[0006]
[Problems to be solved by the invention]
Since the channel region 57 of the TFT is electrically floating, there is a problem that a kink current is generated. It is known that this kink current causes instability of circuit operation (see the above non-patent document).
As a method for suppressing a kink current caused by such a floating substrate, a method of fixing the potential of a channel region 83 (body) by a body contact terminal 87 has been proposed as shown in FIG.
81 is an active layer, 82S is a source region, 82D is a drain region, 83 is a channel region, 84 is a gate electrode, 85 is a source electrode, 86 is a drain electrode, and 87 is a body contact terminal.
However, the addition of a new body contact terminal 87 increases the area occupied by each MOS element, and constrains the layout design. Therefore, there is a problem that it is not suitable for circuit densification. Further, the manufacturing process becomes complicated, and the probability of occurrence of defects increases.
Furthermore, when a complementary transistor is configured based on the technology described in the above-mentioned non-patent document, both the n-channel MOS transistor and the p-channel MOS transistor must be configured as Schottky contact TFTs. In addition, it is necessary to form two different types of Schottky contact layers for the n-channel and the p-channel, and there is a problem that the manufacturing process is complicated.
SUMMARY OF THE INVENTION An object of the present invention is to provide a complementary semiconductor device which can solve the above-described problems and can suppress a kink current caused by a floating substrate, and a method of manufacturing the same.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has a configuration as described in the claims.
That is, the complementary semiconductor device according to claim 1 has a p-channel having a source region and a drain region provided adjacent to a p-type channel region, and a gate electrode provided on the channel region via an insulating film. A complementary MOS transistor comprising an n-type MOS transistor, a source region and a drain region provided adjacent to an n-type channel region, and an n-channel MOS transistor having a gate electrode provided on the channel region via an insulating film. In the semiconductor device, a junction between at least one of a source region and a drain region provided adjacent to an n-type channel region of the n-channel MOS transistor and the n-type channel region is a Schottky junction. ing. According to the present invention, kink current can be suppressed.
According to a second aspect of the present invention, in the complementary semiconductor device according to the first aspect, at least one of a source region and a drain region provided adjacent to the n-type channel region is a silicide layer. It has a configuration. According to the present invention, the kink current can be suppressed at the operating voltage.
According to a third aspect of the present invention, there is provided a method of manufacturing a complementary semiconductor device comprising an n-channel MOS transistor and a p-channel MOS transistor on a single substrate. Forming the first and second semiconductor layers for the n-type and p-channel type MOS transistors apart from each other; and forming an insulator layer serving as a gate insulating film on the substrate and the first and second semiconductor layers. Forming; forming first and second gate electrodes on the first and second semiconductor layers of the insulator layer; and forming the second and third gate electrodes for forming the p-channel MOS transistor. Forming a source region and a drain region in a semiconductor layer; and forming a predetermined region in the first semiconductor layer for forming the n-channel MOS transistor. It has a configuration that is formed by and forming a Schottky junction with at least one of the source and drain regions. According to the production method of the present invention, the production can be performed with relatively few steps.
The method of manufacturing a complementary semiconductor device according to claim 4 is a method of forming a complementary semiconductor device comprising an n-channel MOS transistor and a p-channel MOS transistor on a single substrate. When one of the source region and the drain region that is to be joined to the channel region of the MOS transistor is a Schottky junction and the other is a pn junction, the pn junction is formed in a process prior to the Schottky junction. It has a configuration.
[0008]
The present inventor has found that the drain current characteristics of the n-channel MOS transistor and the p-channel MOS transistor constituting the complementary semiconductor device with respect to the drain voltage are different from those of the kink current generated in the n-channel MOS transistor. It has been found that a kink current generated in a transistor is small, that is, a kink current is generated only in an n-channel MOS transistor in a used drain voltage region.
Further, in the method of manufacturing the complementary semiconductor device, when forming a Schottky junction in the source region or the drain region of the n-channel MOS transistor, the step of forming the pn junction is performed before the step of forming the Schottky junction. This is the optimal manufacturing method. Furthermore, in the method of manufacturing a complementary semiconductor device formed on one substrate, it is preferable that the step of forming the p-channel MOS transistor be performed before the step of forming the n-channel MOS transistor.
That is, in the complementary semiconductor device according to the present invention, at least one of the source region and the drain region adjacent to the channel region of the n-channel MOS transistor among the n-channel and p-channel MOS transistors included in the complementary semiconductor device. Is formed by Schottky junction, so that the substrate floating effect can be suppressed. Therefore, the kink current can be suppressed, and the circuit operation can be stabilized. Further, since it is not necessary to form two types of silicide layers for the n-channel type and the p-channel type MOS transistor, the manufacturing process can be simplified.
Furthermore, since it is not necessary to newly add a body contact terminal, the circuit can be made denser and the manufacturing process can be simplified without increasing the occupied area of the element or restricting the layout design.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
Embodiment 1
Hereinafter, an embodiment in which a complementary semiconductor device is applied to a CMOS transistor included in a display circuit of a liquid crystal display device will be described.
<< CMOS structure >>
FIG. 1 is a cross-sectional structure diagram of a CMOS using the thin film transistor of the present embodiment. As shown in FIG. 1, the insulating substrate 3 is obtained by forming an insulating layer 2 on the surface of an insulating substrate 1 made of a glass substrate or the like. As the insulating substrate 1, in addition to an insulating substrate such as a glass substrate, a quartz substrate, and a plastic substrate, a metal substrate, a silicon substrate, or a ceramic substrate having an insulating coating formed on a surface can be used. As the glass substrate, for example, a low-alkali glass substrate such as a Corning # 1737 substrate is preferably used. The insulating layer 2 is an insulating film containing silicon oxide or silicon nitride as a main component on the surface of the insulating substrate 1 and is preferably formed closely. On the surface of the insulating substrate 3 in which the insulating layer 2 is formed on the surface of the insulating substrate 1, a crystalline semiconductor layer 4 made of a polycrystalline silicon layer or the like is formed.
On the surface of the semiconductor layer 4, a gate insulating layer 8 made of an oxide film or the like is formed.
Further, a gate electrode 9 is formed on the surface of the gate insulating layer 8.
Further, a side wall insulating film 13 is formed on a side surface of the gate electrode 9. Thus, a MOS transistor is configured. The CMOS transistor includes an n-channel MOS transistor 21 and a p-channel MOS transistor 22.
The n-channel type MOS transistor (TFT) 21 is a Schottky contact type TFT constituted by the channel region 7 (left side in FIG. 1) and the source region 5S and the drain region 5D each made of the silicide layer 14. I have.
The p-channel MOS transistor (TFT) 22 has a channel region 7 (on the right in FIG. 1) and a source region 6S including a high-concentration p-type impurity region 15 and a silicide layer 14 adjacent to the channel region 7, respectively. , A pn junction type TFT constituted by the drain region 6D.
The surfaces of the semiconductor layer 4 and the gate electrode 9 are covered with an interlayer insulating layer 10.
A wiring layer 12 is connected to each gate electrode 9, source region 5S, drain region 5D, and p-type source region 6S and p-type drain region 6D through a contact hole 11 formed in the interlayer insulating layer 10. .
The source region 5S and the source region 6S of two MOS transistors having different polarities of the channel region 7, that is, a Schottky contact type n channel type MOS transistor 21 and a pn junction type p channel type MOS transistor 22, are connected in the figure. Thus, the CMOS 20 is formed.
[0010]
<< CMOS manufacturing method >>
Next, an outline of a manufacturing process of the CMOS 20 shown in FIG. 1 will be described below.
2A to 2G and FIGS. 3H to 3M are cross-sectional structural views sequentially showing the manufacturing steps of the CMOS 20 shown in FIG. In this embodiment, when a CMOS is formed on one substrate, a junction between a source region and a drain region of an n-channel MOS transistor and a channel region is made a Schottky junction, and a p-channel MOS transistor is replaced with an n-channel MOS transistor. This is an example in which the MOS transistor is formed before the MOS transistor.
[0011]
First, an insulating layer 2 made of a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like is formed on the surface of an insulating substrate 1 made of a low alkali glass substrate or a quartz substrate by using, for example, a CVD method. For example, such a substrate is referred to as an insulating substrate 3. Next, an amorphous semiconductor layer 40 made of amorphous silicon is formed on the surface of the insulating layer 2 by a known film forming method such as a plasma CVD method or a sputtering method to a thickness of 50 to 250 nm, for example, 200 nm ( FIG. 2 (A)).
In the amorphous semiconductor layer 40, 1 × 10 ¹⁶ ~ 5 × 10 ¹⁶ cm ^-3 A small amount of boron (B) may be added. Boron may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous semiconductor layer 40.
When adding by the ion doping method, a cap layer made of, for example, a silicon oxide film may be formed on the surface of the amorphous semiconductor layer 40 to a thickness of 80 to 150 nm, for example, 120 nm. After the addition, the cap layer is etched.
Next, the amorphous semiconductor layer 40 is crystallized using a known crystallization method to form a semiconductor layer 4 made of, for example, polycrystalline silicon (FIG. 2B). Examples of the crystallization technique include a laser annealing method and a solid phase growth method, but the method for forming the crystalline semiconductor film is not particularly limited. For example, it is most preferable to use a crystalline silicon film in which an amorphous silicon film is formed by a laser crystallization technique or a thermal crystallization technique, but, of course, other semiconductor materials can be used.
Next, a resist film 17 is selectively formed on the surface of the semiconductor layer 4 using a photolithography method in order to define the shape of the active region (FIG. 2C).
Next, in order to form n-channel and p-channel MOS transistors, the semiconductor layer 4 is etched using the resist film 17 as a mask, and then the resist film 17 is removed (FIG. 2D).
Next, a gate insulating film 8 is formed on the surfaces of the insulating substrate 3 and the semiconductor layer 4 (FIG. 2E).
The gate insulating film 8 is formed of a material containing silicon oxide or silicon nitride as a main component, and has a thickness of 10 to 200 nm, preferably 30 to 100 nm. For example, by plasma CVD, SiH ₄ And N ₂ A gate insulating film 8 was formed by laminating a silicon oxide film using O as a raw material to a thickness of 50 nm. Further, in order to obtain a clean surface, it is preferable to perform a plasma hydrogen treatment before forming the gate insulating film 8.
Next, as a conductive layer 19 for forming a gate electrode on the gate insulating layer 8, n is formed using, for example, a CVD method. ⁺ A type polycrystalline silicon layer is formed to a thickness of 200 nm (FIG. 2E). Then, a resist film 27 is selectively formed on the surface of the conductive layer 19 by photolithography in order to define the shape of the gate electrode (FIG. 2G).
Next, the conductive layer 19 is etched using the resist film 27 as a mask to form the gate electrode 9, and then the resist film 27 is removed (FIG. 3H).
The gate electrode 9 is made of a material containing elements such as Ta, Ti, W, Mo, and Al as main components, and a known film forming method such as a sputtering method or a vacuum evaporation method is used. It may be formed. In this case, no silicide layer 14 is formed on gate electrode 9.
Next, a p-channel MOS transistor is formed. First, a resist film 37 serving as an impurity mask is selectively formed in a formation region of an n-channel MOS transistor by using a photolithography method. Next, using the resist film 37 as a mask, a p-type impurity 45 such as boron ions is implanted only into the semiconductor layer 4 to be a p-channel MOS transistor by using an ion implantation method. The boron concentration in this region is, for example, 1.5 × 10 ²⁰ ~ 3 × 10 ²¹ cm ^-3 It was made to become. Thus, the high-concentration p-type impurity regions 15 forming the source and drain regions of the p-channel MOS transistor are formed (FIG. 3I). After that, the resist film 37 was removed.
{Circle around (1)} Next, a heat treatment step was performed to activate the impurity element imparting p-type. This step can be performed by a method such as a furnace annealing method, a laser annealing method, a rapid thermal annealing (RTA) method, or the like. In the present embodiment, the activation step is performed by the furnace annealing method. The heat treatment was performed in a nitrogen atmosphere at 300 to 650 ° C., here 550 ° C., for 4 hours.
(2) A silicon oxide film (SiO 2) is formed on the entire surface of the insulating ₂ The insulating layer 13 is formed to a thickness of 150 to 250 nm, for example, 200 nm (FIG. 3J). Next, a side wall insulating layer (side wall) 13 is formed on the step side surface of the gate electrode 9 by anisotropically etching the insulating layer (FIG. 3K). At this time, the thickness of the sidewall insulating layer 13 in the substrate surface direction (lateral direction) was 80 nm. The order of (1) and (2) may be reversed.
Next, an n-channel MOS transistor is formed.
The n-channel MOS transistor is a Schottky MOS transistor in order to suppress a kink current. First, in order to form a Schottky contact layer on the entire surface of the insulating substrate 3, a material that is in Schottky contact with the semiconductor layer 4, for example, a material such as Er (erbium), Pt, Ni, Co, or Mo is used. A Schottky contact material layer 16 is formed by CVD, sputtering, or the like (FIG. 3L). In this embodiment, Er is formed to have a thickness of, for example, 50 nm in order to form an n-channel Schottky MOS transistor. Next, silicidation of the Er layer was performed by heat treatment (annealing) in vacuum at 400 ° C. for 300 minutes, for example. As a result, the source region 5S and the drain region 5D of the n-channel MOS transistor, the gate electrode 9, and the Schottky contact material layer 16 which is in contact with the high-concentration p-type impurity region 15 of the p-channel MOS transistor react and are silicided. Then, a silicide layer 14 is formed (FIG. 3M). Thereafter, unreacted Er is selectively removed by using dilute nitric acid at 60 ° C. to form a silicide layer (ErSi having a thickness of 40 nm). ₂ The source region 5S and the drain region 5D of the n-channel MOS transistor composed of the layer 14) were formed (FIG. 4 (N)). Thus, the Schottky contact type n-channel MOS transistor 21 is completed. That is, the source region 5S and the drain region 5D and the channel region form a Schottky junction. The silicide layer 14 forming the Schottky contact layer for forming the source region 5S and the drain region 5D of the n-channel MOS transistor 21 is formed on the gate electrode 9 of the n-channel MOS transistor 21 and on the p-channel MOS transistor 22 are formed on the gate electrode 9 and near both sides of the gate electrode 9 of the p-channel MOS transistor 22, respectively. That is, in the p-channel MOS transistor 22, the silicide layer 14 is also formed above each of the high-concentration p-type impurity regions 15, and the source region 6S and the p-type drain region 6D are It is composed of a silicide layer 14.
Next, an interlayer insulating film 10 is formed. The interlayer insulating film 10 may be formed of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film of a combination thereof. The thickness of the interlayer insulating film 10 may be, for example, 200 to 600 nm, and is 400 nm in this embodiment (FIG. 4 (O)).
Next, a contact hole 11 is opened at a predetermined position of the interlayer insulating film 10. Next, a wiring layer 12 is formed inside the contact hole 11 and on the surface of the interlayer insulating film 10 and patterned into a predetermined shape. In the present embodiment, the wiring layer 12 is a laminated film having a three-layer structure in which a Ti film having a thickness of 100 nm, an Al film containing Ti having a thickness of 300 nm, and a Ti film having a thickness of 150 nm are continuously formed by a sputtering method.
Next, as a passivation film (not shown), a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed with a thickness of 50 to 500 nm (typically, 100 to 300 nm). Thereafter, when hydrogenation treatment was performed in this state, favorable results were obtained for improving the characteristics of the MOS transistor. Note that an opening may be formed in the passivation film at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.
Through the above steps, the CMOS 20 shown in FIG. 1 in which the junction of the source region 5S and the drain region 5D adjacent to the channel region of the n-channel MOS transistor is made to be a Schottky junction is completed (FIG. 4 (P)).
[0012]
Embodiment 2
In this embodiment, one of a source region and a drain region which is connected to a channel region of an n-channel MOS transistor has a Schottky junction.
The same steps as those in the first embodiment are denoted by the same reference numerals, and the repeated description thereof is omitted. That is, the steps from FIG. 2 to FIG. 3 (I) are the same as the steps from FIG. 5 to FIG. 6 (I).
Next, an embodiment in which only the source region 5S joined to the channel region of the n-channel MOS transistor is Schottky-joined will be described.
First, an n-channel MOS transistor is formed.
First, a pn junction between the drain region 5D of the n-channel MOS transistor and the channel region is formed. That is, in order to ion-implant impurities, for example, phosphorus (P) into the drain region 5D, the resist film 38 is selectively formed using the photolithography method. Using this resist film 38 as a mask, phosphorus (P) is ion-implanted to form a high-concentration n-type impurity region 39 (FIG. 6J). At this time, the concentration of phosphorus (P) is 1.5 × 10 ²⁰ ~ 3 × 10 ²¹ cm ^-3 Met.
{Circle around (1)} Next, heat treatment was performed to activate the impurity elements imparting n-type and p-type. This step can be performed by a method such as a furnace annealing method or a laser annealing method. In the present embodiment, the activation step is performed by the furnace annealing method. The heat treatment was performed in a nitrogen atmosphere at 300 to 650 ° C., here 550 ° C., for 4 hours. After that, the resist film 38 was removed.
(2) A silicon oxide film (SiO 2) is formed on the entire surface of the insulating ₂ The insulating layer 13 made of a film is formed to a thickness of 150 to 250 nm, for example, 200 nm (FIG. 6K). Next, a side wall insulating layer (side wall) 13 is formed on the step side surface of the gate electrode 9 by anisotropically etching the insulating layer (FIG. 6 (L)). At this time, the thickness of the sidewall insulating layer 13 in the substrate surface direction (lateral direction) was 80 nm. The order of (1) and (2) may be reversed.
Next, a Schottky junction for suppressing a kink current is formed. First, in order to form a Schottky contact layer on the entire surface of the insulating substrate 3, a material that is in Schottky contact with the semiconductor layer 4, for example, a material such as Er (erbium), Pt, Ni, Co, or Mo is used. A Schottky contact material layer 16 is formed by CVD, sputtering, or the like (FIG. 6M). In this embodiment, Er is formed to have a thickness of, for example, 50 nm in order to form an n-channel Schottky MOS transistor. Next, silicidation of the Er layer was performed by heat treatment (annealing) in vacuum at 400 ° C. for 300 minutes, for example. As a result, the Schottky contact material layer 16 in contact with the gate electrode 9 and the high-concentration p-type impurity region 15 reacts to be silicided, and a silicide layer 14 is formed (FIG. 7 (N)). Thereafter, unreacted Er is selectively removed by using dilute nitric acid at 60 ° C. to form a silicide layer (ErSi having a thickness of 40 nm). ₂ The source region 5S and the drain region 5D of the n-channel MOS transistor composed of the layer 14) were formed (FIG. 7 (O)). Thus, the Schottky contact type n-channel MOS transistor 21 is completed. That is, the Schottky junction is formed between the source region 5S and the channel region below the silicide layer 14 to be joined. The silicide layer 14 forming the Schottky contact layer for forming the source region 5S and the drain region 5D of the n-channel MOS transistor 21 is formed on the gate electrode 9 of the n-channel MOS transistor 21 and on the p-channel MOS transistor 22 are formed on the gate electrode 9 and near both sides of the gate electrode 9 of the n-channel MOS transistor 21 and the p-channel MOS transistor 22. That is, in the p-channel MOS transistor 22, the silicide layer 14 is also formed above each of the high-concentration p-type impurity regions 15, and the source region 6S and the p-type drain region 6D are It is composed of a silicide layer 14. Thus, a pn junction type p-channel MOS transistor 22 is completed.
Next, an interlayer insulating film 10 is formed on the surface. The interlayer insulating film 10 may be formed of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film of a combination thereof. The thickness of the interlayer insulating film 10 may be, for example, 200 to 600 nm, and is 400 nm in this embodiment (FIG. 7P).
Next, a contact hole 11 is opened at a predetermined position of the interlayer insulating film 10. Next, a wiring layer 12 is formed inside the contact hole 11 and on the surface of the interlayer insulating film 10 and patterned into a predetermined shape. In the present embodiment, the wiring layer 12 is a laminated film having a three-layer structure in which a Ti film having a thickness of 100 nm, an Al film containing Ti having a thickness of 300 nm, and a Ti film having a thickness of 150 nm are continuously formed by a sputtering method. 7 (Q)). Next, as a passivation film (not shown), a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed with a thickness of 50 to 500 nm (typically, 100 to 300 nm). Thereafter, when hydrogenation treatment was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect is obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.
In the second embodiment, the p-channel MOS transistor is formed before the step of forming the n-channel MOS transistor (FIG. 6I). However, the step of forming the pn junction of the n-channel MOS transistor is performed first. You may go to. In other words, the process of FIG. 6I and the process of FIG.
Through the above steps, the CMOS 20 in which the junction of the source region 5S adjacent to the channel region of the n-channel MOS transistor is made to be a Schottky junction is completed (FIG. 7 (Q)).
In the second embodiment, the Schottky junction is formed only in the source region 5S, but may be formed only in the drain region 5D.
[0013]
As described above, the CMOS of the above embodiment has the first semiconductor layer 4 (the semiconductor layer on the left side in FIG. 1) provided on the insulating substrate 3 as shown in FIGS. 4), a first gate insulating layer 8 provided on the first semiconductor layer 4 (the left gate insulating layer 8 in FIG. 1), and a first gate insulating layer 8 provided on the first gate insulating layer 8. A gate electrode 9 (the left gate electrode 9 in FIG. 1) and a first channel region 7 in the first semiconductor layer 4 located below the first gate electrode 9 (the left channel region 7 in FIG. 1). 1 of the first embodiment, and a first source region 5S and a drain region 5D each of which has only a Schottky contact layer in FIG. 7 (Q) of the second embodiment. Semiconductor device (n-channel MOS transistor 21) and second semiconductor layer 4 provided on insulating substrate 3 The first semiconductor layer 4 on the right side of FIG. 1, the second gate insulating layer 8 provided on the second semiconductor layer 4 (the right gate insulating layer 8 in FIG. 1), and the second gate insulating layer 8 The second gate electrode 9 provided on the upper side (the gate electrode 9 on the right side in FIG. 1) and the second channel region 7 in the second semiconductor layer 4 located below the second gate electrode 9 (FIG. And a second source region 6S and a drain region 6D including at least an impurity introduction layer in contact with the right channel region 7), and the polarity of the second channel region 7 is the same as that of the first channel region 7). And a second semiconductor device (p-channel MOS transistor 22) different from the above is provided on the same substrate.
In the above-described embodiment, the Schottky contact layer is formed of the silicide layer 14, and is formed on the first gate electrode 9, the second gate electrode 9, and the first gate electrode 9 and the second gate electrode 9. The structure has a silicide layer 14 near both sides.
Further, in the above embodiment, the first semiconductor device is the n-channel MOS transistor 21 and the second semiconductor device is the p-channel MOS transistor 22. Further, as shown in FIGS. 2A to 4P and FIGS. 5A to 7Q, the method of manufacturing the CMOS of the above-described embodiment A first step of providing a semiconductor layer 4 serving as a first semiconductor layer and a second semiconductor layer, and a gate insulating layer 8 serving as a first gate insulating layer and a second gate insulating layer on the semiconductor layer 4 A third step of providing a first gate electrode 9 and a second gate electrode 9 on the first gate insulating layer and the second gate insulating layer, respectively. Thereby, the fourth step of providing the second source region 6S and the drain region 6D formed of the impurity introduction layer (high-concentration p-type impurity region 15) and the first step of forming the Schottky contact layer (silicide layer 14) Fifth providing source region 5S and drain region 5D And a degree has a structure that (both Embodiment 1, the source region 5S and drain region 5D, form 2, the source region 5S only exemplary).
Further, in the CMOS 20 of the above embodiment, at least one of the source region 5S and the drain region 5D of the n-channel MOS transistor 21 forming the CMOS 20 is formed by the silicide layer 14 which is a Schottky contact layer, so that the substrate floating effect is reduced. Can be suppressed. Therefore, the kink current caused by the substrate floating can be suppressed, and the circuit operation can be stabilized.
In the above embodiment, only one n-channel MOS transistor 21 of the n-channel and p-channel MOS transistors 21 and 22 of the CMOS 20 is of the Schottky contact type. The ion implantation process for forming the MOS transistor 22 is performed only once, and two types of silicide layers of the n-channel type and the p-channel type do not have to be formed, so that the manufacturing process can be simplified.
Further, since it is not necessary to newly add a body contact terminal, the circuit can be made denser and the manufacturing process can be simplified without increasing the occupied area of the element or restricting the layout design.
Also in the p-channel MOS transistor 22, the silicide layer 14 is formed on each layer above the high-concentration p-type impurity region 15, and the contact resistance of the source region 6S and the drain region 6D can be reduced. A CMOS can be realized.
Further, according to the CMOS manufacturing method of the above embodiment, the CMOS 20 having the above effects can be easily manufactured by a simple manufacturing process.
[0014]
FIG. 8 shows a result of calculation by simulation of gate voltage dependence of drain characteristics of a MOS transistor having a pn junction type source / drain region.
That is, in the drain current characteristic curve diagram with respect to the drain voltage in FIG. 8, no sharp rise is seen in the current characteristic of the p-channel MOS transistor 22. On the other hand, the n-channel MOS transistor 21 has a characteristic in which an increase phenomenon in which the drain voltage sharply increases occurs (kink current). In the above embodiment, the junction between at least one of the source region 5S and the drain region 5D of the n-channel MOS transistor 21 in which the drain current increases rapidly and the channel region is a Schottky junction, so that the kink current of the CMOS 20 is reduced. Can be suppressed.
[0015]
Although the present invention has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.
For example, in the n-channel MOS transistor 21 shown in FIG. 1 of the first embodiment, the source region 5S or the drain region 5D made of a Schottky contact layer is formed in the first semiconductor layer 4 on both sides of the first gate electrode 9. However, as in the second embodiment, the first semiconductor layer 4 on one side of the first gate electrode 9 has a source region 5S (or a drain region 5D) formed of a Schottky contact layer. However, the first semiconductor layer 4 on the other side may be configured to have the drain region 5D (or the source region 5S) formed of the impurity-doped layer.
Further, in the above-described embodiment, a high-concentration polycrystalline silicon layer is used as a material of the gate electrode 9 and the silicide layer 14 is formed on that layer. However, a metal layer such as aluminum may be used. . In this case, no silicide layer 14 is formed on gate electrode 9.
Further, in the above embodiment, the control circuit of the liquid crystal display device has been described. However, a silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, III-V and II-VI Group compound semiconductor devices, III-V and II-VI compound semiconductor integrated circuit devices, silicon carbide semiconductor devices, silicon carbide semiconductor integrated circuit devices, polycrystalline or single crystalline diamond semiconductor devices, polycrystalline or single crystalline diamond Semiconductor integrated circuit device, liquid crystal display device, organic or inorganic electroluminescence (EL) display device, field emission display (FED) device, light emitting polymer display device, light emitting diode display device, CCD area / linear sensor device, CMOS or MOS sensor Device, is suitable for forming a complementary transistor circuit constituting the solar cell device for like.
[0016]
【The invention's effect】
As described above, according to the present invention, the floating effect of the substrate can be suppressed, and the kink current can be suppressed, so that the circuit operation can be stabilized. In addition, the circuit can be densified without increasing the area occupied by the elements or restricting the layout design, and the manufacturing process can be simplified. Further, it can be easily manufactured by a simple manufacturing process.
[Brief description of the drawings]
FIG. 1 is a sectional structural view of a CMOS using a thin film transistor according to Embodiment 1 of the present invention.
FIGS. 2A to 2G are cross-sectional structural views sequentially showing the manufacturing steps of the CMOS according to the first embodiment;
3 (H) to 3 (M) are cross-sectional structural views sequentially showing the manufacturing steps of the CMOS according to the first embodiment.
FIGS. 4 (N) to 4 (P) are cross-sectional structure diagrams sequentially showing the steps of manufacturing the CMOS according to the first embodiment.
FIGS. 5A to 5G are cross-sectional structural views sequentially illustrating the manufacturing steps of the CMOS according to the second embodiment;
6 (H) to 6 (M) are cross-sectional structural views sequentially showing the manufacturing steps of the CMOS according to the second embodiment.
FIGS. 7 (N) to 7 (Q) are cross-sectional structural views sequentially showing the steps of manufacturing the CMOS according to the second embodiment.
FIG. 8 is a diagram comparing drain characteristics of a CMOS transistor in which a Schottky contact is formed in a source / drain region and a MOS transistor having a pn junction type source / drain region.
FIG. 9 is a sectional view of a CMOS using a conventional thin film transistor.
10 (a) to 10 (g) are cross-sectional structural views sequentially showing manufacturing steps of the CMOS shown in FIG.
11 (h) to 11 (l) are cross-sectional structural views sequentially showing the manufacturing steps of the CMOS shown in FIG.
FIG. 12 is a schematic top view of a conventional MOS transistor having a body contact terminal.
[Explanation of symbols]
1 .... insulating substrate
2 ... Insulating layer
3. Insulating substrate
4 ... Semiconductor layer
5S: Source area
5D: drain region
6S: Source area
6D: Drain region
7 ... Channel area
8 ... Gate insulating layer
9 ... Gate electrode
10 ... interlayer insulating layer
11 ... Contact hole
12. Wiring layer
13 ... sidewall insulating film
14 ... Silicide layer
15: High concentration p-type impurity region
16: Schottky contact material layer
17 ... Resist film
19 ... conductive layer
20 ... CMOS
21 ... n-channel MOS transistor
22 ... p-channel MOS transistor
27 ... Resist film
37 ... Resist film
40 ... Amorphous semiconductor layer
45 ... n-type impurity
51 ... insulating substrate
52 ... insulating layer
53 ... insulating substrate
54 ... Semiconductor layer
55S ... n-type source region
55D: n-type drain region
56S ... p-type source region
56D: p-type drain region
57 ... Channel area
58 ... Gate insulating layer
59 ... Gate electrode
60 ... interlayer insulating layer
61 ... Contact hole
62: Wiring layer
70 ... CMOS
71 ... n-channel MOS transistor
72 ... p-channel MOS transistor
81 ... Active layer
82S: Source area
82D: Drain region
83 ... Channel area
84 gate electrode
85 ... Source electrode
86 ... Drain electrode
87… Body contact terminal
810: resist film
820: resist film
830: resist film
840: resist film
540... Amorphous semiconductor layer
550 ... n-type impurity
560: p-type impurity
590 ... conductive layer

Claims (4)

a p-channel MOS transistor having a source region and a drain region provided adjacent to the p-type channel region, and a gate electrode provided on the channel region via an insulating film;
A complementary semiconductor device comprising: a source region and a drain region provided adjacent to an n-type channel region; and an n-channel MOS transistor having a gate electrode provided on the channel region via an insulating film.
A complementary semiconductor wherein a junction between at least one of a source region and a drain region provided adjacent to an n-type channel region of the n-channel MOS transistor and the n-type channel region is a Schottky junction. apparatus. 2. The complementary semiconductor device according to claim 1, wherein at least one of a source region and a drain region provided adjacent to the n-type channel region is a silicide layer. In a manufacturing method for forming a complementary semiconductor device including an n-channel MOS transistor and a p-channel MOS transistor on a single substrate,
Forming first and second semiconductor layers for the n-type and p-channel type MOS transistors on the substrate at a distance;
Forming an insulator layer serving as a gate insulating film on the substrate and the first and second semiconductor layers;
Forming first and second gate electrodes on the first and second semiconductor layers of the insulator layer;
Forming a source region and a drain region in the second semiconductor layer for forming the p-channel MOS transistor;
Forming a Schottky junction in at least one of a predetermined source region and a predetermined drain region of the first semiconductor layer for forming the n-channel MOS transistor. Of manufacturing a semiconductor device. In a manufacturing method for forming a complementary semiconductor device including an n-channel MOS transistor and a p-channel MOS transistor on a single substrate,
When one of the source region and the drain region that is to be joined to the channel region of the n-channel MOS transistor is a Schottky junction and the other is a pn junction, the pn junction is located earlier than the Schottky junction A method for manufacturing a complementary semiconductor device, wherein the method is formed in a process.

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