JP2004273622A - Method for manufacturing connector substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a connector substrate made of a semiconductor substrate, where a passive element, such as a high dielectric capacitor, is incorporated and a conductor is filled into a through hole without generating any inconveniences. <P>SOLUTION: A method for manufacturing connector substrates comprises a process for forming the passive element Q on a first insulating film 12 on the semiconductor substrate 10, a process for forming a resist film 23 having an opening 23a at a hole formation section, a process for forming a hole 11 having an overhang section 12x in the first insulating film 12 by etching the first insulating film 12 and the semiconductor substrate 10 through the opening 23a of the resist film 23, a process for removing the overhang section 12x in the first insulating film 12 with the resist film 23 as a mask, a process for removing the resist film 23, a process for selectively forming a second insulating film on the inner surface of the hole 11, a process for filling a conductor into the hole 11, and a process for exposing one portion of the semiconductor by trimming the semiconductor substrate 10 from the rear side. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a connector board, and more particularly, to a method of manufacturing a connector board applicable to manufacture of an interposer incorporating a high dielectric capacitor.
[0002]
[Prior art]
In recent years, with further miniaturization and higher performance of electronic devices, system LSIs in which functions such as a memory, a CPU, and a logic circuit are integrated on one semiconductor chip are widely used. However, system LSIs have problems in terms of cost, development period, and the like.
[0003]
Therefore, a system package (SIP) has been developed in which individually manufactured components are housed in one package to realize performance close to that of a system LSI. In the system-in-package, a connector board called an interposer is used. Electronic components such as semiconductor chips are joined to the electrodes provided on one surface of the interposer, and connection terminals of the motherboard are joined to the electrodes provided on the other surface. The interposer is provided with a through-hole penetrating from one surface to the other surface, and the connection terminal on one surface and the connection terminal on the other surface are connected via a conductor embedded in the through-hole. And are electrically connected.
[0004]
By the way, some interposers are equipped with a chip capacitor for removing noise or the like of a power supply voltage. However, in this case, it is necessary to route wiring between the chip capacitor and the semiconductor chip, so that a relatively large inductance exists between these leads. Therefore, in a semiconductor chip having a high clock frequency, even if such a chip capacitor is provided, the effect of suppressing the fluctuation of the power supply voltage and reducing the high-frequency noise is small.
[0005]
Therefore, it has been proposed to create an interposer with a built-in capacitor (capacitor) and mount a semiconductor chip on the capacitor, thereby reducing the wiring distance between the semiconductor chip and the capacitor to reduce the inductance.
[0006]
In recent years, high dielectric materials such as BST have been used as dielectric films constituting capacitors. When the BST film is used as a high dielectric film of a capacitor, it is necessary to perform a heat treatment at a high temperature of 700 to 800 ° C. to crystallize the formed BST film. Therefore, a ceramic substrate or the like having high heat resistance is conventionally used as a substrate of the interposer. Such a ceramic substrate is obtained, for example, by forming a through hole in a viscous plate and then firing it. Then, a conductor is formed in the through hole.
[0007]
However, the ceramic substrate as described above has poor flatness of its surface (polished surface) and has unevenness from the surface to the upper surface of the conductor filled in the through-hole, so that a thin BST film is formed on the ceramic substrate. When formed, cracks and the like occur in the BST film, making it difficult to obtain a required BST film. As described above, it is difficult to form a high-performance capacitor circuit on a ceramic substrate with high yield.
[0008]
Further, since the ceramic substrate is formed by firing the viscosity plate having the through holes as described above, shrinkage occurs when firing. Moreover, since the shrinkage becomes non-uniform due to the localization of the binder contained in the viscosity plate, it is extremely difficult to control the firing shrinkage constant over the entire substrate.
[0009]
For this reason, when a ceramic substrate having a fine pitch through-hole is produced, the pitch of the through-hole may vary within the ceramic substrate and may deviate from the design allowance. In particular, when manufacturing a large number of interposers using a large-sized ceramic substrate, the manufacturing yield may be reduced and the manufacturing cost may be increased.
[0010]
Therefore, it has been proposed to use a silicon substrate having good surface flatness, easy microfabrication, and high production yield even when a large substrate is used, as a substrate of the interposer.
[0011]
Patent Documents 1 to 4 disclose forming a trench hole in a semiconductor substrate to form an element isolation region of a semiconductor device. However, Patent Documents 1 to 4 do not form a trench hole for filling a conductor in an interposer semiconductor substrate including a passive element such as a high dielectric capacitor, and do not suggest the present invention.
[0012]
[Patent Document 1]
JP-A-9-8118
[Patent Document 2]
JP-A-11-74340
[Patent Document 3]
JP-A-11-145273
[Patent Document 4]
JP 2001-44273 A
[0013]
[Problems to be solved by the invention]
When a silicon substrate is used as a substrate of an interposer, a method of forming a high dielectric capacitor on a silicon substrate in which a conductor is filled in advance in a trench hole is a method for forming a high dielectric film. As a result, cracks may occur in the high dielectric film and the production yield may be reduced.
[0014]
In order to avoid this problem, it is necessary to polish the surface of the silicon substrate in which the conductor is filled in the trench hole, for example, to polish the surface of the silicon substrate, thereby increasing the manufacturing cost.
[0015]
In the above-described method, the high dielectric film is heat-treated at a high temperature in a state where the conductor is filled in the trench holes of the silicon substrate. Therefore, problems such as cracking of the conductor due to thermal expansion due to the thermal expansion coefficient due to the difference in thermal expansion coefficient between the silicon substrate and the conductor and oxidative expansion and sintering shrinkage of the conductor are apt to occur, and the circuit including the capacitor has a good yield. It becomes difficult to form.
[0016]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has no problems with a connector board including a semiconductor substrate having a built-in passive element such as a high dielectric capacitor and having a through hole filled with a conductor. It is an object of the present invention to provide a method of manufacturing a connector board which can be manufactured without occurrence of a problem.
[0017]
[Means for Solving the Problems]
In order to solve the above problems, the present invention relates to a method for manufacturing a connector substrate, comprising: forming a passive element formed of a thin film on a first insulating film of a semiconductor substrate having the first insulating film; Forming a resist film having an opening in a hole forming portion on the first insulating film on the passive element and the first insulating film; and forming the first insulating film and the semiconductor through the opening in the resist film. A step of forming a hole having an eave portion formed by placing an opening of the first insulating film inside a trench hole of the semiconductor substrate by etching the substrate, and using the resist film as a mask, Removing the eaves of the first insulating film; removing the resist film; selectively forming a second insulating film on the inner surface of the hole; and a conductor connected to the passive element. Into the hole A step of Hama, by cutting the semiconductor substrate from the back side, characterized by a step of exposing a portion of the conductor.
[0018]
In the present invention, first, after a passive element (such as a high dielectric capacitor) is formed on a flat semiconductor substrate via a first insulating film, a resist having an opening in a hole forming portion on the first insulating film is formed. A film is formed. Thereafter, the first insulating film and the semiconductor substrate are etched through the opening of the resist film to form a hole. At this time, the hole is formed in a state where the opening of the first insulating film includes an eave portion formed by being arranged inside the trench hole of the semiconductor substrate.
[0019]
Then, using the resist film as it is as a mask, the eaves of the hole are removed by wet or dry etching or the like. After that, the resist film is removed.
[0020]
Subsequently, after the conductor to be connected to the passive element is formed by being buried in the hole, the semiconductor substrate is scraped from the back side, and a part of the conductor is exposed to the back side of the semiconductor substrate, and the connection terminal is formed. Become.
[0021]
According to the present invention, a passive element (high-dielectric capacitor) formed of a thin film via a first insulating film is formed on a flat semiconductor substrate before forming a hole and a conductor filling the hole in the semiconductor substrate. Etc.) are formed. That is, since the passive element is formed without being affected by surface irregularities due to holes in the semiconductor substrate, cracks and the like are not generated in the thin film of the passive element, and the manufacturing yield of the passive element is improved.
[0022]
In addition, in the step of removing the eaves of the first insulating film, the resist film used for forming the holes is used as a mask as it is, so that a special step of patterning the resist film needs to be added. This eliminates the problem of increased manufacturing costs.
[0023]
In addition, since the holes and the conductor formed in the semiconductor substrate are formed after the passive element is formed on the semiconductor substrate, the conductor is high when a passive element such as a high dielectric capacitor is formed. The dielectric film is not affected by heat when heat-treated at a high temperature. Therefore, the problem that defects occur due to the heat treatment of the conductor at a high temperature is solved, and the production yield of the connector substrate can be improved.
[0024]
In a preferred aspect of the present invention, in the step of forming the hole, the opening of the resist film may be retracted outward to a position where the upper surface of the eaves is exposed.
[0025]
In the above-described invention, since the trench hole of the semiconductor substrate is formed by side-etching outward from the opening of the resist film, after removing the eaves of the first insulating film (before removing the resist), the result is as follows. Then, the resist film blocks the vicinity of the inner wall of the trench hole.
[0026]
For this reason, when the inner surface of the hole is wet-cleaned after the eaves portion of the first insulating film is etched (before removing the resist), especially when the aspect ratio of the hole becomes large, poor circulation of the cleaning liquid occurs due to the effect of the resist film. It is assumed that etching residues caused by reaction products and the like attached to the inner surface of the hole cannot be removed.
[0027]
However, in the present invention, after the resist film is retreated to a position where the upper surface of the eave portion of the first insulating film is exposed, the eave portion is removed, so that the resist film closes the hole (trench hole). Disappears.
[0028]
Therefore, when the wet cleaning is performed after removing the eaves of the first insulating film (before removing the resist), the cleaning liquid is circulated and supplied over the entire hole, so that the etching residue adhering to the inner surface of the hole is removed. Can be easily removed.
[0029]
Further, since the upper surface of the eave portion of the first insulating film is exposed by retreating the resist film, the eave portion of the first insulating film is selectively removed from the semiconductor substrate by anisotropic dry etching or the like. become able to. In this case, when the eaves of the first insulating film are removed, the etching residue in the hole of the semiconductor substrate is simultaneously dry-cleaned, so that the etching residue is further reduced and generation of particles can be suppressed.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0031]
Before describing an embodiment of the present invention, problems in a method of forming a hole in a silicon substrate after forming a circuit including a capacitor on a silicon substrate serving as an interposer will be described. FIG. 9 is a cross-sectional view showing a defect in forming a trench hole in a silicon substrate.
[0032]
As shown in FIG. 9A, first, an insulating film 102 is formed on a silicon substrate 100, and a resist film 104 having an opening 104a for forming a hole is formed on the insulating film 102. Be prepared. Although not specified, a high-dielectric capacitor (not shown) having a structure in which a high-dielectric film such as a BST film is already sandwiched between an upper electrode and a lower electrode is provided at a predetermined portion on the silicon substrate 100. ) Is formed.
[0033]
Thereafter, as shown in FIG. 9B, using the resist film 104 as a mask, the insulating film 102 and the silicon substrate 100 exposed in the opening 104a are sequentially etched by RIE to form a trench hole 100a. At this time, the trench hole 100a is side-etched outside the opening of the insulating film 104 due to a sharp increase in the etching rate when the etching of the insulating film 102 is completed and the etching of the silicon substrate 100 is proceeded. It is formed in the state where it was.
[0034]
Subsequently, as shown in FIG. 9C, the resist film 104 is removed. At this time, the eaves portion 102a of the insulating film 102 projects toward the inside of the trench hole 100a.
[0035]
Next, an insulating film and a seed metal film are sequentially formed on the inner surface of the trench hole 100a, and a conductor is formed to be embedded in the trench hole by electrolytic plating using the seed metal film as a plating power supply layer. At this time, if the eaves 102a of the insulating film 102 protrude into the trench holes 100a as shown in FIG. 9C, the eaves 102a become shaded when forming the seed metal film by the sputtering method. The seed metal film is not formed on the side surface of the trench hole 100a immediately below, and the seed metal film is disconnected in the trench hole 100a.
[0036]
When a conductor is buried in the trench hole 100a by electrolytic plating, the seed metal film is used as a plating power supply image. Therefore, if there is a broken portion in the seed metal film, voids or the like are generated in the trench hole 100a. As a result, it becomes difficult to reliably bury the conductor in the trench hole 100a.
[0037]
Moreover, the step coverage of the insulating film formed on the inner surface of the trench hole 100a is also poor, so that there remains a problem that the reliability of electrical insulation between the conductor and the silicon substrate is poor.
[0038]
As a first method for preventing the eaves 102a of the insulating film 102 from remaining, the resist film 104 is removed after the insulating film 102 is etched, and the resist film having an opening smaller than the opening of the insulating film 102 is formed again. Is formed on the silicon substrate 100 and then the silicon substrate 100 is etched. Since the resist film used when etching the silicon substrate 100 is disposed inside the opening of the insulating film 102 by an amount corresponding to the side etching of the silicon substrate 100, the side surface of the trench hole is formed in the opening of the insulating film 102. As a result, the eaves 102a of the insulating film 102 no longer remain.
[0039]
Further, as a second method, the insulating film 102 and the silicon substrate 100 are sequentially etched using the resist film 104 as a mask, and after removing the resist film 104, a resist having an opening for exposing the eaves portion 102a is again formed. There is a method of forming a film and selectively removing the eaves 102a.
[0040]
However, in the above-described first or second method, it is necessary to pattern the resist film twice in the step of forming the trench hole 100a, which causes an increase in manufacturing cost.
[0041]
Embodiments of the present invention described below can solve the above-described problems.
[0042]
(First Embodiment)
1 to 5 are sectional views sequentially showing a method for manufacturing a connector board according to the first embodiment of the present invention. As shown in FIG. 1A, in the method for manufacturing a connector board according to the first embodiment, first, a silicon substrate 10 (semiconductor substrate) having a thickness of, for example, about 625 μm is prepared, and a film thickness of 500 nm is formed on the silicon substrate 10. The first insulating film 12 is formed to a degree. As the first insulating film 12, a silicon oxide film, a PSG (Phospho-Silicate Glass) film, a silicon nitride film, a titanium nitride (TiN) film, or the like is used.
[0043]
After that, desired passive elements are formed on the silicon substrate 10. In the present embodiment, a high dielectric capacitor is formed as a passive element. More specifically, as shown in FIG. 1B, first, a Pt (platinum) film is formed on the first insulating film 12 by sputtering to form a first conductive film 14a. Next, after a BST-based sol-gel is applied on the first conductive film 14a to form a BST film, the BST film is heat-treated in an oxygen atmosphere at a temperature of 800 ° C. to form a high dielectric film 16a. Subsequently, a Pt film is formed on the high dielectric film 16a by sputtering to form a second conductive film 18a.
[0044]
Next, as shown in FIG. 1C, the second conductive film 18a, the high dielectric film 16a, and the first conductive film 14a are sequentially patterned into a predetermined shape, so that the lower electrode 14, the capacitor A capacitor Q composed of the dielectric film 16 and the upper electrode 18 is formed.
[0045]
In the present embodiment, since the capacitor Q is formed before the hole is formed in the silicon substrate 10, a high-dielectric film having required film characteristics on the silicon substrate 10 having high flatness as a whole has no problem. Are formed without generation. Thus, a high-performance capacitor Q can be easily obtained.
[0046]
In addition, in the present embodiment, as described later, after the capacitor Q is formed, the hole in the silicon substrate 10 is filled with a conductor. Therefore, when the above-described BST film is heat-treated at a high temperature to form the high dielectric film 16a, there is no possibility that a defect or the like due to contraction or expansion of the conductor filled in the hole of the silicon substrate 10 occurs. .
[0047]
After that, as shown in FIG. 2A, a photosensitive polyimide film or the like is patterned on the capacitor Q and the first insulating film 12 to have a contact hole 20a communicating with the lower electrode 14 and the upper electrode 18 of the capacitor Q. An interlayer insulating film 20 is formed. At this time, the interlayer insulating film 20 is simultaneously patterned so that the opening 20b is also formed in the hole forming portion above the silicon substrate 10.
[0048]
Next, a Cr (chromium) film and a Cu (copper) film are sequentially formed on the entire upper surface of the silicon substrate 10 by sputtering to form a seed film (not shown). Subsequently, a metal film (not shown) such as a Cu film is formed on the seed film by electrolytic plating using the seed film as a plating power supply layer.
[0049]
Thereafter, the wirings 22a, 22b, and 22c are formed by patterning the metal film by photolithography. Wiring 22a is connected to upper electrode 18 of capacitor Q via contact hole 20a, and wiring 22b is connected to lower electrode 14 of capacitor Q via contact hole 20a. At this time, other wirings 22c and the like are formed at the same time. Although the embodiment in which the wirings 22a, 22b, and 22c are formed by a subtractive method has been illustrated, the wirings 22a, 22b, and 22c may be formed by a semi-additive method or a full-additive method.
[0050]
Next, as shown in FIG. 2B, a resist film 23 having an opening 23a having a diameter of, for example, about 50 μm on the first insulating film 12 in the opening 20b of the interlayer insulating film 20 is formed as shown in FIG. Formed on the structure. After that, as shown in FIG. 2C, the first insulating film (silicon oxide film) 12 is formed through, for example, C through the opening 23a of the resist film 23. ₄ F ₈ And SF ₆ The opening 12a is formed in the first insulating film 12 by etching by RIE or the like using a mixed gas of
[0051]
Subsequently, using the resist film 23 as a mask, the silicon substrate 10 is, for example, SF ₆ Is etched by RIE or the like to form a trench hole 10a having a depth of, for example, about 150 μm. As a result, a hole 11 composed of the opening 12a of the first insulating film 12 and the trench hole 10a of the silicon substrate 10 is obtained.
[0052]
The first insulating film 12 and the silicon substrate 10 are etched under various etching conditions using a combination of gases selected from the group consisting of a gas containing a fluorine atom, a chlorine atom or a bromine atom, a hydrogen gas, an oxygen gas, and an inert gas. be able to.
[0053]
At this time, as described above, when the etching rate is sharply increased when the etching is transferred from the first insulating film 12 to the silicon substrate 10, as shown in FIG. The ten trench holes 10 a are formed in a state where the trench holes 10 a are side-etched outward from the openings 12 a of the first insulating film 12.
[0054]
That is, the portion of the first insulating film 12 near the opening 12a becomes the eaves 12x protruding inside the trench hole 10a of the silicon substrate 10. As described above, the hole 11 is formed in a state having the eaves 12x formed by disposing the opening 12a of the first insulating film 12 inside the trench hole 10a of the silicon substrate 10.
[0055]
In addition, as a method of etching the first insulating film 12 and the silicon substrate 10, there is a method such as wet etching, ion milling, or sandblasting in addition to dry etching such as RIE. Further, the etching may be performed by combining these methods.
[0056]
Next, as shown in FIG. 3A, the first insulating film (silicon oxide film) 12 is formed using buffered hydrofluoric acid (BHF (HF: 7%)) using the resist film 23 as a mask as it is. Is laterally etched from the side surface exposed to the opening 12a to remove the eaves 12x of the first insulating film 12.
[0057]
When a PSG film is used as the first insulating film 12, side etching can be similarly performed using BHF. When a silicon nitride film or a TiN film is used as the first insulating film 12, the eaves 12x are removed by ion milling using argon (Ar). That is, when the hole 11 is formed in the silicon substrate 10, a part of the resist film 23 is etched by RIE, and the opening 23 becomes tapered (FIG. 2C). The lower edge of the opening 23a and the eaves 12x of the first insulating film 12 are selectively etched.
[0058]
At this time, the bottom of the silicon substrate 10 is also etched at the same time. However, since ion milling has a characteristic that the etching rate decreases as it goes below the hole 11, the disadvantage that the bottom of the silicon substrate 10 is etched in large amounts. Does not occur.
[0059]
As described above, in the present embodiment, the resist film 23 used when forming the trench hole 10a is also used as a mask for removing the eaves 12x of the first insulating film 12. For this reason, it is not necessary to add a special step of forming a resist film in order to remove the eaves 12x of the first insulating film 12, so that the problem that the manufacturing cost is increased is solved.
[0060]
Although FIG. 3A illustrates an example in which the opening 12a of the first insulating film 12 is disposed outside the trench hole 10a, the opening 12a of the first insulating film 12 is formed in the trench hole 10a. It may be arranged at a corresponding position. That is, the amount of side etching of the first insulating film 12 is not particularly limited, and the eaves 12x of the first insulating film 12 may be removed to such an extent that no trouble occurs in a later step.
[0061]
Subsequently, after removing the resist film 23, as shown in FIG. 3B, a second insulating film 24 such as a silicon oxide film is formed on the entire upper surface of the silicon substrate 10 by CVD. The second insulating film 24 is provided to electrically insulate the silicon substrate 10 from a conductor to be filled in the trench hole 10a later. At this time, since the eaves portion 12x of the first insulating film 12 does not exist in the hole 11, the second insulating film 24 is formed on the inner surface of the hole 11 with good step coverage.
[0062]
Next, as shown in FIG. 3B, a dry film resist film 26 covering the portion where the hole 11 is formed and the periphery thereof is patterned on the second insulating film 24. Subsequently, the second insulating film 24 is wet-etched using the dry film resist film 26 as a mask. Thus, as shown in FIG. 3C, the second insulating film 24 is selectively left on the inner surface of the hole 11 and the periphery thereof, and the wirings 22a, 22b, and 22c are exposed.
[0063]
After that, the dry film resist film 26 is removed. At this time, it is preferable to adopt a method of removing the dry film resist film 26 by swelling it so that no peeling residue is generated in the hole 11.
[0064]
Next, as shown in FIG. 4A, a Cr film and a Cu film are sequentially formed on the structure shown in FIG. At this time, since the eaves portion 12x of the first insulating film 12 does not exist in the hole 11, the seed film 28 is formed as a continuous film without disconnection. Subsequently, as shown in FIG. 4B, a resist film 30 having the hole 11 and an opening 30a exposing the hole 11 and its periphery is formed.
[0065]
Thereafter, as shown in FIG. 4C, the Cu film pattern 32 is filled in the holes 11 and the openings 30a of the resist film 30 by electrolytic plating using the seed film 28 as a plating power supply layer. At this time, since the seed film 28 is formed as a continuous film without disconnection in the trench hole 10a, the Cu film pattern 32 is stably embedded in the hole 11 without generating a void.
[0066]
Next, as shown in FIG. 5A, after the resist film 30 is removed, the seed film 28 is etched using the Cu film pattern 32 as a mask until the interlayer insulating film 20 is exposed. Thereby, as shown in FIG. 5B, a conductor 34 including the seed film 28 and the Cu film pattern 32 is obtained. At this time, the wirings 22a, 22b, 22c are electrically separated.
[0067]
In this embodiment, the capacitor Q formed by the heat treatment at a high temperature is already formed before the conductor 34 is formed. Therefore, since the conductor 34 is not subjected to a high-temperature heat treatment in a later step, there is no possibility that a defect or the like due to contraction or expansion of the conductor 34 due to the heat treatment occurs. As a result, the defect rate in the production of the connector substrate is reduced, so that the production yield is improved and the production cost is reduced.
[0068]
Subsequently, the back surface of the silicon substrate 10 (the surface on which the capacitor Q is not formed) is mechanically polished, and the polishing is finished at a position 20 to 30 μm before the bottom of the hole 11. Thereafter, the back surface of the silicon substrate 10 is wet-etched to expose the second insulating film 24 at the bottom of the hole 11. Further, the conductor 34 in the hole 11 is exposed by plasma etching the second insulating film 24 exposed on the back surface of the silicon substrate 10.
[0069]
As a result, as shown in FIG. 5C, the hole 11 becomes a through hole 11a penetrating from the element formation surface of the silicon substrate 10 to the back surface.
[0070]
Thus, the surface of the conductor 34 exposed on the back surface of the silicon substrate 10 becomes the connection terminal 34a, and is connected to the connection pad of the wiring board (mother board). The connection terminal 34a of the conductor 34 is electrically connected to the lower electrode 14 of the capacitor Q via the conductor 34 filled in the through hole 11a and the wiring 22b.
[0071]
Thereafter, a cover insulating film 36 made of polyimide or the like having an opening 36a for exposing the conductor 34 is formed on the back surface of the silicon substrate 10 by printing or the like. Alternatively, the cover insulating film 36 may be formed by attaching an insulating sheet provided with an opening to the back surface of the silicon substrate 10. Alternatively, when a solder resist film is formed on the wiring board on which the connector board is mounted, the cover insulating film 36 may be omitted.
[0072]
As described above, the connector board 1 manufactured by the method for manufacturing a connector board according to the first embodiment of the present invention is obtained.
[0073]
In the method of manufacturing the connector board according to the present embodiment, first, before filling the hole 11 of the silicon substrate 10 with the conductor 34, the capacitor having the high dielectric film 16 on the silicon substrate 10 with the first insulating film 12 interposed therebetween. Q is formed. As described above, since the capacitor Q is formed on the silicon substrate 10 having high flatness, the capacitor Q having the high dielectric film 16 having required film characteristics is formed. Moreover, since the silicon substrate 10 does not need to be polished and flattened, the manufacturing process is simplified as compared with the related art.
[0074]
Thereafter, a resist film 23 having an opening 23a in a hole forming portion on the first insulating film 12 is formed. Next, using the resist film 23 as a mask, the first insulating film 12 and the silicon substrate 10 are sequentially etched to form the holes 11. At this time, an eave portion 12x is formed in the first insulating film 12 in the hole 11. Subsequently, the eave portion 12x of the first insulating film 12 is removed by side etching while the resist film 23 is left.
[0075]
As described above, in the present embodiment, the resist film 23 for forming the hole 11 is also used as a mask for removing the eaves 12x of the first insulating film 12 as it is. For this reason, since the step of patterning the resist film in order to remove the eaves portion 12x is not added, the problem that the manufacturing cost is increased is solved.
[0076]
Subsequently, after the second insulating film 24 is selectively formed on the inner surface of the hole 11 and the periphery thereof, the hole 11 is filled with a conductor 34 electrically connected to the capacitor Q. Next, the back surface of the silicon substrate 10 is shaved, and the connection terminals 34 a on the lower surface of the conductor 34 are exposed on the back surface of the silicon substrate 10. Thereafter, a cover insulating film 36 having an opening 36a from which the connection terminal 34a of the conductor 34 is exposed is formed.
[0077]
As a result, the connection terminal 34a of the conductor portion 34 exposed on the back surface of the silicon substrate 10 is electrically connected to the capacitor Q on the element formation surface of the silicon substrate 10 via the through hole 11a.
[0078]
As described above, in the present embodiment, after the capacitor Q is formed above the silicon substrate 10, the hole 11 a and the conductor 34 filling the hole 11 a are formed in the silicon substrate 10. It is not affected by high-temperature heat treatment when forming the capacitor Q. For this reason, the problem that defects occur due to the heat treatment of the conductor 34 at a high temperature is solved, so that the production yield of the connector substrate can be improved.
[0079]
Further, since the step of forming the holes 10a and the like in the silicon substrate 10 is performed by photolithography and a thin film process, even when a large-area silicon substrate is used, unlike the case where a ceramic substrate is used, the holes 10a are formed. The variation in pitch within the wafer is reduced, and the holes 10a are formed with high accuracy.
[0080]
From the above, a connector substrate applied to a SIP substrate typified by an interposer having a built-in passive element can be easily manufactured at low cost and with high yield.
[0081]
(Second embodiment)
6 and 7 are cross-sectional views illustrating a method of manufacturing the connector board according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that, after forming a trench hole 10a in the silicon substrate 10 using the resist film 23 as a mask, the opening 23a of the resist film 23 is receded outward to form a first insulating film. The object of the present invention is to remove the eaves 12x while exposing the upper surface of the 12 eaves 12x. In the second embodiment, detailed description of the same steps as in the first embodiment will be omitted.
[0082]
In the above-described first embodiment, as shown in FIGS. 2C and 3A, the trench hole 10a of the silicon substrate 10 is formed by side-etching outward from the opening 23a of the resist film 23. Therefore, as a result, the resist film 23 blocks the vicinity of the outer periphery of the trench hole 10a. For this reason, especially when the aspect ratio of the trench hole 10a is increased, in the cleaning step performed after the eaves portion 12x is etched (before removing the resist), poor circulation of the cleaning liquid occurs and the inner surface of the trench hole 10a can be sufficiently cleaned. May disappear. As a result, it is impossible to remove etching residues caused by reaction products and the like attached to the inner surface of the trench hole, which may cause particles to be generated. The second embodiment can avoid such a problem from occurring.
[0083]
As shown in FIG. 6A, the method for manufacturing the connector board according to the second embodiment firstly uses the same method as that of the first embodiment and uses the resist film 23 as a mask as in FIG. (1) The insulating film 12 and the silicon substrate 10 are etched to form the holes 11, and the resist film 23 is left.
[0084]
After that, as shown in FIG. 6B, the structure of FIG. 6A is heated in a clean oven at a temperature of 130 ° C. for 20 minutes to soften the resist film 23, so that the side surface of the opening 23a is removed. It is further inclined outward to form a tapered shape. As the resist film 23 having such characteristics, a thermoplastic resist material or the like is used.
[0085]
Then, oxygen (O ₂ ) Or O ₂ By etching the entire surface of the resist film 23 by dry etching (RIE or the like) using a gas containing, the lower portion of the opening 23a of the resist film 23 is receded outward, for example, by about 5 μm. Thus, as shown in FIG. 6C, the opening 23a of the resist film 23 is disposed outside the outer periphery of the trench hole 10a, and the upper surface of the eaves 12x of the first insulating film 12 is exposed. Become.
[0086]
In addition, as a method of retreating the opening 23a by dry-etching the resist film 23, anisotropic etching may be used, or isotropic etching may be used. Further, ion milling may be used instead of dry etching.
[0087]
Subsequently, the eaves 12x of the first insulating film 12 (silicon oxide film or PSG film) are removed by wet etching with buffered hydrofluoric acid using the resist film 23 in which the opening 23a is receded as a mask.
[0088]
By doing so, as shown in FIG. 7A, the resist film 23 does not block the vicinity of the outer periphery of the trench hole 10a, so that the cleaning solution is contained in the hole 11a during cleaning after removing the eaves 12x. Will be sufficiently circulated and supplied. Therefore, the problem that the etching residue remains in the hole 11a is eliminated.
[0089]
Thereafter, the structure shown in FIG. 7B is obtained by removing the resist film 23.
[0090]
Subsequently, as in the first embodiment, the step of forming the second insulating film 24 in the trench hole (FIG. 3B) and the step of forming the cover insulating film 36 on the back surface of the silicon substrate 10 (FIG. 5 ( By performing the steps up to c)), the connector board 1 having the same structure as that of FIG. 5C is obtained.
[0091]
The second embodiment has the same effect as the first embodiment. In addition, the resist film 23 for forming the hole 11 does not block the vicinity of the outer periphery of the trench hole 10a, so that the etching residue attached to the inner surface of the hole 11 can be easily removed with a cleaning liquid. Thus, the production yield can be improved.
[0092]
(Third embodiment)
FIG. 8 is a cross-sectional view illustrating the method for manufacturing the connector board according to the third embodiment of the present invention. The third embodiment differs from the second embodiment in that the eaves 12x of the first insulating film 12 are removed by dry etching instead of wet etching. In the third embodiment, detailed description of the same steps as those in the first and second embodiments will be omitted.
[0093]
In the method of manufacturing the connector board according to the third embodiment, as shown in FIG. 8A, a structure similar to that of FIG. 6C is formed by a method similar to that of the second embodiment. That is, after the hole 11 is formed in the silicon substrate 10, the opening 23 a of the resist film 23 is retracted outward to expose the upper surface of the eave portion 12 x of the first insulating film 12.
[0094]
Thereafter, as shown in FIG. ₄ F ₈ And O ₂ Then, the eaves 12x of the first insulating film (silicon oxide film or PSG film) 12 are anisotropically etched using the resist film 23 as a mask. Thus, as shown in FIG. 8B, the first insulating film 12 is faithfully etched into the resist film 23 without being side-etched from the opening 23a of the resist film 23, and the eaves 12x are removed.
[0095]
Under such etching conditions, since the etching selectivity (etch rate of the silicon oxide film (PSG film) / etch rate of the silicon substrate) is high, the eaves 12x are selectively etched with respect to the silicon substrate 10. The etching gas is not limited to the above-described example, and any etching gas can be used as long as a similar selection ratio can be obtained.
[0096]
As the dry etching apparatus, various dry etching apparatuses such as an ICP (Inductive Coupled Plasma) type, a TCP (Transfer Coupled Plasma) type, and a parallel plate type can be used.
[0097]
In the above-described first or second embodiment, when the aspect ratio (depth / diameter) of the hole 11 of the silicon substrate 10 is relatively high (for example, 1 or more), it is caused by a reaction product attached to the inner surface of the hole 11. It is assumed that the etching residue cannot be completely removed.
[0098]
However, in the third embodiment, the eave portions 12x of the first insulating film 12 are etched using dry etching, so that the etching residues attached in the trench holes 10a are removed by cleaning with dry etching plasma. You. For this reason, even when the aspect ratio of the trench hole 10a is high, the generation of particles due to the etching residue can be suppressed, and the manufacturing yield can be improved.
[0099]
In addition, although the suitable etching method of the eaves portion 12x when the silicon oxide film or the PSG film is used as the first insulating film 12 has been described, ion milling or sandblasting may be used instead of dry etching, or these may be used. The methods may be combined.
[0100]
Further, as the first insulating film 12, a silicon nitride film or a TiN film can be used in addition to the silicon oxide film and the PSG film. When a silicon nitride film or a TiN film is used as the first insulating film 12, the eaves 12x are etched by ion milling using Ar. At this time, as described in the first embodiment, since the ion milling has a characteristic that the etching rate decreases as it goes below the hole 11, a problem that the bottom of the silicon substrate 10 is etched in large quantities occurs. do not do.
[0101]
Further, since the ion milling is performed in a state where the upper surface of the eaves portion 12x of the first insulating film 12 is exposed, the eaves portion 12x can be removed more stably than in the first embodiment.
[0102]
After etching the eaves 12x of the first insulating film 12 as described above, the resist film 20 is removed, whereby the structure shown in FIG. 8C is obtained.
[0103]
Next, as in the first embodiment, the step of forming the second insulating film 24 on the inner surface of the hole 11 (FIG. 3B) and the step of forming the cover insulating film 36 on the back surface of the silicon substrate 10 (FIG. By performing the steps up to c)), the connector board 1 having the same structure as that of FIG. 5C is obtained.
[0104]
The third embodiment has the same effects as the first and second embodiments. In addition, in the third embodiment, the eaves 12x of the first insulating film 12 are removed by dry etching, so that even when the aspect ratio of the trench hole 10a is high, etching residues are simultaneously removed. Thus, generation of particles can be suppressed.
[0105]
(Supplementary Note 1) A step of forming a passive element formed of a thin film on the first insulating film of the semiconductor substrate having the first insulating film;
Forming a resist film having an opening in a hole forming portion on the first insulating film on the passive element and the first insulating film;
The first insulating film and the semiconductor substrate are etched through the opening of the resist film, so that the opening of the first insulating film includes an eave portion formed inside the trench hole of the semiconductor substrate. Forming a hole;
Removing the eaves of the first insulating film using the resist film as a mask;
Removing the resist film;
Selectively forming a second insulating film on the inner surface of the hole;
Filling a conductor connected to the passive element into the hole;
Exposing a portion of the conductor by shaving the semiconductor substrate from the back side.
[0106]
(Supplementary Note 2) The method for manufacturing a connector board according to Supplementary Note 1, wherein in the step of removing the eaves of the first insulating film, the eaves is side-etched by wet etching.
[0107]
(Supplementary Note 3) After the step of forming the hole, and before the step of removing the eaves of the first insulating film, the opening of the resist film is formed to a position where the upper surface of the eaves is exposed. 3. The method of manufacturing a connector board according to claim 1, further comprising the step of retreating the connector board.
[0108]
(Supplementary Note 4) The step of retracting the opening of the resist film outward to a position where the upper surface of the eaves is exposed includes:
A step of inclining the side surface of the opening of the resist film outward by heat-treating the resist film;
A step of etching a part of the resist film in a thickness direction to retreat an opening of the resist film outward to a position where an upper surface of the eaves is exposed. Manufacturing method of connector board.
[0109]
(Supplementary note 5) The connector substrate according to any one of Supplementary notes 1 to 3, wherein in the step of removing the eaves portion, the eaves portion is removed by wet etching, dry etching, ion milling, or sandblasting. Manufacturing method.
[0110]
(Supplementary Note 6) The device according to any one of claims 1 to 3, wherein the first insulating film is any one selected from the group consisting of a silicon oxide film, a PSG film, a silicon nitride film, and titanium nitride. A manufacturing method of the connector board described in the above.
[0111]
(Supplementary Note 7) The method of manufacturing a connector board according to Supplementary Note 4, wherein the resist film is made of a thermoplastic material.
[0112]
(Supplementary Note 8) The connector board according to Supplementary Note 4, wherein in the step of etching the resist film and retreating the opening, dry etching using a gas containing oxygen atoms or ion milling is used. Production method.
[0113]
(Supplementary Note 9) In the step of forming the hole, the first insulating film and the semiconductor substrate are etched by any one of dry etching, wet etching, ion milling, and sandblasting, or a combination thereof. 9. The method for manufacturing a connector board according to any one of supplementary notes 1 to 8, wherein
[0114]
(Supplementary note 10) In the step of removing the eaves of the first insulating film, when the aspect ratio of the hole is 1 or more, the dry etching or the ion milling is used. A manufacturing method of the connector board described in the above.
[0115]
【The invention's effect】
As described above, according to the present invention, a passive element composed of a thin film is formed on a flat semiconductor substrate with a first insulating film interposed therebetween. As a result, the manufacturing yield of passive elements is improved.
[0116]
In addition, since the resist film for forming the holes in the semiconductor substrate is also used as a mask for removing the eaves of the first insulating film as it is, there is no need to add a special step of patterning the resist film. The problem of increased manufacturing costs is solved.
[0117]
In addition, the conductor filled in the hole of the semiconductor substrate is formed after the passive element is formed on the semiconductor substrate. Therefore, when a passive element such as a high dielectric capacitor is formed, the conductor is high. The dielectric film is not affected by heat when heat-treated at a high temperature. This solves the problem that defects occur due to the heat treatment of the conductor at a high temperature, so that the production yield of the connector substrate can be improved.
[Brief description of the drawings]
FIG. 1 is a sectional view (part 1) illustrating a method for manufacturing a connector board according to a first embodiment of the present invention.
FIG. 2 is a sectional view (part 2) illustrating the method for manufacturing the connector board of the first embodiment of the present invention.
FIG. 3 is a sectional view (part 3) illustrating the method for manufacturing the connector board of the first embodiment of the present invention.
FIG. 4 is a sectional view (part 4) illustrating the method for manufacturing the connector board of the first embodiment of the present invention.
FIG. 5 is a sectional view (part 5) illustrating the method for manufacturing the connector board of the first embodiment of the present invention.
FIG. 6 is a sectional view (No. 1) illustrating the method for manufacturing the connector board according to the second embodiment of the present invention.
FIG. 7 is a sectional view (part 2) illustrating the method for manufacturing the connector board of the second embodiment of the present invention.
FIG. 8 is a sectional view illustrating a method for manufacturing a connector board according to a third embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a defect in forming a trench hole in a silicon substrate.
[Explanation of symbols]
Reference Signs List 10: silicon substrate (semiconductor substrate), 10a: trench hole, 11: hole, 11a: through hole, 12: first insulating film, 12x: eaves portion, 14a: first conductive film, 14: lower electrode, 16a: high Dielectric film, 16: High dielectric film for capacitors, 18a: Second conductive film, 18: Upper electrode, 20: Interlayer insulating film, 20a: Contact hole, 12a, 20b, 23a, 30a, 36a: Opening, 22a , 22b, 22c ... wiring, 23, 30 ... resist film, 24 ... second insulating film, 26 ... dry film resist film, 28 ... seed film, 32 ... Cu film pattern, 34 ... conductor part, 34a ... connection terminal, 36 ... cover insulating film.

Claims (5)

Forming a passive element composed of a thin film on the first insulating film of the semiconductor substrate having the first insulating film;
Forming a resist film having an opening in a hole forming portion on the first insulating film on the passive element and the first insulating film;
The first insulating film and the semiconductor substrate are etched through the opening of the resist film, so that the opening of the first insulating film includes an eave portion formed inside the trench hole of the semiconductor substrate. Forming a hole;
Removing the eaves of the first insulating film using the resist film as a mask;
Removing the resist film;
Selectively forming a second insulating film on the inner surface of the hole;
Filling a conductor connected to the passive element into the hole;
Exposing a portion of the conductor by shaving the semiconductor substrate from the back side. After the step of forming the hole, and before the step of removing the eaves of the first insulating film, the step of retracting the opening of the resist film outward to a position where the upper surface of the eaves is exposed. The method for manufacturing a connector board according to claim 1, comprising: The step of retracting the opening of the resist film outward to a position where the upper surface of the eaves is exposed,
A step of inclining the side surface of the opening of the resist film outward by heat-treating the resist film;
Etching a part of the resist film in the thickness direction to retreat an opening of the resist film outward to a position where an upper surface of the eaves is exposed, wherein A manufacturing method of the connector board described in the above. The method for manufacturing a connector board according to any one of claims 1 to 3, wherein in the step of removing the eaves portion, the eaves portion is removed by wet etching, dry etching, ion milling, or sandblasting. . The connector substrate according to any one of claims 1 to 4, wherein the first insulating film is any one selected from the group consisting of a silicon oxide film, a PSG film, a silicon nitride film, and titanium nitride. Manufacturing method.

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