JP2004265071A - Semiconductor integrated circuit, and its layout design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a slew rate without changing a netlist in layout design of a semiconductor integrated circuit including a network with many branches. <P>SOLUTION: The layout design method is provided with a step S2 of inputting the netlist including a first circuit outputting a signal and a plurality of second circuits operating on the basis of the signal outputted from the first circuit, a step S 3 of carrying out automatic arrangement and wiring of a circuit included in the netlist so that an output terminal of the first circuit is connected to an input terminal of the second circuit by wiring having at least one branch point on the basis of the netlist, and a step S4 of respectively inserting a plurality of buffer circuits within a predetermined distance from any one of the branch points between at least one branch point and the input terminals of the plurality of second circuits. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a layout design method for a semiconductor integrated circuit, and more particularly to a layout design method for a semiconductor integrated circuit such as a gate array, an embedded array, and a standard cell designed using various cells in accordance with specifications of a supplier. About the method. Further, the present invention relates to a semiconductor integrated circuit manufactured using such a layout design method.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a layout design of a semiconductor integrated circuit including a network having many branches, in order to improve a slew rate, one or a plurality of buffer circuits are provided at an output side of a transmitting circuit driving a network having branches. Insertion was done. FIG. 5 shows a layout of such a conventional semiconductor integrated circuit.
[0003]
As shown in FIG. 5, two buffer circuits 22 and 23 are connected in series to the output of the transmission side circuit 1, and the wiring connected to the output terminal of the buffer circuit 23 branches to form the reception side circuit 2. ~ 5. However, even if a plurality of buffer circuits are connected in series as described above, the buffer circuit 23 at the subsequent stage is connected to the four receiving circuits 2 to 5 via long wires, so that the stray capacitance of the wiring and the receiving circuit Therefore, it is difficult to improve the slew rate.
[0004]
Meanwhile, Patent Document 1 below discloses a clock supply circuit having a configuration capable of easily reducing clock skew, and a layout method thereof. The clock supply circuit includes a first buffer element having an input terminal connected to a clock signal source terminal, and a second buffer element having an output terminal connected to a clock input terminal of a flip-flop. The output terminal of the element and the input terminal of the second buffer element are connected without branch and via the third buffer element. However, this layout method is not aimed at improving the slew rate, and in order to perform such a layout design, it is necessary to change the netlist used in the automatic placement and routing tool. It takes.
[0005]
[Patent Document 1]
JP-A-11-111850 (page 1-2, FIG. 1)
[0006]
[Problems to be solved by the invention]
In view of the above, an object of the present invention is to improve the slew rate without changing the netlist in the layout design of a semiconductor integrated circuit including a circuit network with many branches. Another object of the present invention is to provide a semiconductor integrated circuit manufactured using such a layout design method.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, a layout design method according to the present invention is a method for designing a layout of a semiconductor integrated circuit using a computer, wherein a first circuit for outputting a signal and an output from the first circuit are provided. (A) inputting a netlist including a plurality of second circuits operating based on a signal to be input to the computer to the first circuit by wiring having at least one branch point based on the netlist. (B) automatically arranging and wiring the circuits included in the netlist so that the output terminals are connected to the input terminals of the plurality of second circuits; And (c) inserting a plurality of buffer circuits within a predetermined distance from any of the branch points between the input terminals of the circuit.
[0008]
Here, step (c) is a step of inserting a plurality of buffer circuits between at least one branch point and an input terminal of the plurality of second circuits, respectively, Moving the positions of the plurality of buffer circuits so as to approach.
[0009]
In addition, a semiconductor integrated circuit according to the present invention includes a first circuit that outputs a signal, a wiring that has at least one branch point that branches a signal output from the first circuit to a plurality of paths, A plurality of buffer circuits electrically connected to the plurality of paths, respectively; a plurality of buffer circuits disposed within a predetermined distance from any branch point; and a plurality of buffer circuits from the first circuit. And a plurality of second circuits that operate based on the signals output through the first and second circuits, respectively.
[0010]
According to the present invention configured as described above, a layout of a semiconductor integrated circuit including a first circuit that outputs a signal and a plurality of second circuits that operate based on the signal output from the first circuit In the design, after the circuit is automatically arranged and routed based on the netlist, a predetermined distance from any one of the branch points is provided between at least one branch point and the input terminals of the plurality of second circuits. By inserting a plurality of buffer circuits into each of these, the slew rate can be improved without changing the netlist.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a flowchart showing a layout design method of a semiconductor integrated circuit according to one embodiment of the present invention.
First, in step S1, a circuit design of a semiconductor integrated circuit is performed, and a net list is created. Here, it is assumed that the layout of the semiconductor integrated circuit as shown in FIG. 2 is designed. FIG. 2 does not include a buffer circuit.
[0012]
As shown in FIG. 2, the semiconductor integrated circuit includes a transmitting circuit 1 that outputs a signal, and a plurality of receiving circuits 2 to 5 that operate based on the signal output from the transmitting circuit 1. . Here, the output terminal of the transmission side circuit 1 is connected to the input terminals of the reception side circuits 2 to 5 by wiring having three branch points N1 to N3 near the output terminal of the transmission side circuit 1.
[0013]
The netlist includes information on a plurality of cells for forming the transmission-side circuit and the reception-side circuit in the semiconductor device, and information on wiring between these cells.
[0014]
Referring again to FIG. 1, in step S2, the created netlist is input to the computer. Next, in step S3, initial placement and wiring of cells are performed based on the netlist by using an automatic placement and routing tool operating on a computer.
[0015]
In step S4, a plurality of buffer circuits are inserted between the branch points N1 to N3 and the input terminals of the receiving circuits 2 to 5, respectively. For example, as shown in FIG. 3, buffer circuits 12 to 15 are respectively inserted before input terminals of the receiving circuits 2 to 5.
[0016]
Next, in step S5 in FIG. 1, the positions of the buffer circuits 12 to 15 are moved such that the buffer circuits 12 to 15 approach any branch point. Thereby, as shown in FIG. 4, the buffer circuits 12 and 14 are arranged within a predetermined distance from the branch point N2, and the buffer circuits 13 and 15 are arranged within a predetermined distance from the branch point N3.
[0017]
According to the present embodiment, the wiring is branched near the output terminal of the transmission side circuit 1 and the branched wiring is immediately input to the buffer circuits 12 to 15, so that the wiring is connected to the output terminal of the transmission side circuit 1. Even if the stray capacitance of the wiring is small and the number of branches is large, the slew rate of the transmission side circuit 1 does not deteriorate much. On the other hand, although the distance between the buffer circuits 12 to 15 and the receiving circuits 2 to 5 is long, only one receiving circuit is connected to one buffer circuit. There is not much rate degradation. As a result, the slew rate can be improved.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a layout design method according to an embodiment of the present invention.
FIG. 2 is a diagram showing a semiconductor integrated circuit whose layout is to be designed.
FIG. 3 is a diagram showing a state where a buffer circuit is inserted into the circuit of FIG. 2;
FIG. 4 is a diagram showing a state where a buffer circuit has been moved in the circuit of FIG. 3;
FIG. 5 is a diagram showing a layout of a conventional semiconductor integrated circuit.
[Explanation of symbols]
1 transmitting circuit, 2-5 receiving circuit, 12-15 buffer circuit, N1-N3 branch point

Claims (3)

A method of designing a layout of a semiconductor integrated circuit using a computer,
(A) inputting a netlist including a first circuit that outputs a signal and a plurality of second circuits that operate based on the signal output from the first circuit to a computer;
Based on the netlist, the output terminal of the first circuit is included in the netlist such that the output terminal of the first circuit is connected to the input terminals of the plurality of second circuits by a wiring having at least one branch point. (B) performing automatic circuit arrangement and wiring;
(C) inserting a plurality of buffer circuits within a predetermined distance from any of the branch points between the at least one branch point and the input terminals of the plurality of second circuits;
Layout design method comprising: Step (c)
Inserting a plurality of buffer circuits between the at least one branch point and the input terminals of the plurality of second circuits, respectively;
Moving the positions of the plurality of buffer circuits so that the plurality of buffer circuits approach the at least one branch point;
2. The layout design method according to claim 1, comprising: A semiconductor integrated circuit,
A first circuit for outputting a signal,
A wiring having at least one branch point for branching a signal output from the first circuit into a plurality of paths;
A plurality of buffer circuits electrically connected to the plurality of branched paths, respectively, the plurality of buffer circuits disposed within a predetermined distance from any branch point,
A plurality of second circuits that operate based on signals output from the first circuit via the plurality of buffer circuits, respectively;
A semiconductor integrated circuit comprising:

Images