JP2004260464A - Voltage comparator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage comparator capable of a high-speed operation with less erroneous comparisons and hysteresis. <P>SOLUTION: The voltage comparator comprises: MOS transistors 2 and 3, a resistance element 8 and a resistance element 9 constituting a differential amplifier circuit; MOS transistors 6 and 7 for positively feeding back and amplifying a differential voltage; MOS transistors 4, 5, 10 and 11 for switching for switching a positive feedback amplification operation and a differential amplification operation; a first voltage control means connected to a node C provided between the MOS transistors 6 and 7 and the MOS transistors 10 and 11 for switching for suppressing the voltage rise of the node C at the time of starting a positive feedback operation; a second voltage control means for suppressing the voltage rise of the node C during a differential amplification operation period; a MOS transistor 19 provided between output parts; and a third voltage control means for temporarily conducting the MOS transistor 19 for connection during the differential amplification operation. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a voltage comparator used in an A / D converter and the like.
[0002]
[Prior art]
In recent years, with progress in miniaturization of semiconductor processes, integration of a system into one chip and an increase in signal processing speed have been progressing. Along with this, filters for A / D converters, D / A converters, etc., which perform mutual conversion between analog signals and digital signals at the front end and back end of the system, also increase the speed of signal processing and the handling of signals to be handled. Wide band is important. In particular, in an A / D converter, it is important to speed up the operation of a voltage comparator which is a main component thereof.
[0003]
Hereinafter, a conventional voltage comparator will be described.
[0004]
FIG. 3 is a circuit diagram showing a configuration of a conventional voltage comparator.
[0005]
As shown in the figure, the conventional voltage comparator has a source connected to the ground voltage V. _SS And an N-channel MOS transistor 101 having a gate to which a bias voltage Vb1 is applied so as to function as a constant current source, and a source commonly connected to the drain of the N-channel MOS transistor 101, and a gate to be compared with each other. N-channel MOS transistor 102 and N-channel MOS transistor 103 for converting and amplifying a differential voltage between Vinp and Vinn into a differential current, and a source. Are connected to the drain of the N-channel MOS transistor 102, the gate is supplied with the first control voltage Vc1 and the source is connected to the drain of the N-channel MOS transistor 103, and the gate is connected to the N-channel MOS transistor 103. 1 control voltage Vc1 is input An N-channel MOS transistor 105 and a source whose source is connected to the drain of the N-channel MOS transistor 102 and whose gate receives a second control voltage Vc2, which is a complementary (opposite phase) signal of the first control voltage Vc1. A channel type MOS transistor 110, an N-channel type MOS transistor 111 having a source connected to the drain of the N-channel type MOS transistor 103 and a gate to which the second control voltage Vc2 is input, and a source having an N-channel type MOS transistor 110 An N-channel MOS transistor 107 connected to the drain, a source connected to the drain of the N-channel MOS transistor 111, a drain connected to the gate of the N-channel MOS transistor 107, and a gate connected to the drain of the N-channel MOS transistor 107 An N-channel type MOS transistor 106 connected respectively one end connected to the drain of N-channel type MOS transistor 104 and N-channel MOS transistor 107, the power supply voltage V to the other end _DD Is connected to the drain of the N-channel MOS transistor 105 and the N-channel MOS transistor 106, and the other end is connected to the power supply voltage V. _DD And a resistance element 109 to which is applied. Here, the resistance values of the resistance element 108 and the resistance element 109 are the same. The N-channel MOS transistor 102 forms a cascode connection with the N-channel MOS transistors 104 and 110, respectively, and the N-channel MOS transistor 103 forms a cascode connection with the N-channel MOS transistors 105 and 111, respectively. I have. It should be noted that, in this specification, “out-of-phase” means that the polarity and change of the signal are opposite, and “in-phase” means that the polarity and change of the signal are the same. .
[0006]
In the conventional voltage comparator, assuming that a connection point between the drain of the N-channel MOS transistor 104 and the resistance element 108 is a node A, the node A is a second output unit that outputs a second output voltage Voutn, and an N-channel type. It is connected to the drain of the MOS transistor 107 and the gate of the N-channel MOS transistor 106, respectively. Similarly, assuming that a connection point between the drain of the N-channel MOS transistor 105 and the resistance element 109 is a node B, this node B is a first output unit for outputting a first output voltage Voutp, an N-channel MOS transistor The drain 106 is connected to the gate of the N-channel MOS transistor 107.
[0007]
A connection point between the N-channel MOS transistor 110 and the N-channel MOS transistor 107 and a connection point between the N-channel MOS transistor 111 and the N-channel MOS transistor 106 are connected to each other. The connection portion is hereinafter referred to as a node C.
[0008]
A common connection point between the N-channel MOS transistor 102, the N-channel MOS transistor 104, and the N-channel MOS transistor 110 is called a node D, and the N-channel MOS transistor 103, the N-channel MOS transistor 105, and the N-channel MOS transistor The common connection point of the transistors 111 is referred to as a node E.
[0009]
The operation of the voltage comparator configured as described above will be described below with reference to the drawings.
[0010]
FIG. 4A shows the state transition of the first control voltage Vc1 and the second control voltage Vc2 in the conventional voltage comparator and the on / off states of the N-channel MOS transistors 104, 105, 110, and 111. It is an operation timing chart. FIG. 4B is a timing chart showing changes in the first input voltage Vinp and the second input voltage Vinn. FIG. 4C shows changes in the first output voltage Voutp and the second output voltage Voutn. FIG. 6 is a timing chart showing changes in a voltage of a node C (node voltage Vc), a voltage of a node D (node voltage Vd), and a voltage of a node E (node voltage Ve). The voltage change at each node shown in FIG. 4 (c) corresponds to the change in the input voltage shown in FIG. 4 (b).
[0011]
As shown in FIG. 4A, the first control voltage Vc1 and the second control voltage Vc2 are clock signals having phases opposite to each other, and the control voltage Vc is Vc. _DD Control voltage V _SS , The voltage comparator enters the “comparison mode” and the control voltage Vc _SS Control voltage V _DD , The voltage comparator is in the “latch mode”. The latch mode and the comparison mode are alternately repeated at predetermined time intervals. In the A / D converter, a plurality of voltage comparators are arranged in parallel. Each conventional voltage comparator amplifies the difference between two input voltages. Then, the output voltage from the voltage comparator is converted to a digital signal level of “0” or “1” by a dynamic latch circuit arranged at a subsequent stage. Here, the reason why the voltage comparator is not directly connected to the digital circuit is that the output voltage on the low potential side is the logical level V on the low potential side of the digital circuit. _SS (Ground voltage).
[0012]
A more detailed circuit operation of the conventional voltage comparator will be described below with reference to FIGS.
[0013]
First, in the “comparison mode”, the N-channel MOS transistors 104 and 105 are both turned on, and the N-channel MOS transistors 110 and 111 are both turned off. Therefore, the current generated by the N-channel MOS transistor 101, which is the current source, flows through the resistance elements 108 and 109, and then passes through the N-channel MOS transistors 104 and 102 or the N-channel MOS transistors 105 and 103 to the node A. -Between node D and between node B and node E. At this time, the current does not constantly flow through the N-channel MOS transistors 106 and 107. That is, in the “comparison mode”, the N-channel MOS transistors 101, 102, 103, 104, and 105 and the resistance elements 108 and 109 form a differential amplifier circuit, and the first input voltage Vinp and the second input voltage The voltage difference from Vinn is differentially amplified at a predetermined ratio, and the first output voltage Voutp and the second output voltage Voutn are output. At this time, the node C sets the N-channel MOS transistor 106 or the N-channel MOS transistor 107 from the maximum voltage at which either the first output voltage Voutp or the second output voltage Voutn has reached during the “comparison mode”. Is charged with a voltage value lower by the threshold voltage of the upper limit as an upper limit. Therefore, the voltage value at the node C becomes higher than the voltage values at the nodes D and E.
[0014]
Next, in the “latch mode”, both the N-channel MOS transistors 104 and 105 are off, and both the N-channel MOS transistors 110 and 111 are on. Therefore, no current flows between the node A and the node D and between the node B and the node E through the N-channel MOS transistors 104 and 105, and flows through the N-channel MOS transistors 106, 107, 110 and 111 and the node C. A current path is formed.
[0015]
As shown in FIG. 4C, in the “comparison mode” immediately before the state transitions from the “comparison mode” to the “latch mode”, for example, when the magnitude relation of the input voltages is Vinp> Vinn, these input voltages are The output voltage is differentially amplified at a predetermined ratio, and the output voltage also satisfies Voutp> Voutn.
[0016]
Next, the mode is switched to the “latch mode”, and when the N-channel MOS transistors 110 and 111 transition from the off state to the on state, the voltage of the node C, which has been higher than the voltage applied to the nodes D and E, decreases. Thus, the N-channel MOS transistors 106 and 107 also transition to the ON state. At this time, Voutp becomes the gate voltage of the N-channel MOS transistor 107, and Voutn becomes the gate voltage of the N-channel MOS transistor 106. Therefore, the drain current of the N-channel MOS transistor 107 becomes It becomes larger than the current. Therefore, the second output voltage Voutn, which is the drain voltage of the N-channel MOS transistor 107, further decreases, while the first output voltage Voutp, which is the drain voltage of the N-channel MOS transistor 107, further increases. In other words, Voutp = V due to an interaction (positive feedback or latch) in which an increase in Voutp promotes a decrease in Voutn and a decrease in Voutn promotes an increase in Voutp. _DD , Voutn = V _DD −I × R converges. Here, I is the current value of the current flowing through the N-channel MOS transistor 101 serving as a current source, and R is the resistance value of the resistance element 108 and the resistance element 109.
[0017]
If Vinp <Vinn immediately before the start of the “latch mode”, Voutp = V _DD −I × R, Voutn = V _DD It converges to. That is, the N-channel MOS transistors 106 and 107 function as positive feedback amplifiers that amplify the voltage difference between Voutp and Voutn at the start of the “latch mode” to a value of I × R.
[0018]
As described above, the conventional voltage comparator performs the differential amplification of the first input voltage Vinp and the second input voltage Vinn in the comparison mode, and further expands the voltage difference between the differential amplification voltages in the latch mode following the comparison mode. Let me V _DD Or V _DD A voltage comparison operation of outputting any one of -IR as the output voltages Voutp and Voutn is performed.
[0019]
[Non-patent document 1]
Rudy J. Van De Placeche, An 8-bit 100-MHz Full-Nyquist Analog-to-Digital Converter, IEEE JOURNAL OF SOLID-STATE CURTI. 23, no. 6, December 1988, p. 1340
[Non-patent document 2]
G. FIG. W. Benes (GW Venes), An 80-MHz, 80-mW, 8-b CMOS Folding A / D Converter with Distributed Track-and Hold Preprocessing, IEEE JOURNAL OF SOLID. 31, No. 12, December 1996, p. 1852
[0020]
[Problems to be solved by the invention]
In the conventional voltage comparator, the second control voltage Vc2 is V _SS To V _DD When the N-channel MOS transistors 110 and 111 change from the off state to the on state, the voltage change of the second control voltage Vc2 is changed to the N-channel type. The voltage is transmitted to the node C via the parasitic capacitance of the MOS transistors 110 and 111, and the voltage of the node C is transiently pushed up to the high potential side. Therefore, in the conventional voltage comparator, it takes time for the N-channel MOS transistors 106 and 107 to transition from the off state to the on state and to start the positive feedback operation (latch operation). For example, as shown in FIG. 4C, the voltage difference between the output voltages at the end of the latch mode 1 has not reached the value of I × R.
[0021]
Further, at the time of transition from the “latch mode” to the “comparison mode”, the second control voltage Vc2 is _DD To V _SS When the N-channel MOS transistors 110 and 111 change from the ON state to the OFF state, the voltage change of the second control voltage Vc2 is changed to the node via the parasitic capacitance of the N-channel MOS transistors 110 and 111. C, and the voltage is transiently lowered to the lower potential side. Therefore, in the conventional voltage comparator, even after the start of the differential amplification operation, the N-channel MOS transistors 106 and 107 are turned on, and the current continues to flow to the node C. Error voltage was generated, and as a result, there was a possibility of erroneous comparison.
[0022]
Hereinafter, these phenomena will be described a little more with reference to FIGS. 4 (b) and 4 (c).
[0023]
First, at the end of the "comparison mode 1", when the voltage difference between the input voltages Vinp and Vinn is about sub to about 1 mV and is almost the minimum as the input voltage difference of the voltage comparator, the first output voltage Voutp and the second output The voltage Voutn is V _DD With -IR / 2 as the common mode voltage, the voltage value is obtained by amplifying the input voltage by a predetermined ratio.
[0024]
The node voltage Vc is V _DD And the upper limit is a voltage value near the voltage obtained by subtracting the threshold voltages of the N-channel MOS transistors 106 and 107 from the above. I × R is usually set to about 0.3 to 0.5V. When I × R is 0.5 V, the power supply voltage V _DD Is 3.0V, V _DD −I × R is 2.5 V, and each of the node voltages Vc, Vd, and Ve is ideally V _DD A voltage obtained by subtracting about 1 V from the gate-source voltage Vgs of each of the N-channel MOS transistors 104, 105, 106, and 107, that is, about 2.0 V is the upper limit.
[0025]
Next, when the state transits from the “comparison mode 1” to the “latch mode 1”, the first control voltage Vc1 becomes V _DD To V _SS And both the N-channel MOS transistors 104 and 105 transition from the on state to the off state, and the second control voltage Vc2 becomes V _SS To V _DD And both the N-channel MOS transistors 110 and 111 transition from the off state to the on state. Subsequently, when the N-channel MOS transistors 110 and 111 are turned on, the node C conducts with the nodes D and E, so that the node voltages Vc, Vd, and Ve become substantially the same during the latch mode period.
[0026]
In the conventional voltage comparator, when switching from the comparison mode to the latch mode, the change in the second control voltage Vc2 is transmitted to the node C via the parasitic capacitance of the N-channel MOS transistors 110 and 111, and the node voltage is changed. A phenomenon occurs that Vc is pushed up to the high potential side. Therefore, when the node voltage Vc immediately after the start of the latch mode is a voltage sufficient to turn off the N-channel MOS transistors 106 and 107, the positive feedback amplification is not started. During this time, a voltage is applied to the nodes A and B via the resistance elements 108 and 109, so that the voltage values of Voutp and Voutn increase.
[0027]
Thereafter, the voltages of the node voltages Vc, Vd, and Ve are reduced by the current flowing through the N-channel MOS transistor 101 functioning as a current source, so that the N-channel MOS transistors 106 and 107 are gradually turned on and become positive. The feedback operation is started (point α in FIG. 4C). Then, Voutp and Voutn are amplified by positive feedback, and _DD , V _DD −I × R converges.
[0028]
As described above, the conventional voltage comparator has a disadvantage that it takes time from the time of switching to the latch mode to the time when the positive feedback operation is actually started. Further, in the conventional voltage comparator, since the start of the positive feedback operation is delayed, the voltage difference between the first output voltage Voutp and the second output voltage Voutn may not reach I × R at the end of the latch mode. there were. For this reason, in the conventional voltage comparator, when the comparison result is converted into a digital signal level through a dynamic latch circuit connected downstream of the voltage comparator, the conversion of the signal level in the dynamic latch circuit is performed. There is a possibility that the normal comparison is not performed and the probability of occurrence of erroneous comparison increases.
[0029]
Next, when the state transits from the “latch mode 1” to the “comparison mode 2”, the first control voltage Vc1 becomes V _SS To V _DD , The N-channel MOS transistors 104 and 105 transition from the off state to the on state, and the second control voltage Vc2 becomes V _DD To V _SS , The N-channel MOS transistors 110 and 111 transition from the on state to the off state, and function as a differential amplifier for differentially amplifying the input voltage.
[0030]
As shown in FIG. 4B, when the input voltage difference between the input voltages Vinp and Vinn is larger than the dynamic range of the differential amplification (Vinn> Vinp), the output voltages Voutp and Voutn are at the end of this mode. Has V _DD -Converge to IxR, VDD. At this time, the node voltages Vc, Vd, and Ve converge to the voltage values as described in the description of the “comparison mode 1”. The mechanism of the transient voltage response will be described later.
[0031]
When the state transits from the “comparison mode 2” to the “latch mode 2”, the first output voltage Voutp, the second output voltage Voutn, and the node voltages Vc, d, and e transition by the mechanism described in the description of the “latch mode 1”. After the initial voltage change, the voltage converges to a predetermined voltage value, and the first output voltage Voutp and the second output voltage Voutn become V _DD −I × R, V _DD It becomes. In the “latch mode 2”, the difference between the output voltages at the end of the “comparison mode 2” is almost I × R. Therefore, unlike the “latch mode 1”, the first output voltage Voutp is V _DD −R × I, the second output voltage Voutn is V _DD , Respectively.
[0032]
Next, when the mode transits from the “latch mode 2” to the “comparison mode 3”, the N-channel MOS transistors 110 and 111 are turned off, and the N-channel MOS transistors 104 and 105 are turned on sufficiently. Power supply voltage V in the voltage comparator during the transient period of _DD And ground voltage V _SS The current path between them becomes narrower. Then, the first output voltage Voutp, the second output voltage Voutn, and the node voltage Vc become V _DD , And the node voltages Vd and Ve are pulled down by the N-channel MOS transistor 101 functioning as a current source and transition to the low potential side.
[0033]
Subsequently, when the N-channel MOS transistors 104 and 105 are sufficiently turned on, both the node A and the node D and the node B and the node E are turned on, and the node voltages Vd and Ve are set to the high potential side. The node voltage Vc transitions to the low voltage side. After this, the conventional voltage comparator gradually begins to function as a differential amplifier.
[0034]
As described above, in the conventional voltage comparator, when the voltage difference between the two input voltages is as small as in the “comparison mode 1”, it takes much time to converge to the original differential amplification result. I was Therefore, as shown in FIG. 4B, if the time of the “comparison mode” is not sufficiently long compared to the start of the differential amplification operation, the first output voltage Voutp and the second output voltage Voutn become the original differential amplification. The transition to the next "latch mode 3" is made before the result is completely converged, resulting in an erroneous comparison (see the point β in FIG. 2C).
[0035]
Further, in the conventional voltage comparator, the second control voltage Vc2 is V _DD To V _SS When the N-channel MOS transistors 110 and 111 change from the ON state to the OFF state, the voltage change of the second control voltage Vc2 is changed to the node via the parasitic capacitance of the N-channel MOS transistors 110 and 111. It is transmitted to C. Then, immediately after switching to the comparison mode 3, the voltage of the node C is temporarily lowered to the low potential side, and even after the differential amplification operation is started, the N-channel MOS transistors 106 and 107 are turned on, and the node C is turned on. The current continues to flow toward (point γ in FIG. 4C). Therefore, if the gate-source voltages of the N-channel MOS transistors 106 and 107 do not become close to the threshold voltages before the start of the next latch mode, error voltages are generated in the output voltages Voutp and Voutn, and Erroneous comparisons may occur in the digitalization process.
[0036]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems of the conventional voltage comparator, and to provide a voltage comparator which is unlikely to cause erroneous comparison and can operate at high speed when transitioning from a comparison mode to a latch mode. I do.
[0037]
[Means for Solving the Problems]
The first voltage comparator of the present invention includes a first MIS transistor and a second MIS transistor of a first conductivity type, both of which form a differential pair, and the first MIS transistor and the second MIS transistor, respectively. A differential amplifier circuit having a first resistance element and a second resistance element connected thereto and configured to receive a differential input voltage and generate a differential voltage; A third MIS transistor of a first conductivity type connected to the first MIS transistor and a second source / drain region connected to the first resistance element; and a first source / drain region connected to the second MIS transistor. The MIS transistor has a gate at the second source / drain region of the third MIS transistor, and a second source / drain region at the gate and the third terminal of the third MIS transistor. And a fourth MIS transistor of the first conductivity type respectively connected to the first and second resistance elements. The first source / drain regions of the third MIS transistor and the fourth MIS transistor are commonly connected, and A latch circuit for positive feedback amplification or latching of a differential voltage is provided between the first MIS transistor and the first resistance element, and is turned on in a first period by a first signal. A first conduction type first MIS transistor for switching, which is controlled to be in a non-conducting state during a second period, and the second MIS transistor and the second resistance element, A second MIS transistor for a first conductivity type, which is controlled by the first signal to be conductive during the first period and non-conductive during the second period; One MIS transistor and the third MIS transistor are interposed between the first MIS transistor and the third MIS transistor. The second MIS transistor is in a conductive state in the second period by a second signal having a phase opposite to that of the first signal. A third switch MIS transistor of a first conductivity type controlled to be in a non-conductive state, and a second control signal interposed between the second MIS transistor and the fourth MIS transistor; A fourth conductive MIS transistor of a first conductivity type, which is turned on during the second period and is turned off during the first period, and During the transition to the period or during the transition from the second period to the first period, the voltage of the first source / drain region of the third MIS transistor and the fourth MIS transistor is increased First voltage control means for changing the polarity of the second signal to a polarity opposite to that of the second signal is provided.
[0038]
With this configuration, at the time of transition from the first period in which differential amplification of the differential input voltage is performed to the second period in which positive feedback amplification or latching of the differential voltage is performed, or from the second period to the first period During the transition to the period, the voltage of the second signal transmitted to the first source / drain regions of the third MIS transistor and the fourth MIS transistor via the third and fourth switching MIS transistors The effect of the change can be suppressed. Therefore, in the first voltage comparator of the present invention, the positive feedback or the start of the latch operation is started at the transition from the first period to the second period, and the difference is started at the transition from the second period to the first period. Since the start of the dynamic amplification operation is performed promptly, occurrence of erroneous comparison is suppressed, and high-speed operation becomes possible as compared with the conventional comparator.
[0039]
The first voltage control means has one end connected to the first source / drain region of the third MIS transistor and the fourth MIS transistor, and the other end connected to the other end of the first MIS transistor having a phase opposite to that of the second signal. 3 is the first capacitor to which the signal of No. 3 is applied, so that at the time of transition from the first period to the second period and at the time of transition from the second period to the first period, the second signal is The third signal having the opposite phase is transmitted to the first source / drain regions of the third MIS transistor and the fourth MIS transistor via the first capacitor. As a result, voltage fluctuations due to the second signal are suppressed, erroneous comparison is suppressed, and high-speed operation is enabled.
[0040]
During the first period, the voltage between the gate and the first source / drain region of the third MIS transistor and the fourth MIS transistor is substantially changed by the third MIS transistor and the fourth MIS transistor. The second voltage control means for setting the threshold voltage of the third and fourth MIS transistors to a "deep off state" after the start of the first period. Before the start of the second period, the voltage between the gate and the first source / drain region can be set close to the threshold value, so that a positive voltage is applied during the transition from the first period to the second period. The feedback or latch operation can be started quickly.
[0041]
The second voltage control means includes a first current source, a first source / drain region connected to the first current source, and a second power source connected to the second source / drain region and the gate. The fifth MIS transistor of the first conductivity type, the first source / drain regions of the third MIS transistor and the fourth MIS transistor, and the first current source or the fifth MIS transistor. A first switch which is provided between the first switch and the first switch and is controlled to be in a conductive state in the first period and to be in a non-conductive state in the second period. By adjusting the threshold value of the first source / drain region, the potential of the first source / drain region of the third and fourth MIS transistors can be set to a desired value during the first period. That.
[0042]
The second voltage control means further includes a second capacitive element having one end connected to the first switch and the fifth MIS transistor and the other end connected to a second power supply. In the first period, the first source / drain regions of the third and fourth MIS transistors can be more reliably set to the predetermined potential.
[0043]
The second voltage comparator according to the present invention includes a second voltage comparator provided between the second source / drain region of the third MIS transistor and the second source / drain region of the fourth MIS transistor. A sixth MIS transistor of a conductivity type, a third capacitor having one end to which a fourth signal having the same phase as the second signal is applied, and the other end connected to the gate of the sixth MIS transistor; A third resistor connected to one end of the first power supply and the other end connected to the gate of the sixth MIS transistor; and temporarily connecting the sixth MIS transistor during the first period. Third voltage control means for controlling the transistor to conduct.
[0044]
Thereby, even when the voltage difference between the differential input voltages is very small in the first period, it is possible to quickly converge to the original differential amplification value as compared with the conventional voltage comparator. Therefore, in the first voltage comparator of the present invention, it is possible to reduce the probability of occurrence of erroneous comparison in the second period as compared with the related art.
[0045]
The third voltage control means includes a seventh MIS transistor of a second conductivity type, one end of which is connected to the gate of the sixth MIS transistor and the other end of which is connected to a second power supply; An eighth MIS transistor of a second conductivity type, wherein a first power supply is connected to the drain region, and a gate and a second source / drain region are connected to the gate of the seventh MIS transistor; By further including a third current source connected to the gate of the MIS transistor, the gate of the eighth MIS transistor, and the second source / drain region, the gate voltage of the seventh MIS transistor can be reduced. For example, it is possible to prevent the power supply voltage from being equal to or higher than the power supply voltage (first power supply voltage), so that the reliability of operation can be improved.
[0046]
A second voltage comparator according to the present invention includes a first MIS transistor and a second MIS transistor of a first conductivity type, both of which form a differential pair, and the first MIS transistor and the second MIS transistor, respectively. A differential amplifier circuit having a first resistance element and a second resistance element connected thereto and configured to receive a differential input voltage and generate a differential voltage; A third MIS transistor of a first conductivity type connected to the first MIS transistor and a second source / drain region connected to the first resistance element; and a first source / drain region connected to the second MIS transistor. The MIS transistor has a gate at the second source / drain region of the third MIS transistor, and a second source / drain region at the gate and the third terminal of the third MIS transistor. And a fourth MIS transistor of the first conductivity type respectively connected to the first and second resistance elements. The first source / drain regions of the third MIS transistor and the fourth MIS transistor are commonly connected, and A latch circuit for positive feedback amplification or latching of a differential voltage is provided between the first MIS transistor and the first resistance element, and is turned on in a first period by a first signal. A first conduction type first MIS transistor for switching, which is controlled to be in a non-conducting state during a second period, and the second MIS transistor and the second resistance element, A second MIS transistor for a first conductivity type, which is controlled by the first signal to be conductive during the first period and non-conductive during the second period; One MIS transistor and the third MIS transistor are interposed between the first MIS transistor and the third MIS transistor. The second MIS transistor is in a conductive state in the second period by a second signal having a phase opposite to that of the first signal. A third switch MIS transistor of a first conductivity type controlled to be in a non-conductive state, and a second control signal interposed between the second MIS transistor and the fourth MIS transistor; A fourth conductive MIS transistor of a first conductivity type controlled to be conductive during the second period and nonconductive during the first period, and a second MIS transistor of the third MIS transistor. A fifth MIS transistor of the second conductivity type interposed between the source / drain region and the second source / drain region of the fourth MIS transistor; The third signal of the phase is applied, the other end is connected to the capacitive element connected to the gate of the fifth MIS transistor, the other end is connected to the first power supply, and the other end is connected to the gate of the fifth MIS transistor. And a voltage control means for controlling the fifth MIS transistor to temporarily conduct during the first period.
[0047]
As a result, even in the case where the voltage difference between the differential input voltages is small or the input voltage is small in the first period, it is possible to quickly converge to the original differential amplification value as compared with the conventional voltage comparator. Can be. Therefore, in the second voltage comparator of the present invention, it is possible to reduce the probability of occurrence of an erroneous comparison in the second period as compared with the related art.
[0048]
The voltage control means includes a sixth MIS transistor of a second conductivity type having one end connected to the gate of the fifth MIS transistor and the other end connected to a second power supply, and a first source / drain region. Are connected to the first power supply, and a seventh MIS transistor of the second conductivity type, the gate and the second source / drain region of which are connected to the gate of the sixth MIS transistor; Since the semiconductor device further has a gate and a first current source connected to the gate of the seventh MIS transistor and the second source / drain region, the gate voltage of the fifth MIS transistor is reduced to the power supply voltage ( (First power supply voltage) or more, so that the operation reliability can be improved.
[0049]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0050]
(Embodiment of the present invention)
FIG. 1 is a circuit diagram showing a configuration of the voltage comparator according to the embodiment of the present invention. The voltage comparator according to the present embodiment includes a combination of a differential amplifier circuit and a latch circuit that performs a positive feedback operation, and a power supply voltage (first power supply voltage) V _DD Power supply line and ground voltage (second power supply voltage) V _SS And a conventional voltage comparator provided between the power supply and a ground line for supplying a capacitor or a transistor.
[0051]
As shown in FIG. 1, the voltage comparator of the present embodiment has a ground voltage V _SS And an N-channel type current supply MOS transistor 1 having a gate to which a bias voltage Vb1 is applied so as to function as a constant current source, and a source commonly connected to a drain of the current supply MOS transistor 1; , A first input voltage Vinp and a second input voltage Vinn to be compared with each other, and an N-channel first MOS transistor 2 for converting and amplifying a differential input voltage between Vinp and Vinn to a differential current; An N-channel second MOS transistor 3 and an N-channel first switch MOS transistor 4 whose source is connected to the drain of the first MOS transistor 2 and whose gate receives the first control voltage Vc1. And the source is connected to the drain of the second MOS transistor 3, and the first control voltage Vc1 is applied to the gate. The second switching MOS transistor 5 of the N-channel type to be input, and the source is connected to the drain of the first MOS transistor 2, and the gate is the second (complementary (opposite phase) signal of the first control voltage Vc 1) signal. N-channel third switching MOS transistor 10 to which the control voltage Vc2 is input, and an N-channel whose source is connected to the drain of the second MOS transistor 3 and whose gate receives the second control voltage Vc2. -Type fourth switching MOS transistor 11, an N-channel type third MOS transistor 7 having a source connected to the drain of the third switching MOS transistor 10, and a source having a fourth switching MOS transistor 11 And the drain is connected to the gate of the third MOS transistor 7, and the gate is connected to the third MOS transistor 7. A fourth MOS transistor 6 of the N-channel type connected to the drain of Njisuta 7, one end connected to the drain of the first for switching MOS transistor 4 and the third MOS transistor 7, the power supply voltage V to the other end _DD Is applied to one end, and one end is connected to the drains of the second switching MOS transistor 5 and the fourth MOS transistor 6, and the other end is connected to the power supply voltage V. _DD And a second resistance element 9 to which the voltage is applied. In the voltage comparator of the present embodiment, the first switching MOS transistor 4 and the second switching MOS transistor 5 are compared with the third switching MOS transistor 10 and the fourth switching MOS transistor 11, respectively. It functions as a switch for switching between the differential amplification operation in the mode and the positive feedback operation (or the latch operation) in the latch mode.
[0052]
When a connection point between the drain of the first switching MOS transistor 4 and the first resistance element 8 is a node A, the node A is a second output unit that outputs the second output voltage Voutn, It is connected to the drain of the MOS transistor 7 and the gate of the fourth MOS transistor 6, respectively. Similarly, assuming that a connection point between the drain of the second switching MOS transistor 5 and the second resistance element 9 is a node B, the node B is a first output unit that outputs a first output voltage Voutp, The drain is connected to the drain of the fourth MOS transistor 6 and the gate of the third MOS transistor 7, respectively.
[0053]
A connection point between the third switching MOS transistor 10 and the third MOS transistor 7 and a connection point between the fourth switching MOS transistor 11 and the fourth MOS transistor 6 are connected to each other. This connection is hereinafter referred to as a node C.
[0054]
A common connection point of the first MOS transistor 2, the first switch MOS transistor 4, and the third switch MOS transistor 10 is called a node D, and the second MOS transistor 3, the second switch MOS transistor The common connection point of the fifth and fourth switching MOS transistors 11 is referred to as a node E.
[0055]
In the above, the components similar to those of the conventional voltage comparator have been described. Hereinafter, the characteristic portions of the voltage comparator of the present invention will be described.
[0056]
First, the voltage comparator according to the present embodiment includes first voltage control means for suppressing a rise in the potential of the node C immediately after the start of the latch mode, and a voltage control means for bringing the potential of the node C close to a predetermined value during the comparison mode. A second voltage control means, a P-channel type connection MOS transistor 19 interposed between the drain of the third MOS transistor 7 and the drain of the fourth MOS transistor 6, A third voltage control means having a third capacitance element connected to the gate electrode and controlling the connection MOS transistor to be in an on state for a predetermined period after the transition from the latch mode to the comparison mode; Have. Here, the definitions of the “comparison mode” (first period) and the “latch mode” (second period) are the same as in the related art, and Vc1 = V _DD And Vc2 = V _SS Is “comparison mode”, Vc1 = V _SS And Vc2 = V _DD Is a "latch mode" (see FIG. 2A).
[0057]
In the voltage comparator according to the present embodiment, the first voltage control means is the first capacitive element 12 in which the first control voltage Vc1 is applied to one electrode and the other electrode is connected to the node C.
[0058]
The second voltage control means includes: a fifth P-channel MOS transistor 16 having a first source / drain region connected to the node C and a second control voltage Vc2 applied to a gate electrode; A first current source 13 connected to a ground line, a source connected to the first current source 13 and a second source / drain region of the fifth MOS transistor 16, a drain connected to a power supply line, and An N-channel sixth MOS transistor having a drain and a gate electrode connected to each other; and a second capacitive element 15 interposed between the second source / drain region and a ground line. ing. Here, the source of the sixth MOS transistor 14 is a node F.
[0059]
Further, the third voltage control means includes a third resistance element 17 interposed between the connection MOS transistor 19 and the power supply line, a third resistance element 17 and a gate electrode of the connection MOS transistor 19. A third capacitance element 18 having one end connected to a node G, which is a connection point of the third element, and a second control voltage Vc2 applied to the other end, and a P-channel type interposed between the node G and a ground line. A seventh MOS transistor 20, a second current source 21 connected to the ground line, a source connected to the power supply line, and a drain connected to the second current source 21 and the gate electrode, respectively. 20 and a P-channel eighth MOS transistor 22 whose gate electrodes are connected to each other.
[0060]
The operation of the thus configured voltage comparator of the present embodiment will be described below.
[0061]
FIG. 2A shows the state transition of the first control voltage Vc1 and the second control voltage Vc2 in the voltage comparator of the present embodiment, and the ON / OFF states of the first to fourth switching MOS transistors. It is an operation timing chart. FIG. 2B is a timing chart showing changes in the first input voltage Vinp and the second input voltage Vinn in the voltage comparator according to the present embodiment, and FIG. 2C is a timing chart showing the change in the first output voltage Voutp. Changes in the second output voltage Voutn, changes in the voltage of the node C (node voltage Vc), changes in the voltage of the node D (node voltage Vd) and the voltage of the node E (node voltage Ve), and the voltage of the node F (node voltage Vf) FIG. As shown in FIGS. 2A and 2B, the first control voltage Vc1 and the second control voltage Vc2 used in the voltage comparator of the present embodiment are the same as those of the conventional voltage comparator.
[0062]
Further, the voltage comparator according to the present embodiment outputs Voutp and Voutn as Voutp and Voutn during the latch mode according to the magnitude relationship between the input voltages Vinp and Vinn at the start of the latch mode. _DD And V _DD -Output any of I × R. Here, the voltage response of each node when the input voltage condition of the voltage comparator of the present embodiment is the same as the input voltages Vinp and Vinn shown in FIG. 4B is compared with the conventional voltage comparator. explain.
[0063]
First, at the end of the period of the "comparison mode 1", the voltage difference between the first input voltage Vinp and the second input voltage Vinn is about sub to about 1 mV, which is almost the minimum as the input voltage difference of the present voltage comparator. , The output voltages Voutp and Voutn are V _DD With -IR / 2 as the common mode voltage, each input voltage has a voltage value amplified by a predetermined ratio. The node voltage Vc is V _DD And the upper limit is a voltage value near a voltage obtained by subtracting the threshold voltage Vt of the fourth MOS transistor 6 and the third MOS transistor 7 from the above. The value of I × R is generally set to about 0.3 to 0.5V. Here, when the value of I × R is 0.5 V, the power supply voltage V _DD Is 3.0V, V _DD The value of −I × R is 2.5 V, and the node voltage Vc is V _DD A voltage obtained by subtracting about 1 V which is the gate-source voltage of the fourth MOS transistor 6 and the third MOS transistor 7 from the above, that is, about 2.0 V is the upper limit. Similarly, Vd and Ve are both the power supply voltage V _DD From about 1 V, which is the gate-source voltage of the first switching MOS transistor 4 and the second switching MOS transistor 5, from about 2.0 V.
[0064]
Next, when transitioning from “comparison mode 1” to “latch mode 1”, the first control voltage Vc1 _DD To V _SS As a result, the first switching MOS transistor 4 and the second switching MOS transistor 5 change from the on state to the off state. At the same time, the second control voltage Vc2 becomes V _SS To V _DD As a result, the third switching MOS transistor 10 and the fourth switching MOS transistor 11 shift from the off state to the on state.
[0065]
In the conventional voltage comparator, in the transition state from “comparison mode 1” to “latch mode 1”, the second voltage is applied to the second switching MOS transistor 10 and the fourth switching MOS transistor 11 via the parasitic capacitance. Since the voltage change of the control voltage Vc2 is transmitted to the node C, the node voltage Vc is temporarily pushed up to the high potential side (see FIG. 4C).
[0066]
On the other hand, as shown in FIG. 2C, in the voltage comparator of the present embodiment, the first control element 12 is provided, so that the polarity of the voltage comparator changes to the opposite polarity to the second control voltage Vc2. The voltage change of the first control voltage Vc1 is transmitted to the node C, and the voltage Vc of the node C is pushed down to the low potential side. Thereafter, when the third switching MOS transistor 10 and the fourth switching MOS transistor 11 both enter the state, the node C becomes conductive with the nodes D and E, and the node voltages Vc, Vd and Ve are substantially equal to each other. It becomes.
[0067]
As described above, in the voltage comparator according to the present embodiment, the provision of the first capacitive element 12 suppresses a rise in the node voltage Vc during the transition from the comparison mode to the latch mode. MOS transistor 6 and third MOS transistor 7 are quickly turned on (point δ shown in FIG. 2C). Therefore, the voltage comparator of the present embodiment can start the positive feedback operation more quickly than the conventional voltage comparator (point ε in FIG. 2E). As a result, the first output voltage Voutp and the second output voltage Voutn are subjected to positive feedback amplification, and _DD , V _DD -Quickly converges to IxR. Therefore, according to the voltage comparator of the present embodiment, the difference between the output voltages can be more reliably and quickly converged to I × R during the latch mode 1, so that the probability of occurrence of the erroneous comparison is suppressed. Can be. In particular, since it is effective even when the difference between the two input voltages is small, it is possible to perform voltage comparison with higher accuracy than before. Further, since the output voltage can be made to converge in a shorter time than in the related art, it is possible to increase the clock frequency of the first control voltage Vc1 and the second control voltage Vc2 to speed up the operation.
[0068]
Next, when transitioning from “latch mode 1” to “comparison mode 2”, both the third switching MOS transistor 10 and the fourth switching MOS transistor 11 are turned off, and the first switching MOS transistor 11 is turned off. There is a transitional period during which the switching MOS transistor 4 and the second switching MOS transistor 5 are not sufficiently turned on. During this transition period, V _DD And V _SS The first output voltage Voutp, the second output voltage Voutn, and the node voltage Vc transition to a higher potential side than charge inflow from the power supply line. Further, the node voltages Vd and Ve have their electric charges extracted by the current supply MOS transistor 1 and transition to the lower potential side.
[0069]
In the voltage comparator of the present embodiment, immediately after the start of the comparison mode, the voltage of the first control voltage Vc1 _SS To V _DD Is transmitted via the first capacitive element 12, the node voltage Vc is pushed up to the high potential side. Therefore, the fourth MOS transistor 6 and the third MOS transistor 7 are instantaneously turned off, and the charging current stops flowing toward the node C, so that an error occurs in the first output voltage Voutp and the second output voltage Voutn. This makes it difficult to prevent erroneous comparisons.
[0070]
Thereafter, the first switching MOS transistor 4 and the second switching MOS transistor 5 are completely turned on, and the third switching MOS transistor 10 and the fourth switching MOS transistor 11 are sufficiently turned off. Then, the voltage comparator functions as a differential amplifier that differentially amplifies the input voltage.
[0071]
As shown in FIG. 2B, if the input voltage difference between Vinp and Vinn is larger than the dynamic range of differential amplification (for example, 100 mV or more and 200 mV or less) (Vinn> Vinp), the first output voltage Voutp is used. And the second output voltage Voutn at the end of this mode, respectively. _DD −I × R, V _DD Converges to
[0072]
Further, node voltages Vd and Ve converge to the voltage values as described in the description of “comparison mode 1”. Further, the node voltage Vc also converges to the voltage value described in “comparison mode 1” after a predetermined period.
[0073]
The voltage comparator according to the present embodiment includes second control means in addition to the first capacitance element 12. For this reason, the node voltage Vc that has risen immediately after the start of the “comparison mode 2” is substantially reduced to the voltage of the node F (node voltage Vf) during the “comparison mode 2”. This is based on the following mechanism.
[0074]
As shown in FIG. 2C, the node voltage Vf is equal to the power supply voltage V _DD And a voltage value obtained by subtracting a voltage value near the threshold voltage of the sixth MOS transistor 14 from the second MOS transistor 14, and is maintained at a substantially constant value by the second capacitive element 15. In the comparison mode, the second control voltage Vc2 becomes V _DD To V _SS And the fifth MOS transistor 16 changes from the off state to the on state. Therefore, the node voltage Vc substantially converges to the node voltage Vf by the end of the comparison mode (point ζ in FIG. 2C).
[0075]
As described above, in the voltage comparator of the present embodiment, erroneous comparison in the comparison mode can be suppressed by including the first capacitance element 12. In addition, since the voltage comparator of the present embodiment includes the second voltage control means, it is possible to suppress an increase in the node voltage Vc before the transition to the “latch mode”, and to enter the “latch mode”. , It is possible to quickly start the positive feedback operation after the transition. At this time, it is preferable that the threshold value of the sixth MOS transistor 14 is set near the threshold value of the third MOS transistor 7 and the fourth MOS transistor 6.
[0076]
Note that, even when the second voltage control means does not have the second capacitance element 15, it is possible to suppress the rise of the node voltage Vc. However, the provision of the second capacitance element 15 allows the node voltage Vc to be increased. Is more stabilized.
[0077]
Next, when transitioning from “comparison mode 2” to “latch mode 2”, Voutn, Voutp, and node voltages Vc, Vd, Ve change by transient voltages due to the operation described in the description of “latch mode 1”. After that, the voltage converges to a predetermined voltage value. At this time, the first output voltage Voutp and the second output voltage Voutn are V _DD −I × R, V _DD It becomes.
[0078]
Next, when transitioning from “latch mode 2” to “comparison mode 3”, the node voltages Vc, Vd, and Ve change in the same manner as in “latch mode 1” to “comparison mode 2”. Also in this case, since the voltage comparator includes the first capacitor, erroneous comparison in the comparison mode can be suppressed. Further, the rise of the node voltage Vc is suppressed by the second voltage control means before the transition to the “latch mode 3”.
[0079]
By the way, at the start of the “comparison mode 3”, the difference between the first input voltage Vinp and the second input voltage Vinp is at the minimum level for the voltage comparator. In such a case, the output voltages Voutp and Voutn _DD With −IR / 2 as the common mode voltage, the input voltages Vinp and Vinn have respective voltage values amplified by a predetermined ratio. At this time, as shown in FIGS. 2C and 4C, the voltage comparator according to the present embodiment includes the connection MOS transistor 19 and the third voltage control means. The time required for the output voltage to converge is shorter than that of the comparator. This is for the following reason.
[0080]
Immediately before the transition from the “latch mode 2” to the “comparison mode 3”, the gate voltage (node voltage Vg) of the connection MOS transistor 19 is changed to the power supply voltage Vg via the third resistance element 17. _DD , So it is off.
[0081]
Next, when a transition is made from “latch mode 2” to “comparison mode 3”, the second control voltage Vc2 _DD To V _SS Is transmitted through the third capacitive element 18 and the node voltage Vg becomes V _DD From the low potential side. At this time, the connection MOS transistor 19 is turned on during the period in which the gate-source voltage (here, Vg-Voutn) is equal to or lower than the threshold voltage from the transition to the comparison mode. Then, the node A and the node B are brought into conduction, so that the first output voltage Voutp and the second output voltage Voutn converge toward voltages equal to each other (point η in FIG. 2C). During this time, the differential amplification function of the voltage comparator also starts to operate. Further, since the connection MOS transistor 19 is turned off when the gate-source voltage exceeds the threshold value, the first input voltage Vinp and the second input voltage are surely set before the end of the “comparison mode 3”. The first output voltage Voutp and the second output voltage Voutn in a state where the voltage Vinn is differentially amplified are output.
[0082]
Further, in the voltage comparator of the present embodiment, at the time of transition from the comparison mode to the latch mode, the second control voltage Vc2 is set to V _SS To V _DD Before the transition, the power supply voltage V _DD Node voltage Vg transiently changes to power supply voltage V _DD Pushed to higher potential side. However, when the node voltage Vg is V _DD Is exceeded, the charge is extracted through the seventh MOS transistor 20, so that the rise of the node voltage Vg is suppressed. Therefore, the node voltage Vg does not become a high voltage exceeding the absolute maximum rating of the semiconductor device, and the reliability of the voltage comparator is improved.
[0083]
As described above, since the voltage comparator of the present embodiment includes the third capacitive element 18 to which the second control voltage is applied, even when the input voltage difference is small, Since it is possible to quickly converge to the original differential amplification value as compared with the comparator, it is possible to reduce the probability of occurrence of erroneous comparison in the latch mode. In other words, erroneous comparison can be suppressed regardless of the magnitude or history (hysteresis) of the input voltage before entering the comparison mode. In addition, since the output voltages converge quickly in the comparison mode, the operating speed can be improved by increasing the frequencies of the first control voltage Vc1 and the second control voltage Vc2.
[0084]
Note that the third voltage control means described here can be expected to have an effect of suppressing erroneous comparisons when used alone, but by combining it with the first voltage control means and the second voltage control means, a more accurate Voltage comparison becomes possible.
[0085]
As described above, the use of the voltage comparator according to the present embodiment makes it possible to perform voltage comparison with higher accuracy than before.
[0086]
In the voltage comparator of the present embodiment, the first capacitance element 12 and the second voltage control means are used in combination. However, even if the second voltage control means is used alone, occurrence of erroneous comparison can be suppressed. it can. In this case, the node voltage Vf becomes (V _DD It is preferable that the threshold value of the sixth MOS transistor 14 be set to a value obtained by subtracting the threshold voltage of the third MOS transistor 7 and the fourth MOS transistor 6 from (−IR / 2). As a result, similarly to the case where the first capacitive element 12 is provided, it is possible to suppress an increase in the node voltage Vc at the start of the latch mode. Can be suppressed.
[0087]
Further, in the description of the present embodiment, an example has been described in which all the transistors used in the voltage comparator are MOS transistors, but an MIS transistor may be used instead. Further, a bipolar transistor can also be used.
[0088]
The same operation can be performed even if the conductivity types of the MOS transistors constituting the voltage comparator of the present embodiment are all reversed. In that case, Vc1 becomes V _DD At the time of latch mode, V _SS Is the comparison mode.
[0089]
In the voltage comparator according to the present embodiment, the fifth MOS transistor 16 may be an N-channel MOS transistor controlled by the first control voltage Vc1, but is controlled by the second control voltage Vc2. A P-channel MOS transistor is more preferable because the transistor can be reliably operated when the node voltage Vc increases.
[0090]
【The invention's effect】
As described above, the voltage comparator of the present invention includes a differential amplifier circuit that differentially amplifies an input voltage, a latch circuit that positively feedbacks or latches the differentially amplified input voltage, a differential amplification operation and a positive feedback operation. Switching MOS transistor, second switching MOS transistor, third switching MOS transistor and fourth switching MOS transistor, and third switching MOS transistor and fourth switching MOS transistor A first voltage control means connected to a node C between the MOS transistor and the positive feedback circuit; a second voltage control means connected to the node C; And third voltage control means for electrically connecting the output units. The first voltage control means and the second voltage control means can suppress an increase in the potential of the node C at the start of the positive feedback operation and set the potential of the node C to a predetermined value before the start of the next positive feedback operation. Therefore, occurrence of erroneous comparison can be suppressed, and high-speed operation can be performed. Further, the output voltage can be quickly converged to the original differential amplification value during the differential amplification operation by the third voltage control means, so that the occurrence of erroneous comparison is reduced and high-speed operation is enabled. it can.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a voltage comparator according to an embodiment of the present invention.
FIG. 2A shows a state transition of a first control voltage Vc1 and a second control voltage Vc2 in a voltage comparator according to an embodiment of the present invention, and shows ON / OFF states of each switching MOS transistor. It is an operation timing chart. FIG. 3B is a timing chart showing changes in the first input voltage Vinp and the second input voltage Vinn in the voltage comparator, and FIG. 3C is a timing chart showing changes in the first output voltage Voutp and the second output voltage Voutn. FIG. 5 is a timing chart showing changes in node voltages.
FIG. 3 is a circuit diagram showing a configuration of a conventional voltage comparator.
FIG. 4A is an operation timing chart showing a state transition of a first control voltage Vc1 and a second control voltage Vc2 in a conventional voltage comparator and an ON / OFF state of each MOS transistor. FIG. 4B is a timing chart showing changes in the first input voltage Vinp and the second input voltage Vinn, and FIG. 4C is a timing chart showing changes in the first output voltage Voutp and the second output voltage Voutn and the respective node voltages. FIG. 4 is a timing chart showing changes in
[Explanation of symbols]
1 Current supply MOS transistor
2 First MOS transistor
3 Second MOS transistor
4 First switching MOS transistor
5. Second switching MOS transistor
6 Fourth MOS transistor
7. Third MOS transistor
8 First resistive element
9 Second resistive element
10. Third MOS transistor for switch
11 Fourth switching MOS transistor
12 First capacitive element
13 First current source
14 Sixth MOS transistor
15 Second capacitive element
16 Fifth MOS transistor
17 Third resistive element
18 Third capacitive element
19 MOS transistor for connection
20 Seventh MOS transistor
21 Second current source
22 Eighth MOS Transistor
Va, Vb, Vc, Vd, Ve, Vf, Vg Node voltage

Claims (9)

A first MIS transistor and a second MIS transistor of a first conductivity type, both forming a differential pair, and a first resistive element and a second MIS transistor connected to the first MIS transistor and the second MIS transistor, respectively. And a differential amplifier circuit for receiving the differential input voltage and generating a differential voltage,
A first MIS transistor of a first conductivity type having a first source / drain region connected to the first MIS transistor and a second source / drain region connected to the first resistance element; The source / drain region of the third MIS transistor has a source / drain region, the gate of the third MIS transistor has a second source / drain region, and the second source / drain region has a gate and a third terminal of the third MIS transistor. And a fourth MIS transistor of a first conductivity type respectively connected to the second resistance element, wherein the first source / drain regions of the third MIS transistor and the fourth MIS transistor are commonly connected, A latch circuit for amplifying or latching the differential voltage with positive feedback;
A first signal is interposed between the first MIS transistor and the first resistance element, and is controlled to be conductive in a first period and non-conductive in a second period by a first signal. A first MIS transistor for a switch of one conductivity type;
The first signal is provided between the second MIS transistor and the second resistance element, and is controlled by the first signal so as to be conductive during the first period and non-conductive during the second period. A first-conductivity-type second switch MIS transistor,
The second MIS transistor is interposed between the first MIS transistor and the third MIS transistor, and is turned on in the second period by a second signal having a phase opposite to the first signal. A first-conduction-type third switch MIS transistor that is controlled to be in a non-conductive state during the period;
The second control signal is interposed between the second MIS transistor and the fourth MIS transistor, and is turned on in the second period by the second control signal, and is turned off in the first period. A fourth switch type MIS transistor of a first conductivity type to be controlled;
The first source of the third MIS transistor and the fourth MIS transistor at the time of transition from the first period to the second period or at the time of transition from the second period to the first period. A voltage comparator comprising first voltage control means for changing the voltage of the drain region to a polarity opposite to the voltage change of the second signal. The voltage comparator according to claim 1,
The first voltage control means has one end connected to the first source / drain region of the third MIS transistor and the fourth MIS transistor, and the other end connected to the other end of the first MIS transistor having a phase opposite to that of the second signal. A voltage comparator, which is a first capacitive element to which the signal of No. 3 is applied. The voltage comparator according to claim 2,
During the first period, the voltage between the gate and the first source / drain region of the third MIS transistor and the fourth MIS transistor is substantially changed by the third MIS transistor and the fourth MIS transistor. A voltage comparator further comprising a second voltage control means for setting the threshold voltage of the second comparator. The voltage comparator according to claim 3,
The second voltage control means includes:
A first current source;
A fifth MIS transistor of a first conductivity type having a first source / drain region connected to the first current source and a second power source connected to the second source / drain region and a gate;
The first MIS transistor is provided between the first source / drain region of the third MIS transistor and the fourth MIS transistor and the first current source or the fifth MIS transistor, and is in a conductive state during the first period. And a first switch controlled to be non-conductive during the second period. The voltage comparator according to claim 4,
The second voltage control means includes:
A voltage comparator, further comprising a second capacitive element having one end connected to the first switch and the fifth MIS transistor and the other end connected to a second power supply. The voltage comparator according to any one of claims 1 to 5,
A sixth MIS transistor of a second conductivity type interposed between a second source / drain region of the third MIS transistor and a second source / drain region of the fourth MIS transistor;
A fourth signal having the same phase as the second signal is applied to one end, a third capacitive element having the other end connected to the gate of the sixth MIS transistor, and a first power supply connected to one end. A third resistance element having the other end connected to the gate of the sixth MIS transistor; and a control circuit for temporarily controlling the sixth MIS transistor to be conductive during the first period. A voltage comparator further comprising third voltage control means. The voltage comparator according to claim 6,
The third voltage control means includes:
A seventh MIS transistor of a second conductivity type, one end of which is connected to the gate of the sixth MIS transistor and the other end of which is connected to a second power supply;
An eighth MIS transistor of a second conductivity type having a first power supply connected to the first source / drain region, and a gate and a second source / drain region connected to the gate of the seventh MIS transistor;
A voltage comparator, further comprising a third current source connected to a gate of the seventh MIS transistor, a gate of the eighth MIS transistor, and a second source / drain region. A first MIS transistor and a second MIS transistor of a first conductivity type, both forming a differential pair, and a first resistive element and a second MIS transistor connected to the first MIS transistor and the second MIS transistor, respectively. And a differential amplifier circuit for receiving the differential input voltage and generating a differential voltage,
A first MIS transistor of a first conductivity type having a first source / drain region connected to the first MIS transistor and a second source / drain region connected to the first resistance element; The source / drain region of the third MIS transistor has a source / drain region, the gate of the third MIS transistor has a second source / drain region, and the second source / drain region has a gate and a third terminal of the third MIS transistor. And a fourth MIS transistor of a first conductivity type respectively connected to the second resistance element, wherein the first source / drain regions of the third MIS transistor and the fourth MIS transistor are commonly connected, A latch circuit for amplifying or latching the differential voltage with positive feedback;
A first signal is interposed between the first MIS transistor and the first resistance element, and is controlled to be conductive in a first period and non-conductive in a second period by a first signal. A first MIS transistor for a switch of one conductivity type;
The first signal is provided between the second MIS transistor and the second resistance element, and is controlled by the first signal so as to be conductive during the first period and non-conductive during the second period. A first-conductivity-type second switch MIS transistor,
The second MIS transistor is interposed between the first MIS transistor and the third MIS transistor, and is turned on in the second period by a second signal having a phase opposite to the first signal. A first-conduction-type third switch MIS transistor that is controlled to be in a non-conductive state during the period;
The second control signal is interposed between the second MIS transistor and the fourth MIS transistor, and is turned on in the second period by the second control signal, and is turned off in the first period. A fourth switch type MIS transistor of a first conductivity type to be controlled;
A fifth MIS transistor of a second conductivity type interposed between a second source / drain region of the third MIS transistor and a second source / drain region of the fourth MIS transistor;
A third signal having the same phase as the second signal is applied to one end, the other end is connected to a capacitive element connected to the gate of the fifth MIS transistor, one end is connected to a first power supply, and the other end is connected to the other end. A third resistance element connected to the gate of the fifth MIS transistor; and a voltage control means for controlling the fifth MIS transistor to be conductive temporarily during the first period. And a voltage comparator. The voltage comparator according to claim 8, wherein
The voltage control means includes:
A sixth MIS transistor of a second conductivity type having one end connected to the gate of the fifth MIS transistor and the other end connected to a second power supply;
A seventh MIS transistor of a second conductivity type, a first power supply connected to the first source / drain region, and a gate and a second source / drain region connected to the gate of the sixth MIS transistor;
A voltage comparator, further comprising a first current source connected to a gate of the sixth MIS transistor, a gate of the seventh MIS transistor, and a second source / drain region.

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