JP2004259590A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device using an ion implanter capable of performing a quantitative and efficient maintenance and with resolution of ion beams well administered. <P>SOLUTION: An ammeter 17 is electrically connected to a mass spectroscopy slit 4 into which ion beams emitted from a source part are irradiated. Then, a degree of abrasion of the mass spectroscopy slit 4 as a result of irradiation of the ion beams is measured by measuring a current value flowing in the ammeter 17 electrically connected to the mass spectroscopy slit 4. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a semiconductor device manufacturing process for implanting impurities into a semiconductor wafer.
[0002]
[Prior art]
In a process of manufacturing a MOS device on a semiconductor wafer (hereinafter, referred to as a wafer), an N-type impurity such as arsenic (As), phosphorus (P), antimony (Sb) or a P-type impurity such as boron (B) is used. There is a step of injecting into a wafer or a gate electrode. For example, the step of implanting impurities into the wafer includes a step of implanting impurities into a channel region, a step of forming a source region and a drain region, and the like. Further, there is a step of injecting an N-type impurity or a P-type impurity into a gate electrode made of polysilicon to secure conductivity.
[0003]
The ion implantation method is widely used for the addition of the conductive impurities and the formation of the diffusion regions such as the source region and the drain region. This is because the amount and depth of impurities can be accurately controlled by ion implantation. In addition, the ion implantation method also has advantages that an impurity can be selectively added using a photoresist film as a mask, and that the impurity to be implanted can be prevented from spreading in the lateral direction.
[0004]
An ion implantation apparatus is used for the ion implantation. In this ion implantation apparatus, first, a gas containing an N-type impurity or a P-type impurity to be added is ionized in an arc chamber. After the ionized impurities pass through the mass analysis slit, the ion species is accurately selected by a mass analyzer using a magnet. The selected ions are accelerated in the accelerator and implanted on the wafer surface. Thus, impurities can be implanted into the wafer (for example, see Non-Patent Document 1).
[0005]
[Non-patent document 1]
"Electronic Materials Nov. Separate Volume, Guidebook for Ultra LSI Manufacturing and Testing Equipment, 2003 Edition," Industrial Research Committee, published on November 27, 2002, p. 33 to p. 38
[0006]
[Problems to be solved by the invention]
If the above-described ion implantation apparatus is continuously used, the mass analysis slit in the ion implantation apparatus is worn because it is continuously sputtered by the ion beam. Also, ions that are lighter or heavier than the selected ions collide with the analyzer carbon in the mass spectrometer of the ion implantation apparatus, and thus are worn. Furthermore, ions contained in the ion beam collide with the ions in the chamber for forming ions and return to normal atoms, and the atoms are deposited and become contaminated. Therefore, the ion implantation apparatus requires regular maintenance such as replacing the mass analysis slit.
[0007]
At present, the maintenance time of the ion implantation apparatus is determined depending on experience values and apparatus conditions. For example, since the ion implanter is the same type as the ion implanter that is operating separately, it is necessary to perform maintenance at the same maintenance cycle as the ion implanter that operates separately, or to experience several times the recommended period of the manufacturer of the mass spectrometry slit. The maintenance time is determined by the empirical factor that it is all right. Further, the mass spectrometry slit is worn out, the discharge is increased, and the power supply fails, and the mass spectrometry slit is replaced only when the mass spectrometry slit is replaced. That is, the ion implantation apparatus is even replaced by using up the mass analysis slit until a failure occurs.
[0008]
However, in the above-mentioned current situation, there is a problem that the maintenance time differs depending on the use condition of each ion implantation apparatus, and there is a problem that the apparatus does not fail and the quantitative and efficient maintenance cannot be performed. . That is, the type of ions to be implanted in each ion implantation apparatus and the ion beam amount are different, so that the maintenance time of each ion implantation apparatus is different. Therefore, there is a problem that maintenance cannot be performed at a maintenance time suitable for each ion implantation apparatus.
[0009]
Further, when the mass analysis slit is worn, the ion beam resolving ability is reduced, but at present, the ion beam resolving ability is not managed. In the future formation of miniaturized semiconductor devices, it is considered that management of ion beam decomposition capability will be indispensable. For example, if the mass analysis slit deteriorates, the resolution of the ion beam decreases, and the BF having a mass number of 49 is used.₂ ⁺Of BF with mass number 48 which is an isotope when₂ ⁺May also be injected. BF with a light mass of 48₂ ⁺Is implanted into the wafer, which means that the depth of the impurity diffusion region formed on the wafer becomes deeper than designed, which results in abnormal Vth control characteristics, abnormal junction breakdown voltage, and resistance characteristics of the impurity diffusion region. There is a problem that abnormalities occur.
[0010]
An object of the present invention is to provide a method for manufacturing a semiconductor device using an ion implantation apparatus capable of performing quantitative and efficient maintenance.
[0011]
It is another object of the present invention to provide a method for manufacturing a semiconductor device using an ion implantation apparatus in which the resolution of an ion beam is managed.
[0012]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0014]
The present invention provides a method of manufacturing a semiconductor device including a step of implanting impurities into the semiconductor wafer by using a semiconductor manufacturing apparatus that irradiates an ion beam onto a semiconductor wafer, wherein the ions in the ion beam collide with each other. The method includes a step of automatically measuring the degree of wear of the member in the semiconductor manufacturing apparatus to which the ammeter is attached, to which the ammeter is attached, by the ammeter.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0016]
(Embodiment 1)
In the first embodiment, for example, the present invention is applied to a method of manufacturing a semiconductor device in which a CMOS element is formed on a wafer.
[0017]
FIG. 1 is an external view of an ion implantation apparatus 1 used in the method of manufacturing a semiconductor device according to the first embodiment, and FIG. 2 is a diagram illustrating a schematic configuration of the ion implantation apparatus 1.
[0018]
In FIG. 1, an ion implantation apparatus (semiconductor manufacturing apparatus) 1 has a width of about 4700 mm, a depth of about 2200 mm, a height of about 2350 mm, and a total weight of 6.3 tons.
[0019]
In FIG. 2, an ion implantation apparatus 1 according to the first embodiment is an apparatus for implanting impurities on a wafer 2, and includes a source section 3, a mass analysis slit 4, a mass analysis section 5, an acceleration section 6, It has a lens unit 7, a scanning unit 8, and an end station 9.
[0020]
The source section 3 includes an arc chamber and a source gas introduction tube, and an impurity gas is introduced into the inside of the arc chamber from the source gas introduction tube. As the impurities, for example, N-type impurities such as phosphorus (P) and arsenic (As) or boron (B) and boron fluoride (BF)₂) And the like.
[0021]
Then, in the source section 3, ionization of the impurity gas is performed by collision of thermionic electrons generated from the filament in the arc chamber with the impurity gas introduced by the source gas introduction pipe, so that an ion beam can be emitted. It is configured. The source section 3 is in a high vacuum state by a combination of a rotary pump and an oil diffusion pump.
[0022]
The mass analysis slit (member) 4 is configured to pass ions to be implanted into the wafer 2 out of the ions included in the ion beam emitted from the source unit 3 and not to pass other ions. For example, boron fluoride having a mass number of 49 (BF₂ ⁺) Is implanted into a wafer when boron fluoride (BF) having a mass number of 48 is used as an isotope.₂ ⁺). That is, since the difference between the mass and the central portion of the ion beam is different depending on the difference in mass, ions having different masses can be cut off by providing the slit in the mass analysis slit 4.
[0023]
The mass analyzer 5 is configured to be able to select ions with higher accuracy than the mass analysis slit 4, and is configured to bend by applying a magnetic field to the ion beam that has passed through the mass analysis slit 4. . In the mass spectrometer 5, the impurity ions implanted into the wafer 2 are bent, but pass through the mass spectrometer 5 without colliding with the analyzer carbon 5a formed on the side surface. On the other hand, ions that are heavier or lighter than the ions to be implanted into the wafer 2 travel along a different trajectory from the ions to be implanted into the wafer 2 and collide with the analyzer carbon 5a. That is, ions heavier than the ions implanted into the wafer 2 are less likely to be bent than ions implanted into the wafer 2, while lighter ions are more likely to be bent. For this reason, ions having a different mass from the ions to be implanted into the wafer 2 are excluded by the mass analyzer 5.
[0024]
The acceleration unit 6 is configured to accelerate ions in the ion beam emitted from the mass analysis unit 5 by an electrostatic acceleration method. By providing the accelerating unit 6, energy for determining the ion implantation depth can be given to the ions. For example, an energy of up to about 200 keV can be applied.
[0025]
The lens unit 7 is provided for converging the spread ion beam accelerated by the acceleration unit 6 with an electrostatic lens. That is, the ion beam is easy to spread because the ions having the same charge are integrated. For this reason, the ion beam is converged in the lens unit 7.
[0026]
The above-described acceleration unit 6 and lens unit 7 have a vacuum exhaust system, and are configured by, for example, a combination of a rotary pump and a cryopump.
[0027]
The scanning unit 8 is configured to scan the ion beam emitted from the lens unit 7. That is, in order to uniformly implant ions in the ion beam over the entire surface of the wafer 2, the ion beam is electrically scanned at high speed by the electrostatic scanning method. It is necessary to perform the implantation for 10 seconds or more in order to maintain the uniformity of the implanted ions.
[0028]
The end station 9 has an impurity injection chamber 10 and a transfer section 11 at two locations each. The impurity implantation chamber 10 is a processing chamber for implanting ions on the wafer 2, and the wafer 2 is processed in a single wafer type. The impurity implantation chamber 10 is basically made of stainless steel or aluminum whose surface is anodized. In addition, the transfer unit 11 is configured to transfer the wafers 2, and transfers the wafers 2 in a batch process, for example, as a set of 10 pieces of 2 lots on one side.
[0029]
Next, the configuration of the source section 3 and the mass analysis slit 4 is shown in FIG. In FIG. 3, the source unit 3 has an arc chamber 12, an extraction electrode 13, an extraction power supply 14, a suppression power supply 15, and a ground electrode 16.
[0030]
The arc chamber 12 is electrically connected to an extraction electrode 13 via an extraction power supply 14 and a suppression power supply 15. The arc chamber 12 is electrically connected to a ground electrode 16 via an extraction power supply 14, and an extraction electrode 13 is disposed between the arc chamber 12 and the ground electrode 16. Here, for example, the voltage of the extraction power supply 14 is about 40 kV, and the voltage of the suppression power supply 15 is about 1.2 kV.
[0031]
Next, an ammeter 17 is attached to the mass analysis slit 4. In addition, a hole is formed in the center of the mass analysis slit 4, and as shown in FIG. 3, a part of the ion beam emitted from the source unit 3 passes through the hole and the other part is cut off. . When cut off, ions contained in the ion beam collide with the mass analysis slit 4. Since the colliding ions have an electric charge, a current flows through an ammeter 17 electrically connected to the mass analysis slit 4. Here, the value of the current flowing through the ammeter 17 changes depending on the amount of ions blocked by the mass analysis slit 4. That is, as the amount of the ion beam cut off by the mass analysis slit 4 increases, the current value flowing through the ammeter 17 increases, while the amount of the ion beam cut off by the mass analysis slit 4 decreases. The value of the current flowing through 17 decreases.
[0032]
FIG. 4 shows a plan view of the mass analysis slit 4 when new. In FIG. 4, a rectangular hole with a rounded corner is opened at the center of the mass analysis slit 4, and the ion beam passes through this hole. The length of this hole in the vertical direction is about 10 mm, and the length in the horizontal direction is about 5 mm. It is assumed that the ion beam flows from the upper part of the paper to the lower part of the paper.
[0033]
FIG. 5 shows a cross-sectional view taken along the line AA of FIG. As can be seen from FIG. 5, a part of the ion beam passes but the extension of the ion beam is blocked by the mass analysis slit 4.
[0034]
Here, if the ion implantation apparatus 1 is continuously used, the mass analysis slit 4 is worn because the irradiation of the ion beam is continued. In other words, the holes (slits) formed in the mass analysis slit 4 become large because the ions contained in the ion beam continue to receive collisions.
[0035]
FIG. 6 shows a plan view of the mass spectrometry slit 4 that has been continuously used and worn. As shown in FIG. 6, it can be seen that the size of the hole opened in the center of the mass analysis slit 4 is large. Specifically, for example, the vertical length is about 20 mm and the horizontal length is 10 mm. FIG. 7 shows a cross-sectional view taken along the line AA in FIG. Assuming that the ion implantation apparatus 1 was operated under the same conditions of ion energy, ion type, beam amount, and the like when it was new and when it was worn, as can be seen from FIG. Thus, while the amount of the ion beam passing through the mass analysis slit 4 increases, the amount of the ion beam blocked by the mass analysis slit 4 decreases. Therefore, it can be seen that the current value flowing through the mass analysis slit 4 when worn is smaller than the current value flowing through the mass analysis slit 4 when new.
[0036]
FIG. 8 shows a relationship between a current value flowing through the ammeter 17 electrically connected to the mass analysis slit 4 and time (week). In FIG. 8, the vertical axis indicates the value of the current flowing through the ammeter 17 and the horizontal axis indicates the time in week units. The ion implantation apparatus 1 is operated under conditions where the implantation energy is about 100 keV and the ion species is phosphorus (P⁺), The amount of ion beam is about 100 μA. As can be seen from FIG. 8, the current value flowing through the mass analysis slit 4 when it is new is about 0.7 mA, and thereafter, the current value flowing through the mass analysis slit 4 gradually decreases as the week progresses. Around the 39th week, the current flowing through the mass analysis slit 4 becomes about 0.3 mA. After that, it decreases very slowly from 0.3 mA and becomes almost constant at about 0.29 mA. Here, when the current value flowing through the mass analysis slit 4 is about 0.3 mA or less, the mass analysis slit 4 is greatly worn, and the replacement time, that is, the maintenance time is around the 39th week.
[0037]
Here, at the time of abnormal discharge, the current flowing through the mass analysis slit 4 may suddenly increase. As this calibration method, it is conceivable that the current flowing through the mass analysis slit 4 is not counted (not measured) during abnormal discharge. For example, set the upper and lower thresholds from the current value measured in the normal state where the previous abnormal discharge does not occur, and if a current value exceeding this range is measured, do not count the current value as a measured value There is a method of setting. If the gas pressure, voltage and the like in the source section 3 are constant, the current flowing through the mass analysis slit 4 is constant.
[0038]
As described above, since the current value flowing through the mass analysis slit 4 and the degree of wear of the mass analysis slit 4 have a relationship such that the current value decreases as the degree of wear increases, the current value is quantitatively measured by measuring the current value. Thus, the degree of wear of the mass analysis slit 4 can be measured. Therefore, the timing for replacing the mass analysis slit 4 can be quantitatively determined, so that efficient maintenance can be performed.
[0039]
In addition, since maintenance with good timing can be performed, the mass analysis slit 4 is not replaced early, and the running cost of the ion implantation apparatus 1 can be reduced. It is also possible to prevent a failure of the ion implantation apparatus 1 caused by the use described above and a decrease in throughput due to the failure.
[0040]
Further, the ion beam resolving power is determined by the size of the hole provided in the mass analysis slit 4. However, conventionally, the degree of wear of the mass analysis slit 4 could not be quantitatively controlled, so that the ion beam resolving power could not be controlled. Could not be managed. However, in the first embodiment, since the degree of wear of the mass analysis slit 4 can be measured by the current value of the ammeter 17 attached to the mass analysis slit 4, the ion beam decomposition ability can be managed by the current value corresponding to the degree of wear. It becomes possible.
[0041]
If the ion beam resolving ability is not managed, the mass analysis slit 4 is worn (deteriorated), so that the ion beam resolving ability is reduced. May occur. However, in the present embodiment, since the ion beam decomposition ability can be managed, device elements such as abnormal Vth control characteristics, abnormal junction breakdown voltage, and abnormal resistance characteristics of the impurity diffusion region caused by isotope implantation can be used. Can be prevented from deteriorating the electrical characteristics. That is, formation of a defective product can be prevented.
[0042]
In the first embodiment, the ammeter 17 is attached to the mass analysis slit 4, and the degree of wear of the mass analysis slit 4 is measured by measuring the current value with the ammeter 17. Here, if the ion implantation apparatus 1 is continuously used, not only the mass analysis slit 4 but also the arc chamber 12 in the source unit 3 is continuously used. This is caused when ions collide into the arc chamber 12 and return to the original element.
[0043]
As described above, when the mass spectrometry slit 4 is worn while the ion implantation apparatus 1 is continuously used, foreign matter is accumulated in the arc chamber 12 and becomes dirty. That is, there is a certain relationship that as the degree of wear of the mass analysis slit 4 increases, the degree of contamination in the arc chamber 12 also increases. Therefore, by utilizing the fact that the degree of wear of the mass analysis slit 4 is measured by measuring the current value by the ammeter 17, the degree of contamination in the arc chamber 12 is indirectly determined by measuring the current value. Can be measured. Therefore, maintenance of the ion implantation apparatus 1 can be performed with good timing, in other words, efficiently, and the generation of foreign substances can be suppressed. Further, since the generation of foreign matters can be suppressed, the yield of semiconductor products can be improved.
[0044]
Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIG. 2 and FIGS. Here, a method for manufacturing a semiconductor device having a CMOS element will be described.
[0045]
First, a wafer 20 made of single crystal silicon processed into a disk is prepared. Then, a silicon oxide film is formed on the element formation surface of the wafer 20 by using a thermal oxidation method, and a silane gas (SiH₄) And ammonia gas (NH₃) Is used as a raw material to form a silicon nitride film by using a CVD (Chemical Vapor Deposition) method.
[0046]
Subsequently, after a resist film is formed on the silicon nitride film by using a spin coating method, the resist film is patterned by using a photolithography technique. The patterning is performed so that a resist film does not remain in an element isolation region where an element isolation groove is formed. Then, the silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using the patterned resist film as a mask. Thereafter, the wafer 20 in the element isolation region is again etched by dry etching to form an element isolation groove.
[0047]
Next, silane gas (SiH₄) And oxygen gas (O₂9), a silicon oxide film is deposited on the wafer 20 by a CVD method, and then the silicon oxide film is polished by using a CMP (Chemical Mechanical Polish) method using the silicon nitride film as a stopper. Such an element isolation layer 21 is formed.
[0048]
Then, after applying a resist film 22 on the wafer 20 on which the element isolation layer 21 is formed, the resist film 22 is patterned by exposing and developing. The patterning is performed so that the resist film 22 is formed only on the PMOS type element formation region as shown in FIG.
[0049]
Subsequently, boron (B), which is a P-type impurity, is implanted into the NMOS-type element formation region of the wafer 20 by ion implantation using the patterned resist film 22 as a mask to form a P-type well 23. When forming the P-type well 23, ion implantation with different energies and ion species is performed a plurality of times. Next, after the patterned resist film 22 is removed, a resist film 24 is formed on the wafer 20 again. Then, the resist film 24 is patterned using the photolithography technique as shown in FIG. The patterning is performed so that the resist film 24 remains only on the NMOS element formation region. Subsequently, an N-type impurity such as phosphorus (P) or arsenic (As) is implanted into the PMOS-type element formation region of the wafer 20 by ion implantation to form an N-type well 25 as shown in FIG. .
[0050]
After that, a conductive impurity is implanted into the channel formation region of the PMOS device formation region and the channel formation region of the NMOS device formation region by ion implantation using an ion implantation method, and the threshold voltage (Vth) is increased. adjust. Here, in the ion implantation apparatus 1 for performing ion implantation, since the degree of wear of the mass analysis slit 4 is measured and managed by the current value by the ammeter 17, the isotope is worn so that the isotope is implanted into the wafer 20. The mass analysis slit 4 is not used. Therefore, by using the worn mass analysis slit 4, the injection of isotope ions into the wafer 20 can be suppressed. Therefore, abnormalities in the control characteristics of the threshold voltage can be prevented.
[0051]
Next, as shown in FIG. 12, a silicon oxide film 26 is formed on the wafer 20 by using a thermal oxidation method. Then, as shown in FIG. 13, a silane gas is thermally decomposed in a nitrogen gas by a CVD method to form a polysilicon film 27 on the silicon oxide film 26. During the deposition of the polysilicon film 27, a conductive impurity such as phosphorus is added. After the polysilicon film 27 is formed, conductive impurities may be implanted into the polysilicon film 27 using an ion implantation method. Subsequently, a gate insulating film 28 and a gate electrode 29 as shown in FIG. 14 are formed by using a photolithography technique and an etching technique. Then, using a photolithography technique, a resist film is formed to cover only the PMOS element formation region of the wafer 20.
[0052]
Thereafter, the wafer 20 in which the gate insulating film 28 and the gate electrode 29 are formed and the NMOS type element formation region is covered with the resist film is transferred from the loading section 11 of the ion implantation apparatus 1 as shown in FIG. It is carried in. Then, boron (B), which is a P-type impurity, is implanted into the PMOS formation region of the wafer 20 using an ion implantation method, and a low-concentration P-type impurity diffusion region 30 is formed as shown in FIG.
[0053]
Here, the operation of the ion implantation apparatus 1 when the low concentration P-type impurity diffusion region 30 is formed by performing ion implantation on the wafer 20 will be described. In FIG. 2, first, boron, which is a P-type impurity, is ionized by collision of a thermal electron and an impurity gas in the source portion 3. Then, the ionized impurities pass through the mass analysis slit 4 as an ion beam, but a part thereof collides with the mass analysis slit 4. Since the colliding substance is an ion, a current flows through the ammeter 17 electrically connected to the mass analysis slit 4. The value of the current flowing through the ammeter 17 is a value corresponding to the degree of wear of the mass analysis slit 4. As described above, the ion implantation apparatus 1 operates while the degree of wear of the mass analysis slit 4 is monitored by the ammeter 17 electrically connected to the mass analysis slit 4. Here, the relationship between the degree of wear and the current value according to the ion implantation conditions (the energy to be implanted, the ion species to be implanted, the beam quantity to be implanted, etc.) when forming the low-concentration P-type impurity diffusion region 30 in advance is known. It is assumed that
[0054]
In addition, the ion implantation apparatus 1 is started up under a certain condition (eg, energy to be implanted, ion species to be implanted, beam quantity to be implanted), for example, once a week, not when the ion implantation apparatus 1 is in operation. The abrasion degree of the mass analysis slit may be measured by measuring the current value of the ammeter 17 electrically connected.
[0055]
Next, the ion beam that has passed through the mass analysis slit 4 enters the mass analysis unit 5. Then, in this mass analyzer 5, the ion beam is bent by the magnetic field, but boron is emitted from the mass analyzer 5. On the other hand, ions lighter or heavier than boron deviate from the trajectory of the ion beam and collide with the analyzer carbon 5a.
[0056]
Subsequently, the ion beam emitted from the mass analysis unit 5 is accelerated by the acceleration unit 6 to have a predetermined implantation energy, and then converged by the lens unit 7. Thereafter, the wafer 2 is injected into the wafer 2 (wafer 20 in FIG. 15) shown in FIG. Thus, the low-concentration P-type impurity diffusion region 30 can be formed as shown in FIG. Here, the ion implantation apparatus 1 that performs the ion implantation manages the degree of wear of the mass analysis slit 4 by measuring the degree of wear of the mass analysis slit 4 with a current value by the ammeter 17. Therefore, implantation of isotope ions into the wafer 20 can be suppressed. Accordingly, it is possible to prevent the resistance characteristic of the impurity diffusion region from being abnormal. Similarly, a low-concentration N-type impurity diffusion region 31 is formed by implanting phosphorus or arsenic as an N-type impurity into the NMOS-type element formation region.
[0057]
Next, after forming a silicon oxide film on the wafer 20 using the CVD method, anisotropic etching is performed to form side spacers 32 as shown in FIG. Subsequently, high-concentration P-type impurity diffusion regions 33 and high-concentration N-type impurity diffusion regions 34 as shown in FIG. 17 are formed by ion implantation using the above-described ion implantation apparatus 1. In this manner, a MOS element having an LDD (Lightly Doped Drain) structure can be formed.
[0058]
Subsequently, after forming cobalt (Co) on the wafer 20 by using a sputtering method, the wafer 20 is subjected to a heat treatment, so that cobalt silicide (CoSi) is formed as shown in FIG._x) A film 35 is formed. Then, after the silicon oxide film 36 is formed on the wafer 20 using the CVD method, the surface of the silicon oxide film 36 is flattened using the CMP method. After that, the connection hole 37 is formed by using a photolithography technique and an etching technique.
[0059]
Next, after a Ti / TiN film 38a is formed on the wafer 20 by using the sputtering method, a tungsten (W) film 38b is formed on the Ti / TiN film 38a by using the CVD method. Then, the Ti / TiN film 38a and the tungsten film 38b in the region other than the connection hole 37 are removed by using the CMP method. Subsequently, after an aluminum film is formed on the wafer 20 by using a sputtering method, an aluminum wiring 39 is formed by using a photolithography technique and an etching technique. Thereafter, a semiconductor device having a CMOS element formed thereon is completed by a normal semiconductor device manufacturing method.
[0060]
(Embodiment 2)
In the first embodiment, the case where the degree of wear of the mass analysis slit 4 is quantitatively measured has been described. In the second embodiment, the degree of wear of the analyzer carbon 5a in the mass analysis unit 5 is quantitatively measured. Will be described.
[0061]
FIG. 19 shows a configuration of the analyzer carbon (member) 5 a in the mass spectrometry unit 5. In FIG. 19, an ammeter 40 and a current integrator 41 are electrically connected to the analyzer carbon 5a. An ion beam passes between the analyzer carbons 5a. This ion beam is bent by the magnetic field, but the ions to be implanted flow between the analyzer carbons 5a without contacting the analyzer carbons 5a. However, the ions 42a and 42b, which are heavier than the ions to be implanted, draw a different trajectory from the ions to be implanted and collide with the analyzer carbon 5a. That is, the analyzer carbon 5a is provided to absorb ions different from the ions to be implanted.
[0062]
The analyzer carbon 5a wears due to collision of ions 42a and ions 42b which are heavier than the ions to be implanted. The degree of wear of the analyzer carbon 5a increases as the total amount of colliding ions increases.
[0063]
On the other hand, current flows through the ammeter 40 electrically connected to the analyzer carbon 5a due to the collision of individual ions, and the total amount of the flowing current is measured by the current integrator 41. From this, the total amount of colliding ions is proportional to the current integrated amount measured by the current integrator 41.
[0064]
FIG. 20 shows the relationship between the amount of current integrated by the current integrator 41 and time. In FIG. 20, the vertical axis represents the current integration amount, and the horizontal axis represents time. As the time elapses, the total number of ions that collide with the analyzer carbon 5a increases, and thus it can be seen that the current integration amount increases as the time elapses.
[0065]
As described above, the degree of wear of the analyzer carbon 5a is proportional to the total amount of colliding ions, and the total amount of colliding ions can be measured by the integrated current. From this, the degree of wear of the analyzer carbon 5a can be quantitatively measured by measuring the amount of current integration by the current integrator 41, and the timing for replacing the analyzer carbon 5a can be quantitatively determined. Therefore, efficient maintenance can be performed.
[0066]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0067]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0068]
A method for manufacturing a semiconductor device using an ion implantation apparatus capable of performing quantitative and efficient maintenance can be provided. Further, it is possible to provide a method for manufacturing a semiconductor device using an ion implantation apparatus in which the resolution of an ion beam is controlled.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an external appearance of an ion implantation apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a diagram showing a schematic configuration of an ion implantation apparatus according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a schematic configuration of a source section and a mass analysis slit.
FIG. 4 is a plan view showing a new mass analysis slit.
FIG. 5 is a cross-sectional view taken along the line AA of FIG. 4;
FIG. 6 is a plan view showing a worn mass analysis slit.
FIG. 7 is a cross-sectional view taken along the line AA of FIG. 6;
FIG. 8 is a diagram showing a relationship between time and a current value flowing in an ammeter electrically connected to a mass analysis slit.
FIG. 9 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;
FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 9;
FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 10;
FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 11;
FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 12;
FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 13;
FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 14;
FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 15;
FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 16;
FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 17;
FIG. 19 is a diagram showing a state where a current integrator is attached to the analyzer carbon according to the second embodiment of the present invention.
FIG. 20 is a diagram illustrating a relationship between time and a current integration amount.
[Explanation of symbols]
1 ion implantation equipment (semiconductor manufacturing equipment)
2 wafer
3 Source section
4 Mass analysis slit (member)
5 Mass spectrometry section
5a Analyzer carbon (member)
6 Accelerator
7 Lens section
8 Scanning section
9 End station
10 Impurity injection chamber
11 Transport unit
12 Arc chamber
13 Extraction electrode
14 Extraction power supply
15 Suppression power supply
16 Ground electrode
17 Ammeter
20 wafers
21 Device isolation layer
22 Resist film
23 P-type well
24 Resist film
25 N-type well
26 Silicon oxide film
27 polysilicon film
28 Gate insulating film
29 Gate electrode
30 Low-concentration P-type impurity diffusion region
31 Low concentration N-type impurity diffusion region
32 Side spacer
33 High-concentration P-type impurity diffusion region
34 High-concentration N-type impurity diffusion region
35 Cobalt silicide film
36 Silicon oxide film
37 Connection hole
38a Ti / TiN film
38b Tungsten film
39 aluminum wiring
40 ammeter
41 Current Integrator
42a heavy ion
42b light ion

Claims (5)

By using a semiconductor manufacturing apparatus that irradiates a semiconductor wafer with an ion beam, a method of manufacturing a semiconductor device comprising a step of implanting impurities into the semiconductor wafer,
A step of measuring the degree of wear of a member in the semiconductor manufacturing apparatus, which is worn by collision of ions in the ion beam, with the ammeter attached thereto, by measuring a current value flowing through the ammeter. A method for manufacturing a semiconductor device, comprising: By using a semiconductor manufacturing apparatus that irradiates a semiconductor wafer with an ion beam, a method of manufacturing a semiconductor device comprising a step of implanting impurities into the semiconductor wafer,
A member in the semiconductor manufacturing apparatus, which is worn due to collision of ions in the ion beam, is measured for a member to which a current integrator is attached by measuring a current integrated amount by the current integrator. A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device, comprising: irradiating a semiconductor wafer with an ion beam through a mass analysis slit to inject impurities into the semiconductor wafer.
A step of measuring the abrasion degree of the mass analysis slit, which is worn due to collision of ions in the ion beam with the ions in the ion beam, to which an ammeter is attached, by measuring a current value flowing through the ammeter. A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device, comprising: irradiating a semiconductor wafer with the ion beam through a mass analyzer that selects ions contained in the ion beam with a magnetic field, thereby implanting impurities into the semiconductor wafer.
An analyzer carbon that is in the mass spectrometer and is worn by collision of ions in the ion beam. A method for manufacturing a semiconductor device, comprising a step of measuring by measurement. By using a semiconductor manufacturing apparatus that irradiates a semiconductor wafer with an ion beam, a method of manufacturing a semiconductor device comprising a step of implanting impurities into the semiconductor wafer,
The method further comprises a step of measuring a degree of contamination in an arc chamber in the semiconductor manufacturing apparatus, which is contaminated by the collision of the ion beam, by measuring a current value flowing through a mass analysis slit to which an ammeter is attached. Manufacturing method of a semiconductor device.

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