JP2004259287A - Information processor, card member, and information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a card member and a card system having high security. <P>SOLUTION: This information processor is allowed to consume, in response to a power consumption state in a signal line for transmitting a signal from the information processor, power separated from the power consumption state. Another embodiment has at least the information processor, and a signal line connected to the information processor and can encrypt a signal from the information processor between the information processor and the signal line; and the information processor can decrypt the signal encrypted and transmitted from the signal line. A still another embodiment has at least the information processor, an information storage device and a signal line connected to at least the information processor; storage of information at least into the information storage device is carried out by encrypting the information to be stored; and the information processor can decrypt the information stored in the information storage device. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to an information processing device and an information storage device having high security. Further, the present invention relates to a card member and an information processing system. Examples of the card member include a card member having a one-chip CPU (Central Processing Unit) typified by an IC card (smart card) as an information processing device.

  A microcomputer chip with high security typified by an IC card holds information that cannot be rewritten without permission, and encrypts data to be concealed and decrypts ciphertext using an encryption key that is secret information. There is.

  As shown in FIG. 1, the basic configuration of the microcomputer includes a central processing unit 8001, a storage device 8002, and a signal line 8003 which is a path for exchanging information of each unit. The central processing unit 8001 is a device that performs a logical operation or an arithmetic operation, and the storage device 8002 is a device that stores programs and data. The storage device 8002 includes, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), and a FRAM (Ferromagnetic Anywhere). The ROM is a memory that cannot be changed, and is a memory that mainly stores programs. The RAM is a memory that can be freely rewritten, but when power supply is interrupted, stored contents are erased. Therefore, when the power supply to the device is interrupted, the contents of the RAM cannot be retained. EEPROMs and FRAMs are memories that can retain the contents even when power supply is interrupted.

  For example, FIG. 2 shows an example of a computer main body provided for a contact type IC card. FIG. 2 shows only the terminal arrangement of the chip 51 of the semiconductor device. The main body of the computer is a chip called COT arranged at the center of the card. FIG. 2 shows an example of the terminal arrangement. That is, the IC card has terminals for Vcc (supply power), GND (ground), RST (reset), I / O (input / output), and CLK (clock). The chip operates by receiving these signals externally, ie, for example, from a terminal. It should be noted that it is sufficient to use a conventional card system for the terminal itself. In this case, the power consumption can be measured by observing the signals of Vcc and GND. The measurement of this power consumption is described in John Wiley & sons, W.C. Rankl W. This is described in Effing, "Smart Card Handbook", 1997, 8.5.1.1 Passive protective mechanisms (page 263) (Non-Patent Document 1).

John Wiley & sons, W.C. Rankl W. Effing, 1997, "Smart Card Handbook", 8.5.5.1 Passive protective mechanisms (page 263).

  An object of the present invention is to provide an information processing apparatus having high security. A typical example of the information processing apparatus is a computer system, especially a microcomputer system.

  Further, the present invention provides a card member represented by an IC card (smart card) and a card system having high security.

  A more technical problem of the present invention is to reduce the relationship between data processing in a microcomputer chip and power consumption. In particular, an IC card is used for storing important information and performing an encryption process in the card. This is because programs and important information are sealed in the IC card chip. Decryption of a cipher with an IC card was considered to be as difficult as deciphering an algorithm for the cipher. However, it is suggested that the contents of the encryption processing and the encryption key may be estimated by observing the power consumption when the IC card performs the encryption processing and analyzing the state of the power consumption. This method of observing power consumption is expected to be easier than a method of directly decrypting an algorithm for encryption.

  Therefore, if the relationship between the power consumption and the processing of the chip becomes weak, it becomes difficult to estimate the processing in the IC card chip and the encryption key from the observed waveform of the power consumption. The point of the present invention is to reduce the relation between the power consumption of the microcomputer and the data to be processed. The main means is to make charging and discharging of signal lines (for example, bus lines, bit lines in RAM, word lines, etc.) one of the causes of the difference in power consumption uniform, or This is due to the fact that it differs from the original data.

  First, the possibility of deciphering a processing signal based on observation of power consumption, which is the background of the present invention, will be described. If this is understood, the gist of the present invention will be easily understood.

  The outline of the power consumption measurement described above is as follows. 2. Description of the Related Art A gate circuit of a CMOS (Complementary Metal-Oxide-Semiconductor) included in an IC card chip consumes power when the output state changes from 1 to 0 or from 0 to 1. In particular, since the signal line has a large wiring capacitance, the gate circuit consumes a large amount of power for charging and discharging when the data value of the bus changes from 1 to 0 or from 0 to 1. Therefore, if such power consumption is observed, the contents of the information processing in the IC card chip may be decoded.

  FIG. 3 shows a waveform of power consumption in one cycle of the IC card chip. Various waveforms of power consumption differ like 1101 and 1102 depending on the values of various data being processed. Such a difference in waveform with respect to a plurality of power consumptions occurs depending on data flowing through a signal line, data being processed by a central processing unit, and the like.

  At present, there are roughly two types of control methods for signal lines of an IC card chip. One is a static signal line control method, and the other is a precharge signal line control method.

  In the static signal line control method, data on the bus is not cleared. On the other hand, the precharge signal line control method is a control method in which the data on the signal line is all set to 1 or 0 and then the next data is loaded in order to clear the data each time one process is completed. Whether the precharge is made to have a signal value of 1 or 0 depends on whether the logic circuit is forward logic or reverse logic. However, the essence of the operation does not change.

  As is clear from the above description of the basic operation, the power consumption waveform is different due to the difference in the control method. From the difference in the power consumption waveform, it is possible to determine which control method is used.

  If the control method of the signal line is known, since the encryption key is determined, the influence of the bit value of the encryption key may be observed by changing the data to be processed and observing the power consumption. In addition, there is a possibility that the encryption key can be estimated by analyzing the waveform of the power consumption.

  First, the basic concept of the present invention will be described, and then the main aspects of the invention disclosed in the present application will be listed. The basic idea of the present invention is roughly divided into the following four methods.

<1. Equalizing power consumption of signal lines>
The first method is a method of reducing a difference in power consumption based on, for example, a driving method of a memory or data content in an information processing apparatus. Specifically, in addition to the power consumption on the signal line inside the microcomputer, for example, this method simply corresponds to the power consumption on the signal line and separately supplies the charging / discharging device with the signal line. By consuming power in this manner, the difference in power consumption between each transmitted signal sequence is reduced.

<2. Encryption of data in signal line>
The second method is a method in which, for example, in an information processing apparatus, data on a signal line is encrypted, and power consumption on the signal line is disturbed. That is, in this method, data is encrypted when data is put on a signal line inside the microcomputer, and the data is decrypted when the data is input to a device that receives data. Thus, power consumption in the signal line can be disturbed.

<3. Encryption of stored information>
A third method is a method of storing encrypted data in a storage unit in, for example, an information processing device. That is, in this method, for example, encrypted data is stored in a storage device of a microcomputer, and the data is decrypted and used when performing an operation or the like of the data, thereby disturbing power consumption in a signal line. .

<4. Exchange of data transfer order>
The fourth method is a method of changing the data transfer order in, for example, an information processing device. That is, when data stored in the storage device of the microcomputer is transferred on the signal line, the power consumption on the signal line is disturbed by changing the transfer order.

  The above four embodiments can be combined and used as needed. In addition, high security of the semiconductor device can be more effectively ensured by using such various forms in combination. The following method is an example of this combination.

  They are (1) a method of encrypting data in a signal line while equalizing power consumption of a signal line, (2) a method of encrypting storage information while equalizing power consumption of a signal line, and (3). ) A method of exchanging the data transfer order while making the power consumption uniform, (4) A method of encrypting the stored information while encrypting the data in the signal line, and (5) A data while encrypting the data in the signal line. (6) A method of exchanging the data transfer order while encrypting the stored information.

  Further, two or more methods can be used in combination. That is, they are: (7) a method of making the power consumption of the signal line uniform while encrypting the data in the signal line and encrypting the stored information; and (8) a method of encrypting the data in the signal line while encrypting the data in the signal line. (9) A method of achieving equalization of power consumption and exchanging data transfer order, (9) A method of encrypting storage information and exchanging data transfer order while encrypting data in a signal line, and (10) Storage. This is a method for exchanging the data transfer order while at the same time encrypting the information and making the power consumption of the signal lines uniform. Further, it is a method of (11) equalizing power consumption of signal lines, encrypting data in signal lines, encrypting stored information, and exchanging a data transfer order.

  Hereinafter, various forms will be described in detail with the above four basic forms as pillars.

(1) Equalization of Power Consumption of Signal Lines As described above, the first aspect of the present invention is a method of reducing a difference in power consumption based on, for example, a memory driving method and data contents.

  In this method, in addition to the power consumption in the signal line inside the microcomputer exemplified above, means for causing power consumption corresponding to the power consumption accompanying the transfer of digital data on the signal line to be performed, for example, In brief, a means and a device for charging and discharging electric charges are provided. This charge / discharge device consumes power corresponding to the power consumption associated with the transfer of digital data on the signal line, and reduces the difference in power consumption regardless of the transmission signal sequence. That is, the sum of the power consumed by the signal line of the microcomputer and the power consumed by the charging / discharging device is made equal. If the sum of the two power consumptions for the signal lines of each storage device is always the same, it is very difficult to know the internal information even if the power consumption data of the device can be extracted.

  Hereinafter, the means and device for charging and discharging electric charges will be simply referred to as a charging and discharging device. As described below, the charge / discharge device may be configured using, for example, a dummy data line.

  In one example according to the present invention, based on the above-described concept, when data is transferred via a signal line connecting two data processing devices inside a microcomputer, bits are transferred in accordance with a digital signal of the data. The power is inverted and input to the charging / discharging device, and the power consumed by the signal line and the power consumed by the charging / discharging device are made the same. By operating the steady current consumption generator in response to the signal generated by the control signal generator, the data to be carried on the signal line is changed so that the power consumed by the charge / discharge device and the power consumed by the signal line are always constant. The relationship between the power consumption of the microcomputer chip and the data being processed is reduced.

  The two data processing devices are specifically configured to include, for example, a ROM, a PROM, an EPROM, an EEPROM, a RAM, and a FRAM.

  Hereinafter, the present embodiment will be described including the correspondence to the difference in the control method of the signal line. That is, the input bit data differs depending on the control method of the signal line.

  In a so-called CMOS circuit, power is consumed particularly when bit inversion is performed, that is, when data changes from 0 to 1 or from 1 to 0. Thus, the power consumption of the signal line increases when bit inversion occurs. Therefore, according to the present invention, the charge / discharge device provided in the storage device causes the charge / discharge device to perform the same power consumption according to the number of times of the bit inversion. Thus, the sum of the power consumed by the signal line and the power consumed by the charging / discharging device becomes constant, and the relationship between the data flowing through the signal line and the power consumption of the microcomputer chip can be reduced. .

  The number of bit inversions in the signal line depends on the control method of the signal line. As described above, the signal line control method includes a static signal line control method and a precharge signal line control method. Each of them will be described.

  First, consider the case of the static signal line control method. In this case, the data is not cleared, and the previous data remains on the signal line. In an actual device, the signal line has substantially the same function as a capacitor. Therefore, the “remaining” described above physically means that electric charges remain. Therefore, by storing the value of the data previously on the signal line, it is possible to know how the power consumption changes in accordance with the next data.

  In order to make the power consumption equal to the power consumed by the charge / discharge device, when power consumption is performed on the signal line, data input to the charge / discharge device is not changed, and power consumption is not performed on the signal line. In some cases, data input to the charging / discharging device is changed so that the total power consumption of both devices is always constant. In this case, the power consumption is the same as the state in which bit inversion always occurs on a single signal line except for the power consumption of the internal processing that does not pass through the signal line, and becomes irrelevant to the internal processing data. In addition, the relationship between the internal processing data and the power consumption can be reduced.

  On the other hand, in the precharge signal line control method, data is cleared every time data is transferred. Therefore, the power consumption of the signal line is proportional to the number of 1s that appear when the next data to be ridden is displayed in binary notation, regardless of the data that was immediately before the signal line. In the case of reverse logic, the power consumption in the signal line is proportional to the number of zeros.

  Therefore, in the case of the precharge signal line control method, in order to make the power consumption equal to the power consumed by the charging / discharging device, the data is loaded on the signal line and the bit inversion value of the data is charged at the same time. It is to flow to the discharge device. Thus, the sum of the power consumed by the signal line and the power consumed by the charge / discharge device is always kept constant. Also in this case, the power consumption of the microcomputer is the same as the state in which bit inversion always occurs on a single signal line, except for the power consumption of the internal processing that does not pass through the signal line. Since it becomes irrelevant, the relationship between internal processing data and power consumption can be reduced.

  In many microcomputer chips, a static signal line control method and a precharge signal line control method are mixed. Therefore, in order to reduce the relationship between the power consumption change of the entire microcomputer chip and the processing data, it is necessary to use an information processing apparatus using both of the above methods.

(2) Encryption of Data on Signal Line Next, a method of encrypting data on the signal line will be described. According to this method, the power consumption of the signal line is different from the power consumption based on actual data. Therefore, even if power consumption data can be extracted from the semiconductor device, it is difficult to know the internal information of the semiconductor device.

  In the embodiment of the present invention, data transfer is performed via a signal line connecting two data processing devices (including a ROM, a PROM, an EPROM, an EEPROM, a RAM, and an FRAM) inside a microcomputer. When performing the data transfer, the data transfer side transfers the data encrypted by the encryption device that performs encryption according to the determined encryption method. On the other hand, the device that receives the data decrypts the encrypted data with a decryption device that decrypts the encrypted data and performs processing. According to such a process, the signal line performs charging and discharging with data different from the original data, so that the relationship between the internal processing data and the power consumption can be reduced. The effect of this method can be expected regardless of whether the control method of the signal line is the static method or the precharge method.

(3) Encryption of Storage Information A third method is to encrypt and store data to be stored in a storage device. In this method, for example, data is encrypted by a predetermined encryption method when writing data to a ROM that is a read-only memory, and then stored. When this data is used in a data processing device or the like, the encrypted data is decrypted by a decryption device that decrypts the encrypted data according to a predetermined method, and then input to the data processing device. In this method, the transfer data on the signal line becomes encrypted data, and the signal line performs charging and discharging with data different from the original data, so that the relationship between internal processing data and power consumption can be reduced. . The effect of this method can be expected regardless of whether the control method of the signal line is the static method or the precharge method.

(4) Exchange of Data Transfer Order A fourth method is to change the transfer order of data to be put on a signal line from the original. According to this method, for example, data to be transferred is transferred in the order of A, B, C, D, and E at every clock, but is transferred in the order of E, A, B, D, and C. This data transfer order is, of course, an example. With this method, the charge / discharge pattern of the signal line is not performed in the original order. Therefore, the signal line performs charging and discharging with data different from the original data, so that the relationship between the internal processing data and the power consumption can be reduced. The effect of this method can be expected regardless of whether the control method of the signal line is the static method or the precharge method.

  The main modes of the present invention are listed below.

  According to a first aspect of the present invention, there is provided an information processing apparatus and a signal line connected to the first information processing apparatus, and a power consumption state of the signal line transmitting a signal from the information processing apparatus. The information processing apparatus is characterized in that power consumption different from the power consumption state is enabled in response to the power consumption.

A second embodiment has a first information processing device, a second information processing device, and a signal line connecting the two, and transmits a signal from at least one of the first and second information processing devices. A second power consumption state is determined corresponding to a first power consumption state in the signal line to be transmitted, and a first power consumption and a second power consumption in the signal line are determined. Are enabled during periods of conflict with each other.

  A third mode has an information processing device and a signal line connected to the information processing device, and corresponds to a first power consumption state of the signal line transmitting a signal of the information processing device. Information characterized in that a second power consumption state is determined, and that the sum of the first power consumption and the second power consumption in the signal line is set to a desired value. Processing device.

  A fourth mode has an information processing device and a signal line connected to the information processing device, and corresponds to a first power consumption state of the signal line transmitting a signal of the information processing device. During a period in which the second power consumption state is determined and the first power consumption is performed on the signal line, the second power is not consumed and the first power consumption on the signal line is not performed. The information processing apparatus is characterized in that the second power can be consumed during a period in which the power is not consumed.

  A fifth mode has an information processing device and a signal line connected to the information processing device, and the power of the signal is inverted in response to the inversion of the signal value on the signal line that transmits the digital signal of the information processing device. An information processing apparatus characterized in that it can be consumed.

  According to a sixth aspect, a first information processing device, a second information processing device, a signal line connecting the two, and a digital signal from at least one of the first or second information processing device. Means for consuming the second power in response to the inversion of the signal value of the transfer signal in the signal line in response to the first power consumption state in the signal line; Processing device.

  A seventh embodiment includes an information processing device and a signal line connected to the information processing device, and a signal from the information processing device can be encrypted between the information processing device and the signal line. And an information processing apparatus capable of decoding a signal encrypted and transferred from the signal line.

  An eighth aspect has a first information processing device, a second information processing device, and a signal line connecting the two, and at least one of the first information processing device and the second information processing device. Between the user and the signal line, it is possible to encrypt a signal from the first information processing device or the second information processing device, and to decode a signal transferred from the signal line. An information processing apparatus characterized by the following.

  A ninth embodiment has a first information processing device, a second information processing device, and a signal line connecting the two, encrypts a signal from the first information processing device, and performs the encryption. Decrypts the input signal from the first information processing apparatus and inputs the decrypted signal to the second information processing apparatus, and encrypts the output of the second information processing apparatus. The information processing device is characterized in that the signal can be decoded and input to the first information processing device.

  A tenth aspect has an information processing device, an information storage device, and at least a signal line connected to the information processing device, and at least storing information in the information storage device encrypts the information to be stored. An information processing apparatus characterized by being capable of decoding information stored in the information storage device.

  An eleventh aspect has an information processing device, an information storage device, and at least a signal line connected to the information processing device, and at least storing information in the information storage device encrypts the information to be stored. An information processing apparatus characterized in that the information stored in the information storage apparatus is decoded and input to the information processing apparatus via the signal line.

  A twelfth aspect has an information processing device and a signal line connected to the information processing device, and a signal sequence output from the information processing device is transmitted through the signal line in a different order. And an information processing apparatus capable of restoring the changed order of the signal sequence.

  A thirteenth mode has an information processing device and a signal line connected to the first information processing device, and corresponds to a power consumption state of the signal line transmitting a signal from the information processing device. The card member is characterized in that power consumption different from the power consumption state is enabled.

  The present application can provide various card members having the above-mentioned various information processing devices or the above-mentioned various information storage devices, in addition to the examples given here, while avoiding their listing. Furthermore, the present application can provide various card members having an information processing device or various information storage devices described below.

  A fourteenth aspect has at least a terminal and a card member connectable to the terminal, wherein the card member has an information processing device and a signal line connected to the first information processing device. And a card which is capable of consuming power different from the power consumption state in response to the power consumption state of the signal line transmitting a signal from the information processing device. System.

  In addition, this application can provide various card systems having the information processing device or the information storage device other than the examples listed here, although the list is avoided. Further, the present application can provide an information processing device to be described later or various card systems having the above-described various information storage devices.

  In addition, further embodiments of the present invention are listed. From these, various aspects of the present invention will be more specifically understood.

  In a fifteenth embodiment, two data processing devices A and B and a signal line connecting them (a signal line controlled by a control method that does not clear data on a bus line by a control signal: a static signal line), a control signal generation In a microcomputer having a device, when information is transferred between the data processing devices A and B via the signal line, the sum of the power consumed by the signal line and the power consumed by the charge / discharge device is In accordance with the signal from the control signal generator, the data (DATA) output from the data processing device A, the data (PBD) immediately on the signal line, and the charge / discharge immediately before The data (CDD) input to the device is input to the charging / discharging device according to the following Table 1, and the data (DATA) output from the data processing device A is provided on the signal line. An information processing apparatus characterized by having a power generating apparatus C connected to the data processing device A to enter.

  Here, in order to facilitate understanding, the term “power generation device” is used in the specification of the present application, but as described above, in addition to the power consumption in the signal line, This is a means for consuming power corresponding to power consumption associated with data transfer on the signal line. That is, "power generation" in the above term means that the power consumption of the signal line is made uniform and basically the same power is consumed regardless of the signal sequence to be transmitted. Note that this device does not generally "generate power".

  In a sixteenth mode, two data processing devices A and B and a signal line connecting them (a signal line controlled by a control method that does not clear data on a bus line by a control signal: a static signal line), a control signal generation In a microcomputer having a device, when information is transferred between the data processing devices A and B via the signal line, the sum of the power consumed by the signal line and the power consumed by the charge / discharge device is In accordance with the signal from the control signal generator, the data (DATA) output from the data processing device A, the data (PBD) immediately on the signal line, and the charge / discharge immediately before The data (CDD) input to the device is input to the charging / discharging device according to Table 1 above, and the data (DATA) output from the data processing device A is connected to the signal line. The data processing device A to enter, respectively connected power generator C B, which is an information processing apparatus characterized by having a D (C and D including the case is the same).

  According to a seventeenth mode, a first data processing device, a second data processing device, a signal line connecting them, a precharge signal control unit, and a first power consumed by the signal line are provided. And at least means for consuming a second power different from the power consumption of the signal line, wherein the first or second data processing device has a means for consuming the second power. And the second or first data processing device is connected to the control means for the precharge signal, and performs signal transfer between the first and second data processing devices via the signal line. , An information processing apparatus characterized in that the sum of the first power consumption and the second power consumption is set to a predetermined value.

  An eighteenth embodiment is directed to a microcomputer including a data processing device A, a data processing device B, a signal line connecting these devices, and a precharge signal line control device for precharging the signal line. Is connected to the precharge signal line controller, and is also connected to a complementary precharge bus controller, the precharge bus controller being connected to the data signal line, the complementary precharge bus controller Is connected to the charging / discharging device, and transmits data flowing to the bus immediately after precharging the data signal line so that the sum of power consumption in the data signal line and power consumed in the charging / discharging device becomes constant. An information processing device comprising the complementary precharge bus control device for inverting a bit and inputting the inverted signal to the charge / discharge device.

  A nineteenth embodiment is an information processing apparatus having two data processing devices A and B, a signal line connecting the data processing devices A and B, and a precharge signal line control device for precharging the signal line. An information processing apparatus, comprising: a signal line including positive logic and negative logic signal lines having the same wiring capacitance with an inverting device interposed therebetween.

  According to a twentieth aspect, in an information processing apparatus including a data processing device A, a data processing device B, and a signal line connecting the data processing device A and the data processing device B, an encryption device for encrypting the data of the signal line and the data processing device B is provided. An information processing apparatus characterized in that the apparatus is provided between a data processing apparatus A and a signal line.

  According to a twenty-first aspect, in an information processing apparatus having a data processing device A, a data processing device B, and a signal line connecting the data processing device A and the data processing device B, an encryption / decryption process for encrypting / decrypting the signal line and data in the data processing device B is performed. An information processing apparatus comprising a decoding device between a data processing device A and a signal line and between a data processing device B and a signal line.

  The following are, in particular, various embodiments of the main invention relating to the information storage device of the present application.

  According to a twenty-first aspect, in an information processing apparatus having a data processing device, an information storage device, and a signal line connecting the data processing device and the information storage device, an encryption device is provided between the data processing device and the signal line. An information processing device characterized by having a decryption device between them.

  According to a twenty-second aspect, a plurality of pieces of information can be stored, storage locations of the plurality of pieces of stored information are distinguished by addresses, and information is encrypted when information is stored in a recordable / readable information storage device. An information storage device comprising: an encryption device that performs encryption and a decryption device that reads information.

  The twenty-third mode is a data processing device, an information storage device that stores information by encrypting information in advance, a signal line connecting the information storage device and the data processing device, and a decoding device that decrypts the encrypted information. An information processing device characterized by having an encoding device.

  A twenty-fourth aspect is an information transfer control which is connected to a storage device, a data processing device including the storage device, and a signal line connecting the storage device, and controls information transfer between the storage device and the data processing device including the storage device. In the device, an address register for storing an address where information of a transfer source is stored, an address register for storing an address of a transfer destination, and a counter for storing a numerical value for counting the number of information to be transferred An arithmetic circuit for decrementing the value of the counter, a data buffer for temporarily storing data to be transferred between the storage devices, an arithmetic circuit for updating the value of the address register, and a transfer order of the transfer address. An information transfer control device having a randomizing circuit.

  The main aspects of the present invention related to the present invention have been described above. Further, in the present invention, the charge / discharge device includes a dummy signal line having a wiring capacity equivalent to a signal line for delivering data. Can be used. Furthermore, a device having a precharge dummy signal line equivalent to a signal line for delivering data can be used as the charge / discharge device.

  In the mode using key information, an automatic encryption key setting device that automatically sets key information used for encryption at the time of startup can be used. Alternatively, in a mode using key information, an automatic encryption key resetting apparatus that automatically resets key information used for encryption periodically can be used.

  Further, an encryption / decryption device that uses the address information of the storage device as a part of the encryption key information can be used. Further, the encryption / decryption device may be an encryption / decryption device having means for setting and changing encryption key information.

  Further, the information processing device of the present invention includes a data processing device B having an area for storing key information used for encryption and encryption information necessary for decryption such as an encryption method, and a data processing device B. It can be configured using a decryption device that performs decryption based on the stored encryption information. In addition, as an encryption / decryption device, the storage device is divided into a plurality of regions, and an encryption region designation device is provided for designating the presence or absence of encryption for each region. It can be configured using an encryption / decryption device that can be specified according to the area of the device. Also, the encryption / decryption device can be configured using an encryption / decryption device that does not perform encryption for a specific data pattern.

  Further, the information processing apparatus according to the present invention can be configured using an automatic encryption key setting apparatus that automatically sets key information used for encryption at the time of startup. Furthermore, the present invention can be configured using an encryption key automatic resetting device that automatically resets key information used for encryption periodically.

  Further, the information processing apparatus of the present invention can store a plurality of pieces of information, distinguishes storage locations of the plurality of pieces of stored information by addresses, and stores information in a recordable / readable information storage device. An encryption device for encrypting information and a decryption device for reading information can be used. Furthermore, an automatic encryption key setting device that automatically initializes the encryption key of the encryption / decryption device can be used. Further, the information processing apparatus of the present invention refers to an encryption area designation register for designating a storage area to be encrypted, a value of the encryption area designation register, and address information to determine whether or not to perform encryption. It is possible to use an encrypted area determination device that makes the determination as to whether or not only the information in the specific storage area can be encrypted.

  The present invention can provide an information processing device having high security. The present invention can provide an information storage device having high security. Further, the present invention can provide a card member having high security and an information processing system.

  FIG. 5 is a basic configuration diagram illustrating an outline of an information processing apparatus for describing the first embodiment of the present invention. Of course, FIG. 5 illustrates only the main part of the portion of the information processing apparatus according to the present invention. The other parts of the information processing apparatus suffice to use the usual configuration.

  The information processing device of the example of the present embodiment includes a data processing device A (ROM) 0101 (Read Only Memory), a data processing device B (CPU) 0102 (Central Processing Unit: central processing device), Are connected by a signal line (bus line) 0113. The power generation device C 0114 is provided on the information processing device A side.

  Examples of the power generation device C include exclusive OR operation devices (EXOR) 0103 and 0104, an inverter 0105, a PMOS gate circuit 0107, an NMOS gate circuit 0108, a resistor R0109, a capacitor C 0110, and a latch for temporarily storing data. It has a circuit (flip-flop) and the like and is configured as shown in the figure. Note that the read-only memory is a memory dedicated to reading data, and cannot write data. The latch circuit for temporarily storing data includes 0111 and 0112.

  Here, the display of the data processing device (ROM) or the like means a data processing device mainly including a ROM. The same applies to other information processing devices (RAM).

  In this example, the resistance value of the resistor R 0109 is equal to the resistance value of the signal line, and the capacitance of the capacitor C0110 is equal to the signal capacitance of the signal line. Here, for the sake of simplicity, it is assumed that the size of the signal line is 1 bit and the CPU is an 8-bit processor. Note that the size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  First, how a conventional semiconductor memory device not using the present invention can estimate internal information of a semiconductor device from observation of power consumption via a signal line will be described. This description will fully understand the effectiveness of the present invention.

  When data stored in the data processing device A (ROM) 0101 is transferred to the data processing device B (CPU) 0102, the data must be transferred on a signal line (bus line) 0113.

  Here, if there is an observer observing the power consumption required for data transfer of the signal line (bus line) 0113, the observer observes the following facts without the power generation device C according to the present invention. You can do it. That is, assuming that the data is arranged in the order of “01010001001”, by observing the power consumption that occurs when bits are inverted from 0 to 1 and from 1 to 0, “inversion, inversion, uninversion, uninversion, inversion, , Inversion, inversion, inversion, non-inversion, and inversion. "

The “inverted and non-inverted” data sequence based on the power consumption observation result is determined to be in the following two states based on the value of the data bit immediately before the data sequence. That is, when the value of the data bit immediately before the data is unknown, there are the following two states.
(1) Assuming that the immediately preceding data is 0, the data string is 01000101001.
(2) Assuming that the immediately preceding data is 1, the data string is 10111010110.

  As described above, in the analysis based on the observation of the power consumption, a data string originally having 2 to the 12th power, that is, 4096 kinds of data strings is reduced to only the above two kinds. Therefore, the possibility of the information which exists very much is estimated up to only two possibilities. Therefore, if there are only two possibilities, the internal information can be sufficiently grasped from the possibility. .

  The present invention provides one measure for preventing such power consumption analysis.

  Here, prior to describing the operation of the information processing apparatus of the present invention, an example of a power generating apparatus according to the present invention will be described. Of course, a specific configuration other than the illustrated power generation device can be considered. The same applies to the following cases.

  A portion 0115 surrounded by a dotted line in FIG. 5 indicates a circuit region where a logical operation of the power generation device is performed. Reference numerals 0203 and 0204 are circuits for performing an exclusive OR operation. Reference numeral 0205 denotes an inverting circuit which outputs “1” in response to an input of “0”.

  The logical expression of this circuit is as follows.

R = not (CDD exor (PBD exor DATA))
The output of this logical expression is as shown in Table 1 above. This can be easily understood from the exclusive OR (exor) shown in Table 2.

  Here, CDD is the data input to the charging / discharging device immediately before the data signal to be considered, PBD is the data on the signal line immediately before the data signal to be considered, and DATA is the data processing device A. This is the data output from.

As a method for temporarily storing PBD or CDD data, a flip-flop illustrated in FIG. 6 can be given. Here, the NANDs (902, 903, 904, 905) are arithmetic units that output according to Table 3. NOT (901) is a device for inverting bits, and is the same as the bit inversion circuit in FIG.

  In the flip-flop circuit for temporarily storing data shown in FIG. 6, when the control signal is 1, the PBD outputs the data on the bus, and when the control signal is 0, the PBD keeps its previous value. A more specific usage form of the flip-flop circuit will be described later.

Actually, if the control signal is indicated as CS (Control Signal) and the data of the bus line is indicated as BUS, the operation of this flip-flop circuit can be expressed by the following four logical expressions.
x = BUS nand CS
y = (not BUS) and CS
PBD = x nd PBD
z = y nd PBD
Now, assuming that the control signal CS is 1, since nand inverts the bit, the above logical expression is as follows.
x = not BUS
y = BUS
z = y nd PBD
PBD = x and z
Therefore, if BUS is 1, PBD = 1 since 0 nd z = 1. If BUS is 0, z = 0 nd PBD = 1, PBD = (notBUS) nd 1 = BUS = 0. Thus, PBD coincides with BUS.

  On the other hand, when the control signal is 0, since both x and y are 1, the PBD holds the previous value.

<Operation in First Embodiment of the Present Invention>
Next, a data transfer process in the information processing apparatus of the present example will be specifically described with reference to FIG.

  Consider a case where an instruction [EXOR R2, R4], which is a part of a program, is transferred from the ROM 0101 to the CPU through the signal line 0113. This is a hexadecimal number corresponding to the machine language [CA 24]. When this data is sent to the signal line, it becomes a bit pattern of 11001010001000100.

  First, consider the following initial conditions. First, it is assumed that the data on the signal line immediately before this data is 0. Second, it is assumed that the capacitor of the steady-state power generation device C is in a charged state. That is, this state corresponds to the state where data 1 is on. Thirdly, it is assumed that a control signal for notifying that data has got on the bus from the CPU is input to the latches 0111 and 0112.

[(1) Transfer of the first "1" in the signal sequence = conversion operation of "1" from data "0"]
First, when the first 1 gets on, the signal line 0113 is charged, and the 1 is on the signal line 0113. At this time, the same data is input to the steady power consumption generator C0114. At this time, how the power generation device C0114 operates will be described in detail.

  Data 1 from the CPU is input to the exclusive OR operation unit 0103. At the same time, upon receiving a data output signal from the CPU, the latch circuit 0112 inputs the value 0 immediately before the held signal line 0113 to the exclusive logical operation device 0103. At this time, since the exclusive logical operation device 0103 performs the operation according to Table 2 below, the exclusive OR of 0 and 1 becomes 1. This value is input to the exclusive OR operation device 0104.

  Upon receiving the data output signal from the CPU, the latch circuit 0111 inputs the held data (charge) 1 of the capacitor 0110 to the exclusive OR operation device 0104. 0 is output according to Table 2. This value is input to the inverter 0105, and outputs the value 1 according to Table 3 described above.

  This value of 1 is input to the PMOS gate 0107. The PMOS is energized only when the gate voltage is LOW, and is not energized in this case. On the other hand, the value 1 output from the inverter 0105 is input to the NMOS gate 0108. As a result, the gate 0108 conducts, and the capacitor 0111 discharges. As a result, the sum of the power consumption in the signal line 0113 and the capacitor 0111 becomes the same as when one signal line is charged.

[(2) Conversion operation of data from “1” to “1”]
The next data is 1, and the data of the immediately preceding signal line 0113 is also 1. The capacitor is charged. The operation of the steady power consumption generator at this time is as follows.

First, when the data 1 from the information processing device B (CPU) 0102 rides, the signal line 0113 is already in a charged state, and the signal line 0113 is not charged. At this time, the same data is input to the steady power consumption generator C0114. Data 1 from the information processing device B (CPU) 0102 is input to the exclusive OR operation device 0104.
At the same time, upon receiving a data output signal from the information processing device B (CPU) 0102, the latch circuit 0112 inputs the value 1 immediately before the held signal line 0113 to the exclusive logical operation device 0103. At this time, since the exclusive logical operation device 0103 performs the operation according to Table 2, the exclusive OR of 1 and 1 is 0. This value is input to the exclusive OR operation device 0104.

  In response to the data output signal from the information processing device B (CPU) 0102, the latch circuit 0111 inputs the held data (charge) 1 of the capacitor 0110 to the exclusive OR operation device 0104. The logical sum operation unit 0104 outputs 1 according to Table 2. This value is input to the inverter 0105 and outputs a value 0 according to Table 3.

  This value of 0 is input to the PMOS gate 0107. This PMOS is energized only when the gate voltage is Low. Therefore, in this case, the power is turned on, Vdd is supplied, and the capacitor 0110 is charged. On the other hand, the value 0 output from the inverter 0105 is input to the NMOS gate 0108. As a result, the NMOS gate 0108 does not conduct. Here, the capacitor 0110 consumes one bit of power, so that the sum of power consumption in the signal line 0113 and the capacitor 0110 becomes the same as when one signal line is charged.

[(3) Conversion operation of data from “1” to “0”]
The next data is 0. The data of the signal line 0113 is 1, and the capacitor 0110 is in a discharged state. The operation of the power generation device 0114 at this time is as follows.

  First, when the data 0 from the information processing apparatus B (CPU) 0102 rides, the signal line 0113 is in a charged state, and thus the signal line 0113 is discharged. The electric charge on the signal line 0113 consumes 1-bit power by discharging. At this time, the same data 0 is input to the steady power consumption generator C0114. Data 0 from the information processing device B (CPU) 0102 is input to the exclusive OR operation device 0103. At the same time, upon receiving a data output signal from the information processing device B (CPU) 0102, the latch circuit 0112 inputs the value 1 immediately before the held signal line 0113 to the exclusive logical operation device 0103. At this time, since the exclusive logical operation device 0103 performs the operation according to Table 2, the exclusive OR of 0 and 1 becomes 1. This value is input to the exclusive OR operation device 0104.

  Upon receiving a data output signal from the information processing device B (CPU) 0102, the latch circuit 0111 inputs the data (charge) 0 of the capacitor 0110 held therein to the exclusive OR operation device 0104, so that the exclusive operation is performed. The logical sum operation unit 0104 outputs 1 according to Table 2. This value is input to the inverter 0105 and outputs a value 0 according to Table 3.

  This value of 0 is input to the PMOS gate 0107. This PMOS is energized only when the gate voltage is Low. Accordingly, in this case, the power is turned on, Vdd is supplied, and the capacitor 0110 is charged. On the other hand, the value 0 output from the inverter 0105 is input to the NMOS gate 0108. As a result, the NMOS gate 0108 does not conduct. As a result, the sum of the power consumption in the signal line 0113 and the capacitor 0110 becomes the same as when one signal line is charged.

  Hereinafter, all the cases shown in Table 1 can be derived in exactly the same flow. FIG. 7B shows the flow of data and the state of the capacitor with respect to the instruction code “1100101000100100”.

  In this way, for all patterns, the sum of the power consumption of the signal line 0113 and the capacitor 0110 is the same as the power consumed in 1-bit charging / discharging of the signal line 0113. Therefore, it is difficult to estimate data on the signal line 0113 by checking the power consumption of the device.

  By applying the semiconductor integrated circuit device incorporating the information processing device manufactured as described above to a card member, a high-security card member can be provided. The arrangement of the semiconductor integrated circuit device on the card member is basically the same as that shown in FIG. Although there are a contact type and a non-contact type as a card member, the present invention can be naturally applied to any type.

  The chip operates by receiving these signals from the outside, that is, for example, from a terminal.

  It should be noted that it is sufficient to use a conventional card system for the terminal itself. The operation of the card system will be briefly described below. FIG. 3 illustrates the concept of this card system.

  An example is shown in which an IC card 52 has a chip 51 and exchanges data with a reader / writer 53. The reader / writer includes a control processor 54 and a magnetic disk 55 serving as a database. First, the reader / writer 53 inquires the IC card 52 about the ID. First, an inquiry is made from the reader / writer 53 to the IC card 52 for an ID (IDENTIFICATION), for example, a name code or an identification code for specifying a person in charge of the card. FIG. 3 shows this state as (1). This name code or recognition code is stored in a predetermined area in the IC chip. The IC card replies the name code to the reader / writer. FIG. 3 shows this state as (2). The reader / writer retrieves the name code in the database 53 and acquires the key code on the database.

  The reader / writer sends a random number to the IC card. This random number is generated in a circuit by, for example, an MPU in a reader / writer. A random number can be supplied from the server side via a LAN or the like. Upon receiving the random number, the IC card receives an instruction from the reader / writer by a command, and creates a random number encrypted by the key code generated by the key code generation unit.

  On the other hand, the reader / writer encrypts the same random number sent to the IC card using the key code obtained from the database in the same manner as the IC card. The result of the encrypted random number thus obtained is compared with the encrypted random number from the preceding IC card, and if a match is obtained, mutual recognition between the IC card and the reader / writer is completed, and the IC card Legitimacy is recognized.

  In this way, in the present system, when this key code is transmitted to the reader / writer, the reader / writer searches the ID in the magnetic disk and recognizes that the ID is based on the correctly registered key code.

  The generated key code (ID code) of the IC card is stored in the database together with the name code or the recognition code.

  The generated key code can be used for personal authentication and forgery check when the IC card is used as electronic money, and for mutual authentication between the IC card and the reader / writer.

  The above-described system can be applied to many fields such as payment at a general store, purchase of a ticket, ticketing with a commuter pass, checking of a license, telephone using a telephone card, and the like.

  It goes without saying that the card member and the card system as described above can be implemented by using various aspects of the invention described below.

  Next, various embodiments of the information processing apparatus according to the present invention will be described.

  FIG. 8 is a schematic basic configuration diagram of an information processing apparatus for explaining a second embodiment of the present invention. This example is an example in which signals are transmitted bidirectionally between information processing devices, and the power generation device is shared by both information processing devices.

  In the information processing apparatus of this embodiment, an information processing apparatus A (CPU) 0201 and an information processing apparatus B (RAM) 0202 (Pandom Access Memory: a memory capable of reading and writing data) are connected by a signal line (bus line) 0213. I have. A power generation device C0114 is provided for the information processing device A (CPU) 0201 and the information processing device B (RAM) 0202.

  The power generation device C0114 includes an exclusive OR operation device (EXOR) 0203, 0204, an inverter 0205, an NMOS gate circuit 0207, a PMOS gate circuit 0208, a resistor R0209, a capacitor C0210, and a latch circuit (flip-flop) for temporarily storing data. P) 0211 and 0212. Here, it is assumed that the resistance value of the resistor R0209 is equal to the resistance value of the signal line, and the capacitance of the capacitor C0210 is equal to the signal capacitance of the signal line. Here, for simplicity, the size of the signal line is 1 bit, and the CPU is an 8-bit processor. Note that the size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  In the present embodiment, a part of the configuration of the first embodiment of the information processing apparatus described above is used as it is. In particular, when data is transferred from the information processing device A (CPU) 0201 to the information processing device B (RAM) 0202 via the signal line 0213, the data is transferred from the ROM in the example of the information processing device of the first embodiment to the RAM. The operation is exactly the same as the operation of the steady power consumption generator when transferring data.

  What is characteristic in this example is that signals are transmitted bidirectionally between information processing apparatuses. That is, it is not a one-sided data transfer as in the example of the information processing apparatus of the first embodiment, but only a data transfer from the information processing apparatus A (CPU) 0201 to the information processing apparatus B (RAM) 0202. That is, data transfer from the information processing apparatus B (RAM) 0202 to the information processing apparatus A (CPU) 0201 is also performed.

  Accordingly, the steady-state power consumption generator 0114 is connected so as to fulfill its function when transferring both data.

  In this example, the information processing apparatus A (CPU) 0201 sends a data read signal to the information processing apparatus B (RAM) 0202, and the information processing apparatus B (RAM) 0202 transmits the data read signal to the signal line. At the same time, the data is also transmitted to the exclusive OR operation device 0203. Subsequent operations are the same as those of the information processing apparatus according to the first embodiment. In the example of the information processing apparatus according to the first embodiment, a steady power consumption generation apparatus for transferring data from the information processing apparatus A (ROM) 0101 to the information processing apparatus B (CPU) 0102. The operation is exactly the same as the operation of 0114. Therefore, detailed description of the operation is omitted.

  In FIG. 8, the distance between information processing device A (CPU) 0201 and steady power consumption generating device C0114 is shorter than the distance between information processing device B (RAM) 0202 and steady power consumption generating device C0114. ing. However, in an actual configuration, the signal line for exchanging data between the information processing apparatus A (CPU) 0201 or the information processing apparatus B (CPU) 0202 and the stationary power consumption generation apparatus C 0114 is located at substantially the same distance, It is assumed that the length is shorter than the signal line between the processing device A (CPU) 0201 or the information processing device B (CPU) 0202 and the signal line 0213. At this time, it is difficult to estimate the data on the signal line 0213 by examining the power consumption.

  FIG. 9 is a basic configuration diagram of an information processing apparatus for describing a modification of the second embodiment of the present invention. This example is an example in which a signal is transmitted bidirectionally between information processing devices, and a power generation device is provided corresponding to both information processing devices.

  In the information processing apparatus of this embodiment, an information processing apparatus A (CPU) 0251 and an information processing apparatus B (RAM) 0252 are connected by a signal line (bus line) 0263. Then, a power generation device C0115 and a power generation device D0116 are provided for both of the information processing devices.

  The power generation device C0115 includes an exclusive OR operation device (EXOR) 0253, 0254, an inverter 0255, a PMOS gate circuit 0257, an NMOS gate circuit 0258, a resistor R 0259, a capacitor C0260, a latch circuit for temporarily storing data (flip-flop). P) 0261 and 0262. The power generation device D includes an exclusive OR operation device (EXOR) 0264, 0265, an inverter 0266, a PMOS gate circuit 0268, an NMOS gate circuit 0269, a resistor R0270, a capacitor C0271, a latch circuit for temporarily storing data (a flip-flop ) 0272 and 0273.

  Next, the operation is considered under the following conditions. The resistance value of the resistor R0259 is equal to the resistance value of the signal line, and the capacitance of the capacitor C0260 is equal to the signal capacitance of the signal line.

  Here, for simplicity, the size of the signal line is 1 bit, and the CPU is an 8-bit processor. Note that the size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  In this example, a part of the configuration of the example of the information processing apparatus according to the first embodiment is used as it is. In particular, when data is transferred from the information processing device A (CPU) 0251 to the information processing device B (RAM) 0252 via the signal line 0263, the information processing device A in the example of the information processing device of the first embodiment is used. It performs exactly the same operation as the operation of the steady power consumption generator when data is transferred from the (ROM) 0101 to the information processing device B (CPU) 0102. Therefore, the detailed description is omitted.

  What is characteristic in this example is that signal transmission between the information processing apparatuses is performed bidirectionally, instead of unilateral data transfer as in the example of the information processing apparatus in the first embodiment. That is, in this example, not only data transfer from the information processing apparatus A (CPU) 0251 to the information processing apparatus B (RAM) 0252, but also transfer of data from the information processing apparatus B (RAM) 0252 to the information processing apparatus A (CPU) 0251. It also performs data transfer. In the present embodiment, the information processing device A (CPU) 0251 sends a data read signal to the information processing device B (RAM) 0252, and the information processing device B (RAM) 0252 receives the At the same time as putting the data on the line 0263, the data is also transmitted to the exclusive OR operation device 0264 in the steady power consumption generator D0116. The stationary power consumption generator D0116 is the same as the stationary power consumption generator C0115. Then, the subsequent operations are the same as those in the example of the information processing apparatus according to the first embodiment, except for the steady consumption when data is transferred from the information processing apparatus A (ROM) 0101 to the information processing apparatus B (CPU) 0102. The operation is exactly the same as that of the power generation device. At this time, it is difficult to estimate the data on the signal line 0263 by checking the power consumption.

  FIG. 10 is a basic configuration diagram of an information processing apparatus for explaining a third embodiment of the invention.

  The basic structure of this embodiment is the same as that of the first embodiment. In this example, a dummy signal line is used. That is, in this example, the portion of the resistor 0109 and the capacitor 0110 illustrated in the first embodiment is replaced with the dummy signal line 0309.

  In the information processing apparatus of this embodiment, a data processing device A (ROM) 0301 and a data processing device B (CPU) 0302 are connected by a signal line (bus line) 0312. Further, a power generation device C0117 is provided for the data processing device A (ROM) 0301. The power generation device C0117 includes an exclusive OR operation device (EXOR) 0303, 0304, an inverter 0305, a PMOS gate circuit 0307, an NMOS gate circuit 0308, a dummy signal line 0309, a latch circuit (flip-flop) 0310 for temporarily storing data. , 0311.

  Here, the capacitance of the dummy signal line 0309 is assumed to be equal to the capacitance of the signal line 0312, and the resistance value is substantially the same as that of the signal line 0312. That is, it may be considered that the dummy signal line 0309 uses exactly the same signal line as the signal line 0312. Here, for the sake of simplicity, it is assumed that the size of the signal line is 1 bit and the CPU is an 8-bit processor. Note that the size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  In this example, the capacitance of the dummy signal line 0309 plays a role equivalent to that of the resistor 0109 and the capacitor 0110 illustrated in the first embodiment. Therefore, the operation of this example is basically the same as that of the information processing apparatus according to the first embodiment. Therefore, the detailed description is omitted.

  FIG. 11 is a basic configuration diagram of an information processing apparatus for explaining a fourth embodiment of the invention. This is an example of a precharge signal line control method and having a power generation device.

  In the information processing apparatus of this embodiment, a data processing device A (ROM) 0401 and a data processing device B (CPU) 0402 are connected by a signal line 0408. The power generation device C0118 is provided on the data processing device A (ROM) 0401 side. In addition, since the present example is a control of a precharge method, it has a precharge signal line control device 0407.

  The precharge signal line control device 0407 has two PMOS gate circuits 0409 and 0410, and a data control signal from the data processing device B (CPU) 0402 is input to the gate portion. Vdd is connected to the source side, and supplies Vdd to the signal line 0408 and the power generation device C0118 according to a control signal from the data processing device B (CPU) 0402. The power generation device C0118 includes an NMOS gate circuit 0404, a resistor (R) 0405, a capacitor C0406, and an AND operation circuit 0411. Here, it is assumed that the resistance value of the resistor R0405 is equal to the resistance value of the signal line, and the capacitance of the capacitor C0406 is equal to the signal capacitance of the signal line. Here, for the sake of simplicity, it is assumed that the size of the signal line is 1 bit and the CPU is an 8-bit processor. The size of the signal line is not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  When transferring data stored in the data processing device A (ROM) 0401 to the data processing device B (CPU) 0402, the data signal must be transferred on a signal line (bus line) 0408.

  Here, consider a case where there is an observer who observes the power consumption required for data transfer of the signal line (bus line) 0408. Now, suppose that the data is tentatively arranged as "01010001001". When there is no steady-state power generation device C0118, the power sequence generated when the data value changes from 0 to 1 is observed by the operation of the precharge signal line control device 0407. It can be seen directly that it is "01010001001". Here, it is assumed that positive logic is used. That is, when the potential of the signal line is LOW, the data value is 0, and when the potential of the signal line is HIGH, the data value corresponds to 1. Of course, in the case of negative logic as well, the data string can be estimated by observing the power consumption that occurs when the data value changes from 1 to 0.

  The present invention provides one measure for preventing such power consumption analysis. The data transfer process of this example is as follows.

  It is assumed that an instruction [EXOR R2, R4], which is a part of a program, is transferred from the ROM 0401 to the data processing device B (CPU) 0402 through the signal line 0408. This is a hexadecimal number corresponding to the machine language [CA 24]. When this data is sent to the signal line, it becomes a bit pattern of “1100101000100100”.

  When the data processing device B (CPU) 0402 transmits a control signal, the gates of the two PMOSs 0409 and 0410 of the precharge signal line control device 0407 are energized to supply Vdd to the signal line 0408 and clear it to 1 (HIGH). . Further, the potential charges the capacitor 0406 of the power generation device C0118. First, when the first data (MD-DATA) 1 is loaded, the signal line is discharged and power is consumed. At this time, the same data (MD-DATA) 1 and the MACK signal are input to the power generation device C0118.

  At this time, how the stationary power generation device C0118 operates will be described in detail.

  In the case of the first value "1" of the data string, data (MD-DATA) 1 from the data processing device A (ROM) 0401 is prepared. By preparing the first value “1”, the data processing device A (ROM) 0401 outputs a MACK signal. The MACK signal is 1 when the output is determined, and becomes 0 when the output is not determined.

  The MACK signal is input to the logical product operation device 0411, and at the same time, data (MD-DATA) 1 is loaded on the signal line 0408. Then, the data (MD-DATA) 1 is further input to the AND operation device 0411.

  Since both the MD-DATA and MACK signals are “1”, the output of the AND operation unit 0411 is “1”. Then, this value is input to the NMOS gate circuit 0404. Since the NMOS gate circuit 0404 conducts electricity to the input 1 (HIGH), the capacitor 0406 discharges. On the other hand, since the value on the signal line 0408 does not change, charging / discharging on the signal line 0408 is not performed.

  No power is consumed in the signal line 0408 which does not perform charging / discharging, whereas power is consumed in the capacitor 0406 which performs discharging. Therefore, the sum of the two is equal to the power consumed by charging one signal line.

  Next, in the case of the second value "1" of the data string, data 1 is on the signal line 0407. At this time, since the signal line 0407 has been precharged and cleared to 1, the same operation as described above is performed again, and the sum of the power consumption of the signal line 0408 and the power consumption of the capacitor 0406 becomes the signal line It is equal to the power consumed by one charge.

  Next, in the case of the third value "0" of the data string, data (MD-DATA) 0 is on the signal line 0408. At this time, since the signal line 0408 has already been precharged and cleared to 1, power consumption is performed according to the change from the value “1” to “0”. MD-DATA0 and the MACK signal 1 are input to the AND operation device 0411. The output value of the logical product operation unit 0411 becomes 0, and this value is input to the NMOS gate circuit 0404. Since the NMOS gate circuit 0404 does not conduct electricity to the input 0 (LOW), the power consumption of the capacitor 0406 is not performed.

  The signal line where the data value changes from “1” to “0” consumes power, while the capacitor 0406 consumes no power. Therefore, the sum of the power consumption of the two is equal to the power consumption consumed by charging one signal line.

Since the same operation is performed thereafter, the sum of the power consumption in the signal line 0408 and the power consumption in the capacitor 0406 is always equal to the power consumption in charging one signal line.

  The state of the capacitor 0406 for the data “1100101000100100” on the signal line 0408 is shown in FIG.

  FIG. 12 is a basic configuration diagram of an information processing apparatus for explaining a fifth embodiment of the present invention. This is an example of a precharge signal line control method, and uses a so-called dummy signal line as a power generation device.

  The basic structure of this embodiment is the same as that of the fourth embodiment, except that the resistor and the capacitor are replaced by dummy signal lines. The information processing apparatus of this embodiment includes a data processing device A (ROM) 0501, a data processing device B (CPU) 0502, a precharge signal line control device 0505, a signal line (bus line) 0506, and a steady power generation device C0119. . Here, it is assumed that the capacitance of the dummy signal line 0507 is equal to the capacitance of the signal line 0506, and the resistance value is the same as that of the signal line 0506. That is, the dummy signal line 0507 and the signal line 0506 use substantially the same signal line. Note that the stationary power generation device C0119 includes an NMOS gate circuit 0504, a dummy signal line 0507, and a logical product operation device 0503.

  Here, for simplicity, the size of the signal line is 1 bit, and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  The operation is basically the same as that of the example of the information processing apparatus according to the first embodiment. Therefore, the detailed description is omitted.

  FIG. 13 is a basic configuration diagram of an information processing apparatus for explaining a sixth embodiment of the invention. This example is a precharge signal line control method and an example having an inversion device.

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 5001 and a data processing device B (RAM) 5002 are connected to signal lines 5007 and 5006, respectively. An inverting device 5003 is provided between the signal lines 5007 and 5006. Further, this example includes a precharge signal line control device 5008.

  The inversion device 5003 includes four CMOS inverters 5004, 5005, 5009, and 5010, PMOS gate circuits 5011 and 5013, and NMOS gate circuits 5014 and 5012. Note that the capacitance and the resistance of the signal line 5006 and the signal line 5007 are substantially the same.

When transferring data from the data processing device A (CPU) 5001 to the data processing device B (RAM) 5002, the data processing device A (CPU) 5001 transmits a control signal to the precharge bus control device 5008. With this signal, the PMOS gate and the NMOS gate in the precharge bus control device 5008 are energized.
Then, the potential Vdd charges the signal lines 5007 and 5006 to be in a HIGH state. Further, a control signal from the data processing device A (CPU) 5001 is input to the inverter 5010 and the NMOS gate circuit 5012, and the PMOS gate circuit 5011 and the NMOS gate circuit 5012 are turned on. Thereafter, data is transmitted from data processing apparatus A (CPU) 5001.

  When data from the data processing device A (CPU) 5001 is 0, the signal line 5007 is discharged. This value is converted to 1 by the inverter 5004 and a signal is sent to the signal line 5006. However, as described above, since the signal line 5006 is already charged, no charge / discharge occurs. Then, the value 1 is input to the data processing device B (RAM) 5002. This value “1” is inverted from the data “0” sent by the data processing device A (CPU) 5001.

  Conversely, when the data from the data processing device A (CPU) 5001 is 1, no charging / discharging occurs on the signal line 5007 and a discharge occurs on the signal line 5006. The same applies when data is sent from the data processing device B (RAM) 5002 to the data processing device A (CPU) 5001. Since the capacitance and the resistance of the signal line 5006 and the signal line 5007 are substantially the same, in all cases, the total of the charging and discharging of the signal lines 5006 and 5007 is caused by the charging and discharging of the signal line 5006 or 5007. Power is consumed and the sum is constant.

  Next, various embodiments of the seventh embodiment to the twenty-second embodiment are examples of encrypting data carried on a signal line.

  FIG. 14 is a basic configuration diagram of an information processing apparatus for explaining a seventh embodiment of the present invention. This example is a basic example of encrypting data to be put on a signal line using an encryption device.

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 0601 and a data processing device B (RAM) 0602 are connected by a signal line (bus line) 0605. Further, an encryption device and a decryption device are provided between the data processing device A (CPU) 0601 and the signal line (bus line) 0605. An exclusive OR operation device 0603 is used as the encryption device of this example, and an exclusive OR operation device 0604 is used as the decryption device. It goes without saying that various devices having other configurations can be used as the encryption device and the decryption device.

  Here, for ease of explanation, it is assumed that the size of the signal line 0605 is 8 bits and the data processing device A (CPU) 0601 is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  Here, the control method of the signal line 0605 is described as a static signal line control method. The effect of the concept of the present embodiment is the same in the precharge signal line control method.

  The encryption device of this example is an exclusive logical operation device for each bit of a fixed 8-bit key (Key) and 8-bit data from the CPU. On the other hand, the decryption device of this example is also an exclusive OR operation device for each bit of the same key and data. In addition, the key (Key) itself is sufficient with a conventional technique.

  As described in the embodiment of the first embodiment of the present invention, in the case of the static signal line control method, power consumption is performed in proportion to the number of bit inversions with the value immediately before the signal line. Hereinafter, the power consumption for one bit is represented by P.

  For example, assume that data “0110100” is transmitted from data processing apparatus A (CPU) 0601. Assuming that the data immediately before the signal line 0605 is “11010101”, the bit inversion number is 5. Therefore, the power consumed by this signal line 0605 is 5P.

  The data “10110111” is transferred from the data processing device A (CPU) 0601 to the data processing device B (RAM) 0602 through the signal line 0605, and is transferred from the data processing device B (RAM) 0602 to the data processing device A (CPU) again. ) Consider the process of returning to 0601. In this case, it is assumed that the data immediately before the signal line 0605 is “00010101”. It is assumed that the key is “10101110”.

  If there is no encryption device and no decryption device, the data of the signal line changes from “00010101” to “10110111”. Accordingly, in this case, the power consumption is 3P corresponding to the number of bit inversions of three.

  However, in the case of this example, the data on the signal line 0605 is generated by the encryption device, that is, the exclusive OR operation device 0603, and the data from the information processing device A (CPU) 0601 is transmitted to the key (Key) “10101110”. Exclusive OR for each bit with “10110111”. That is, the result is “00011001”.

  At this time, the data of the signal line 0605 changes from the data “00010101” immediately before the signal line 0605 to the output “00011001” of the exclusive OR described above. Therefore, in this case, the power consumption is 2P, corresponding to the number of bit inversions 2. This power consumption is a value different from 3P that should be consumed because there is no encryption device and no decryption device.

  The data processing device B (RAM) 0602 stores the encrypted value “00011001”. Let us consider the case where this encrypted value is returned to the data processing device A (CPU) 0601 again via the signal line 0605.

  Data output from the data processing device B (RAM) 0602 to the signal line 0605 does not change from "00011001" to "00011001". Therefore, the signal line 0605 is not charged / discharged and power is not consumed.

The value from the signal line 0605 is converted into the exclusive OR “10110111” of the data “00011001” and the key “10101110” from the signal line 0605 by the operation of the decoding device, that is, the exclusive OR operation device 0604. The data is input to the data processing device A (CPU) 0601. Since the exclusive OR of the same number becomes 0, the data processing device A (CPU) can perform the operation without contradiction. In addition, power consumption due to charging and discharging in the signal line 0605 is different from the original data. Therefore, it is difficult to estimate the original data based on the power consumption.
FIG. 15 is a basic configuration diagram of an information processing apparatus for explaining an eighth embodiment of the present invention. This example is an example in which data to be carried on a signal line is encrypted. In the encryption or decryption, a random number is used as a key (Key). In this example, encryption is performed using the data transmitted from the data processing device and a random number, and decryption is performed using the data transmitted to the data processing device and the same random number as described above.

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 0701 and a data processing device B (RAM) 0702 are connected by a signal line (bus line) 0705. An encryption device and a decryption device are provided between the data processing device A (CPU) 0701 and the signal line 0705. An exclusive OR operation device 0703 is used as an encryption device, and an exclusive OR operation device 0704 is used as a decryption device.

  In this example, a random number is used as a key for the encryption device and the decryption device. Therefore, in this example, a random number generator (RNG) 0706 and key buffers 0707 and 0708 for the encryption device 0703 and the decryption device 0708 are prepared. As the random number generator itself and the like, a conventional one is sufficient.

  The random number generator 0706 operates in response to a reset signal (Reset) when the information processing apparatus is started, generates an 8-bit random number, stops, and remains stopped until a reset signal is input again. The key buffers 0707 and 0708 store the above-described 8-bit random numbers, and have eight flip-flops.

  Here, for the sake of explanation, it is assumed that the size of the signal line 0705 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general. The control method of the signal line 0705 is a static signal line control method. The effect of the present embodiment is the same in the precharge signal line control method.

  The encryption device 0703 is a device that performs an exclusive logical operation for each bit of the fixed 8-bit key (Key) and the 8-bit data from the data processing device A (CPU) 0701. The decryption device 0704 is also a device that performs an exclusive OR operation of the same key and data for each bit.

  This example may be the same as the example of the sixth exemplary embodiment of the present invention, except that the random number generation device 0706 is activated at the time of reset and a new 8-bit key is set. Therefore, the operation after the random number key is set in the key buffer is basically the same as that of the example of the sixth embodiment. Therefore, the power consumed by charging / discharging in the signal line is different from the original data, and since the key used for encryption changes every reset, it is more difficult to estimate the original data from the power consumption. It will be difficult.

  FIG. 16 is a basic configuration diagram of an information processing apparatus for explaining a ninth embodiment of the invention. This example is another example of encrypting data to be carried on a signal line, and is an example in which the encryption device has an automatic encryption key setting device. This embodiment is particularly characterized by a source of encryption key information.

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 0801 and a data processing device B (RAM) 0802 are connected by a data signal line 0806. An exclusive OR operation device 0803 as an encryption device, an exclusive OR operation device 0804 as a decryption device, and a key buffer 0805 are provided. Further, an upper 4-bit address signal line 0807 and a lower 4-bit address signal line 0808 are provided for the data processing device A (CPU) 0801 and the data processing device B (RAM) 0802.

  Here, for the sake of explanation, it is assumed that the size of the data signal line 0806 is 8 bits, the size of the address signal lines 0807 and 0808 is also 8 bits, and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general. The control method of the data signal line 0806 and the address signal lines 0807 and 0808 is a static signal line control method. The effect of this example is the same in the precharge signal line control method.

  The encryption device 0803 is a device that performs an exclusive logical operation for each bit of the fixed 8-bit key (Key) and the 8-bit data from the data processing device A (CPU) 0801. The decryption device is also a device that performs an exclusive OR operation of the same key and data for each bit. The upper 4 bits of the key buffer 0805 are a fixed key, and the lower 4 bits store the lower 4 bits of the address signal line.

  This is illustrated in the key buffer 0805 of FIG. Hereinafter, it is assumed that the four bits of the fixed part of the key are D (hexadecimal notation).

  It is assumed that data processing apparatus A (CPU) 0801 transfers data to a certain address of data processing apparatus B (RAM) 0802. Now, assume that the data processing device B (RAM) 0802 ranges from address F0 to address FF. Here, this value is not essential. The data processing device A (CPU) 0801 transfers the following data shown in Table 4 in order from the address F4.

  It is assumed that the data on the data signal line 0806 immediately before the data 5D is transferred from the data processing device A (CPU) 0801 is CF. When the transfer of the data 5D is performed, F4 rides on the address signal line, and the transfer position of the data processing device B (RAM) 0802 is determined.

  The data 5D enters the exclusive OR operation unit 0803, and exclusive ORs 5Dexor D4 of the fixed key 4 bits D (hexadecimal notation) and 4 of the lower 4 bits of the address F4 = 01101101 exor 11010100 (binary notation) ) = 10001001 (binary representation) = 89 (hexadecimal representation) is transmitted. That is, the encrypted data is transmitted by performing an exclusive OR operation for each bit of [fixed key 4 bits / address lower 4 bits] and [data upper 4 bits / data lower 4 bits] and then transmitted.

  The power consumed when this 89 (this value is expressed in hexadecimal) is on the data signal line 0806 is 3P. This is because the bit inversion value is 3 because the data changes from CF (11001111) to 89 (10001001). Note that P used here is the symbol used in the seventh embodiment of the present invention. That is, P is power consumption for one bit.

  Through the same process, the data on the signal line 0806 changes from CF (11001111) to 89 (10001001), and this information changes to 75 (01110101) and further to 28 (00101000).

  The power consumption on the signal line 0805 corresponding to this change changes from 3P to 6P and further changes to 2P.

  This is different from the original change, that is, the change from CF (11001111) to 5D (01011101), and further from A0 (10100000) to FE (11111110). That is, when viewed as a change in power consumption, it corresponds to a change from 3P to 7P and further to 5P. Therefore, it is difficult to estimate the internal data from the measurement of the power consumption of the semiconductor device.

  FIG. 17 is a basic configuration diagram of an information processing apparatus for explaining a tenth embodiment of the present invention. This example is another example of encrypting data to be carried on a signal line, but is an example in which an encryption or decryption device further has a setting unit.

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 0901 and a data processing device B (RAM) 0902 are connected by a signal line 0907. This example has an exclusive OR operation device 0903 as an encryption device, an exclusive OR operation device 0904 as a decryption device, and a key buffer 0905 that holds 8-bit key data. Here, for the sake of explanation, it is assumed that the size of the signal line 0907 is 8 bits and the data processing device A (CPU) 0901 is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  The key buffer 0905 is connected to the data processing device A (CPU) 0901. Then, data can be written into the key buffer 0905 from the data processing device A (CPU) 0901, and the key buffer 0905 can encrypt the output data from the data processing device B (RAM) 0902 and decrypt the input data. Used for chemical conversion.

  Except that the key can be rewritten from the data processing device A (CPU) 0901, the other configuration is the same as that of the example in the sixth embodiment of the present invention. Therefore, the detailed description is omitted.

  Here, a specific example of the key buffer 0905 is illustrated in FIG. Note that the key buffer illustrated here can be appropriately used as an example of mounting the key buffers 1607, 1406, 1407, and 1607 shown in FIGS. 25, 28, and 29, which will be described below as embodiments of the present invention. Needless to say.

  The above-described key buffer will be described with reference to FIG. In this example, 1-bit shift registers 1461, 1462, 1463, 1464, 1465, 1466, 1467, and 1468, 1-bit exclusive-OR units 1470, 1471, 1472, and a random number generator (RNG) 1469 Become.

It is assumed that shift registers 1461, 1462, 1463, 1464, 1465, 1466, 1467, and 1468 store initial bits. Here, for the sake of explanation, it is assumed that the numbers are 10101110 when arranged in order. It is assumed that the random number generator 1469 generates a 1-bit column number each time one bit shift is performed. It is assumed that a random number is generated one bit at a time and becomes, for example, 011. At this time, the sequence of 8-bit values generated by the key buffer is as follows.
10101110->01011100->101111101-> 011
11111
It is known that this 8-bit behavior is very close to a random number. Generally, it often takes time to generate a correct random number. However, in this example, an 8-bit (pseudo) random number sequence can be generated only by using a 1-bit random number. Therefore, extremely high-speed processing can be performed by the random number generating means of this embodiment. As described above, an extremely practical information processing apparatus can be provided by the pseudo-random number generating means operating at high speed.

  FIG. 18 is a basic configuration diagram of an information processing apparatus for explaining an eleventh embodiment of the present invention. This example is another example of encrypting data to be carried on a signal line. Further, this example is an example in which a key (Key) is selected using a key selection device (multiplexer).

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 1001 and a data processing device B (RAM) 1002 are connected by a data signal line 1009. An exclusive OR operation device 1003 is used as an encryption device, and an exclusive OR operation device 1004 is used as a decryption device.

  It has key selection devices (multiplexers) 1006 and 1014, key tables 1007 and 1015, key buffers 1008 and 1013, and a key number transfer signal line 1010. The key tables 1007 and 1015 are fixed and cannot be rewritten. The key tables 1007 and 1015 store Key0 and Key1. Of course, in the present invention, a rewritable key table can be used as the key table. The key selection device 1006 is connected to the key buffer 1008 and used for the encryption device 1003. The key selection device 1014 is connected to the key buffer 1013 and used for the decryption device 1004. The key number is transferred by the key number transfer signal line 1010.

  Here, for ease of explanation, it is assumed that the size of the signal line 1009 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  According to this example, a user (for example, a company that produces an application for an IC card) can select which key in the key table 1007 to use for encryption by designating it in the key selection bit buffer 1011. Hereinafter, the value stored in the key selection bit buffer 1011 is referred to as SKEYBIT.

  The key selection device 1006 refers to the SKEYBIT stored in the key selection bit buffer 1011, extracts a Key to be used from the key table 1007, and stores it in the key buffer 1008. Here, if SKEYBIT is 0, the key selection device (multiplexer) 1006 selects Key0 in the key table 1007 and stores it in the key buffer 1008. If SKEYBIT is 1, selects Key1 in the key table 1007. Then, it is stored in the key buffer 1008.

  When the data processing device A (CPU) 1001 transfers data to the data processing device B (RAM) 1002, the exclusive-OR operation device 1003 stores the 8-bit key data stored in the key buffer 1011 and the data processing device The exclusive OR with the 8-bit data from A (CPU) 1001 is obtained. Then, this value is put on the data signal line 1010 and transferred to the data processing device B (RAM) 1002. At the same time, the value of SKEYBIT stored in the key selection bit buffer 1011 is transferred to the data processing device B (RAM) 1002 through the key number transfer signal line 1010. At this time, the data in the data processing device B (RAM) 1002 is stored in the form shown in Table 5.

This indicates that DATA is encrypted with a key whose key number is SKEYBIT. When SKEYBIT in the key selection bit buffer 1011 is rewritten by a program or the like, it is encrypted by another key. For example, the internal data of the data processing device B (RAM) is as follows.
1 EF
0 A3
13E
1 54
0 3D
When returning these data to data processing apparatus A (CPU) 1001 for use, the following operation is performed. Before transferring these encrypted data, a key selection bit is transferred from the data processing device B (RAM) 1002 to the key selection device 1014 through the key number transfer signal line 1010. The key selection device 1014 selects a key stored in the key table 1015 according to the key selection bit, and transfers the key to the key buffer 1013. Then, the data processing device A (CPU) 1001 requests data from the data processing device B (RAM) 1002 and puts the corresponding data of the data processing device B (RAM) 1002 on the data signal line 1009. Further, an exclusive OR operation of the corresponding data and the key stored in the key buffer 1013 is performed by the exclusive OR operation device 1004 and input to the data processing device A (CPU) 1001. Since the decryption is performed according to the key number used for encrypting the data, the data processing apparatus A (CPU) 1001 performs the processing without contradiction.

  FIG. 19 is a basic configuration diagram for explaining an outline of an information processing apparatus for explaining a twelfth embodiment of the invention. This example is one example in which data of a signal line is encrypted and transmitted. Further, this example is a method of dividing a storage device into a plurality of areas, and specifying whether or not to encrypt each area, and performing encryption and decryption.

  In the information processing apparatus of this embodiment, a data processing device 51101 and an information storage device 51102 are connected by a data bus 51107. The data processing device 51101 is provided with an encryption device 51103 and a decryption device 51104. Then, in this example, whether or not to encrypt is determined by the encryption determination circuit 7312, and this information is provided to the encryption device 51103 and the decryption device 51104. For this operation, an encryption key storage device 51106, an encryption area designation register 7311, an encryption determination circuit 7312, an AND circuit 51112, and the like are provided. Furthermore, this example has an address bus 51108 between the information storage device and the data processing device.

  Here, the configuration of the information storage device 51102 itself is sufficient as usual. The storage area of the information storage device is classified into a plurality of areas according to the address value of the storage area, and whether or not to encrypt each area is specified by the encryption area specification register 7311. The encryption determination circuit 7312 determines whether to perform encryption based on the address value appearing on the address bus 51108 and the value of the encryption area designation register 7311.

  FIG. 20 shows one embodiment of the encryption judgment circuit. In this example of the encryption judgment circuit, the upper p bits at the time of dividing the memory are referred to, the area of the memory array is identified in each state of p bits, and the memory array is divided into 2 ＾ p areas. The encryption area designation register 7311 has a length of 2 ^ p bits, and each bit corresponds to one area on the memory array, and controls whether or not to perform encryption.

  For each bit of the encryption area specification register 7311 and a bit pattern representing an address area corresponding to the bit, a NOT is inserted so that all the bits become 1, and then the corresponding bit of the encryption area specification register is set. Perform a logical conjunction. When the logical product is 1, encryption is performed, and when the logical product is 0, encryption is not performed. A similar circuit is created for each bit of the encryption area designation register 7311, and then the logical sum of all the bits of the logical product is calculated by the logical sum operation device 7314. When the logical sum is 1, encryption is performed, and when it is 0, encryption is not performed.

  The AND of the output of the encryption determination circuit 7312 with the encryption key is calculated by the logical product operation unit 51112 and sent to the encryption device 51103 and the decryption device 51104. The output of the AND operation device 51112 has the same value as the encryption key when performing encryption, but becomes 0 when not performing encryption. When 0 is given as the encryption key, the input and output of the encryption device 51103 become equal, which is equivalent to not performing encryption.

  The decryption procedure at the time of reading, as in the case of writing, depends on the value of the address and the value of the encryption area designation register 7311 to determine whether the encryption key at the time of decryption is 0 or the value of the encryption key. Control and perform decryption.

  In this manner, the information storage device is divided into a plurality of areas by address, and the presence or absence of encryption can be set for each area. In the encrypted area, the bit pattern appearing on the data bus 51107 and the bit pattern of the data recorded in the information storage device are different from the actual data, so that the consumption when writing / reading data to / from the information storage device is performed. It is difficult to estimate actual data from current patterns and current patterns consumed by buses.

  FIG. 21 is a basic configuration diagram for explaining an outline of an information processing apparatus for explaining a thirteenth embodiment of the present invention. This example is another example for encrypting and decrypting data to be carried on a signal line. This example is an example in which a specific data pattern is not encrypted.

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 1101 and a data processing device B (RAM) 1102 are connected by a signal line 1109. An exclusive OR operation device 1103 is provided as an encryption device, and an exclusive OR operation device 1104 is provided as a decryption device. A latch circuit 1105, an 8-bit encryption prohibition data buffer 1106, a decryption prohibition data buffer 1113, a key table 1107, 1112, a key selection device 1108, 1111, etc. are provided for selecting a key for the encryption device and the decryption device. Have been.

  Here, the same data as the data inside the encryption prohibited data buffer 1106 is stored in the data inside the decryption prohibited data buffer 1113. The key tables 1107 and 1112 store exactly the same key data.

  Here, for the sake of explanation, it is assumed that the size of the signal line 0705 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  It is assumed that the key table 1107 stores an encryption key (Key) and 0. The encryption prohibition data buffer 1106 and the decryption prohibition data buffer 1113 store prohibition data (FDATA) and the value of the exclusive OR of FDATA and the encryption key (Key). The value of the exclusive OR of FDATA and Key is called CO-FDATA. The reason why CO-FDATA is required is as follows. If the exclusive OR of the data and the Key matches FDATA, when the encrypted data is returned from the data processing device B (RAM) 1102 to the data processing device A (CPU) 1101, encryption is performed. This is because the data is input to the data processing device A (CPU) 1101 as it is and the processing is inconsistent.

  Since the exclusive OR with the key (Key) matches FDATA only in CO-FDATA, the data that must be stored in the encryption prohibited data buffer 1106 and the decryption prohibited data buffer 1113 is the prohibited data. (FDATA) and CO-FDATA only.

  When data is transferred from the data processing device A (CPU) 1101 to the data processing device B (RAM) 1102 via the signal line 1109, the data is input to the key selection device 1108 and the latch circuit 1105. The latch circuit 1105 continues to hold the data until the value (OUTDATA-BIT) of the data holding release signal from the key selection device 1108 becomes 1, and when the OUTDATA-BIT becomes 1, the latch circuit 1105 releases the holding and exclusive. Is input to the logical OR operation device 1103. The data input to the key selection device 1108 is compared with 8-bit encryption prohibition data (FDATA) and CO-FDATA held in the encryption prohibition data buffer 1106. If the data input to the key selection device 1108 is the same as one of them, the value 0 is selected and held from the key table 1107, OUTBIT-DATA1 is sent to the latch circuit 1105, and exclusive OR is performed. The value 0 is transmitted to the arithmetic unit 1103. Since the exclusive OR of an arbitrary bit value x and 0 is equal to x, at this time, the data is put on the signal line 1109 without being encrypted and input to the data processing device B (RAM).

  On the other hand, when the data is not the same as FDATA or CO-FDATA, the value Key is selected and held from the key table, OUTBIT-DATA1 is sent to the latch circuit 1105, and the value Key is sent to the exclusive OR operation device 1103. Send. At this time, the data is encrypted, put on the signal line 1109, and input to the data processing device B (RAM). Conversely, when transferring data from the information processing device B (RAM) to the data processing device A (CPU), the data is transferred as it is onto the signal line 1109. Also at this time, if the data and FDATA or CO-FDATA match in the same process as described above, decoding is not performed, and if they do not match, decoding is performed using the same Key, and processing is performed without contradiction.

  FIG. 22 is a basic configuration diagram illustrating an outline of an information processing apparatus for describing a fourteenth embodiment of the present invention. This example is another example of encrypting data to be put on a signal line. Further, this embodiment is an example in which an encryption and decryption device is inserted between both data processing devices for transmitting data and a signal line.

  In the information processing apparatus of this embodiment, a data processing device A (CPU) 1301 and a data processing device B (RAM) 1302 are connected by a signal line 1307. XOR devices 1303 and 1305 are used as encryption devices, and XOR devices 1304 and 1306 are used as decryption devices. The exclusive-OR operation devices 1303, 1304, 1305, and 1306 all calculate and output the exclusive-OR of the same key Key and data. Data output from the data processing device A (CPU) 1301 is encrypted by the exclusive OR operation device 1303 and transferred to the data processing device B (RAM) 1302 through the signal line 1307. However, on the other hand, the data is decoded by the exclusive OR operation unit 1306 before being input to the data processing device B (RAM) 1302, and then input to the data processing device B (RAM) 1302.

  Unlike the sixth embodiment of the present invention, in this embodiment, the data in the data processing device B (RAM) 1302 is the original data that has not been encrypted. When data in the data processing device B (RAM) 1302 is transferred to the data processing device A (CPU) 1301, the data is encrypted by the exclusive OR operation device 1305, and the data processing device A is transmitted through the signal line 1307. The data is transferred to the (CPU) 1301, but before being input to the data processing device A (CPU) 1301, it is decoded by the exclusive OR operation device 1304 and then input to the data processing device A (CPU) 1301.

  At this time, the charge and discharge in the signal line are exactly the same as those in the information processing device according to the sixth embodiment of the present invention.

  FIG. 23 is a basic configuration diagram illustrating an outline of an information processing apparatus for describing a fifteenth embodiment of the present invention. This example is another example of encrypting data to be carried on a signal line. In this example, an encryption / decryption device and a device for setting key information are inserted between a data processing device and a signal line.

  The information processing apparatus according to the present embodiment is a bidirectional version of the example of the information processing apparatus according to the sixth embodiment of the present invention. In this example, a data processing device A (CPU) 1401, a data processing device B (RAM) 1402, a signal line 1410, exclusive OR operation devices 1403 and 1411 as encryption devices, and exclusive logic as a decryption device It has sum operation devices 1404 and 1412, a random number generation device (RNG) 1409, and key buffers 1405, 1406, 1407 and 1408.

  The random number generation device 1409 operates upon receiving a reset signal (Reset) at the time of activation of the information processing device, generates and stops an 8-bit random number, and remains stopped until a reset signal is input again. The key buffer stores an 8-bit random number and is composed of eight flip-flops. Here, for the sake of explanation, it is assumed that the size of the signal line 1410 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general. The control method of the signal line 1410 is a static signal line control method. The effect of this example is the same in the precharge signal line control method.

  This example is the same as the information processing apparatus according to the thirteenth embodiment of the present invention except for the part that activates the random number generation apparatus 1409 at the time of reset and sets a new 8-bit key. Therefore, the operation after the random number key is set in the key buffer is the same. Detailed description of the operation is omitted.

  Also in this example, of course, the power consumption due to charging / discharging on the signal line is different from the original data, and the key used for encryption changes at each reset. Is difficult to guess.

  FIG. 24 is a basic configuration diagram illustrating an outline of an information processing apparatus for describing a sixteenth embodiment of the present invention. This example is another example of encrypting data to be carried on a signal line. This example is an example in which address information of a storage device is used as a part of key information used for encryption.

  The information processing apparatus according to the present embodiment is basically a bidirectional version of the information processing apparatus according to the seventh embodiment of the present invention. In this example, a data processing device A (CPU) 1501, a data processing device B (RAM) 1502, exclusive OR operation devices 1503 and 1505 as encryption devices, an exclusive OR operation device 1504 as a decryption device, 1506, a key buffer 1507, a data signal line 1510, upper 4 bits of an address signal line 1508, and lower 4 bits of an address signal line 1509. Here, for the sake of explanation, it is assumed that the size of the data signal line 1510 is 8 bits, the size of the address signal lines 1508 and 1509 is also 8 bits, and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general. It is assumed that the control method of the data signal line 1510 and the address signal lines 1508 and 1509 is a static signal line control method. The effect of this example is the same in the precharge signal line control method.

  The encryption device is a bitwise exclusive logical operation device of a fixed 8-bit key (Key) and 8-bit data from the CPU, and the decryption device is also a bitwise exclusive operation of the same key and data. Logical OR operation device. The upper 4 bits of the key buffer 1507 are a fixed key, and the lower 4 bits store data of the lower 4 bits 1509 of the address signal line.

  The operation when data is transferred from the data processing device A (CPU) is the same as that described in the information processing device according to the seventh embodiment of the present invention.

  However, the data is not input to the data signal line 1510 while being encrypted, but is input to the data processing device B (RAM) 1502 after being decrypted using the encryption key stored in the key buffer 1507. . Conversely, when data inside the data processing device B (RAM) 1502 is transferred to the data processing device A (CPU) 1501, the corresponding address is transferred from the data processing device A (CPU) 1501 via the address lines 1508 and 1509. The value of the key buffer 1507 is determined using the value. Then, the exclusive OR of the value of the key buffer 1507 and the data is put on the data signal line 1510. The exclusive OR operation device 1504 decrypts the value by taking the exclusive OR of this value and the key of the key buffer 1507 used for encryption, and inputs the result to the data processing device A (CPU). At this time, the operation of charging and discharging the signal line is exactly the same as that in the example of the information processing apparatus according to the seventh embodiment.

  FIG. 25 is a basic configuration diagram illustrating an outline of an information processing apparatus for describing a seventeenth embodiment of the present invention. This example is another example of encrypting data to be carried on a signal line. Further, this example is an example in which an encryption / decryption device is inserted between a data processing device and a signal line, and key information used for encryption is automatically reset.

  The information processing apparatus according to the present embodiment includes a data processing device A (CPU) 1601, a data processing device B (RAM) 1602, exclusive OR operation devices 1603 and 1605 as encryption devices, and exclusive logic as a decryption device. Sum operation units 1604 and 1606, a key buffer 1607 for storing an 8-bit key, a random number generation unit (RNG) 1608, a 5-bit input / one output OR operation unit 1609, a counter 1610 having a 5-bit size, a signal line 1611. The counter 1610 counts according to the rising edge of the clock signal (CLK), and a portion larger than 5 bits is ignored. Here, for the sake of explanation, it is assumed that the size of the signal line 1611 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  When transferring data from the data processing device A (CPU) 1601 to the data processing device B (RAM) 1602, the data processing device A (CPU) 1601 transfers data in synchronization with a clock signal. When the clock signal is transmitted, the counter 1610 starts counting. The logical sum operation device 1609 transmits the logical sum of all the bits of the counter to the random number generation device 1608. If the value of the logical sum is 0, the random number generation device 1608 generates an 8-bit random number, transmits the 8-bit random number to the key buffer 1607, and stops. At this time, the random number generation device 1608 receives 0 only when all the values of the counter become 0, so that the key exchanges the key used for encryption and decryption every 32 clocks. The key buffer 1607 supplies the same key to all of the exclusive OR operation units 1603, 1604, 1605, and 1606.

  When data is transferred from the data processing device A (CPU) to the data processing device B (RAM) through the signal line 1611, first, the exclusive OR operation device 1603 performs an exclusive OR operation on the value of the key buffer 1607 and the data. On the signal line 1611 for transfer. This encrypted data is subjected to an exclusive OR operation with the value of the same key buffer 1607 before entering the data processing device B (RAM). (RAM) 1602. The same applies to the case where the data of the data processing device B (RAM) 1602 is transferred to the data processing device A (CPU) 1601.

  FIG. 26 is a basic configuration diagram illustrating an outline of an information processing apparatus for describing an eighteenth embodiment of the present invention. This example is another example of encrypting data to be carried on a signal line. This example is an example in which the key can be rewritten from the data processing device A (CPU) 1701.

  The information processing apparatus according to the present embodiment includes a data processing apparatus A (CPU) 1701, a data processing apparatus B (RAM) 1702, exclusive OR operation apparatuses 1703 and 1705 as encryption apparatuses, and exclusive logic as a decryption apparatus. It comprises sum operation devices 1704 and 1706, a key buffer 1707 for storing 8 bits, and a signal line 1709. Here, for the sake of explanation, it is assumed that the size of the signal line 1709 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  The key buffer 1707 is connected to the CPU 1701, and the contents of the key buffer 1707 can be changed from the CPU 1701. The key information held in the key buffer 1707 is used for encrypting output data from the data processing device A (CPU) 1701 and decrypting input data. Except that the key can be rewritten from the data processing device A (CPU) 1701, the other configuration is the same as the example in the fifteenth embodiment of the present invention.

  FIG. 27 is a basic configuration diagram for explaining an outline of an information processing apparatus for explaining a nineteenth embodiment of the present invention. This example is an example of encrypting and decrypting data to be put on a signal line and storing the data.

  The information processing apparatus of this embodiment includes a data processing apparatus A (CPU) 1301, a data processing apparatus B (RAM) 1302, an exclusive OR operation apparatus 1303 as an encryption apparatus, and an exclusive OR operation as a decryption apparatus. The device 1306 includes a signal line 1307. The exclusive OR operation devices 1303 and 1306 calculate and output the exclusive OR of the same key Key and data.

  The data output from the data processing device A (CPU) 1301 is encrypted by the exclusive OR operation device 1303 and transferred to the data processing device B (RAM) 1302 through the signal line 1307. The data is decoded by the exclusive OR operation unit 1306 before being input to the (RAM) 1302, and then input to the data processing device B (RAM) 1302.

  Unlike the sixth embodiment of the present invention, in this embodiment, the data in the data processing device B (RAM) 1302 is the original data that has not been encrypted. At this time, information sent from the data processing device A (CPU) 1301 to the data processing device B (RAM) 1302 is encrypted on the signal line. Therefore, it is difficult to estimate the transmitted information from the charge / discharge current of the signal line.

  FIG. 28 is a basic configuration diagram illustrating an outline of an information processing apparatus for describing a twentieth embodiment of the invention. This example is an example in which data to be put on a signal line is encrypted and decrypted and stored. Further, this example is an example using a key using a random number.

  The information processing apparatus according to the present embodiment includes a data processing device A (CPU) 1401, a data processing device B (RAM) 1402, a signal line 1410, an exclusive OR operation device 1403 as an encryption device, and a decryption device. It comprises an exclusive OR operation unit 1412, a random number generation unit (RNG) 1409, and key buffers 1406 and 1407.

  The random number generation device 1409 operates upon receiving a reset signal (Reset) at the time of activation of the information processing device, generates and stops an 8-bit random number, and remains stopped until a reset signal is input again. The key buffer stores an 8-bit random number and includes eight flip-flops. Here, for the sake of explanation, it is assumed that the size of the signal line 1410 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general. The control method of the signal line 1410 is a static signal line control method. The effect of this example is the same in the precharge signal line control method.

  This example is the same as the example of the information processing apparatus according to the nineteenth embodiment of the present invention, except that the random number generating apparatus 1409 is activated at the time of reset and a new 8-bit key is set. Therefore, the operation after the random number key is set in the key buffer is the same. Therefore, the power consumption due to charge / discharge in the signal line is different from the original data, and since the key used for encryption changes at each reset, it is difficult to estimate the original data from the power consumption. It becomes.

  FIG. 29 is a diagram showing a basic configuration of an information processing apparatus for explaining a twenty-first embodiment of the present invention. This example is an example of encrypting data to be put on a signal line. Further, this example is an example in which key information is set using random numbers.

  The information processing apparatus according to the present embodiment includes a data processing device A (CPU) 1601, a data processing device B (RAM) 1602, an exclusive OR operation device 1603 as an encryption device, and an exclusive OR operation as a decryption device. It comprises a device 1606, a key buffer 1607 for storing an 8-bit key, a random number generator (RNG) 1608, a 5-bit input 1-output logical sum operation device 1609, a 5-bit counter 1610, and a signal line 1611. You. The counter 1610 counts according to the rising edge of the clock signal (CLK), and a portion larger than 5 bits is ignored. Here, for the sake of explanation, it is assumed that the size of the signal line 1611 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  In this example, when data is transferred from the data processing device A (CPU) 1601 to the data processing device B (RAM) 1602, the data processing device A (CPU) 1601 transfers the data in synchronization with a clock signal. When the clock signal is transmitted, the counter 1610 starts counting. The logical sum operation device 1609 transmits the logical sum of all the bits of the counter to the random number generation device 1608. If the value of the logical sum is 0, the random number generation device 1608 generates an 8-bit random number, transmits the 8-bit random number to the key buffer 1607, and stops. At this time, the random number generation device 1608 receives 0 only when all the values of the counter become 0, so that the key exchanges the key used for encryption and decryption every 32 clocks. The key buffer 1607 supplies the same key to all the exclusive OR operation units 1603 and 1606.

  When data is transferred from the data processing device A (CPU) to the data processing device B (RAM) through the signal line 1611, first, the exclusive OR operation device 1603 performs an exclusive OR operation on the value of the key buffer 1607 and the data. On the signal line 1611 for transfer. This encrypted data is subjected to an exclusive OR operation with the value of the same key buffer 1607 before entering the data processing device B (RAM). (RAM) 1602. The power consumed by charging and discharging on the signal line 1611 is different from the original data, and the key used for encryption changes periodically. Therefore, it is difficult to estimate the original data from the power consumption of the signal line 1611.

  FIG. 30 is a basic configuration diagram of an information processing apparatus for describing a twenty-second embodiment of the present invention. This example is an example of encrypting data to be put on a signal line. Further, this example is an example having a device capable of setting and changing key information.

  The information processing apparatus of this embodiment includes a data processing device A (CPU), a data processing device B (RAM), an exclusive OR operation device 1703 as an encryption device, and an exclusive OR operation device 1706 as a decryption device. , A key buffer 1707 for storing 8 bits, and a signal line 1709. Here, for the sake of explanation, it is assumed that the size of the signal line 1709 is 8 bits and the CPU is an 8-bit processor. The size of the signal line and the number of bits of the CPU are not essential in the present invention. Therefore, the above description of the conditions is sufficient to explain the present invention in general.

  The key buffer 1707 is connected to the data processing device A (CPU) 1701, and can change the contents of the key buffer 1707 from the data processing device A (CPU) 1701. The key information held in the key buffer 1707 is used for both encryption and decryption of data sent from the data processing device A (CPU) 1701 to the data processing device B (RAM) via the signal line 1709. Except that the key can be rewritten from the data processing device A (CPU) 1701, the other configuration is the same as that of the nineteenth embodiment of the present invention. Therefore, detailed description of the operation is omitted.

  The following twenty-third to twenty-ninth embodiments of the present invention are examples in which the basic idea of the present invention is applied to a semiconductor memory device or a semiconductor memory device included in a larger information processing device. Therefore, the following twenty-third to twenty-ninth embodiments can be applied to, for example, a storage unit included in a so-called microcomputer system. Further, it is naturally possible to apply the method as in this example to the storage section of such a large semiconductor device system, and further apply the various inventions of the present application to the processing of information of the entire system.

  FIG. 31 is a basic configuration diagram of an information processing device for explaining a twenty-third embodiment of the invention. The information storage device 7001 of the twenty-third embodiment is an example of a so-called semiconductor storage device.

This semiconductor memory device has a memory cell array 7 similar to a basic semiconductor memory device.
002, an address decoder 7005, and a data bus 7007. The present example includes an encryption device 7003, a decryption device 7004, and an encryption key storage device 7006 for signal encryption.

  Here, the configuration itself of the memory cell array 7002 is sufficient as usual. In many cases, the memory cell is constituted by one transistor and one capacitance. Furthermore, other forms are possible.

  FIG. 32 is a circuit diagram showing a typical example of the memory cell array 7002. A region 66 surrounded by a dotted line in FIG. 32 is a region corresponding to one memory cell. Each memory cell 66 is connected to a sense amplifier 60, 61 by a bit line 65, respectively. On the other hand, each word line 64 is connected to word line drivers 62 and 63, respectively. By applying the technical idea to the present invention to such a semiconductor memory device, an extremely useful effect regarding security can be obtained. The outputs of the sense amplifiers 60 and 61 shown in FIG. 32 are, for example, read data from the memory cell array 7002 in FIG. On the other hand, according to the write data in the memory cell array 7002, the capacitance of the memory cell 66 selected by the word line is charged and discharged through the bit line 66. It should be noted that the memory cell array of this example is sufficient for various embodiments of the present invention using the memory cell array described below. Of course, it goes without saying that as another embodiment of the present invention, a memory cell array of another form can be used.

  Hereinafter, the operation of the present example will be described in detail. Writing data to the memory array 7002 is performed as follows. Data is sent from the data bus 7007 to the encryption device 7003. Then, in the encryption device 7003, the data is encrypted by the encryption device 7003 with reference to the information in the encryption key storage device (key buffer) 7006. On the other hand, the address specified by the address bus 7008 is coded by the address decoder 7005 and sent to the memory cell array 7002 as a word selection signal. In the memory cell array, a memory cell to which data is to be written is selected according to the coded address. Then, data encrypted by the encryption processing device 7003 is written in the memory cell.

  Reading data from the memory cell array 7002 is performed as follows. The address specified by the address bus 7008 is decoded by the address decoder 7005 and sent to the memory cell array 7002 as a word select signal. Then, the contents of the memory cell selected by the word selection signal are read. The content of the read memory cell is sent to the decoding device 7004. The decryption device 7004 performs decryption by referring to the encryption key information extracted from the encryption key storage device (key buffer) 7006. The decoded data is output to the data bus 7007. Here, the key information of the encryption key storage device 7006 can be rewritten from outside. The same can be said for the encryption key storage device in an example other than the present embodiment in the specification of the present application.

  As described above, in one embodiment of the present invention, data sent from the data bus 7007 is encrypted before being stored in the memory cell array 7002, and decryption is performed when data is read from the memory cell array 7002. And output to the data bus 7007.

  Therefore, even a semiconductor device including a memory cell array can be handled in the same manner as the various information processing devices described above. As a result, since the bit pattern of the data actually recorded on the memory cell is different from the data to be stored, the data on the cell is estimated from the current consumption pattern when writing / reading the data on the cell. Things become difficult.

  As described above, the present invention can be applied to a semiconductor memory device having ordinary memory cells. It goes without saying that the present invention is not limited to this example and the following examples. In the above-described example, the address for selecting a row of a general matrix memory array has been described. However, the inventive idea of the present embodiment can be applied to the columns of the memory array. Further, the inventive idea of the present application can be applied to both the rows and columns of the memory array.

  Against this background, a so-called semiconductor memory device is referred to as an information processing device in the following embodiments. Therefore, in the specification of the present application, the information processing device includes a so-called semiconductor memory device.

  FIG. 33 is a basic configuration diagram of an information processing apparatus for describing a twenty-fourth embodiment of the invention. This example is an example of a so-called semiconductor memory device. In this example, an encryption key is used for encryption.

  The information storage device of this embodiment includes a memory cell array 7002, an address decoder 7005, and a data bus 7007, as in a general semiconductor storage device. Then, in this example, for encrypting and decrypting a signal, a new encryption is performed from the encryption device 7003, the decryption device 7004, the encryption key storage device 7006, the key of the encryption key storage device, and a part of the address information. An EOR circuit 7109 for generating the encryption key is provided. Here, the configuration of the memory cell array 7002 is sufficient as usual.

  Writing data to the memory array 7002 is performed as follows. Data is sent from the data bus 7007 to the encryption key storage device 7006. Then, in the encryption key storage device 7006, the information in the encryption key storage device 7006 and the information on the address bus 7008 are combined by the exclusive OR operation device 7109. Using the encryption key thus obtained, the data sent from the data bus 7007 is encrypted by the encryption device 7003. On the other hand, the address specified by the address bus 7008 is coded by the address decoder 7005 and sent to the memory cell array 7002 as a word selection signal.

  In the memory cell array, a memory cell to which data is to be written is selected according to the coded address. Thus, data encrypted by the encryption processing device 7003 is written to the memory cell.

  Reading data from the memory cell array is as follows. The address specified by the address bus 7008 is coded by the address decoder 7005 and sent to the memory cell array 7002 as a word selection signal. Then, the contents of the memory cell selected by the word selection signal are read. The content of the read memory cell is sent to the decoding device 7004. The decryption device 7004 uses the encryption key obtained by synthesizing the information in the encryption key storage device (key buffer) 7006 and the information on the address bus 7008 by the EOR circuit 7109 to read out the content read from the memory cell. Is decrypted. The decoded data is output to the data bus 7007.

  As described above, the data sent from the data bus 7007 is encrypted before being stored in the memory cell array 7002, while the data is read from the memory cell array and is decrypted and stored in the data bus 7007. Is output. Therefore, the semiconductor storage device can be handled in the same manner as a normal information storage device. As a result, since the bit pattern of the data recorded on the cell is different from the data to be stored, the actual data on the cell can be easily estimated from the current consumption pattern when writing / reading the data on the cell. Things become difficult.

  FIG. 34 is a basic configuration diagram of an information processing apparatus for explaining a twenty-fifth embodiment of the invention. This example is an example of a so-called semiconductor memory device. In this example, an encryption key is used for encryption, but this encryption key is automatically initialized.

  In the information storage device of the present embodiment, an encryption key automatic initialization device 7210 is connected to the encryption key storage device 7006 of the embodiment of FIG. 31, and the encryption key is initialized by the encryption key automatic initialization device 7210. It is like that. Other configurations of this example are the same as those of the above-described example, and thus detailed description thereof will be omitted.

  The automatic encryption key initialization device 7210 is configured to set an initial value using a usual random number generation device. When the information processing apparatus is started or reset-started, the encryption key automatic initialization device 7210 automatically generates an encryption key using a random number and sets the encryption key in the encryption key storage device 7006. As a result, the encryption key is changed every time the apparatus is started or reset, and even when the same data is stored, the current consumption pattern at the time of writing and reading data on the cell changes each time the apparatus is started. Therefore, it is difficult to easily estimate the actual data on the cell from the current consumption pattern.

  FIG. 35 is a basic configuration diagram of an information processing device for describing a twenty-sixth embodiment of the invention. This example is an example of a so-called semiconductor memory device. In the present embodiment, whether or not to perform encryption is controlled.

  The information storage device of this embodiment includes a memory cell array 7002, an address decoder 7005, an encryption device 7003, a decryption device 7004, an encryption key storage device 7006, an encryption area designation register 7311, and an encryption determination circuit 7312. Here, the configuration of the memory cell array 7002 is sufficient as usual.

  The memory array 7002 is classified into a plurality of areas according to the address value, and the encryption area specification register 7311 specifies whether to encrypt each area. The encryption determination circuit 7312 determines whether to perform encryption based on the address value appearing on the address bus 7008 and the value of the encryption area designation register 7311.

  FIG. 20 shows one embodiment of the encryption judgment circuit used in this embodiment. This example is the same as described above. In this embodiment of the encryption judging circuit, the memory array is identified in each state of p bits by referring to the upper p bits at the time of dividing the memory, and divided into 2 ＾ p regions. The encryption area designation register 7311 has a length of 2 ^ p bits, and each bit corresponds to one area on the memory array, and controls whether or not to perform encryption.

  Each bit of the encryption area designation register 7311 and a bit pattern representing an address area corresponding to the bit are interleaved with NOT so that all the bits become 1, and then the corresponding bit of the encryption area designation register is set. Perform a logical conjunction. When the logical product is 1, encryption is performed, and when the logical product is 0, encryption is not performed. A similar circuit is created for each bit of the encryption area designation register 7311, and then the logical sum of all the bits of the logical product is obtained by the OR circuit 7314. When the logical sum is 1, encryption is performed, and when it is 0, encryption is not performed.

  Next, the logical product of the output of the encryption determining circuit 7312 and the AND of the encryption key is calculated by the logical product calculating device 7313. The output of the AND operation device 7313 has the same value as the encryption key when performing encryption, but outputs 0 when not performing encryption. When 0 is given as the encryption key, the input and output of the encryption device 7003 become equal, which is equivalent to not performing encryption.

  The procedure of decryption of the reading is the same as in the writing, based on the value of the address and the value of the encryption area designation register 7311, whether the encryption key at the time of decryption is set to 0 or the value of the encryption key. Control and perform decryption.

  In this way, the memory cell array is divided into a plurality of areas by the address, and the presence or absence of encryption can be set for each area. In the encrypted area, the bit pattern of the data recorded on the cell is different from the data to be stored. The data becomes difficult to guess easily.

  The twenty-seventh to twenty-eighth embodiments are examples in which a so-called semiconductor storage device and another information processing device are included in one device.

  FIG. 36 is a basic configuration diagram of an information processing apparatus for describing a twenty-seventh embodiment of the present invention.

  In this example, the subsequent operation will be described assuming that the information storage device 7052 stores data that has been encrypted in advance. The storage of the encrypted data can be performed by the various methods described above. In the information storage device of this embodiment, a data processing device 7051 and an information storage device 7052 are connected by a data bus 7057. Further, between the data processing device 7051 and the data bus 7057, there are provided a decryption device 7053 and a key buffer 7056 storing key information for decrypting the encryption by the decryption device.

  Here, the decryption device and the key buffer itself described above are sufficient. As described above, the information storage device 7052 stores in advance information encrypted in a format that can be decrypted by the decryption device 7053 and the encryption key stored in the key buffer 7056. The encrypted information is sent to the decryption device 7053 via the data bus 7057, and is decrypted by the decryption device 7053. Then, the decrypted data is sent from the decryption device 7053 to the data processing device 7051.

  Therefore, the information flowing through the information storage device and the signal line has a bit pattern different from the information used in the data processing device, and the information is estimated from the current consumption pattern in the information storage device 7052 and the data bus 7057. Things become difficult.

  FIG. 37 is a basic configuration diagram of an information processing apparatus for describing a twenty-eighth embodiment of the present invention. This example is an example in which an encryption key is used to decrypt data.

  In this example, the subsequent operation will be described assuming that the information storage device 7052 stores data that has been encrypted in advance. The storage of the encrypted data can be performed by the various methods described above.

  In the information storage device of this embodiment, a data processing device 7051 and an information storage device 7052 are connected by a data bus 7057. Further, between the data processing device 7051 and the data bus 7057, a decryption device 7053, a key buffer 7056 storing key information for decrypting encryption by the decryption device, and an address bus 7058 are provided. . Here, the decryption device and the key buffer itself described above are sufficient.

  The decryption device 7053 calculates the EOR of a part of the storage address of the information storage device 7052 and the encryption key stored in the key buffer 7056 as an encryption key at the time of decryption. use. Information encrypted in a format that can be decrypted by the decryption device 7053 is stored in the information storage device 7052 in advance.

  When the data processing device 7051 outputs the address information to the address bus 7058, the information storage device 7052 outputs the data encrypted to the data bus to the data bus 7057 as it is. The decryption device 7053 stores the EOR of a part of the storage address of the information storage device 7052 and the encryption key stored in the key buffer 7056 with the information obtained by encrypting the decryption key calculated by the EOR circuit 7054. Is sent as the key. Then, the information on the data bus 7057 is decrypted by this key and sent to the data processing device 7051.

  In this case, the information flowing through the information storage device 7052 and the data bus 7057 has a bit pattern different from the information used in the data processing device 7051. In addition, since the encryption key information differs for each storage address, even if the power consumption is the same value, encryption is performed in different bit patterns depending on the address. Therefore, it is more difficult to infer information from the current consumption pattern in the information storage device and the signal lines than in the invention according to the twenty-seventh embodiment. FIG. 38 is a diagram showing the basic configuration of an information processing apparatus for explaining a twenty-ninth embodiment of the present invention. This example is an example having a so-called semiconductor storage device and another information processing device.

  In the information storage device of this embodiment, a data processing device 7051 and an information storage device 7052 are connected by a data bus 7057. Further, between the data processing device 7051 and the data bus 7057, a decryption device 7053, a key buffer 7056 storing key information for decrypting encryption by the decryption device, and an address bus 7058 are provided. . In addition, an AND circuit 1112, an encryption area specification register 7311, and an encryption determination circuit 7312 are provided to specify which area of the storage area is to be encrypted. Here, the configuration of the information storage device 7052 is sufficient as usual. In addition, individual means such as the decryption device and the key buffer itself, for example, those described so far are sufficient.

  The operation relating to the specification of the encryption area characteristic of the present embodiment will be mainly described.

  Whether or not each storage area has been encrypted is designated by an encryption area designation register 7311. The encryption determination circuit 7312 determines whether to perform decryption based on the address value appearing on the address bus 7058 and the value of the encryption area designation register 7311. The configuration of the encryption determination circuit is the same as that of FIG. Information encrypted in a format that can be decrypted by the decryption device 7053 is stored in the information storage device 7052 in advance. When the data processing device 7051 outputs address information to the address bus 7058, the information storage device 7052 outputs the encrypted data to the data bus. The encryption determination circuit 7312 refers to a part of the address value output to the address bus 7058 and the value of the encryption area designation register 7311 to determine whether or not the data at the address is encrypted. If it is encrypted, it returns 1; if it is not encrypted, it returns 0.

  The output of the encryption determination circuit 7312 is ANDed with the key buffer 7056 by the AND circuit 1112. As a result, the contents of the key buffer 7056 are passed to the decryption device 7053 when the encrypted address area is accessed, and 0 is passed when the unencrypted address area is accessed. Since the decryption device 7053 is an EOR circuit, when 0 is passed, the input value is passed to the data processing device 7051 as it is. Therefore, the data in the encrypted area is correctly decrypted using the value of the key buffer 7056, while the data in the unencrypted area is passed to the data processing device 7051 as it is. In the encrypted area, the bit pattern appearing on the data bus 7057 and the bit pattern of the data recorded in the information storage device 7052 are different from the actual data. It is difficult to estimate actual data from the current pattern consumed by the data bus 7057.

  FIG. 39 is a basic configuration diagram of an information processing apparatus for describing a thirtieth embodiment of the invention. This example is an example of a semiconductor device system having a so-called semiconductor memory device and another information processing device.

  The random transfer control device of the present embodiment includes an address register 18002 for storing a source address, an address register 18003 for storing a destination address, a multiplexer 18004 for switching between a source and a destination register, An adder 18005 for updating the value of the transfer source address register, an exclusive OR operation device 18007 for taking the address register, the random number, and the EOR to randomize the transfer order of the transfer address, and an exclusive OR. An arithmetic unit 18007 generates a random number used for an exclusive OR operation for changing the transfer order, a random number generator 18006 for generating a random number value, a counter 18009 for counting the number of transfers, and an address generated by changing the order. An address buffer 18008 for temporarily storing data to be transferred, Temporarily stores the data buffer 18011 to data, it is constituted by an address register for storing the address when lend random transfer order, the control circuit 18012 to perform transfer by controlling each of these circuits. First, the transfer source address is set in the transfer source address register 18002, the transfer destination address is set in the transfer destination address register 18003, and the number of transfer bytes is set in the counter 18009. Here, the initial value of the number of transfer bytes set in the counter is a power of two. The value set as the initial value in the transfer source address register 18002 and the transfer destination address register 18003 needs to be a value that becomes 0 when the surplus is calculated based on the number of transfer bytes. Next, the transfer operation of the control device 18012 will be described step by step.

  STEP 0: First, a random number generation request is sent from the control circuit 18012 to the random number generation circuit 18006, and the random number generation circuit 18006 generates and holds a random number having a value smaller than the number of transfer bytes before transfer.

  STEP 1: Next, a selection signal is sent from the control circuit 8012 to the multiplexer 18004 to select the source address register 18002, and the source address passed through the multiplexer is stored in the random number generation circuit 18006. The exclusive OR operation with the numerical value is performed by the exclusive OR operation device 18007 and stored in the address buffer 18008.

  STEP 2: The control circuit 18012 outputs the address value of the address buffer 18008 to the address bus, and after the content of the address value on the address bus 18032 is loaded on the data bus 18031, the control circuit 18012 outputs the latch signal to the data buffer. 18011 to store the value of the data bus in the data buffer 18011. In the addition circuit 18005, calculation for adding 1 to the value of the transfer source address register is performed. After the addition, the control circuit 18012 controls the latch signal for the transfer source address register, and stores the output of the adder circuit in the transfer source address register.

  STEP3: Next, the control circuit 18012 sends a selection signal from the control circuit 18012 to the multiplexer 18004 so as to select the transfer destination address register 18003, and the transfer destination address passing through the multiplexer is held in the random number generation circuit 18006. The EOR circuit 18007 performs an EOR operation on the obtained random number value and stores the result in the address buffer 18008.

  STEP 4: The control circuit 18012 sends a control signal to output the address value of the address buffer 18008 to the address bus 18032 and to output the data value of the data buffer 18011 to the data bus 18031. Further, a control signal is issued to write the data on the data bus 18031 to the address on the address bus 18032.

  STEP 5: The addition circuit 18005 calculates that 1 is added to the value of the transfer destination address register. After the addition is completed, the control circuit 18012 controls the latch signal for the transfer destination address register 18003 and stores the output of the addition circuit 18005 in the transfer destination address register 18003.

  STEP 6: −1 is added to the value of the counter 18009 by the addition circuit 18010, and 1 is subtracted. The control circuit 18012 sends a latch signal to the counter 18009, and stores the operation result of the adding circuit 18010 in the counter 18009.

  STEP 7: Next, the control circuit checks whether or not the content of the counter 18009 is 0. If the content is not zero, the control circuit repeats the processing from STEP 1.

  With the above operation, even when the same content is transferred to the same address due to the difference in the random number value, the data transfer order is different due to the different random number value generated by the random number generation circuit, and the The current consumption pattern differs for each transfer, and it becomes difficult to estimate whether or not the same data is being transferred from the current consumption pattern.

FIG. 1 is a diagram showing a basic configuration of a microcomputer. FIG. 2 is a diagram showing an arrangement of the semiconductor integrated circuit device in the IC card. FIG. 3 is a configuration diagram showing an outline of the card system. FIG. 4 is a diagram showing a current waveform indicating power consumption in one cycle in a conventional semiconductor device for an IC card. FIG. 5 is a basic configuration diagram showing the first embodiment of the information processing apparatus of the present application. FIG. 6 is a diagram showing an example of a flip-flop for temporarily storing data. FIG. 7 is a diagram showing the state of the signal line and the state of the capacitor for power consumption. FIG. 7A shows various examples in the case of the precharge system, and FIG. 7B shows various examples in the case of the static system. It is shown. FIG. 8 is a basic configuration diagram showing a second embodiment of the information processing apparatus of the present application. FIG. 9 is a basic configuration diagram showing another example of the second embodiment of the information processing apparatus of the present application. FIG. 10 is a basic configuration diagram showing a third embodiment of the information processing apparatus of the present application. FIG. 11 is a basic configuration diagram showing a fourth embodiment of the information processing apparatus of the present application. FIG. 12 is a basic configuration diagram showing a fifth embodiment of the information processing apparatus of the present application. FIG. 13 is a basic configuration diagram showing a sixth embodiment of the information processing apparatus of the present application. FIG. 14 is a basic configuration diagram showing a seventh embodiment of the information processing apparatus of the present application. FIG. 15 is a basic configuration diagram showing an eighth embodiment of the information processing apparatus of the present application. FIG. 16 is a basic configuration diagram showing a ninth embodiment of the information processing apparatus of the present application. FIG. 17 is a basic configuration diagram showing a tenth embodiment of the information processing apparatus of the present application. FIG. 18 is a basic configuration diagram showing an eleventh embodiment of the information processing apparatus of the present application. FIG. 19 is a basic configuration diagram showing a twelfth embodiment of the information processing apparatus of the present application. FIG. 20 is a diagram illustrating an example of the encryption determination circuit. FIG. 21 is a basic configuration diagram showing a thirteenth embodiment of the information processing apparatus of the present application. FIG. 22 is a basic configuration diagram showing a fourteenth embodiment of the information processing apparatus of the present application. FIG. 23 is a basic configuration diagram showing a fifteenth embodiment of the information processing apparatus of the present application. FIG. 24 is a basic configuration diagram showing a sixteenth embodiment of the information processing apparatus of the present application. FIG. 25 is a basic configuration diagram showing a seventeenth embodiment of the information processing apparatus of the present application. FIG. 26 is a basic configuration diagram showing an eighteenth embodiment of the information processing apparatus of the present application. FIG. 27 is a basic configuration diagram showing a nineteenth embodiment of the information processing apparatus of the present application. FIG. 28 is a basic configuration diagram showing a twentieth embodiment of the information processing apparatus of the present application. FIG. 29 is a basic configuration diagram showing a twenty-first embodiment of the information processing apparatus of the present application. FIG. 30 is a basic configuration diagram showing a twenty-second embodiment of the information processing apparatus of the present application. FIG. 31 is a basic configuration diagram showing a twenty-third embodiment of the information processing apparatus of the present application. FIG. 32 is a diagram showing one example of a memory cell array. FIG. 33 is a basic configuration diagram showing a twenty-fourth embodiment of the information processing apparatus of the present application. FIG. 34 is a basic configuration diagram showing a twenty-fifth embodiment of the information processing apparatus of the present application. FIG. 35 is a basic configuration diagram showing a twenty-sixth embodiment of the information processing apparatus of the present application. FIG. 36 is a basic configuration diagram showing a twenty-seventh embodiment of the information processing apparatus of the present application. FIG. 37 is a basic configuration diagram showing a twenty-eighth embodiment of the information processing apparatus of the present application. FIG. 38 is a basic configuration diagram showing a twenty-ninth embodiment of the information processing apparatus of the present application. FIG. 39 is a basic configuration diagram showing a thirtieth embodiment of the information processing apparatus of the present application. FIG. 40 is a diagram illustrating a mounting example of the key buffer.

Explanation of reference numerals

8001 is a central processing unit, 8002 is a storage device, 51 is a semiconductor chip, 52 is a card member, 53 is a reader / writer, 54 is a control processor, 55 is a magnetic disk, 0101, 0401, 0501 are information processing devices (ROM), 0102, 0201, 0251, 0301, 0402, 0502 are information processing devices (CPU), 0202, 0252, 0302 are information processing devices (RAM), 1101, 1301, 1401, 1501, 1601, 1701, 1301, 1401, 1601, 1701 is a data processing device (CPU), 1102, 1302, 1402, 1502, 1602, 1702, 1302, 1402, 1602, and 1702 are data processing devices (RAM), 0113, 0213, 0263, 0312, 0408, and 0506 are signal lines. 0114, 0115, 0116, 0117, 0118, and 0119 are power generators, 0309 and 0507 are dummy signal lines, 0407, 0505, and 5008 are precharge signal controllers, 5003 is an inverting device, 51101 is a data processing device, and 51102 is information. A storage device, 51107 and 7007 are data buses, 51108 and 7008 are address buses, and 7002 is a memory cell array.

Claims (11)

An information processing device and at least a signal line connected to the first information processing device, the power consumption corresponding to a power consumption state of the signal line transmitting a signal from the information processing device. An information processing apparatus wherein power consumption different from a state is enabled. An information processing device, and at least a signal line connected to the information processing device, and a second power consumption corresponding to a first power consumption state of the signal line transmitting a signal of the information processing device. An information processing apparatus, wherein a consumption state is determined, and the information processing apparatus is configured such that the sum of the first power consumption and the second power consumption in the signal line has a desired value. An information processing device, and at least a signal line connected to the information processing device, a signal sequence output from the information processing device is transmitted through the signal line in a different order, and the signal sequence An information processing apparatus characterized by being able to restore the changed order. A first data processing device, a second data processing device, a signal line connecting the two, a control signal generating means, a first power consumed by the signal line, and a power on the signal line At least means for consuming a second power different from the power consumption, wherein the first or second data processing device is connected to the second power consuming means, and the control signal generating means Is controlled by a control method that does not clear the signal mounted on the signal line by the control signal. When the signal is transferred between the first and second data processing devices via the signal line, the first A signal output from the first or second data processing device in response to a signal from the control signal generating means, such that a sum of the power consumption of the second power consumption and the second power consumption becomes a predetermined value; Get on the signal line just before signal transfer The exclusive OR is obtained for a signal that has been input and a signal input to the charging / discharging device immediately before the transfer of the signal, and the output signal can be input to the second power consuming means. An information processing apparatus characterized by the above-mentioned. A first data processing device, a second data processing device, a signal line connecting the two, a control signal generating means, a first power consumed by the signal line, and a power on the signal line At least means for consuming a second power different from consumption, wherein the first and second data processing devices each have a first means for consuming the second power and a second means for consuming the second power. Connected to a second means for consuming power, controlled by a control signal from the control signal generation means in a control method that does not clear a signal mounted on the signal line, and provided between the first and second data processing devices. When transferring a signal via the signal line in the above, according to a signal from the control signal generating means, so that a sum of the first power consumption and the second power consumption becomes a predetermined value. Output from the first or second data processing device The exclusive OR of the signal, the signal on the signal line immediately before the transfer of the signal, and the signal input to the charging / discharging device immediately before the transfer of the signal is obtained, and the output signal is obtained. An information processing apparatus wherein an input to the second power consuming means is possible. 2. The information processing apparatus according to claim 1, wherein the second unit that consumes the second power has a dummy signal line. A first data processing device, a second data processing device, a signal line connecting the two, a precharge signal control means, a first power consumed by the signal line, At least means for consuming a second power different from the power consumption of the first, the first or second data processing device is connected to the means for consuming the second power, and The second or first data processing device is connected to the control means for the precharge signal, and transfers the first power when the signal is transferred between the first and second data processing devices via the signal line. An information processing apparatus characterized in that the sum of the power consumption and the second power consumption is set to a predetermined value. A first data processing device, a second data processing device, a signal line connecting them, and a precharge signal line control device for precharging the signal line; Is connected to the precharge signal line control device, and further connected to a complementary precharge bus control device, wherein the precharge bus control device is connected to the signal line, and the complementary precharge bus control device is Connected to means for consuming a second power different from the first power consumption in the signal line, wherein a sum of the first power consumption and the second power consumption in the data signal line is a predetermined value. An information processing apparatus characterized in that data to be sent to a bus is bit-inverted and input to a second power consuming means immediately after precharging of the signal line. 9. An information processing apparatus according to claim 7, wherein said second means consuming said second power has a precharge dummy signal line. A storage device, a data processing device including the storage device, a signal line connecting them, and at least an information transfer control device device that controls information transfer between the storage device and the data processing device including the storage device, An address register for storing the address where the information of the transfer source is stored, an address register for storing the address of the transfer destination, and a numerical value for counting the number of information to be transferred; And an arithmetic circuit for decrementing the value of the counter, a data buffer for temporarily storing data to be transferred between the storage devices, an arithmetic circuit for updating the value of the address register, and a transfer address. An information processing apparatus comprising a circuit for randomizing the transfer order of the information. An information processing device and at least a signal line connected to the first information processing device, the power consumption corresponding to a power consumption state of the signal line transmitting a signal from the information processing device. A card member characterized by being able to consume power different from the state.

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