JP2004258871A - Bus arbitration circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus arbitration circuit capable of reducing area and consumption power without decreasing data transfer speed by effectively utilizing bus resource. <P>SOLUTION: The bus arbitration circuit has a parallel data bus 11 of two systems and a serial data bus 12 of one system. A bus arbitration part 10 controls to use the serial data bus 12 when bus use priority levels of bus use request source masters 15-1, 15-2 are at level 1. For level 2, the parallel data bus 11 is controlled to use a system and data transfer is performed with doubled clock frequency of usual operation by a parallel/serial mixed transfer method. For level 3, 4, the parallel data bus 11 are controlled to use two systems. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bus arbitration technique for controlling data transfer between various devices by effectively utilizing bus resources.
[0002]
[Prior art]
FIG. 9 shows the configuration of a conventional bus arbitration circuit. Since the bus arbitration circuit 90 includes a plurality of 32-bit high-speed parallel buses 91, the CPU (Central Processing Unit), the RAM (Random Access Memory), the DMAC (Direct Memory Access Controller), the LCD (Liquid Crystal), and the like. High-speed data transfer between a plurality of devices. (See, for example, Patent Document 1)
[0003]
[Patent Document 1]
JP-A-7-230420 (page 1, FIG. 3)
[0004]
[Problems to be solved by the invention]
However, in the above-described conventional bus arbitration circuit, when a low-speed device such as an LCD or a hard disk drive (HDD) uses the bus, the bus becomes overspec. That is, when the data transfer speed to the low-speed device is, for example, 8 bits, only 1/4 of the bus width of 32 bits is used. Further, since the number of buses needs to be increased with the increase in the number of slave devices, there is a problem that the area of the bus arbitration circuit is greatly increased.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the conventional technology, and has been developed to provide a bus arbitration circuit that can effectively utilize bus resources and reduce the area and power consumption without lowering the data transfer rate. The purpose is to provide.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a bus arbitration circuit of the present invention includes a parallel data bus, a serial data bus, and a bus arbitration unit that controls use of a bus by various devices. The right to use the parallel data bus or the serial data bus is given to the bus use requesting device in accordance with the data transfer amount and the data transfer request speed from the requesting device.
[0007]
With this configuration, the bus resources can be effectively used, and the area can be reduced and the power consumption can be reduced without lowering the data transfer speed.
[0008]
Further, in the bus arbitration circuit of the present invention, the parallel data bus has two systems and the serial data bus has one system. When performing data transfer to a high-speed device, the bus arbitration unit includes the two systems of parallel data buses. Is given to the bus requesting device, thereby enabling data transfer by the high-speed parallel data transfer method using the two parallel data buses. When performing data transfer to a low-speed device, the serial data bus is used. By granting the right to use the device to the bus use requesting device, it is possible to perform data transfer by the serial data transfer method using the serial data bus, perform data transfer to a high-speed device, and perform data transfer to a low-speed device. The right to use the two parallel data buses is transferred to the high-speed device. A bus use requesting device that performs data transfer and a right to use the serial data bus to a bus use requesting device that performs data transfer to the low-speed device. Data transfer by the parallel data transfer method and data transfer by the serial data transfer method using the serial data bus can be simultaneously performed.
[0009]
With this configuration, data transfer using the high-speed parallel data transfer method, the serial data transfer method, or both transfer methods simultaneously can be performed.
[0010]
In the bus arbitration circuit of the present invention, when the bus width of the parallel data bus is m (m is a positive number) bits, the bus arbitration unit uses the parallel data bus to make n (n is a positive number). It is desirable to have a function that enables data transfer by a parallel / serial mixed transfer method that performs bit-serial transfer and mxn bit transfer at a clock frequency that is n times the normal clock frequency.
[0011]
According to this configuration, data transfer by the parallel / serial mixed transfer method can be performed by effectively utilizing the bus width of the parallel data bus.
[0012]
In the bus arbitration circuit of the present invention, it is preferable that the bus arbitration unit has a function of changing a bus width used by each bus use request source device according to the bus use priority level.
[0013]
According to this configuration, for example, when data transfer is performed between a plurality of devices at the same time, data transfer by the parallel / serial mixed transfer method can be performed by more effectively utilizing the bus width of the parallel data bus.
[0014]
Further, in the bus arbitration circuit of the present invention, the bus arbitration unit may be configured to perform a request when a new bus use request for the parallel data bus occurs during the data transfer using the high-speed parallel data transfer method. It is desirable to have a function of switching to data transfer using the parallel / serial mixed transfer method.
[0015]
According to this configuration, when both parallel data buses are used by the high-speed parallel data transfer method, the data transfer is switched to the parallel / serial mixed transfer method as necessary, so that the data transfer during the data transfer is performed. And the data transfer for which a new bus use request has occurred can be performed simultaneously by the parallel / serial mixed transfer method.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
FIG. 1 is a circuit diagram showing an example of an embodiment of a bus arbitration circuit of the present invention. The bus arbitration circuit 1 includes two parallel data buses 11, one system serial data bus 12, these buses 11 and 12, and various devices (CPU 15-1, DMAC 15-2, RAM 16-1, LCD 16-2). ,...).
[0018]
Slave devices such as the RAM 16-1 and the LCD 16-2 (hereinafter simply referred to as slaves) transmit a busy signal 13 indicating the status of their own device to a master device such as the CPU 15-1 and DMAC 15-2 (hereinafter simply referred to as master). Output to
[0019]
When performing data transfer, each master outputs the ID signal 21 of the data transfer destination slave to the bus arbitration unit 10.
[0020]
The bus arbitration unit 10 recognizes the ID signal 21 as a bus request signal. Then, the master that has issued the bus request signal and the transfer destination slave are connected, and the bus use permission signal 22 is output to give the bus request right to the bus request source master.
[0021]
Further, each master has a function of outputting a bus use priority signal simultaneously with the ID signal 21. The bus use priority signal indicates any one of the levels 1 to 4 of the bus use priority level. The bus use priority level is determined by the data transfer amount and the data transfer request speed from each master.
[0022]
When the bus use priority level is level 1, the bus arbitration unit 10 determines that low-speed data transfer is to be performed, and controls the serial data bus 12 to be used. In the case of level 2, it is determined that the transfer is medium speed data, and control is performed so that one system of the parallel data bus 11 is used. Then, the data transfer is performed by a parallel / serial mixed transfer method in which the clock (CLK) frequency is doubled and the 32-bit (bit) transfer is performed. At levels 3 and 4, high-speed data transfer is determined, and control is performed so that two parallel data buses 11 are used. However, only at level 4, all other parallel data transfers already in progress at that time are stopped, two parallel data buses 11 are secured with the highest priority, and other parallel data transfers are performed until the transfer is completed. Perform rejection control.
[0023]
Next, an operation example of the bus arbitration circuit 1 will be specifically described with reference to FIGS. The bus width of each parallel data bus 11 is 16 bits, and the usable bus width of the CPU 15-1, DMAC 15-2, and RAM 16-1 is 32 bits at the maximum.
[0024]
FIG. 2 is an operation explanatory diagram in the case where high-speed data transfer (32-bit high-speed parallel data transfer) is performed between the CPU 15-1 and the RAM 16-1. In this case, after confirming from the busy signal 13 of the RAM 16-1 that the RAM 16-1 is not busy, the CPU 15-1 outputs the ID signal 21 of the RAM 16-1 to the bus arbitration unit 10 (FIG. 1). Make a bus request. The bus arbitration unit 10 confirms that no other bus 11 is used, gives the right to use the two parallel buses 11 to the CPU 15-1 and the RAM 16-1, and transmits a 32-bit data between the CPU 15-1 and the RAM 16-1. Set to a state where high-speed parallel data transfer can be performed. The bus use priority signal level at this time is level 3 or level 4.
[0025]
FIG. 3 is an operation explanatory diagram in the case where low-speed data transfer (8-bit serial data transfer) is performed between the DMAC 15-2 and the LCD 16-2. In this case, the DMAC 15-2 confirms from the busy signal 13 of the LCD 16-2 that the LCD 16-2 is not in a busy state, and then outputs the ID signal 21 of the LCD 16-2 to the bus arbitration unit 10 (FIG. 1). Make a bus request. The bus arbitration unit 10 confirms that the serial data bus 12 is not used, gives the right to use the serial data bus 12 to the DMAC 15-2 and the LCD 16-2, and transfers serial data between the DMAC 15-2 and the LCD 16-2. Ready to perform At this time, the bus use priority signal level is level 1.
[0026]
FIG. 4 is an operation explanatory diagram in a case where high-speed data transfer between the CPU 15-1 and the RAM 16-1 and low-speed data transfer between the DMAC 15-2 and the LCD 16-2 occur simultaneously. In this case, after confirming that the RAM 16-1 is not in the busy state, the CPU 15-1 outputs the ID signal 21 of the RAM 16-1 to the bus arbitration unit 10 (FIG. 1) to make a bus request. Similarly, the DMAC 15-2 confirms that the LCD 16-2 is not in a busy state, and outputs an ID signal 21 of the LCD 16-2 to the bus arbitration unit 10 to make a bus request. The bus arbitration unit 10 can simultaneously perform high-speed data transfer and low-speed data transfer by giving the CPU 15-1 the right to use the two parallel buses 11 and the DMAC 15-2 to use the serial data bus 12. State.
[0027]
FIG. 5 is an explanatory diagram of the operation when a data transfer request by the CPU 15-1 and the DMAC 15-2 to the dual port SRAM occurs simultaneously when the RAM 16-1 is a dual port SRAM. In this case, each of the CPU 15-1 and the DMAC 15-2 confirms that the RAM 16-1 is not busy, and outputs the ID signal 21 of the RAM 16-1 to the bus arbitration unit 10 (FIG. 1) to make a bus request. The bus arbitration unit 10 gives the right to use the parallel bus 11 to the CPU 15-1 and the DMAC 15-2 one system at a time, and performs control so that the transfer is performed by the mixed parallel / serial transfer method. The bus use priority signal level at this time is level 2.
[0028]
Next, details of the parallel / serial mixed transfer system of FIG. 5 will be described with reference to FIG. 6, when the master 15 issues a bus request by issuing the ID signal 21 of the slave 16 to the bus arbitration unit 10, the bus arbitration unit 10 confirms the availability of the parallel bus 11 and uses the bus of the parallel bus 11. The permission signal 22 is output to the master 15 and the slave 16. At this time, the bus use permission signal 22 specifies that the n-bit parallel / serial mixed transfer is performed. The master 15 and the slave 16 having received the bus use permission signal 22 use the respective parallel / serial converters (transmission side) 61 and 71 and serial / parallel converters (reception side) 62 and 72 to perform n-bit parallel Perform serial mixed transfer. After the transfer is completed, the master 15 cancels the bus request. The bus arbitration unit 10 releases the parallel bus 11.
[0029]
FIG. 7 is an explanatory diagram of a data conversion method in the parallel / serial mixed transfer method. FIG. 7 exemplifies a case where 8-bit parallel transfer data is converted into 2-bit parallel / serial mixed transfer data. The parallel transfer data D0, D1, D2, D3, D4, D5, D6, and D7 are converted into 2 bits. By serially converting the data into serial data, serial mixed transfer data D01, D23, D45, and D67 are generated. By doing so, the number of used data lines (used bus width) can be reduced to 1 / n (1/2 in this case).
[0030]
However, if the data transfer by the n-bit parallel / serial mixed transfer method is performed at the same clock frequency as that of the parallel transfer method, it takes n times longer transfer time than the parallel transfer method. I can't. Therefore, when performing high-speed data transfer, it is necessary to increase the clock frequency to n times the normal frequency. The clock frequency is changed by clock generators in the master and the slave. However, in a system for portable devices, it is not desirable to always increase the clock frequency to n times the normal from the viewpoint of power consumption. Therefore, a configuration in which high-speed data transfer is performed only when the bus use priority signal level is level 4 is adopted. I do.
[0031]
Next, the operation of the bus arbitration unit 10 when a new use request of the two parallel data buses occurs during the high-speed data transfer will be described with reference to the flowchart of FIG.
[0032]
In the example of FIG. 8, when high-speed data transfer using both the parallel data buses 11 is performed between the CPU 15-1 and the dual port RAM 16-1 (hereinafter referred to as (1)) (step S1), A bus request (a 32-bit high-speed parallel data transfer request) has occurred between the DMAC 15-2 and the dual port RAM 16-1 (step S2).
[0033]
If the bus use priority signal level of (1) is level 4 (level 4 in step S3), the bus arbitration unit 10 checks the bus use priority signal level of (2) (step S4). As a result, if the bus use priority signal level of (2) is level 3 (level 3 in step S4), a new bus request of (2) is rejected, and high-speed data transfer of (1) is prioritized.
[0034]
In step S4, if the bus use priority signal level of (2) is level 4, the parallel data bus 11 is assigned to each of (1) and (2), and data transfer is performed by the parallel / serial mixed transfer method. (S5). When the data transfer of (1) or (2) is completed (S6), two systems of the parallel data bus 11 are allocated to the uncompleted data transfer, and the high-speed parallel transfer is switched (S7).
[0035]
In step S3, if the bus use priority signal level of (1) is level 3, the data transfer of (1) is temporarily stopped (S8). If the bus use priority signal level of (2) is level 4 (level 4 in S9), two parallel data buses 11 are allocated to (2) and high-speed parallel transfer is started (S10). When the data transfer of (2) is completed (S11), the data transfer of (1) is restarted (S12).
[0036]
In step S9, if the bus use priority signal level of (2) is level 3, one parallel data bus 11 is assigned to each of (1) and (2), and data transfer is performed by the parallel / serial mixed transfer method. (S13). In this case, even after the data transfer of either (1) or (2) is completed (S14), the uncompleted data transfer is performed by the mixed parallel / serial transfer using one parallel data bus 11. The process is continued according to the method (S15).
[0037]
As described above, according to the bus arbitration circuit 1 of this embodiment, data transfer can be performed by an appropriate transfer method according to the bus use priority level determined by the data transfer amount and the data transfer request speed. As a result, the bus resources can be effectively used, and data can be transferred between various devices without lowering the data transfer speed. Further, since various devices can share the bus, the area can be reduced and the power consumption can be reduced. Further, even if the number of devices to which data is transferred increases, the degree of increase in the area (chip area) of the bus arbitration circuit 1 is small, so that the manufacturing cost can be reduced.
[0038]
In addition to the parallel data bus 11, a serial data bus 12 is provided for a low-speed device such as the LCD 16-2, and the serial data bus 12 is used for data transfer to the low-speed device. As a result, wasteful use of bus resources can be prevented, and highly efficient data transfer can be performed with less bus resources.
[0039]
Further, at the time of parallel data transfer, a parallel / serial mixed transfer method is employed in which data obtained by serially converting a plurality of bits of parallel transfer data is put on each data line of the parallel data bus and transferred, thereby increasing the use efficiency of bus resources. be able to. Therefore, the total number of data lines (bus width) can be reduced, and the area of the bus arbitration circuit 1 can be reduced.
[0040]
In the above embodiment, a dual-port SRAM is illustrated as a dual-port high-speed device, but the present invention is not limited to this. In the above embodiment, a circuit configuration including two parallel data buses and one serial data bus has been described. However, a circuit configuration including three or more parallel data buses and a circuit configuration including three or more parallel data buses may be used. A circuit configuration including a serial data bus may be used.
[0041]
【The invention's effect】
As described above, according to the present invention, a bus arbitration circuit capable of effectively utilizing bus resources and reducing the area and power consumption without lowering the data transfer speed can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of an embodiment of a bus arbitration circuit of the present invention.
FIG. 2 is an explanatory diagram of an operation when high-speed data transfer is performed between a CPU and a RAM in FIG. 1;
FIG. 3 is an operation explanatory diagram in a case where low-speed data transfer is performed between a DMAC and an LCD in FIG. 1;
FIG. 4 is an operation explanatory diagram in a case where high-speed data transfer between a CPU and a RAM and low-speed data transfer between a DMAC and an LCD occur simultaneously.
FIG. 5 is an operation explanatory diagram in a case where a data transfer request by a CPU and a DMAC is simultaneously generated for a dual-port SRAM;
FIG. 6 is a block diagram used for describing a parallel / serial mixed transfer system.
FIG. 7 is an explanatory diagram of a data conversion method in a parallel / serial mixed transfer system.
FIG. 8 is a flowchart showing the operation of the bus arbitration unit when a new use request of two parallel data buses occurs during high-speed data transfer.
FIG. 9 is a configuration diagram of a conventional bus arbitration circuit.
[Explanation of symbols]
1: Bus arbitration circuit 10: Bus arbitration unit 11: Parallel data bus 12: Serial data bus 15-1: CPU (master device)
15-2: DMAC (master device)
16-1: RAM (slave device)
16-2: LCD (slave device)
21: ID signal (bus request signal)
22: Bus use permission signal

Claims (5)

A parallel data bus, a serial data bus, and a bus arbitration unit that controls use of the bus by various devices,
The bus arbitration unit,
A bus arbitration circuit for granting a right to use the parallel data bus or the serial data bus to a bus use request source device in accordance with a data transfer amount or a data transfer request speed from the bus use request source device. The parallel data bus has two systems, the serial data bus has one system,
The bus arbitration unit,
When performing data transfer to a high-speed device, the right to use the two parallel data buses is given to the bus requesting device, so that the data transfer by the high-speed parallel data transfer method using the two parallel data buses is performed. Possible,
When performing data transfer to a low-speed device, by granting the right to use the serial data bus to a bus use requesting device, it is possible to perform data transfer by the serial data transfer method using the serial data bus,
When performing data transfer to a high-speed device and performing data transfer to a low-speed device, the right to use the two parallel data buses is given to a bus use requesting device that performs data transfer to the high-speed device, and the serial data bus is used. Is given to the bus use requesting device that performs data transfer to the low-speed device, so that data transfer by the high-speed parallel data transfer method using the two parallel data buses and serial communication using the serial data bus are performed. 2. The bus arbitration circuit according to claim 1, wherein data transfer by a data transfer method is enabled at the same time. When the bus width of the parallel data bus is m bits (m is a positive number),
The bus arbitration unit,
It has a function of enabling data transfer by the parallel / serial mixed transfer method of performing n (n is a positive number) bit serial transfer using the parallel data bus and mxn bit transfer at a clock frequency of n times the normal frequency. 2. The bus arbitration circuit according to claim 1, wherein The bus arbitration unit,
4. The bus according to claim 3, further comprising a function of changing a bus width used by the bus use request source device according to a data transfer amount and a data transfer request speed from the bus use request source device. Arbitration circuit. The bus arbitration unit,
When a new bus use request of the parallel data bus is generated during data transfer by the high-speed parallel data transfer method, a function to switch to the data transfer by the parallel / serial mixed transfer method is provided as necessary. 4. The bus arbitration circuit according to claim 3, wherein

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