JP2004253631A - Deposition pattern restoration device, deposition pattern restoration method, and manufacturing method of electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely restore a defective part by preventing the sticking of dust. <P>SOLUTION: A deposition pattern restoration device is provided with a removal means 107 for irradiating the deposition pattern of a top layer among the respective deposition patterns formed in layers on a substrate 83 with ion beams and removing at least a part of the deposition pattern of the top layer. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a film forming pattern repairing apparatus and a film forming pattern repairing method suitable for repairing a pattern abnormality of a film forming pattern of an electro-optical device such as an active matrix type liquid crystal substrate, and a method of manufacturing the electro-optical device.
[0002]
[Prior art]
In general, an electro-optical device, for example, a liquid crystal device that performs a predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among them, in an electro-optical device such as a liquid crystal device of an active matrix drive system using a TFT drive, a TFD drive or the like, each intersection of a number of scanning lines (gate lines) and data lines (source lines) arranged vertically and horizontally is provided. Correspondingly, a pixel electrode and a switching element are provided on a substrate (active matrix substrate).
[0003]
A switching element such as a TFT element is turned on by an ON signal supplied to a gate line, and writes an image signal supplied via a source line to a pixel electrode (transparent electrode (ITO)). As a result, a voltage based on the image signal is applied to the liquid crystal device between the pixel electrode and the counter electrode to change the arrangement of the liquid crystal molecules. Thus, the image display is performed by changing the transmittance of the pixel and changing the light passing through the pixel electrode and the liquid crystal layer according to the image signal.
[0004]
An element substrate that constitutes such a switching element is formed by stacking a semiconductor thin film, an insulating thin film, or a conductive thin film having a predetermined pattern on a glass or quartz substrate. That is, the TFT substrate and the like are formed by repeating the film formation process of various films and the photolithography process.
[0005]
However, dust may adhere to the mask during the photolithography process. In addition, dust may be attached during an etching process in a photolithography process. Then, an abnormal pattern may be formed by these dusts. In addition, when dry etching is used in the photolithography process, an abnormal pattern due to dust is formed to a sufficient thickness due to the anisotropy.
[0006]
FIG. 15 is an explanatory diagram showing an example in which transparent electrodes of adjacent pixels formed on the uppermost layer of the TFT substrate are short-circuited due to a pattern abnormality. As shown in FIG. 15, the pixel electrode 151 and the pixel electrode 152 are short-circuited to each other by an abnormal pattern portion of the residual resist 153 caused by dust or the like.
[0007]
In a liquid crystal device, application of a DC voltage to the liquid crystal causes degradation of the liquid crystal, such as decomposition of the liquid crystal component, contamination by impurities generated in the liquid crystal cell, and burn-in of a displayed image. Therefore, in general, inversion driving is performed in which the polarity of the driving voltage of each pixel electrode is inverted at a constant period such as one frame or one field in an image signal. Further, a line inversion drive system such as a 1H inversion drive system in which the polarity of the drive voltage is inverted for each row of the pixel electrode at a constant cycle, and a 1S inversion drive system for inverting the polarity of the drive voltage for each column of the pixel electrode are also employed.
[0008]
That is, in the line inversion, for example, drive voltages of opposite polarities are applied between two vertically adjacent pixels. Therefore, when the pixel electrodes of two adjacent vertical pixels are short-circuited as described above, the potentials of the two inverted pixels are mutually affected, and the potential difference between these pixel electrodes and the opposite potential is small. Thus, these two pixels are displayed as bright spots.
[0009]
In particular, due to the miniaturization accompanying the recent increase in resolution, the interval between pixels has become narrower, and the possibility of short-circuiting between films such as pixel electrodes in the same layer has increased. ing.
[0010]
[Patent Document 1]
JP 2000-241833 A
[0011]
[Problems to be solved by the invention]
There is also a technique for repairing a pattern abnormality by irradiating such a pixel defect with a laser beam. However, when the laser beam is used, a large amount of dust is generated, and the dust affects the pixels, and the pixel defects cannot always be repaired effectively.
[0012]
In particular, when a liquid crystal device is used for a projector, since the size of the TFT substrate is extremely small, the influence of dust accompanying the irradiation of the laser beam is remarkable. For the projector application, a method of repairing pixel defects by the laser beam is adopted. It is not possible.
[0013]
Patent Document 1 also discloses a technique of forming a bypass line that bypasses a short-circuit portion. However, in this method, it is necessary to form a repair wiring, an opening, and the like, which complicates the element structure.
[0014]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and provides a film forming pattern repairing apparatus that can reliably repair pixel defects and other film forming pattern abnormalities by enabling repair using a focused ion beam. It is another object of the present invention to provide a method for restoring a film formation pattern and a method for manufacturing an electro-optical device.
[0015]
[Means for Solving the Problems]
The film formation pattern repairing apparatus according to the present invention irradiates the uppermost film formation pattern among the respective film formation patterns formed in layers on the substrate with an ion beam, and at least a part of the uppermost layer film formation pattern. A removing means for removing the
[0016]
According to such a configuration, when a defective portion such as a residual resist has occurred in the film formation pattern of the uppermost layer on the substrate, the removing unit irradiates the defective portion with an ion beam. Defects that form part of the film formation pattern are removed by the ion beam. Thereby, the film formation pattern of the uppermost layer is repaired.
[0017]
Further, the removing unit includes an ion optical system that focuses and emits the ion beam, a control unit that controls the emission of the ion beam from the ion optical system, and atoms or molecules removed from the film formation pattern. Discharging means for discharging the water.
[0018]
According to such a configuration, by converging the ion beam with the ion optical system and irradiating the film pattern with the ion beam, a sputtering phenomenon occurs in the film pattern and the atoms or molecules can be released from the film pattern. it can. The control unit controls the emission range of the film pattern by controlling the emission of the ion beam. The released atoms or molecules are discharged by the discharging means, and the removed portions do not re-attach to the film formation pattern. As a result, reliable repair can be performed without being affected by dust and the like, and for example, a short circuit of a metal pattern can be reliably repaired without affecting the element.
[0019]
Further, the control means is capable of controlling the irradiation position of the ion beam.
[0020]
According to such a configuration, a pattern portion at a desired position of the film formation pattern of the uppermost layer can be removed, and for example, a defective portion can be surely repaired.
[0021]
Further, an observation means for irradiating an electron beam to a defective portion of the uppermost film formation pattern and observing the defective portion is further provided.
[0022]
According to such a configuration, it is possible to repair the defective portion by the removing unit while observing the defective portion by the observation unit.
[0023]
Further, the observation means is constituted by a scanning electron microscope.
[0024]
According to such a configuration, it is possible to observe and repair a defective portion even with a fine pattern on the substrate.
[0025]
Further, a characteristic inspection means for detecting a characteristic of the film formation pattern of each of the uppermost layers to obtain a position of the defective portion is further provided.
[0026]
According to such a configuration, the position of the portion of the film formation pattern to be removed on the substrate can be known by the characteristic inspection means.
[0027]
Further, a characteristic inspecting means for detecting a characteristic of a film forming pattern of each of the uppermost layers to determine a position of the defective portion, and a characteristic inspecting device for detecting the position of the defective portion determined by the characteristic inspecting device, An observation unit configured to irradiate an electron beam to a defect portion of the film formation pattern so as to observe the defect portion.
[0028]
According to such a configuration, the observation unit can automatically observe the defective portion by acquiring information on the position of the defective portion of the film formation pattern to be removed on the substrate by the characteristic inspection unit. As a result, the defective portion in the fine pattern can be reliably found and observed, and the defective portion can be surely repaired by the removing means.
[0029]
Further, the substrate is a display substrate in which pixel electrodes forming pixels are formed in a matrix, and a short-circuit portion between the short-circuited pixel electrodes is removed.
[0030]
According to such a configuration, it is possible to repair the defective pixel by removing the portion of the film formation pattern that becomes a pixel defect on the display substrate by the removing unit.
[0031]
The uppermost film formation pattern is a wiring formed on the substrate.
[0032]
According to the present invention, a pattern defect of a wiring pattern can be repaired.
[0033]
Further, the removing means removes a part of a film forming pattern in which an interlayer insulating film is formed as a lower layer.
[0034]
According to such a configuration, when a part of the film formation pattern is removed by the removing unit, if the layer below the film formation pattern to be removed is an interlayer insulation film, a part of the interlayer insulation film is replaced with the uppermost film formation pattern. At the same time, even if it is removed at the same time, the effect on the element is extremely small, so that a sufficient margin can be taken as the removal range, and the entire portion of the film formation pattern to be removed can be reliably removed.
[0035]
The method for repairing a film formation pattern according to the present invention includes the steps of: removing at least a part of the film formation pattern of the uppermost layer among the film formation patterns formed in layers on the substrate; The method includes a process of irradiating a beam and a process of discharging a removed portion of the film formation pattern.
[0036]
According to such a configuration, a portion of the uppermost layer on the substrate from which the film formation pattern is to be removed is irradiated with the ion beam. The portion of the film formation pattern to be removed by the ion beam is emitted from the inside of the film formation pattern and further discharged without reattaching to the film formation pattern. As a result, a defective portion or the like of the film formation pattern of the uppermost layer is repaired.
[0037]
A process of detecting a characteristic of a film formation pattern of an uppermost layer among the film formation patterns formed in a layer on the substrate to obtain a position of a defect portion of the film formation pattern of the uppermost layer; A process of irradiating a defective portion of the film formation pattern of the uppermost layer with an electron beam based on the information on the position of the portion so that the defective portion can be observed.
[0038]
According to such a configuration, the characteristics of the film formation pattern of the uppermost layer are detected, and the position of the defective portion is obtained. Based on the obtained information on the position of the defective portion, the defective portion is irradiated with an electron beam, and the defective portion can be observed. This makes it possible to repair the defective portion while observing the defective portion.
[0039]
Further, the method of manufacturing an electro-optical device according to the present invention includes irradiating an ion beam to a film formation pattern of an uppermost layer among the film formation patterns formed in layers on a substrate, thereby forming the film formation pattern of the uppermost layer. A film forming pattern is formed by using a film forming pattern repairing apparatus provided with a removing means for partially removing the film.
[0040]
According to such a configuration, it is possible to remove a defective portion of the film-forming pattern, so that a defect-free image display or the like can be performed.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram for explaining a film formation pattern repairing apparatus according to the first embodiment of the present invention. This embodiment is an example in which the present invention is applied to an active matrix substrate of a liquid crystal device as a substrate on which a film formation pattern is to be repaired. FIG. 2 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels constituting a pixel region of a liquid crystal device manufactured by assembling a substrate to be inspected. FIG. 3 is a plan view of the TFT substrate (element substrate) constituting the liquid crystal device of FIG. 2 together with the components formed thereon as viewed from the counter substrate side. FIG. 4 shows the TFT substrate and the counter substrate bonded together. FIG. 4 is a cross-sectional view of the liquid crystal device after completion of an assembling step of sealing and enclosing the liquid crystal, taken along the line HH ′ in FIG. 3. FIG. 5 is a sectional view showing the pixel structure of the liquid crystal device in detail. FIG. 6 is an explanatory view showing the relationship between the tip of the emitted light of the FIB, the tip of the lens barrel of the SEM, and the substrate wafer. In each of the above drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.
This embodiment shows an example applied to a case where a liquid crystal device is manufactured by an array manufacturing method having excellent productivity. In the array manufacturing method, a plurality of TFT substrates (active matrix substrates) are cut out from one mother glass substrate. Each element for a plurality of active matrix substrates is formed simultaneously on the mother glass substrate by repeating the film formation and photolithography steps while keeping the size at the time of putting the mother glass substrate. Then, each active matrix substrate is obtained by dividing the mother glass substrate.
[0042]
In the manufacture of a liquid crystal device using an active matrix substrate, from the viewpoint of productivity and yield, each active matrix substrate arranged in the state of a mother glass substrate is replaced with a counter substrate divided into a single unit. A chip mount method is employed in which a single liquid crystal device is obtained by bonding each active matrix substrate after enclosing the liquid crystal and dividing the liquid crystal device into each active matrix substrate.
[0043]
In the present embodiment, an SEM (Electron Microscope) as a means for observing a pixel defect of each active matrix substrate by performing an electrical characteristic test on the active matrix substrate in a mother glass substrate state and observing a detection address. (Scanning electron microscope) to detect defects in the substrate state. Then, the found defect is repaired by using FIB (focus ion beam). Then, by confirming the restoration result by an electrical characteristic inspection, reliable restoration is enabled.
[0044]
A liquid crystal panel using an active matrix substrate to be repaired has a configuration in which an active matrix substrate and a counter substrate are attached to each other with a certain gap therebetween, and a liquid crystal, which is an electro-optical material, is sandwiched in the gap. . A transparent substrate such as a glass substrate is used as the active matrix substrate and the opposing substrate, and a peripheral driving circuit and the like are formed on the active matrix substrate together with transistors for driving pixels.
[0045]
First, a liquid crystal panel formed using a TFT substrate for which a film formation pattern is to be repaired will be described with reference to FIGS.
[0046]
As shown in FIGS. 3 and 4, the liquid crystal device is configured by sealing a liquid crystal 50 between a TFT substrate 10 and a counter substrate 20. Pixel electrodes and the like constituting pixels are arranged in a matrix on the TFT substrate 10. FIG. 2 shows an equivalent circuit of an element on the TFT substrate 10 constituting a pixel.
[0047]
As shown in FIG. 2, in the pixel area, a plurality of scanning lines 3a and a plurality of data lines 6a are wired so as to intersect with each other, and a pixel electrode is formed in an area defined by the scanning lines 3a and the data lines 6a. 9a are arranged in a matrix. Then, a TFT 30 is provided corresponding to each intersection of the scanning line 3a and the data line 6a, and the pixel electrode 9a is connected to the TFT 30.
[0048]
The TFT 30 is turned on by the ON signal of the scanning line 3a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. In addition, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 allows the voltage of the pixel electrode 9a to be held for a time that is, for example, three digits longer than the time during which the source voltage is applied. The storage capacitor 70 improves voltage holding characteristics and enables image display with a high contrast ratio.
[0049]
FIG. 5 is a schematic cross-sectional view of a liquid crystal device focusing on one pixel.
[0050]
A groove 11 is formed in a TFT substrate 10 made of glass, quartz, or the like. A TFT 30 having an LDD structure is formed on the groove 11 via a light shielding film 12, a first interlayer insulating film 13a, and a second interlayer insulating film 13b. The groove 11 flattens the boundary surface between the TFT substrate and the liquid crystal 50.
[0051]
The TFT 30 includes a semiconductor layer having a channel region 1a, a source region 1d, and a drain region 1e provided with a scanning line 3a serving as a gate electrode via lower and upper insulating films 2a and 2b. The light-shielding film 12 is formed in a region corresponding to the formation region of the TFT 30, a formation region of the data line 6a and the scanning line 3a described later, that is, a region corresponding to a non-display region of each pixel. The light shielding film 12 prevents reflected light from entering the channel region 1a, the source region 1d, and the drain region 1e of the TFT 30.
[0052]
A third interlayer insulating film 14 is laminated on the TFT 30, and an intermediate conductive layer 15 is formed on the third interlayer insulating film 14. A capacitance line 18 is disposed on the intermediate conductive layer 15 with a dielectric film 17 interposed therebetween. The capacitance line 18 is composed of a capacitance layer and a light-shielding layer, forms a storage capacitance with the intermediate conductive layer 15, and has a light-shielding function of preventing internal reflection of light. Since the intermediate conductive layer 15 is formed at a position relatively close to the semiconductor layer, diffused reflection of light can be efficiently prevented.
[0053]
A fourth interlayer insulating film 19 is disposed on the capacitance line 18, and the data lines 6 a are stacked on the fourth interlayer insulating film 19. The data line 6a is electrically connected to the source region 1d via contact holes 24a and 24b penetrating the fourth and third interlayer insulating films 19 and 14. The pixel electrode 9a is stacked on the data line 6a via the fourth interlayer insulating film 25. The pixel electrode 9a is electrically connected to the drain region 1e via the capacitance line 18 by contact holes 26a, 26b penetrating the fifth to third interlayer insulating films 25, 19, 14. An alignment film 16 made of a polyimide-based polymer resin is laminated on the pixel electrode 9a and rubbed in a predetermined direction.
[0054]
When an ON signal is supplied to the scanning line 3a (gate electrode), the channel region 1a becomes conductive, the source region 1d and the drain region 1e are connected, and the image signal supplied to the data line 6a is supplied to the pixel electrode 9a.
[0055]
On the other hand, the opposing substrate 20 is provided with a first light-shielding film 23 in a region facing the data line 6a, the scanning line 3a, and the region where the TFT 30 is formed on the TFT array substrate, that is, a non-display region of each pixel. The first light-shielding film 23 prevents incident light from the counter substrate 20 from entering the channel region 1a, the source region 1d, and the drain region 1e of the TFT 30. A counter electrode (common electrode) 21 is formed over the entire surface of the substrate 20 on the first light shielding film 23. An alignment film 22 made of a polyimide polymer resin is laminated on the counter electrode 21 and rubbed in a predetermined direction.
[0056]
Then, a liquid crystal 50 is sealed between the TFT substrate 10 and the counter substrate 20. Thus, the TFT 30 writes the image signal supplied from the data line 6a to the pixel electrode 9a at a predetermined timing. In accordance with the written potential difference between the pixel electrode 9a and the counter electrode 21, the orientation and order of the molecular assembly of the liquid crystal 50 are changed, thereby modulating light and enabling gray scale display.
[0057]
As shown in FIGS. 3 and 4, the opposing substrate 20 is provided with a light-shielding film 42 as a frame for dividing a display area. The light shielding film 42 is formed of, for example, the same or different light shielding material from the light shielding film 23.
[0058]
A sealing material 41 for enclosing liquid crystal is formed between the TFT substrate 10 and the counter substrate 20 in a region outside the light shielding film 42. The sealing material 41 is arranged so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other. The sealing material 41 is missing on a part of one side of the TFT substrate 10, and a liquid crystal injection port 78 for injecting the liquid crystal 50 is formed in a gap between the bonded TFT substrate 10 and the counter substrate 20. You. After the liquid crystal is injected from the liquid crystal injection port 78, the liquid crystal injection port 78 is sealed with a sealing material 79.
[0059]
A data line driving circuit 61 and a mounting terminal 62 are provided along a side of the TFT substrate 10 in a region outside the sealing material 41 of the TFT substrate 10, and a scanning line is formed along two sides adjacent to the one side. A drive circuit 63 is provided. On one remaining side of the TFT substrate 10, a plurality of wirings 64 for connecting the scanning line driving circuits 63 provided on both sides of the screen display area are provided. In at least one of the corners of the counter substrate 20, a conductive material 65 for electrically connecting the TFT substrate 10 and the counter substrate 20 is provided.
[0060]
When a defect due to a pattern abnormality occurs in the TFT substrate 10 configured as described above, before the assembling step of bonding the TFT substrate 10 and the opposing substrate 20, the mother substrate substrate state (wafer state) shown in FIG. Can be repaired by the film formation pattern repairing apparatus.
[0061]
In FIG. 1, a Y-axis stage 81 is guided by a guide member (not shown) and is movable in a horizontal plane in a predetermined direction (Y-axis direction). The X-axis stage 82 is guided by a guide member (not shown) on the Y-axis stage 81, and is movable in a horizontal plane in the X-axis direction orthogonal to the Y-axis. A substrate wafer 83 is mounted on the X-axis stage 82. The substrate wafer 83 on which the film formation pattern is to be repaired is, for example, a mother glass substrate on which a plurality of TFT substrates 10 shown in FIGS. 2 to 5 are formed.
[0062]
The electrical characteristic inspection device 85 can connect an unillustrated inspection pin to the mounting terminal 62 of each TFT substrate on the substrate wafer 83. The electrical characteristic inspection device 85 can inspect each pixel of each TFT substrate for a defect. For example, the electrical characteristic inspection device 85 can detect this pixel defect when adjacent pixel electrodes 9a formed of an ITO film are short-circuited. The electrical characteristic inspection device 85 inspects the electrical characteristics of each TFT substrate on the substrate wafer 83 and outputs an inspection result to the control unit 86. For example, the electrical characteristic inspection device 85 can output an address indicating the pixel position of the detected pixel defect to the control unit 86 as an inspection result.
[0063]
The control unit 86 controls the stage driving unit 87, the SEM driving unit 88, and the FIB driving unit 89. The control unit 86 gives the stage drive unit 87 the X and Y addresses of the defective pixel. The pulse conversion unit 101 of the stage driving unit 87 generates a pulse signal for driving the X-axis and the Y-axis motor 104 and the Y-axis motor 105 as a stepping motor based on the input X and Y addresses. The pulse signal from the pulse conversion unit 101 is supplied to the X-axis drive circuit 102 and the Y-axis drive circuit 103. The X- and Y-axis driving circuits 102 and 103 supply the input pulse signals to the X-axis motor 104 or the Y-axis motor 105 to drive them. Thus, the X-axis motor 104 moves the X-axis stage 82 in the X-axis direction, and the Y-axis motor 105 moves the Y-axis stage 81 in the Y-axis direction. The driving of the X-axis motor 104 and the Y-axis motor 105 is accurately controlled by a pulse signal. Moving.
[0064]
The X and Y stages 81 and 82 are driven to rotate by a drive unit (not shown) so that the surface on which the substrate wafer 83 is mounted can be inclined by a predetermined angle from a horizontal plane.
[0065]
On the other hand, the control unit 86 also gives the X and Y addresses to the SEM drive unit 88 that constitutes the SEM. The SEM includes a lens barrel (not shown) and an SEM driving unit 88. The lens barrel is configured to generate an electron beam by an electron gun, narrow down the electron beam by an electron lens (formation of an electron probe), shape the electron probe (correct astigmatism), and observe a region of the electron probe on the surface of the substrate wafer 83 by the deflection coil. And the like. In the vicinity of the substrate wafer 83 on the X-axis stage 82, a detector (not shown) for detecting a signal emitted from the substrate wafer 83 is provided. In addition, the lens barrel generally needs to be maintained at a vacuum, and a vacuum exhaust device (not shown) is provided.
[0066]
The SEM driving unit 88 controls generation of an electron beam, lens action of an electron lens, astigmatism correction, a scanning range (magnification) of an electronic probe, a scanning speed, and the like. When the SEM driving section 88 drives the lens barrel, the substrate wafer 83 is irradiated with an electron beam. Some of the electrons incident on the substrate wafer 83 collide with atoms in the substrate wafer 83 and excite electrons in the atoms. As a result, some electrons in the substrate wafer 83 are scattered in the substrate wafer 83 and jump out of the substrate wafer 83. Thus, signals such as reflected electrons, secondary electrons, Auger electrons, characteristic X-rays, and phosphorescence are emitted.
[0067]
The SEM drive unit 88 also drives a detector that detects the emitted signal. The signal detected by the detector is displayed as an image on a display (not shown) by the SEM drive unit 88.
[0068]
The control unit 86 controls the FIB driving unit 89 constituting the FIB based on a user operation. The FIB has an ion optical system (not shown). The ion optical system emits ionized gallium (ion beam) from the tip of the tungsten needle by using a liquid phase gallium as an ion source and applying a voltage of several kV to the tungsten needle via an extraction electrode. ing. This ion beam is emitted through a lens, and the irradiation position is controlled by a scanning deflector. The FIB drive section 89 is controlled by the control section 86 to emit an ion beam focused to a predetermined diameter onto the surface of the substrate wafer 83.
[0069]
Also in the FIB, the substrate wafer 83 needs to be set in an ultra-high vacuum atmosphere in order to discharge atoms released from the substrate wafer 83, and is set in such an environment by the above-described vacuum exhaust device. I have.
[0070]
FIG. 6 is an explanatory diagram showing the relationship between the lens barrel tip 106 and the emitted light tip 107 of the FIB and the substrate wafer 83 provided in the SEM. As shown in FIG. 6, the electron beam from the SEM lens barrel tip 106 and the ion beam from the FIB emission light tip 107 can be incident on the surface of the substrate wafer 83 at a predetermined angle. ing. Secondary electrons generated when the FIB ion beam is irradiated can be visualized by an SEM and observed. Further, the processing position can be confirmed by observing the vicinity of the incident position of the FIB ion beam from the front side using the SEM. Thereby, high-precision pinpoint processing is possible.
[0071]
FIG. 7 is an explanatory diagram for explaining the principle of processing the surface of the substrate wafer 83 by FIB. FIG. 7A shows a state before the ion beam irradiation, and FIG. 7B shows a state after the ion beam irradiation.
[0072]
As shown in FIG. 7A, it is assumed that the surface layer of the substrate wafer 83 is formed of SiO2. When the surface of the substrate wafer 83 is irradiated with a gallium ion (Ga +) beam, the gallium ions travel into the substrate wafer 83 and emit atoms or molecules in the substrate wafer 83 to the outside of the substrate wafer 83. That is, by irradiating the substrate wafer 83 with an ion beam, a sputtering phenomenon occurs in which atoms or molecules (Si, O) forming the substrate wafer 83 are knocked out.
[0073]
By appropriately focusing the ion beam diameter, it is possible to cut the surface of the substrate wafer 83 with an arbitrary width. By utilizing this phenomenon, in the present embodiment, for example, a defective portion due to a residual resist formed between the pixel electrodes 9a in the uppermost layer is repaired. In this case, the interlayer insulating film such as a BPSG film as a base layer of the pixel electrode 9a has a sufficiently high atomic density as compared with the resist film, and the BPSG film has a sufficiently large thickness of several hundred nm, so that gallium is used. The ions do not penetrate the BPSG film, and do not cause defects in the lower layer of the BPSG film.
[0074]
Next, a method for manufacturing a TFT substrate will be described in detail. As described above, the TFT substrate is formed in a wafer state by array manufacturing.
First, baking is performed on the TFT substrate 10. This firing is performed by N ₂ Annealing is performed in an inert gas atmosphere such as (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pre-processing is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced.
[0075]
Next, a groove 11 (see FIG. 5) is formed in the TFT substrate 10 by etching or the like. The groove 11 is formed in a region where each TFT element 30 is arranged. Next, a light-shielding film 12 is formed, and then a first interlayer insulating film 13 is formed. For example, using a TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl-borate) gas, a TMOP (tetra-methyl-oxy-foslate) gas or the like by a normal pressure or reduced pressure CVD method or the like, The first interlayer insulating film 13 is formed of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like.
[0076]
Next, a semiconductor layer is formed on the first interlayer insulating film 13. That is, in a relatively low-temperature environment of about 450 to 550 ° C., preferably about 500 ° C., low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like at a flow rate of about 400 to 600 cc / min. Then, a semiconductor layer such as an amorphous silicon film is formed.
[0077]
Next, the polysilicon film is annealed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably for 4 to 6 hours, so that the polysilicon film has a particle size of about 50 to 200 nm, preferably Is grown in a solid phase until the particle size becomes about 100 nm. As a method for solid phase growth, annealing treatment using RTA (Rapid Thermal Anneal) or laser annealing using excimer laser or the like may be used. At this time, depending on whether the pixel switching TFT 30 is of an n-channel type or a p-channel type, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.
[0078]
Next, the gate insulating film 2 is formed on the semiconductor layer. That is, first, the semiconductor layer 1a forming the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C. A gate insulating film 2 made of a silicon oxide film (HTO film) or a silicon nitride film is formed. Then, firing of the gate insulating film 2 is performed.
[0079]
Next, in order to control the threshold voltage Vth of the pixel switching TFT 30, a predetermined amount of a dopant such as boron is doped into the N-channel region or the P-channel region of the semiconductor layer 1a by ion implantation or the like. I do.
[0080]
Next, a scanning line is formed. That is, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to make the polysilicon film conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of the polysilicon film is about 100 to 500 nm, preferably about 350 nm. After the firing, the scanning lines 3a having a predetermined pattern including the gate electrode portion of the TFT 30 are formed by photolithography and etching.
[0081]
Next, for example, when the TFT 30 is an n-channel TFT having an LDD structure, the scanning line 3a (gate electrode) is formed to form a low-concentration source region and a low-concentration drain region in the semiconductor layer 1a. Is used as a mask, and a dopant of a group V element such as P is used at a low concentration (for example, P ^Thirteen / Cm ² Doping). Thus, the semiconductor layer 1a below the scanning line 3a becomes the channel region 1a '.
[0082]
Further, in order to form the high-concentration source region 1d and the high-concentration drain region 1e constituting the pixel switching TFT 30, a resist layer having a plane pattern wider than the scanning line 3a is formed on the scanning line 3a. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions ^Fifteen / Cm ² Doping).
[0083]
Thus, an element having an LDD structure having low-concentration source / drain regions and high-concentration source / drain regions is formed. Note that, for example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask. The resistance of the scanning line 3a is further reduced by the impurity doping.
[0084]
Next, a second interlayer insulating film 14 is formed. That is, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, A second interlayer insulating film 14 made of a film or the like is formed. The thickness of the second interlayer insulating film 14 is, for example, about 500 to 2000 nm.
[0085]
Next, contact holes 24a and 26a are simultaneously opened by dry etching such as reactive ion etching and reactive ion beam etching on the second interlayer insulating film 14. Next, the intermediate conductive layer 15 is formed on the TFT element 30. Note that the contact hole 26a connects between the semiconductor layer and the intermediate conductive layer 15.
[0086]
Next, a dielectric film 17 is formed, and further a capacitance line 18 having a multilayer structure is formed. This constitutes a storage capacity.
[0087]
Next, a third interlayer insulating film 19 is formed. That is, the third interlayer insulating film 19 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using, for example, a normal pressure or reduced pressure CVD method, a TEOS gas, or the like. . The thickness of the third interlayer insulating film 19 is, for example, about 500 to 1500 nm. In this case, baking is performed at a temperature of 900 ° C. or more, and annealing is performed at a low temperature.
[0088]
Next, after the hydrogenation treatment, a contact hole 24b is formed by dry etching such as reactive ion etching or reactive ion beam etching on the third interlayer insulating film 19.
[0089]
Next, a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed on the entire surface of the third interlayer insulating film 19 by sputtering or the like so as to fill the contact holes 24a and 24b. Deposit to a thickness, preferably about 300 nm. Then, a data line 6a having a predetermined pattern is formed by photolithography and etching.
[0090]
Next, a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is used to cover the data line 6a by using, for example, normal pressure or reduced pressure CVD, TEOS gas, or the like. A fourth interlayer insulating film 25 is formed. The thickness of the fourth interlayer insulating film 25 is, for example, about 500 to 1500 nm.
[0091]
Next, a contact hole 26b is formed by dry etching such as reactive ion etching or reactive ion beam etching on the fourth interlayer insulating film 25 and the third interlayer insulating film 19. Next, a transparent conductive film such as an ITO film is deposited on the inner peripheral surface of the contact hole 26b and the fourth interlayer insulating film 25 by sputtering or the like to a thickness of about 50 to 200 nm. Then, a pattern of the pixel electrode 9a is formed by photolithography and etching. The contact hole 26b connects the first intermediate conductive layer 15 and the pixel electrode 9a. Finally, low-temperature annealing is performed in step S26.
[0092]
Next, a method of repairing the TFT substrate thus formed according to the present embodiment will be described with reference to FIGS. FIG. 8 is a flowchart showing a repair method, FIG. 9 is an explanatory diagram for explaining processing conditions, FIG. 10 is a graph showing a correlation between the processing depths of the BPSG film, and FIG. FIG. 12 is a cross-sectional view of FIG. 11A, FIG. 13 is an explanatory view showing a display of a pixel defect detected by an electrical characteristic test, and FIG. 14 is a display of a pixel defect after a partial repair. FIG.
[0093]
On the X-axis stage 82, a substrate wafer 83 which is a TFT substrate formed in a state of a mother glass substrate according to the above-described manufacturing method is mounted. In step S1 of FIG. 8, the electrical characteristic inspection device 85 connects an unillustrated inspection pin to the mounting terminal 62 on the substrate wafer 83, and inspects the electrical characteristics of each pixel for each TFT substrate on the substrate wafer 83. . The inspection result by the electrical characteristic inspection device 85 is given to the control unit 86, and the control unit 86 displays a display based on the inspection result on a display screen of a display (not shown).
[0094]
Now, it is assumed that the inspection result of the electrical characteristic inspection device 85 is as shown in FIG. In the display shown in FIG. 13, a square display 112 indicating a formation region of each TFT substrate is displayed in a frame display 111 indicating the outer shape of the substrate wafer 83. The position of a defective pixel in each TFT substrate is indicated by a black square display 113. The example in FIG. 13 shows that pixel defects have occurred at nine positions shown in the display 113 on the eight TFT substrates. .
[0095]
In step S <b> 2, the control device 86 acquires the addresses of these defective pixels based on the output of the electrical characteristic inspection device 85 and outputs the addresses to the stage drive section 87. The stage driving section 87 moves the X and Y stages 81 and 82 according to the address in step S3. That is, the pulse conversion unit 101 converts the input address into a pulse signal and outputs the pulse signal to the X-axis and Y-axis drive circuits 102 and 103. The X-axis and Y-axis drive circuits 102 and 103 drive the X-axis motor 104 and the Y-axis motor 105 based on the input pulse signals. Thus, the Y-axis stage 81 and the X-axis stage 82 move in the horizontal plane, and move so that the SEM lens barrel end portion 106 is located at a position near one of the defective pixels indicated by black marks in FIG. . On the other hand, the control unit 86 outputs a control signal to the SEM driving unit 88, and the SEM emits an electron beam from the lens barrel tip 106 to obtain an observation image of the surface of the substrate wafer 83 (step S4).
[0096]
For example, assume that the predetermined defective pixel of interest in FIG. 13 is the defect shown in FIG. That is, the defective pixel to be repaired remains between the adjacent pixel electrodes 121 and 122 (corresponding to the pixel electrode 9a in FIG. 5) with the resist 123 used for pattern formation, and connects the pixel electrodes 121 and 122 to each other. It shows the state that it is. Due to the residual resist 123, the pixel electrodes 121 and 122 are short-circuited to each other, causing a pixel defect. FIG. 12 shows a cross section of the resist 123. As shown in FIG. 12, a BPSG film 124 (corresponding to the fourth interlayer insulating film 25 in FIG. 5) is formed below the pixel electrodes 121 and 122, and between the pixel electrodes 121 and 122 on the BPSG film 124. , The remaining resist 123 remains. Note that a data line 125 (corresponding to the data line 6a in FIG. 5) is formed below the BPSG film 124.
[0097]
In the present embodiment, the residual resist 123 component is removed from the front side of the substrate wafer 83 by FIB (step S5). That is, gallium ions are emitted from the emission light tip 107 of the FIB ion optical system. In this case, for example, beam irradiation is performed with a beam current of 100 PA and a processing frequency of 2000 Hz. As a result, the portion of the residual resist 123 and the vicinity thereof are removed. That is, gallium ions from the emission light tip 107 of the FIB ion optical system enter the residual resist 123 in the substrate wafer 83 and emit their atoms and molecules from the surface of the substrate wafer 83 to the outside. Further, the released atoms or molecules are discharged to the outside by an ultra-high vacuum mechanism. Thus, the remaining resist 123 is removed without the atoms or molecules removed by the FIB reattaching to the surface of the substrate wafer 83 as dust.
[0098]
When the residual resist 123 is removed by the FIB, not only the part of the pixel electrodes 121 and 122 and the residual resist 123 but also the surface portion of the BPSG film 124 thereunder are removed. 9 and 10 show the processing depth by FIB. As shown in FIG. 9, assuming that the processing area in the vertical direction extends to the lower end position of the ITO film forming the pixel electrode, and the area where the area of the BPSG film below the area is removed is the processing depth. When the FIB is driven, the relationship between the processing time and the processing depth is as shown in FIG.
As is clear from the graph of FIG. 10, the BPSG film 124, which is the base material of the pixel electrodes 121 and 122, is scraped off by about 350 to 3500 in accordance with the processing time of about 40 to 250 seconds. However, the thickness of the BPSG film is sufficiently large (approximately 800 nm in the example of FIG. 12), and the processing time can be controlled to remove only a desired film portion without substantially affecting the element.
[0099]
FIG. 11B shows a state after the residual resist 123 is removed. The FIB processing has been performed on the dashed regions in FIGS. 11A and 12, and as shown in FIG. 11B, a part of the residual register 123 and a part of the BPSG film 124 therebelow. Has been removed.
[0100]
FIG. 11 shows an example in which the processing time is set to 80 seconds with reference to the graph of FIG. In this case, the BPSG film 124 is removed by a depth of 100 nm or less. Since the process of shaving the surface portion of the BPSG film 124 is performed, the residual register 123 on the upper surface of the BPSG film 124 can be surely removed to prevent a short circuit.
[0101]
The electrical characteristics of the TFT substrate repaired by the FIB are re-examined by the electrical characteristic inspection device 85 (step S6). FIG. 14 is a display showing the inspection result in this case. As is clear from the comparison between FIG. 14 and FIG. 13, it can be seen that the FIB has repaired several defective pixels and improved the electrical characteristics.
[0102]
As described above, in the present embodiment, the pixel defect of each active matrix substrate is detected by the electrical characteristic inspection, and the defect in the substrate state can be found by the SEM based on the address of the detected defective pixel. Then, the found defect is repaired by using the FIB, and the repair result is confirmed by an electrical characteristic inspection, thereby enabling a reliable repair. Since the defective portion is scraped off using the FIB, it is possible to surely repair the defective portion while suppressing generation of dust.
[0103]
In the above embodiment, an example in which a film formed on an active matrix substrate in a state of a mother glass substrate manufactured by an array manufacturing method is repaired, but a substrate manufactured by a method other than the array manufacturing method is used. However, the present invention can also be applied to a divided active matrix substrate.
[0104]
Also, an example in which the defect of the pixel electrode in the uppermost layer of the active matrix substrate is repaired has been described. However, if repairing from the substrate surface side is possible, after the formation of each patterned layer, the film of the uppermost layer at that time is repaired. It is also possible to apply for restoration. For example, when a pattern abnormality is detected by image processing or the like in a process in the middle of the TFT substrate process by using a pattern inspection device, an SEM observation position may be specified by an address from the pattern inspection device. In particular, when an interlayer insulating film is formed below the film to be repaired, the damage to the film below the film to be repaired is relatively small. It is also effective in repairing wiring patterns and the like.
[0105]
As an example other than the repair of the pixel defect, the present invention can be applied to a wiring pattern such as one in which a scanning line and a capacitor line are formed in parallel and a short circuit between the scanning line and the capacitor line is removed.
[0106]
Further, as an example using a TFT, not only a top-gate transistor but also a bottom-gate transistor and a transistor using an amorphous or single crystal transistor in addition to a polysilicon TFT can be applied.
[0107]
Further, the present invention can be applied not only to the repair of the liquid crystal substrate but also to the repair of the film formation pattern of the semiconductor substrate. Further, the present invention can be applied to an electro-optical device such as an EL device and an electrophoretic device.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram for explaining a film formation pattern repairing apparatus according to a first embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of various elements, wiring, and the like in a plurality of pixels constituting a pixel region of a liquid crystal device manufactured by assembling a substrate to be inspected.
3 is a plan view of a TFT substrate (element substrate) constituting the liquid crystal device of FIG. 2 together with components formed thereon as viewed from a counter substrate side.
FIG. 4 is a cross-sectional view showing the liquid crystal device after the assembly step of bonding the liquid crystal by bonding the TFT substrate and the counter substrate together and cutting the liquid crystal device along the line HH ′ in FIG. 3;
FIG. 5 is a cross-sectional view illustrating a pixel structure of a liquid crystal device in detail.
FIG. 6 is an explanatory diagram showing a relationship between a front end portion of an emitted light of an FIB, a front end portion of a lens barrel of an SEM, and a substrate wafer.
FIG. 7 is an explanatory diagram for explaining the principle of processing the surface of a substrate wafer 83 by FIB.
FIG. 8 is a flowchart showing a repair method.
FIG. 9 is an explanatory diagram for explaining processing conditions.
FIG. 10 is a graph showing a correlation between processing depths of a BPSG film.
FIG. 11 is a plan view showing a state before and after repair of a pixel defect portion to be repaired.
FIG. 12 is a sectional view of FIG.
FIG. 13 is an explanatory diagram showing a display of a pixel defect detected by an electrical characteristic test.
FIG. 14 is an explanatory diagram showing a display of a pixel defect after a partial restoration.
FIG. 15 is an explanatory diagram showing a pattern abnormality of a pixel electrode.
[Explanation of symbols]
81: Y-axis stage, 82: X-axis stage, 83: substrate wafer, 85: electric property inspection device, 86: control unit, 87: stage drive unit, 88: SEM drive unit, 89: FIB drive unit.

Claims (13)

It is characterized by comprising a removing means for irradiating an ion beam to an uppermost film formation pattern among the respective film formation patterns formed in layers on the substrate to remove at least a part of the uppermost film formation pattern. Film pattern repair device. An ion optical system that focuses and emits the ion beam,
Control means for controlling the emission of the ion beam from the ion optical system,
2. The apparatus according to claim 1, further comprising a discharge unit configured to discharge atoms or molecules removed from the film pattern. The apparatus according to claim 1, wherein the control unit is capable of controlling an irradiation position of the ion beam. 2. The apparatus according to claim 1, further comprising an observation unit configured to irradiate an electron beam to a defective portion of the uppermost film forming pattern to observe the defective portion. The apparatus according to claim 4, wherein the observation unit is configured by a scanning electron microscope. 2. A film pattern repairing apparatus according to claim 1, further comprising a characteristic inspecting means for detecting a characteristic of the film pattern of each of said uppermost layers to obtain a position of said defective portion. Characteristic inspection means for detecting the characteristics of the film formation pattern of each of the uppermost layers to determine the position of the defective portion;
An observation unit configured to irradiate an electron beam to the defect portion of the film formation pattern of the uppermost layer based on the information on the position of the defect portion obtained by the characteristic inspection unit so that the defect portion can be observed. The film pattern repairing apparatus according to claim 1, wherein: 2. The apparatus according to claim 1, wherein the substrate is a display substrate on which pixel electrodes forming pixels are formed in a matrix, and removes a short-circuit portion between the short-circuited pixel electrodes. 3. . 2. The apparatus according to claim 1, wherein the uppermost film pattern is a wiring formed on the substrate. The film forming pattern repair apparatus according to claim 1, wherein the removing unit removes a part of a film forming pattern in which an interlayer insulating film is formed as a lower layer. In order to remove at least a part of the film formation pattern of the uppermost layer among the film formation patterns formed in a layer on the substrate, a process of irradiating the film formation pattern of the uppermost layer with an ion beam,
Discharging the removed portion of the film formation pattern. A process of detecting the characteristics of the uppermost layer film formation pattern among the respective film formation patterns formed in layers on the substrate to obtain the position of a defective portion of the uppermost layer film formation pattern;
Irradiating an electron beam on a defective portion of the film formation pattern of the uppermost layer based on the obtained information on the position of the defective portion to enable observation of the defective portion. A method for repairing a film formation pattern according to claim 11. A film forming pattern repairing device comprising a removing means for irradiating an ion beam to the film forming pattern of the uppermost layer among the film forming patterns formed in layers on the substrate to remove a part of the film forming pattern of the uppermost layer. A method for manufacturing an electro-optical device in which a film formation pattern is formed using the device.

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