JP2004252554A - Rounding processing device of numerical coprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rounding processing device for a numerical coprocessor capable of creating the magnitude relation between the magnitude of a rounding error and an operation result as a rounding error, further converting the rounding error to a floating point format so as to be smoothly usable for an operation to be successively performed. <P>SOLUTION: This rounding processing device for a numerical coprocessor comprises a rounding error creation part 17 for determining the difference between a mantissa b (S17) before rounding and a mantissa d after rounding (S22) in the rounding part 10 of the numerical coprocessor 3, and generating a rounding error S23 having the sign and magnitude of the rounding error; and a rounding error storage part 18 for storing the rounding error generated by the creation part 17, which is controlled by an operation part strobe bus S21 so as to enable a host processor to read the stored rounding error at an optional point of time through an internal data bus S4. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a rounding device of a numerical processor that calculates a floating point.
[0002]
[Prior art]
First, the floating point format of the IEEE754 standard will be described with reference to FIGS. FIG. 7 is a diagram showing a floating-point format, and FIG. 8 is a diagram showing guard bits.
The floating-point number N1 is obtained by encoding the sign part N2, the exponent part N3, and the mantissa part N4 as shown in FIG. For example, in the case of single precision, the floating point number is 32 bits, the sign part is 1 bit, the exponent part is 8 bits, and the mantissa part is 23 bits. The sign part is positive or negative, the exponent part is magnitude, and the mantissa part is precision. The mantissa is
1.0 ≦ mantissa <2.0
It is normalized so that Since there is always one to the left of the decimal point, assuming that this one bit is present, the mantissa part contains the decimal to the right of the decimal point. Next, the IEEE 754 standard describes that the mantissa is calculated as having an infinite precision when performing calculations at floating point. For this purpose, an arithmetic circuit is formed by adding an extra bit called a guard bit N5 to the LSB side of the mantissa as shown in FIG. 8 to satisfy the IEEE754 standard. Therefore, it is necessary to finally perform some processing on the guard bit, which is a rounding processing.
[0003]
Next, a conventional numerical processor will be described with reference to FIGS. FIG. 5 is a block diagram of a rounding device of a numerical processor showing a conventional technique, and FIG. 6 is a block diagram showing details of a calculation unit of FIG.
In FIG. 5, 1 is a microprocessor, 2 is a memory, 3 is a numerical operation processor, 4 is a control unit, 5 is a control register unit, 6 is a data register unit, 7 is an operation unit, 8 is an operation unit, and 9 is normalization. The part 10 is a rounding part. The microprocessor 1, the memory 2, and the numerical processor 3 are connected by a data bus S1, an address bus S2, and a strobe bus S3. The numerical operation processor 3 is connected to the data bus S1 by an internal data bus S4, and a control unit 4, a control register unit 5, a data register unit 6, and an operation unit 7 provided in the processor are connected by the internal data bus S4. Each is connected. The operation unit 7 receives the data of the data register unit 6 as input, executes the operation indicated by the operation code S9, and generates a code a (S12), an exponent a (S13), and a mantissa a (S14). , The sign a (S12), the exponent a (S13) and the mantissa a (S14) are input and normalization is performed to generate the sign b (S15), the exponent b (S16) and the mantissa b (S17). It comprises a unit 9 and a rounding unit 10 which receives a sign b (S15), an exponent b (S16) and a mantissa b (S17) and performs rounding in accordance with a rounding mode S10 to generate a floating-point number as an operation result.
Since there is a possibility that a denormalized number is generated in the rounding unit 10, an exponent c (S 18), a mantissa c (S 19) and a denormalized number generation signal S 20 are generated when the denormalized number is generated. Re-enter. The arithmetic unit 8, the normalizing unit 9 and the rounding unit 10 generate an exception S11 such as overflow or inaccuracy. The internal address bus S5 connected to the address bus S2 and the internal strobe bus S6 connected to the strobe bus S3 are connected to the control unit 4. Reading and writing of data to and from the control register unit 5 for setting the operation mode and the like of the arithmetic unit 7 are controlled by the control register unit strobe bus S7. Similarly, reading and writing of data from and to the data register unit 6 serving as data of the arithmetic unit 7 are controlled by the data register unit strobe bus S8. Operations such as data input / output of the arithmetic unit 7 are controlled by the arithmetic unit strobe bus S21. In the above configuration, the numerical operation processor 3 executes the operation based on the floating-point number in the operation unit 7 using the data written in the data register unit 6 as an input, and writes the result in the data register unit 6.
[0004]
Next, the rounding unit 10 will be described with reference to FIG.
In FIG. 6, 11 is a rounding calculation unit, 12 is a floating-point number generation unit, 13 is an exception generation unit, 14 is a denormalized number detection unit, 15 is an exponent generation unit, and 16 is a mantissa generation unit.
The rounding unit 10 receives the sign b (S15), the exponent b (S16), and the mantissa b (S17) generated by the normalization unit 9. The mantissa b (S17) is input to the rounding calculator 11 and is rounded according to the rounding mode S10 to generate a mantissa d (S22).
The IEEE 754 defines four rounding modes: round-to-nearest, round toward zero, round toward positive infinity, and round toward negative infinity. The sign b (S15), the exponent b (S16), and the mantissa d (S22) are input to the floating-point number generator 12 to generate a floating-point number as a calculation result. The mantissa b (S17) is input to the exception generation unit 13, which detects an inexact exception that occurs when the rounding is performed, and generates an exception S11. The mantissa d (S22) is further input to the denormalized number detection unit 14, and checks whether or not a denormalized number has occurred after rounding, and generates a denormalized number generation signal S20. The exponent generation unit 15 receives the denormalized number generation signal S20 and the exponent b (S16) as inputs, and receives the exponent c (S18). The mantissa generation unit 16 receives the denormalized number generation signal S20 and the mantissa b (S17). Are respectively generated and input to the normalization unit 9 again. As described above, normalization and rounding are time-consuming processes, and a rounding circuit of a conventional numerical processor that improves the speed of the rounding process has been proposed (for example, see Patent Document 1).
[0005]
[Patent Document 1]
JP-A-8-202531 (specification pages 7, 10, 11; FIG. 2)
[0006]
In FIG. 2 of JP-A-8-202531, a device for rounding a solution generated during execution of a certain operation by a multi-stage execution pipeline detects when the operation is repeated and an accuracy bit associated with the solution. And a first circuit for determining whether a rounding calculation is necessary. When the first circuit detects that a rounding calculation is required, it sets a solution correction factor according to the rounding mode and the detection accuracy. In the method performed by the apparatus, the rounding of the solution that occurs during the execution of the ALU operation includes, when the operation is repeated, detecting the precision bits associated with the solution to determine whether a rounding calculation is required; When computation is required, it occurs through the step of setting a solution correction factor according to the rounding mode and the detection precision bit. Thereby, the conventional rounding circuit shortens the operation time.
[0007]
[Problems to be solved by the invention]
However, the rounding circuit of the prior art aims to reduce the processing time of the rounding process, and there is no consideration for the rounding error generated at the time of rounding, and unlike the rounding of integers and fixed points, the rounding error in the arithmetic of floating point numbers is not considered. There is a problem that the decimal point position changes. Thus, the range of values that the rounding error can take is very wide, and this becomes a problem when it is necessary to manage including the rounding error, for example, in an operation of a control system.
Next, for example, by increasing the size of the guard bit as in the case of multiplication, the operation accuracy in the operation circuit can be increased, but this operation accuracy is discarded in the rounding process.
Furthermore, since the value before rounding cannot be read out by software, there is a fundamental problem that the magnitude of the rounding error cannot be known.
[0008]
The present invention has been made to solve the above-described problem. By comparing a rounding error with a calculation result without deteriorating calculation accuracy in a calculation circuit, a magnitude relationship between the magnitude of the rounding error and the calculation result is created as a rounding error. It is another object of the present invention to provide a rounding device for a numerical processor that can convert a rounding error into a floating-point format and can smoothly use the rounding error in subsequent calculations.
[0009]
[Means for Solving the Problems]
In order to solve the above problem, the invention according to the rounding device for a numerical processor according to claim 1, performs rounding on a mantissa b generated by a normalization unit according to a rounding mode to generate a mantissa d. A floating-point number creation unit that creates an operation result from a sign b, an exponent b, and a mantissa d; an exception generation unit that creates overflow and underflow exceptions from the mantissa d; A denormalized number detecting unit for checking whether or not an unnormalized number is detected by the denormalized number detecting unit, an exponent generating unit for generating an exponent c from the mantissa d, and a mantissa c from the mantissa d. In a numerical operation processor having a rounding section composed of a mantissa generating section for generating a rounding error, a difference between a mantissa b before rounding and a mantissa d after rounding is taken to generate a rounding error having a sign and a magnitude of the rounding error. And a rounding error storage unit that stores the rounding error generated by the rounding error creating unit, is controlled by the arithmetic unit strobe bus, and can read out the stored rounding error from the host processor via the internal data bus at any time. It is a thing.
[0010]
By such a means, by comparing the rounding error with the calculation result, it is possible to obtain the magnitude relation between the magnitude of the rounding error and the calculation result.
Also, the calculation accuracy of hardware that is originally discarded by rounding can be obtained as a rounding error.
[0011]
According to a second aspect of the present invention, in the rounding device for a numerical processor according to the first aspect, the rounding error creating section generates the code f from a comparison between the magnitudes of the mantissa b before rounding and the mantissa d after rounding. And a rounding error mantissa generating unit that normalizes the absolute value of the difference between the mantissa b before rounding and the mantissa d after rounding to generate a mantissa e and an exponent adjustment value for performing exponent adjustment accompanying the normalization. A rounding error exponent generating unit that generates an exponent f from the exponent b and the exponent adjustment value, and generates a mantissa adjustment value from the difference between the exponent adjustment value and the exponent b when the exponent adjustment value is greater than the exponent b; A rounding error mantissa adjustment unit that re-adjusts the mantissa e using the adjustment value to generate a mantissa f, and a round that generates a rounding error in a floating-point number format defined by the IEEE754 standard from the sign f, the exponent f, and the mantissa f. It is those with the error floating-point number generating unit.
[0012]
By generating a rounding error in the format of the IEEE 754 standard by such means, the rounding error can be uniformly managed by a floating point number.
In addition, by rounding, the calculation accuracy of hardware that is originally discarded can be obtained as a rounding error. Therefore, the calculation accuracy of the hardware can be reflected on the software.
Furthermore, since the rounding error has the same format as the floating-point number on which the operation is being performed, an extremely accurate operation can be performed by using the rounding error in the operation.
[0013]
According to a third aspect of the present invention, in the rounding device for a numerical processor according to the first or second aspect, a control register unit is used as the rounding error storage unit.
[0014]
By storing the rounding error in the control register section by such means, a circuit around storage can be simplified.
[0015]
According to a fourth aspect of the present invention, in the rounding device for a numerical processor according to the first or second aspect, the rounding error output from the floating-point number generating section and the rounding error generating section is connected to the rounding section into one data. A data register unit is used as the rounding error storage unit for storing the output of the data pack unit.
[0016]
By storing the operation result and the rounding error in a pair in the data register unit by such means, the operation result and the rounding error generated as a result of the operation can be handled in a pair, so that the operation result and the rounding error can be managed in more detail. Can be.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[First embodiment]
FIG. 1 is a block diagram of a rounding device for a numerical processor according to a first embodiment of the present invention. Note that the same components as those of the related art are denoted by the same reference numerals and the description thereof will be omitted, and only different points will be described.
In the figure, reference numeral 17 denotes a rounding error creating unit, and reference numeral 18 denotes a rounding error storage unit.
The differences between the present invention and the prior art are as follows.
That is, the rounding unit 10 calculates the difference between the mantissa b (S17) before rounding and the mantissa d (S22) after rounding, and generates a rounding error (S23) having the sign and magnitude of the rounding error (17). And the rounding error generated by the rounding error generating unit (17) is stored, and the rounding error stored by the host processor is controlled by the arithmetic unit strobe bus (S21) via the internal data bus (S4) at any time. In that a rounding error storage section (18) that can be used in the above is provided.
[0018]
Next, a rounding process using the rounding unit 10 of the numerical processor 3 will be described.
.
First, the operation by the floating-point number is the same as that of the conventional example described with reference to FIG. 6, so that the sign b (S15), the exponent b (S16) and the mantissa b (S17) generated by the normalization unit 9 are used. , Generating a rounding error and storing the rounding error will be described. Note that the nearest value rounding is performed as the rounding mode.
The rounding calculation unit 11 performs a rounding process on the mantissa b (S17) including the guard bit according to the rounding mode to generate a mantissa d (S22). The rounding error creating unit 17 creates a rounding error using the mantissa b (S17) and the mantissa d (S22) as follows. First, the mantissa b (S17) is
01000000000000000000000000000
In the case of, the lower 2 bits are guard bits and there is a decimal point between the upper 2nd bit and the 3rd bit. This is the same in the following description. At this time, since the mantissa b (S17) has a guard bit of 0, the rounding process is not performed and 000 is generated as a rounding error. The mantissa b (S17) is
000000000000000000000000000001
In the case of, the mantissa d (S22) resulting from the rounding process is
01000000000000000000000000000
And
00000000000000000000000000010001
Rounding error occurs. In the least significant 2 bits of the mantissa d (S22), since the mantissa b> mantissa d indicates negative, the most significant bit is set to 1 and 101 is generated as a rounding error. The mantissa b (S17) is
0100000000000000000000000000010
In the case of, the mantissa d (S22) resulting from the rounding process is
0100000000000000000000000000100
And
0000000000000000000000000000010
Rounding error occurs. Further, since mantissa b <mantissa d, the sign is set to 0 and 010 is generated as a rounding error. The mantissa b (S17) is
000000000000000000000000000011
In the case of, the mantissa d (S22) resulting from the rounding process is
0100000000000000000000000000100
And
00000000000000000000000000010001
Rounding error occurs. Further, since the mantissa b <the mantissa d, the sign is set to 0 and 001 is generated as a rounding error. In this example, the guard bit is described as two bits. However, if the number of guard bits is increased, the accuracy of the rounding error is improved. For example, consider the square of a single-precision floating-point number that is 3f800001 in hexadecimal with guard bits being 23 bits. The mantissa is
0100000000000000000000000001
And the result of the multiplication is
01000000000000000000000000000000000000000000000000001
It becomes. Regarding the mantissa after rounding, regardless of the number of guard bits,
0100000000000000000000000001
It becomes. Without considering the sign, if the guard bit is 2 bits, the rounding error is
00
, But in the case of 23 bits,
0000000000000000000000000001
It becomes.
[0019]
The rounding error thus obtained is stored in the rounding error storage unit 18. When there is access from the microprocessor, the control unit generates the arithmetic unit strobe bus S21, and the value of the rounding error storage unit 18 is read. By using the read-out rounding error and the exponent part of the operation result, software can also convert the data into a floating-point number in the IEEE754 standard format.
[0020]
[Second embodiment]
FIG. 2 is a block diagram of a rounding device of a numerical processor according to a second embodiment of the present invention.
In the figure, 19 is a rounding error code generator, 20 is a rounding error mantissa generating unit, 21 is a rounding error exponent generating unit, 22 is a rounding error mantissa adjusting unit, and 23 is a rounding error floating point number generating unit.
The differences between the second embodiment and the first embodiment are as follows.
That is, the rounding error generator 17 is composed of a rounding error code generator 19, a rounding error mantissa generating unit 20, a rounding error exponent generating unit 21, a rounding error mantissa adjusting unit 22, and a rounding error floating point number generating unit 23.
Here, the rounding error code generation unit 19 generates a code f (S27) by comparing the magnitudes of the mantissa b (S17) before rounding and the mantissa d (S22) after rounding. In addition, the rounding error mantissa generating unit 20 normalizes the absolute value of the difference between the mantissa b (S17) before rounding and the mantissa d (S22) after rounding to adjust the mantissa e (S25) and the exponent accompanying the normalization. And an index adjustment value (S24). Further, the rounding error index generation unit 21 generates an index f (S28) from the index b (S16) and the index adjustment value (S24), and adjusts the index when the index adjustment value (S24) is larger than the index b (S16). A mantissa adjustment value (S26) is generated from the difference between the value (S24) and the index b (S16).
Then, the rounding error mantissa adjusting unit (22) re-adjusts the mantissa e (S25) using the mantissa adjustment value (S26) to generate a mantissa f (S29). The rounding error floating point generator (23) generates a rounding error (S23) in a floating point format defined by the IEEE754 standard from the sign f (S27), the exponent f (S28) and the mantissa f (S29). . The operation using the same floating-point number in the second embodiment is the same as that in the conventional example described with reference to FIG. 6, as in the first embodiment.
[0021]
Next, how the rounding error is generated using the code b (S15), exponent b (S16), and mantissa b (S17) generated by the normalizing unit 9 and how the rounding error is stored will be described. The rounding mode is the nearest round.
The rounding error code generation unit compares the mantissa b (S17) before the rounding with the mantissa d (S22) after the rounding, and when the mantissa b (S17) ≦ the mantissa d (S22), 0 indicating a positive value is added to the mantissa b ( If S17)> mantissa d (S22), sign f (S27) is generated with 1 indicating a negative value as a value. The rounding error mantissa generating unit obtains the absolute value of the difference between the mantissa b (S17) before rounding and the mantissa d (S22) after rounding to obtain a temporary rounding error. The obtained provisional rounding error is normalized to generate a mantissa e (S25). Since the mantissa e (S25) is normalized by multiplying by 2 to the power of n, this n is set as an exponent adjustment value S24. For example, the mantissa b (S17) is
000000000000000000000000000011
The mantissa d (S22)
0100000000000000000000000000100
Then the rounding error is
00000000000000000000000000010001
This is multiplied by 2 to the power of 25 to obtain a normalized mantissa e (S25).
01000000000000000000000000000
Can be obtained. At this time, the index adjustment value is 25. The rounding error finger generation unit calculates the difference between the index adjustment values from the index b (S16) and generates an index f (S28). If the index b <the index adjustment value, the index f (S28) is set to 0, and the difference of the index b (S16) from the index adjustment value is generated as the mantissa adjustment value S26. For example, when the index adjustment value is 25 when the index b (S16) is 127, the index f (S28) is 102. When the index b (S16) is 20 and the index adjustment value is 25, since the index b <the index adjustment value, the index f (S28) is set to 0 and the mantissa adjustment value is set to 5. The rounding error mantissa adjusting unit shifts the mantissa f (S29) to the left by the mantissa adjustment value to generate the mantissa f (S29) because the mantissa needs to be adjusted when the exponent b <the exponent adjustment value. When exponent b ≧ exponential adjustment value, it is not necessary to adjust the mantissa, so mantissa f (S29) becomes mantissa e (S25). The rounding error floating point number creation unit encodes the sign f (S27), the exponent f (S28), and the mantissa f (S29) into the format of the IEEE754 standard, and creates a rounding error S22 of the floating point number. For example, the mantissa b (S17) is
000000000000000000000000000011
The mantissa d (S22)
0100000000000000000000000000100
Then, when the exponent b (S16) is 127, the sign f (S27) becomes 0 because the mantissa b <mantissa. The mantissa e (S25) is
01000000000000000000000000000
Since the index adjustment value is 25, the index f (S28) is 102. At this time, since the mantissa adjustment value is 0, the mantissa f (S29) is
01000000000000000000000000000
It becomes. When encoding to IEEE 754 format
001100111000000000000000000000000000
That is, 33300000 in hexadecimal is obtained as a rounding error. For reference, the calculation result is assuming that the code b (S15) is 0.
0011111110000000000000000000000001,
That is, it becomes 3f800001 in hexadecimal. In this example, the guard bits are two bits. However, as in the first embodiment, the precision of the rounding error can be increased by increasing the number of guard bits.
[0022]
[Third embodiment]
FIG. 3 is a block diagram of a rounding device for a numerical processor according to a third embodiment of the present invention.
In the figure, reference numeral 24 denotes a data pack unit.
The third embodiment is the same as the first and second embodiments in that a rounding error creating unit 17 is provided, but differs in that a control register unit 5 is used as a rounding error storage unit 18.
In such a configuration, the rounding error S23 created by the rounding error creating unit 17 is sent to the control register unit 5, and the rounding error is stored in the control register unit. The host processor can obtain a rounding error by reading the corresponding portion of the control register section.
[0023]
[Fourth embodiment]
FIG. 4 is a block diagram of a rounding device for a numerical processor according to a fourth embodiment of the present invention.
The fourth embodiment is the same as the first and second embodiments in that a rounding error generator 17 is provided. However, as a rounding error storage unit 18, the output of the floating point number generator 12 and the output of the rounding error generator 17 are provided to the rounding unit 10. This is different from the first embodiment in that the data register unit 6 is used as a rounding error storage unit 18 that stores the output of the data packing unit 24, and a data pack unit 24 that connects the rounding error S23 to one data.
In such a configuration, the rounding error S23 created by the rounding error creating unit 17 is combined with the floating-point number creating unit 12 by the data pack unit, transferred to the data register unit 6 via the internal data bus S4, and the calculation result and the rounding error Are paired and stored in the data register section. The host processor can obtain only the operation result, only the rounding error, and the operation result and the rounding error by reading the corresponding portion of the data register section.
[0024]
【The invention's effect】
As described above, according to the rounding device of the numerical processor according to the first aspect, by comparing the rounding error with the calculation result, it is possible to obtain the magnitude relationship between the magnitude of the rounding error and the calculation result. Also, the calculation accuracy of hardware that is originally discarded by rounding can be obtained as a rounding error.
[0025]
According to the rounding device of the numerical processor according to the second aspect, by generating the rounding error in the format of the IEEE754 standard, the rounding error can be uniformly managed by the floating point number. In addition, by rounding, the calculation accuracy of hardware that is originally discarded can be obtained as a rounding error. Therefore, the calculation accuracy of the hardware can be reflected on the software. Furthermore, since the rounding error has the same format as the floating-point number on which the operation is being performed, an extremely accurate operation can be performed by using the rounding error in the operation.
[0026]
According to the rounding device of the numerical processor according to the third aspect, by storing the rounding error in the control register section, the circuit around the storage can be simplified.
[0027]
According to the rounding device of the numerical processor according to the fourth aspect, the arithmetic result and the rounding error generated as a result of the arithmetic can be handled as a pair by storing the arithmetic result and the rounding error in a pair in the data register section. Results and rounding errors can be managed in more detail.
[Brief description of the drawings]
FIG. 1 is a block diagram of a rounding device of a numerical processor showing a first embodiment of the present invention;
FIG. 2 is a block diagram of a rounding device of a numerical processor showing a second embodiment of the present invention;
FIG. 3 is a block diagram of a rounding device of a numerical processor showing a third embodiment of the present invention;
FIG. 4 is a block diagram of a rounding device of a numerical processor according to a fourth embodiment of the present invention;
FIG. 5 is a block diagram of a rounding device of a numerical processor showing a conventional technique.
FIG. 6 is a block diagram showing details of a calculation unit in FIG. 5;
FIG. 7 is a diagram showing a floating-point format.
FIG. 8 is a diagram showing guard bits.
[Explanation of symbols]
1 Microprocessor
2 memory
3 Numerical processor
4 control unit
5 Control register section
6 Data register section
7 Operation part
8 arithmetic unit
9 Normalization part
10 Rounding part
11 Rounding calculation unit
12 Floating point generator
13 Exception generator
14 Denormalized number detector
15 exponent generator
16 Mantissa generator
17 Rounding error generator
18 Rounding error storage unit
19 Rounding error code generator
20 Rounding error mantissa generator
21 Rounding error exponent generator
22 Rounding error mantissa adjustment unit
23 Rounding error floating point generator
24 Data pack section
S1 data bus
S2 address bus
S3 strobe bath
S4 Internal data bus
S5 Internal address bus
S6 Internal strobe bus
S7 Control register section strobe bus
S8 Data register section strobe bus
S9 operation code
S10 Rounding mode
S11 exception
S12 code a
S13 index a
S14 Mantissa a
S15 code b
S16 index b
S17 Mantissa b
S18 index c
S19 Mantissa c
S20 Denormalized number generation signal
S21 Operation unit strobe bus
S22 Mantissa d
S23 Rounding error
S24 Index adjustment value
S25 Mantissa e
S26 Mantissa adjustment value
S27 code f
S28 index f
S29 Mantissa f
N1 floating point number
N2 code part
N3 index part
N4 mantissa
N5 guard bit

Claims (4)

A rounding calculation unit (11) that rounds the mantissa b (S17) generated by the normalization unit (9) according to the rounding mode and generates a mantissa d (S22);
A floating-point number creation unit (12) for creating an operation result from the sign b (S15), the exponent b (S16), and the mantissa d (S22);
An exception generation unit (13) for generating overflow and underflow exceptions from the mantissa d (S22);
A denormalized number detector (14) for checking whether the mantissa d (S22) is a denormalized number,
An exponent generation unit (15) that generates an exponent c (S18) from the mantissa d (S22) when the denormalized number detection unit (14) detects a denormalized number;
In a numerical processor (3) including a rounding section (10) including a mantissa generating section (16) for generating a mantissa c (S19) from the mantissa d (S22),
A rounding error creating unit (17) that calculates a difference between the mantissa b (S17) before rounding and the mantissa d (S22) after rounding and generates a rounding error (S23) having the sign and magnitude of the rounding error;
The rounding error generated by the rounding error creating unit (17) is stored, controlled by the arithmetic unit strobe bus (S21), and the stored rounding error is read from the host processor via the internal data bus (S4) at any time. A rounding processor for a numerical processor, comprising a rounding error storage unit (18) capable of performing the rounding. A rounding error code generation unit (19) configured to generate a code f (S27) from a comparison between the magnitude of the mantissa b (S17) before rounding and the size of the mantissa d (S22) after rounding;
The absolute value of the difference between the mantissa b (S17) before rounding and the mantissa d (S22) after rounding is normalized to obtain a mantissa e (S25) and an exponent adjustment value (S24) for performing exponent adjustment accompanying normalization. A rounding error mantissa generating unit (20) to be generated;
An index f (S28) is generated from the index b (S16) and the index adjustment value (S24). If the index adjustment value (S24) is larger than the index b (S16), the index adjustment value (S24) and the index b (S16) are generated. ), A rounding error exponent generator (21) that generates a mantissa adjustment value (S26) from the difference
A rounding error mantissa adjusting unit (22) for re-adjusting the mantissa e (S25) using the mantissa adjustment value (S26) and generating a mantissa f (S29);
A rounding error floating point number generating unit (23) for generating a rounding error (S23) in a floating point number format defined by the IEEE 754 standard from the sign f (S27), the exponent f (S28) and the mantissa f (S29). 2. The rounding device for a numerical processor according to claim 1, wherein 3. A rounding device for a numerical processor according to claim 1, wherein a control register unit (5) is used as said rounding error storage unit (18). The rounding section (10) includes a data pack section (24) for linking the rounding error (S23) output from the floating point number generating section (12) and the rounding error generating section (17) into one data. 3. The rounding processing device for a numerical processor according to claim 1, wherein a data register section (6) is used as the rounding error storage section (18) for storing the output of (24).

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