JP2004247608A - Solid-state image sensor, method of manufacturing the same and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image sensor that can discharge unnecessary electric charges generated in the deep portion of a substrate. <P>SOLUTION: The solid-state image sensor has n-type channel regions 50 formed in the surface of a p-type semiconductor substrate 66, p-type isolating regions 52 formed in the surface of the substrate 66 in a state where the regions 52 are extended in parallel with each other and divide the channel regions 50, and n-type drain regions 54 formed in a state where the regions 54 are extended in parallel with the isolating regions 52. The drain regions 54 are formed deeper than the channel regions 50 in the depthwise direction of the semiconductor substrate 66. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frame transfer type solid-state imaging device, a method of manufacturing the solid-state imaging device, and a method of driving the solid-state imaging device.
[0002]
[Prior art]
In a CCD solid-state image pickup device having a semiconductor photoelectric conversion element, when information charge is excessively generated in an image pickup section due to excessive exposure or the like, a blooming phenomenon in which the information charge overflows to other peripheral pixels occurs. In order to suppress the blooming phenomenon, an overflow drain structure for discharging excessively generated information charges is employed.
[0003]
As the overflow drain structure, a vertical overflow drain structure that discharges excess information charges deep into the semiconductor substrate and a horizontal overflow drain structure that discharges excess information charges to a drain region provided in the surface region of the semiconductor substrate are used. Has been.
[0004]
The horizontal overflow drain structure is mainly used for a frame transfer type CCD solid-state imaging device. FIG. 8 is a schematic configuration diagram of a frame transfer type CCD solid-state imaging device. The frame transfer type CCD solid-state imaging device includes an imaging unit 10i, a storage unit 10s, a horizontal transfer unit 10h, and an output unit 10d. The two-dimensional array of information charges generated by the imaging unit 10i is transferred to the storage unit 10s at high speed. The information charges are held in the storage unit 10s, transferred to the horizontal transfer unit 10h one row at a time, and further transferred from the horizontal transfer unit 10h to the output unit 10d in pixel units. The output unit 10d converts the charge amount for each pixel into a voltage value, and the change in the voltage value is output as a CCD output.
[0005]
A plurality of vertical shift registers are arranged in the imaging unit 10i and the storage unit 10s so as to extend in a direction toward the horizontal transfer unit 10h. The vertical shift register is configured to include a plurality of channel regions arranged parallel to each other toward the horizontal transfer unit 10h, and a plurality of transfer electrodes extending orthogonal to the channel region and arranged parallel to each other. . In the horizontal overflow drain structure, an isolation region and a drain region are formed between adjacent channel regions.
[0006]
FIG. 9 is a schematic plan view showing a part of an imaging unit 10i or a storage unit 10s of a frame transfer type CCD solid-state imaging device employing a conventional horizontal overflow drain structure. The channel region 20 of the vertical shift register is defined by an isolation region 22, and a drain region 24 is provided at a substantially central position of the isolation region 22.
[0007]
The channel region 20 is formed by an N well in which an N type impurity is added to a surface region of a P type semiconductor substrate. The isolation region 22 is formed by implanting a P-type impurity into the semiconductor substrate. The drain region 24 is formed by implanting a high-concentration N-type impurity from the surface of the isolation region 22 in parallel with the direction in which the channel region 20 extends.
[0008]
The transfer electrode 26 is formed on the semiconductor substrate via an insulating film, and is arranged to extend in a direction crossing the channel region 20. These transfer electrodes 26 are insulated from each other and arranged in parallel with each other. A vertical transfer clock is applied to each of the transfer electrodes 26, the state of the potential well formed in the surface region of the channel region 20 is controlled, and the stored information charges are sequentially transferred.
[0009]
For example, in the case of three-phase driving, one pixel is assigned to every three adjacent transfer electrodes 26, and transfer clocks φ1, φ2, and φ3 are applied to the transfer electrodes 26-1, 26-2, and 26-3, respectively. .
[0010]
FIG. 10 is a schematic sectional view of the XX section shown in FIG. 9 and a diagram showing a potential profile corresponding to the section. As shown in FIG. 10A, the channel region 20, the isolation region 22, and the drain region 24 are respectively formed with N wells (NW) 30 and P formed on the surface of a P-type semiconductor substrate 36. ⁺ Diffusion layer 32, N ⁺ It is composed of a diffusion layer 34. On the surface of the substrate, a conductive film 40 as the transfer electrode 26 is disposed via an insulating film 38. The state of the potential across the channel region 20, the isolation region 22, and the drain region 24 indicates a profile having a potential well 42 separated by a potential barrier 48 in the isolation region 22, as shown in FIG. Information charges 44 can be stored in the potential well 42.
[0011]
FIG. 11 shows a potential state in the vertical shift register included in the imaging unit 10i at times t1 to t4 when the CCD solid-state imaging device is driven.
[0012]
FIG. 11A shows the potential of the vertical shift register along the transfer direction at each time. FIG. 11B shows the potential at a position crossing the channel region 20 below the transfer electrode 26-2. FIG. 11C shows a potential at a position crossing a deeper portion of the substrate than the channel region 20 below the transfer electrode 26-2.
[0013]
At time t1, the transfer clock φ2 is raised to H level (for example, 5V), and the transfer clocks φ1 and φ3 are lowered to L level (for example, 0V) which is a lower potential than the transfer clock φ2. As a result, as shown in FIG. 11A, a potential well 100 is formed below the transfer electrode 26-2 and deeper than under the other transfer electrodes 26-1 and 26-3. In the region of the channel region 20, as shown in FIG. 11B, the isolation region 22 adjacent to the channel region 20 forms a potential barrier 102 between itself and the drain region 24. Incidentally, under the transfer electrodes 26-1 and 26-3, a potential barrier 104 indicated by a broken line is formed.
[0014]
The information charges generated below the transfer electrodes 26-1 to 26-3 by the light incident on the semiconductor substrate 36 are restricted from moving to the drain region 24 by the potential barriers 102 and 104, and have the lowest potential in the peripheral region. It moves to the potential well 100 of the transfer electrode 26-2 and is accumulated.
[0015]
At time t2, an H level (for example, 5 V) discharge clock φb is applied to a drain electrode (not shown) provided in the drain region 24. When the discharge clock φb rises, the potential barrier formed by the isolation region 22 is modulated, and the potential barrier between the channel region 20 and the drain region 24 is reduced. That is, as shown in FIG. 11B, a potential barrier 108 is formed below the transfer electrode 26-2. Since the potential barrier 108 is lower than the barrier potential 110 along the channel region 20, of the information charges 112 stored in the potential well 100, charges having an energy level exceeding the potential barrier 108 are discharged to the drain region 24. You.
[0016]
For example, when excessive light is applied to the CCD solid-state imaging device and excessive information charges are generated in the channel region 20, charges exceeding the allowable storage amount of the potential well 100 in the channel region 20 are discharged to the drain region 24. Such an operation suppresses a blooming phenomenon in which an excessive information charge leaks to peripheral pixels and disturbs an image.
[0017]
At time t3, the voltage applied to the drain region 24 falls to L level (for example, 0 V) again, and transfer clocks φ1 to φ3 having different phases from each other are applied to the transfer electrodes 26-1 to 26-3. Thus, the potential well formed below the transfer electrode 26 can be moved in the direction in which the channel region 20 extends, and the information charges 112 can be transferred using the channel region 20 as a transfer path (for example, downward in FIG. 9). By limiting the amount of information charge 112 stored in potential well 100 at time t2, it is possible to prevent information charge 112 from leaking to drain region 24 during transfer.
[0018]
Further, an electronic shutter operation can be performed. At time t4, the discharge clock φb applied to the drain region 24 rises to H level (for example, 5 V), and the vertical transfer clocks applied to all the transfer electrodes 26 rise to L level (for example, 0 V). Can be lowered. As a result, the potential in the channel region 20 is raised, the potential well 100 disappears, and the potential barriers 102 and 104 between the channel region 20 and the drain region 24 are lowered. The information charge 112 accumulated in the channel region 20 moves along the potential gradient and is discharged to the drain region 24 via the separation region 22. With this operation, the information charges 112 stored in the imaging unit 10i and the storage unit 10s can be discharged, and an electronic shutter operation can be performed.
[0019]
[Patent Document 1]
Japanese Patent No. 32762086
[0020]
[Problems to be solved by the invention]
In the solid-state imaging device having the above-described configuration, charges generated in a deep portion of the semiconductor substrate are accumulated in the potential well 100 of the channel region 20. That is, in the depth direction of the semiconductor substrate, there is formed a potential gradient that is minimized in the channel region 20 and rises toward the depth of the substrate. Therefore, the charges generated in the deep part of the substrate flow into the potential well in the channel region 20 along the potential gradient.
[0021]
FIG. 12 shows the wavelength dependence of the light penetration depth in a CCD solid-state imaging device using a single crystal silicon substrate as a semiconductor substrate. As the wavelength increases, the light absorption coefficient decreases and the penetration depth increases. Therefore, when light is incident from the surface side where the channel region is formed, light in a long wavelength region such as infrared light reaches a deep portion of the semiconductor substrate 36 and generates electric charges there. As a result, when a CCD solid-state imaging device is used for a camera that performs imaging in the visible light region, charges generated in a deep portion of the substrate due to incidence of infrared light are not discharged to the drain region but are accumulated in the potential well of the channel region. It will be. For this reason, it is easy to be affected by an infrared region unrelated to imaging.
[0022]
When the camera does not have a mechanical shutter, the imaging unit 10i is exposed to light and continues to generate charges even when information charges are transferred. For example, in the case where light is incident from the back surface side of a semiconductor substrate in which a channel region is not formed, when imaging a material having extremely high luminance in a visible light region, a deep portion of the semiconductor substrate (a channel region Charge is generated on the back side (where no is formed) and continues to be accumulated in the potential well. As a result, the influence of light incident upon transfer cannot be ignored, and problems such as occurrence of smear in a captured image occur.
[0023]
SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device having a horizontal overflow drain structure, a method of manufacturing the solid-state imaging device, and a method of driving the solid-state imaging device, which can solve at least one of the problems of the related art.
[0024]
[Means for Solving the Problems]
The present invention, which can solve the above problems, has a first semiconductor region of one conductivity type formed on a surface of a semiconductor substrate and a first semiconductor region formed to extend substantially parallel to the surface of the semiconductor substrate. A plurality of isolation regions of opposite conductivity type that divide the region, a plurality of drain regions of one conductivity type formed extending in the isolation region, and intersecting the isolation region and the drain region on the semiconductor substrate A solid-state imaging device comprising: a transfer electrode disposed in the solid-state imaging device, wherein the drain region is formed deeper in the depth direction of the semiconductor substrate than the first semiconductor region. An image sensor.
[0025]
Another embodiment of the present invention that can solve the above-described problem is a first step of forming a first semiconductor region by implanting one conductivity type impurity into a surface of a semiconductor substrate; A second step of injecting impurities of the opposite conductivity type substantially in parallel at predetermined intervals to form a plurality of isolation regions for partitioning the first semiconductor region; A third step of implanting impurities deeper in the depth direction of the semiconductor substrate than the first semiconductor region to form a plurality of drain regions; and intersecting the isolation region and the drain region on the semiconductor substrate. And a fourth step of forming a plurality of transfer electrodes by using the method.
[0026]
Another embodiment of the present invention which can solve the above-described problem is a first semiconductor region of one conductivity type formed on a surface of a semiconductor substrate, and a first semiconductor region formed so as to extend substantially parallel to the surface of the semiconductor substrate. A plurality of isolation regions of opposite conductivity type for partitioning the first semiconductor region, a plurality of drain regions of one conductivity type formed to extend in the isolation region, and the isolation region on the semiconductor substrate. And a transfer electrode disposed to intersect with the drain region, wherein the potential is applied to the drain region and the semiconductor substrate, and is generated in a deep portion of the semiconductor substrate. A method for driving a solid-state imaging device, comprising discharging charges to the drain region.
[0027]
Here, a potential for forming a potential well in the first semiconductor region is applied to the transfer electrode, and a potential applied to the drain region and the semiconductor substrate is changed to change the potential of the potential well with respect to incident light having a long wavelength. It is preferred to limit the storage sensitivity.
[0028]
In addition, a potential for extinguishing a potential well in the first semiconductor region is applied to the transfer electrode, and a potential applied to the drain region and the semiconductor substrate is changed to change the electric charge accumulated in the potential well and the semiconductor. It is preferable that charges generated in a deep part of the substrate are discharged to the drain region.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
<Structure of solid-state imaging device>
A CCD solid-state imaging device according to an embodiment of the present invention will be described in detail with reference to the drawings. The overall configuration of the CCD solid-state imaging device according to the present embodiment basically includes an imaging unit 10i, a storage unit 10s, a horizontal transfer unit 10h, and an output unit 10d, as in FIG.
[0030]
FIG. 1 is a schematic plan view showing a part of the imaging unit 10i or the storage unit 10s of the CCD solid-state imaging device according to the present embodiment. The imaging unit 10i and the storage unit 10s include a plurality of vertical shift registers arranged in parallel with each other, similarly to a conventional CCD solid-state imaging device.
[0031]
The channel region 50 of the vertical shift register is defined by an isolation region 52, and a drain region 54 is provided at a substantially central position of the isolation region 52. This forms a horizontal overflow drain structure.
[0032]
The transfer electrode 56 is formed on the surface of the semiconductor substrate on which the channel region 50 is provided via an insulating film. A plurality of transfer electrodes 56 are arranged so as to extend in a direction substantially orthogonal to the channel region 50. These transfer electrodes 56 are arranged in parallel with a predetermined interval from each other.
[0033]
At the time of imaging and transfer of information charges, a predetermined potential is applied to each of the transfer electrodes 56, the state of a potential well formed in the surface region of the channel region 50 is controlled, and accumulation and transfer of information charges are performed. You.
[0034]
For example, in the case of three-phase driving, one pixel is assigned to each set of three adjacent transfer electrodes 56-1, 56-2, and 56-3, and transfer clocks φ1, φ2, and φ3 are respectively set to transfer electrodes 56-1. , 56-2, 56-3.
[0035]
FIG. 2A is a schematic cross-sectional view of the imaging unit 10i and the storage unit 10s having the planar structure illustrated in FIG. The channel region 50, the isolation region 52, and the drain region 54 are respectively formed by N wells 60, P formed on the surface of the P-type semiconductor substrate 66. ⁺ Diffusion layer 62, N ⁺ It is composed of a diffusion layer 64. On the surface of the substrate, a conductive film 70 serving as the transfer electrode 56 is disposed via an insulating film 68.
[0036]
When a single crystal silicon substrate is used as the P-type semiconductor substrate 66, the P-type impurity concentration contained in the semiconductor substrate 66 is 10%. ¹⁴ / Cm ³ More than 10 ¹⁶ / Cm ³ The following is preferable. As the N-type impurity added to the N well 60, arsenic (As), phosphorus (P), antimony (Sb) or the like can be used, and the effective impurity concentration in the N well 60 is 10%. ¹⁶ / Cm ³ More than 10 ¹⁸ / Cm ³ The following is preferable, and 10 ¹⁶ / Cm ³ More than 10 ¹⁷ / Cm ³ The following is more preferable.
[0037]
P ⁺ As the P-type impurity added to the diffusion layer 62, boron (B), aluminum (Al), gallium (Ga), indium (In), or the like can be used. ⁻ The effective impurity concentration in the diffusion layer 62 is 10 ¹⁶ / Cm ³ More than 10 ¹⁸ / Cm ³ The following is preferable, and 10 ¹⁶ / Cm ³ More than 10 ¹⁷ / Cm ³ The following is more preferable.
[0038]
Furthermore, N ⁺ As the N-type impurity added to the diffusion layer 64, arsenic (As), phosphorus (P), antimony (Sb), or the like can be used. ⁺ The effective impurity concentration in the diffusion layer 64 is 10 ¹⁸ / Cm ³ More than 10 ²⁰ / Cm ³ The following is preferable, and 10 ¹⁸ / Cm ³ More than 10 ¹⁹ / Cm ³ The following is more preferable.
[0039]
As the insulating film 68, a silicon-based material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a high dielectric material such as a titanium oxide-based material can be used. For the transfer electrode 56, a conductive material such as metal or polycrystalline silicon can be used.
[0040]
Here, N which becomes the drain region 54 of the horizontal overflow drain structure is used. ⁺ The diffusion layer 64 is formed deeper than the N well 60 which is the channel region 50 adjacent to the deep portion of the semiconductor substrate 66.
[0041]
N which is the drain region 54 ⁺ The lower limit of the depth of the diffusion layer 64 is determined based on the penetration depth of incident light in the wavelength region that generates unnecessary charges, the diffusion length of charges in the semiconductor substrate 66, the drive voltage that can be applied to each electrode, and the like. . On the other hand, N ⁺ The upper limit of the depth of the diffusion layer 64 is N ⁺ It is limited based on the difficulty of the impurity implantation step in forming the diffusion layer 64 and the like.
[0042]
Specifically, when a single crystal silicon substrate is used as the semiconductor substrate 66, the channel region 50 has a width of 1 μm to 10 μm and a depth of 0.5 μm to 1.5 μm, and the width of the isolation region 52 is 0.1 μm. When the width of the drain region 54 is 0.1 μm or more and 1 μm or less, the lower limit of the depth of the drain region 54 is preferably 0.5 μm or more and 10 μm or less. However, the depth of the drain region 54 is deeper than the depth of the channel region 50.
[0043]
For example, as shown in FIG. 12, since the penetration depth L at which infrared light having a wavelength of 800 nm decreases to 1 / e of the incident intensity is about 1 μm, light from the surface of the semiconductor substrate 66 where the channel region 50 is formed is emitted. In order to discharge unnecessary charges generated in the deep part of the semiconductor substrate 66 by the incident light having a wavelength of 800 nm when ⁺ It is preferable that the diffusion layer 64 is formed to a depth of about 1 μm.
[0044]
When a negative voltage is applied to the conductive film 70 serving as the transfer electrode 56, the potential state along the line A in FIG. 2A has a potential well 72 in the channel region 50 as shown in FIG. Indicates a profile. A potential barrier 78 is formed in the isolation region 52 between the channel region 50 and the drain region 54, and serves as a barrier separating the potential well 72 of the channel region 50 and the drain 76 of the drain region 54. In this potential well 72, information charges 74 generated by photoelectric conversion can be stored.
[0045]
Further, by raising the discharge clock φb applied to the drain region 54 to the H level (for example, 5 V), the potential barrier 78 in the isolation region 52 is lowered (78 ′ in the figure). When the imaging unit 10i is excessively exposed at the time of imaging and an excessive information charge exceeding the allowable charge storage capacity of the potential well 72 is generated, the excess charge flows into the drain region 54 over the potential barrier 78 in the isolation region 52. . With such a horizontal overflow drain structure, excess charges are discharged to the drain region 54, and the blooming phenomenon can be suppressed.
[0046]
Further, the discharge clock φb applied to the drain region 54 is raised to H level (for example, 5 V), and the transfer clocks φ1 to φ3 applied to all the transfer electrodes 56 are lowered to L level (for example, 0 V). Thus, an electronic shutter operation can be performed. At this time, the potential barrier 78 in the isolation region 52 is lowered, and the potential well 72 in the channel region 50 disappears. The information charges 74 stored in the potential well 72 move according to the potential gradient and are discharged to the drain region 54. With this electronic shutter operation, the information charges 74 accumulated in the potential well 72 of the channel region 50 of the imaging unit 10i and the accumulation unit 10s can be reset, and preparation for imaging and transfer of a new image can be performed. .
[0047]
Further, when the discharge clock φb is applied so that the potential of the drain region 54 becomes higher than the potential of the semiconductor substrate 66, the state of the potential along the line B in FIG. 2A becomes as shown in FIG. 5 shows a profile having a gentle potential gradient 80 from the deep portion of the semiconductor substrate 66 toward the drain region 54. As a result, charges generated in the deep portion of the semiconductor substrate 66 can be drawn into the drain region 54 and discharged.
[0048]
<Driving method of solid-state imaging device>
Next, a method of driving the CCD solid-state imaging device according to the present embodiment will be described in detail. FIG. 3 is a diagram illustrating a potential state in the vertical shift register included in the imaging unit 10i at times t1 to t4.
[0049]
FIG. 3A shows a change in potential along the channel at each time. FIG. 3B shows a change in potential across the depth of the channel region 50 below the transfer electrode 56-2 (line A in FIG. 2A). FIG. 3C shows a change in potential across the substrate deeper than the channel region 50 below the transfer electrode 56-2 (line B in FIG. 2A). 4 shows transfer clocks φ1 to φ3 respectively applied to the transfer electrodes 56-1 to 56-3 corresponding to the operation of FIG. 3, a discharge clock φb applied to the drain region 54, and a substrate potential Vsub applied to the semiconductor substrate 66. It is a timing diagram.
[0050]
At time t1, as shown in FIG. 4, the transfer clocks φ1 and φ3 fall to L level (for example, 0V), and the transfer clock φ2 rises to H level (for example, 5V). As a result, an empty potential well 150 is formed in the channel region 50 below the transfer electrode 56-2. Along the channel direction, as shown in FIG. 3A, a shallow potential formed in the channel region 50 below the transfer electrodes 56-1 and 56-3 serves as a barrier, and the adjacent potential well 150 is separated. Can be In the channel region along the line A, a potential barrier 152 is formed in the separation region 52 separating the channel region 50 and the drain region 54, as shown in FIG. Incidentally, the potential barrier 154 formed below the transfer electrodes 56-1 and 56-3 is also indicated by a broken line.
[0051]
The imaging unit 10i is exposed to light from the imaging target, and generates charges by photoelectric conversion under the transfer electrodes 56-1, 56-2, and 56-3. The charge generated in the channel region 50 is restricted from moving to the drain region 54 by the potential barriers 152 and 154 formed in the isolation region 52, and the information charge is transferred to the potential well 150 formed in the transfer electrode 56-2. Is accumulated as As the information charges are accumulated, the potential of the potential well 150 gradually becomes shallower.
[0052]
At time t2, as shown in FIG. 4, the transfer clocks φ1 and φ3 are held at L level, the transfer clock φ2 is held at H level, and the discharge clock φb applied to the drain region 54 is at H level (for example, 5 V). And the substrate potential Vsub applied to the semiconductor substrate 66 falls to the L level (for example, −2 V).
[0053]
When the discharge clock φb rises, the potential barrier in the isolation region 52 is lowered as shown in FIG. FIG. 3B shows a potential barrier 158 formed in the isolation region 52. Among the information charges 162 stored in the potential well 150, those existing at a high energy level exceeding the potential barrier 158 are discharged to the drain region 54 over the potential barrier 158. By having such a horizontal overflow drain structure, a blooming phenomenon that disturbs an image due to excessive information charges leaking to peripheral pixels is suppressed.
[0054]
On the other hand, in a deep portion of the semiconductor substrate 66, a potential gradient 164 that gradually decreases toward the drain region 54 is formed as shown in FIG. Electric charges (electrons) generated in a deep portion of the semiconductor substrate 66 by light irradiation are drawn into the drain region 54 along a potential gradient 164 toward the drain region 54.
[0055]
When light enters from the surface side where the channel region 50 is formed, light in the visible light region is almost absorbed in the channel region 50, and light in the remaining infrared light region reaches the deep portion of the semiconductor substrate 66 and is absorbed. Is done. Unnecessary charges generated in a deep portion of the semiconductor substrate 66 due to absorption of light in the infrared light region are discharged to the drain region 54. That is, by adopting the structure of the CCD solid-state imaging device in the present embodiment, the sensitivity in the infrared region at the time of imaging can be relatively reduced as shown by the line C in FIG.
[0056]
Conversely, when light enters from the back surface side of the semiconductor substrate 66 where the channel region 50 is not formed, light in the visible light region is absorbed on the back surface side of the semiconductor substrate 66 (deep portion of the semiconductor substrate 66). In this case, as shown by the line D in FIG. 6, the relative sensitivity of the visible light region at the time of imaging can be adjusted.
[0057]
The relative sensitivity can be adjusted by the substantial impurity concentration of the semiconductor substrate 66, the channel region 50, and the drain region 54, and the voltages applied to the transfer clocks φ1 to φ3, the discharge clock φb, and the substrate potential Vsub.
[0058]
At time t3, as shown in FIG. 4, the voltage applied to the drain region 54 falls to L level (for example, 0 V) again, and the transfer clocks having different phases from each other are applied to the transfer electrodes 56-1 to 56-3. φ1 to φ3 are applied. As a result, the information charges 162 accumulated in the potential well 150 are transferred along the channel region 50 (for example, downward in FIG. 1). By having the horizontal overflow drain structure as in this embodiment, the amount of information charges 162 accumulated in the potential well 150 is limited, so that the information charges 162 leak to the drain region 54 during transfer. Can be prevented.
[0059]
Further, by maintaining the substrate potential Vsub applied to the semiconductor substrate 66 at the L level (for example, -2 V), the potential gradient 164 from the deep portion of the semiconductor substrate 66 toward the drain region 54 as shown in FIG. Is maintained. Therefore, electrons generated in the deep portion of the semiconductor substrate 66 during the transfer of the information charge are discharged to the drain region 54.
[0060]
For example, when light having a very high luminance is incident from the back surface side of the semiconductor substrate 66 and unnecessary light is generated by the light being absorbed in a deep part of the semiconductor substrate 66, the unnecessary charge is transferred to the drain region 54. Can be discharged. Therefore, smear generated during the transfer of the information charges can be suppressed.
[0061]
At time t4, the discharge clock φb applied to the drain region 54 is raised to H level (for example, 5 V), and the vertical transfer clock applied to the transfer electrode 56 is lowered to L level (for example, 0 V). . At the same time, the substrate potential Vsub rises to the H level, whereby the information charges 162 accumulated in the potential well 150 in the channel region 50 are discharged to the drain region 54, and the electronic shutter operation can be performed.
[0062]
<Method of manufacturing solid-state imaging device>
Next, a method for manufacturing the CCD solid-state imaging device according to the present embodiment will be described in detail with reference to FIG. In the following description, a case where a P-type silicon substrate is used as the semiconductor substrate 66 will be described.
[0063]
After forming a silicon oxide film as the insulating film 68 on the semiconductor substrate 66, a polysilicon film 200 and a silicon nitride film 202 are further laminated. Thereafter, the polysilicon film 200 and the silicon nitride film 202 are patterned so as to have a predetermined opening, thereby forming a mask 204 on which the polysilicon film 200 and the silicon nitride film 202 are laminated (FIG. 7A). . The mask 204 is used in a later-described impurity ion implantation step. One side wall 206 of mask 204 defines a region for ion implantation of an N-type impurity forming channel region 50, and the other side wall 208 defines a region for ion implantation of a P-type impurity forming isolation region 52.
[0064]
A resist is applied on the semiconductor substrate 66 on which the mask 204 is formed, and is exposed through a predetermined mask to form a resist pattern 210. The resist pattern 210 is formed so as to cover a region where the separation region 52 is formed. Using the mask 204 and the resist pattern 210 as a mask, N-type impurities are ion-implanted to form an N-type impurity region 212 (FIG. 7B).
[0065]
The boundary between the N-type impurity region 212 and the P-type semiconductor substrate 66 coincides with the position of the side wall 206 of the mask 204. When a silicon substrate is used, arsenic (As), phosphorus (P), antimony (Sb), or the like can be used as the N-type impurity. The effective impurity concentration in the N-type impurity region 212 is 10 ¹⁶ / Cm ³ More than 10 ¹⁸ / Cm ³ The following is preferable, and 10 ¹⁶ / Cm ³ More than 10 ¹⁷ / Cm ³ The following is more preferable.
[0066]
After removing the resist pattern 210, the N-type impurity implanted into the N-type impurity region 212 is diffused by performing a heat treatment to form the N-well 60 as the channel region 50 (FIG. 7C). Due to the diffusion, the N-type impurity region 212 expands in the depth direction and the horizontal direction, and the N well 60 is formed such that the boundary is located below the side wall 208 of the mask 204.
[0067]
Next, a resist is applied on the semiconductor substrate 66 on which the N well 60 is formed, and is exposed through a predetermined mask pattern to form a resist pattern 214. The resist pattern 214 covers a region where the N well 60 is formed. Using the resist pattern 214 and the mask 204 as a mask, P-type impurity ions are implanted, and the P ⁺ The diffusion layer 62 is formed (FIG. 7D).
[0068]
P ⁺ The boundary between the diffusion layer 62 and the N well 60 coincides with the position of the side wall 208 of the mask 204. When a silicon substrate is used, boron (B), aluminum (Al), gallium (Ga), indium (In), or the like can be used as a P-type impurity. ⁺ The effective impurity concentration in the diffusion layer 62 is 10 ¹⁶ / Cm ³ More than 10 ¹⁸ / Cm ³ The following is preferable, and 10 ¹⁶ / Cm ³ More than 10 ¹⁷ / Cm ³ The following is more preferable.
[0069]
After removing the resist pattern 214, an oxide film is laminated on the semiconductor substrate 66, and the oxide film is subjected to isotropic etching to form sidewalls 216 on both sides of the mask 204 (FIG. 7 ( e)). This sidewall 216 is used as a mask for defining the boundary between the isolation region 52 and the drain region 54.
[0070]
After the sidewalls 216 are formed, a resist is applied on the semiconductor substrate 66 and exposed through a predetermined mask pattern to form a resist pattern 218. The resist pattern 218 covers a region where the N well 60 is formed. N-type impurities are ion-implanted by using the resist pattern 218, the mask 204, and the sidewalls 216 as a mask, and the N ⁺ The diffusion layer 64 is formed (FIG. 7F).
[0071]
When a silicon substrate is used, arsenic (As), phosphorus (P), antimony (Sb), or the like can be used as the N-type impurity. ⁺ The effective impurity concentration in the diffusion layer 64 is 10 ¹⁸ / Cm ³ More than 10 ²⁰ / Cm ³ The following is preferable, and 10 ¹⁸ / Cm ³ More than 10 ¹⁹ / Cm ³ The following is more preferable.
[0072]
Further, by adjusting the ion energy at the time of implanting the N-type impurity, N is deeper toward the deeper portion of the semiconductor substrate 66 than the N well 60 serving as the channel region 50. ⁺ A diffusion layer 64 is formed.
[0073]
Finally, after removing the resist pattern 218, the polysilicon film 200 and the silicon nitride film 202 constituting the mask 204 (FIG. 7G), a transfer electrode and a protection film are formed.
[0074]
【The invention's effect】
According to the present invention, it is possible to provide a solid-state imaging device having a horizontal overflow drain structure capable of discharging unnecessary charges generated in a deep portion of a substrate, a method of manufacturing the solid-state imaging device, and a method of driving the solid-state imaging device.
[Brief description of the drawings]
FIG. 1 is a plan view of a vertical shift register of an imaging unit or a storage unit of a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a cross-sectional view and a potential profile of a vertical shift register of an imaging unit or a storage unit of the solid-state imaging device according to the embodiment of the present invention.
FIG. 3 is a potential distribution diagram during operation of the vertical shift register according to the embodiment of the present invention.
FIG. 4 is a timing chart at the time of operation of the vertical shift register according to the embodiment of the present invention.
FIG. 5 is a diagram illustrating spectral sensitivity of the solid-state imaging device according to the embodiment of the present invention.
FIG. 6 is a diagram illustrating the spectral sensitivity of the solid-state imaging device according to the embodiment of the present invention.
FIG. 7 is a diagram showing a manufacturing process chart of the vertical shift register of the solid-state imaging device according to the embodiment of the present invention.
FIG. 8 is a schematic diagram illustrating a configuration of a CCD solid-state imaging device.
FIG. 9 is a plan view of a vertical shift register of an imaging unit or a storage unit of a conventional solid-state imaging device.
FIG. 10 is a diagram illustrating a cross-sectional view and a potential profile of a vertical shift register of an imaging unit or a storage unit of a conventional solid-state imaging device.
FIG. 11 is a potential distribution diagram during operation of a conventional vertical shift register.
FIG. 12 is a diagram showing the wavelength dependence of the penetration depth of light into single crystal silicon.
[Explanation of symbols]
10d output unit, 10i imaging unit, 10h horizontal transfer unit, 10s storage unit, 20 channel region, 22 separation region, 24 drain region, 26 transfer electrode, 30 N well, 32P ⁺ Diffusion layer, 34 N ⁺ Diffusion layer, 36 semiconductor substrate, 38 insulating film, 40 conductive film, 42 potential well, 44 information charge, 48 potential barrier, 50 channel region, 52 isolation region, 54 drain region, 56 transfer electrode, 60 N well, 62 P ⁺ Diffusion layer, 64 N ⁺ Diffusion layer, 66 semiconductor substrate, 68 insulating film, 70 conductive film, 72 potential well, 74 information charge, 76 drain, 78 potential barrier, 80 potential gradient, 100 potential well, 102, 104, 106, 108 potential barrier, 110 barrier Potential, 112 information charge, 150 potential well, 152, 154, 158 potential barrier, 162 information charge, 164 potential gradient, 200 polysilicon film, 202 silicon nitride film, 204 mask, 206, 208 sidewall, 210, 214, 218 resist Pattern, 212 N-type impurity region, 216 sidewall.

Claims (5)

A first conductivity type first semiconductor region formed on the surface of the semiconductor substrate; and a plurality of opposite conductivity type formed on the surface of the semiconductor substrate so as to extend substantially parallel to each other and partition the first semiconductor region. An isolation region, a plurality of drain regions of one conductivity type formed extending in the isolation region, and a transfer electrode disposed on the semiconductor substrate to intersect with the isolation region and the drain region, A solid-state imaging device comprising:
The solid-state imaging device according to claim 1, wherein the drain region is formed deeper in a depth direction of the semiconductor substrate than the first semiconductor region. A first step of forming a first semiconductor region by injecting one conductivity type impurity into the surface of the semiconductor substrate;
A second step of injecting impurities of the opposite conductivity type into the first semiconductor region in a substantially parallel manner at a predetermined interval to form a plurality of isolation regions partitioning the first semiconductor region;
A third step of implanting an impurity of one conductivity type deeper into the isolation region in a depth direction of the semiconductor substrate than the first semiconductor region to form a plurality of drain regions;
A fourth step of forming a plurality of transfer electrodes on the semiconductor substrate so as to intersect with the isolation region and the drain region. A first conductivity type first semiconductor region formed on the surface of the semiconductor substrate; and a plurality of opposite conductivity type formed on the surface of the semiconductor substrate so as to extend substantially parallel to each other and partition the first semiconductor region. An isolation region, a plurality of drain regions of one conductivity type formed extending in the isolation region, and a transfer electrode disposed on the semiconductor substrate to intersect with the isolation region and the drain region, A method for driving a solid-state imaging device including:
A method for driving a solid-state imaging device, comprising: changing a potential applied to the drain region and the semiconductor substrate to discharge charges generated in a deep portion of the semiconductor substrate to the drain region. The method for driving a solid-state imaging device according to claim 3,
The potential for forming a potential well in the first semiconductor region is applied to the transfer electrode, and the potential applied to the drain region and the semiconductor substrate is changed to reduce the accumulation sensitivity of the potential well to long-wavelength incident light. A driving method for a solid-state imaging device, wherein the driving method is limited. The method for driving a solid-state imaging device according to claim 3,
A potential for extinguishing a potential well in the first semiconductor region is applied to the transfer electrode, and a potential applied to the drain region and the semiconductor substrate is changed so that the electric charge accumulated in the potential well and the potential of the semiconductor substrate A method for manufacturing a solid-state imaging device, comprising discharging a charge generated in a deep portion to the drain region.

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