JP2004247039A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing the sub-threshold current during a standby cycle and the active DC current during an active cycle. <P>SOLUTION: A variable impedance power source line 770 and a variable impedance ground line 772 are put into a low-impedance state during the standby cycle and a high-impedance state during the active cycle by MOS transistors Q60a and Q60b. The threshold voltage is regulated by regulating their MOS transistor back gate biases according to operation modes. The semiconductor device which operates at a high speed and less consumes current is thus provided by using the MOS transistors of the low threshold voltage. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a configuration for reducing current consumption of a semiconductor device including a logic gate formed of a CMOS transistor (complementary insulated gate type field effect transistor) without adversely affecting operation characteristics. More specifically, the present invention relates to a configuration for reducing a subthreshold current of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).

  As a semiconductor circuit with extremely low power consumption, a CMOS circuit is well known.

  FIG. 60 shows a configuration of the CMOS inverter. 60, a CMOS inverter is provided between power supply node 1900 receiving one operating power supply voltage Vcc and output node 1901, and has a gate receiving p-channel MOS transistor (input gate field effect transistor) receiving input signal IN. PT includes an n-channel MOS transistor NT provided between PT and another power supply node 1902 receiving the other operating power supply voltage Vss (normally, ground potential) and output node 1901 and having its gate receiving input signal IN. The output node 1901 has a load capacitance C. When the input signal IN is at a low level, the p-channel MOS transistor PT is turned on, the n-channel MOS transistor NT is turned off, the load capacitance C is charged via the p-channel MOS transistor PT, and the output signal OUT is changed to the power supply voltage Vcc. Level. When the charging of the load capacitance C is completed, the p-channel MOS transistor PT has the same source and drain potential, and is turned off. Therefore, at this time, no current flows and power consumption can be ignored.

  When input signal IN is at a high level, p-channel MOS transistor PT is turned off, n-channel MOS transistor NT is turned on, and load capacitance C is discharged to the other power supply potential Vss level via n-channel MOS transistor NT. . When this discharge is completed, the n-channel MOS transistor NT has the same source and drain potential, and is turned off. Therefore, even in this state, the power consumption can be ignored.

  The drain current IL flowing through the MOS transistor is represented by a function of the gate-source voltage of the MOS transistor. When the absolute value of the gate-source voltage becomes larger than the absolute value of the threshold voltage of the MOS transistor, a large drain current flows. Even if the absolute value of the gate-source voltage becomes equal to or less than the absolute value of the threshold voltage, the drain current does not become completely zero. The drain current flowing at this voltage is called a subthreshold current, and is exponentially proportional to the gate-source voltage.

  FIG. 61 shows the sub-threshold current characteristics of the n-channel MOS transistor. In FIG. 61, the horizontal axis shows the gate-source voltage VGS, and the vertical axis shows the logarithmic value of the drain current IL. In FIG. 61, the straight line regions of the straight lines I and II are the subthreshold currents. The threshold voltage is defined as a gate-source voltage that gives a predetermined current in this sub-threshold current region. For example, in a MOS transistor having a gate width (channel width) of 10 μm, a gate-source voltage when a drain current of 10 mA flows is defined as a threshold voltage. FIG. 61 shows the predetermined current I0 and the corresponding threshold voltages VT0 and VT1.

  As the MOS transistor becomes finer, the power supply voltage Vcc is also reduced in accordance with the scaling rule. Therefore, the performance cannot be improved unless the absolute value Vth of the threshold voltage of the MOS transistor is similarly reduced in accordance with the scaling rule. For example, in the CMOS inverter shown in FIG. 60, when power supply voltage Vcc is 5 V and threshold voltage Vth of n-channel MOS transistor NT is 1 V, when input signal IN changes from 0 V to 1 V or more, a large drain current Occurs, and the discharge of the load capacitance C starts. At this time, even when power supply voltage Vcc is reduced to, for example, 3 V while threshold voltage Vth is kept at the same value, n-channel MOS transistor NT is turned on unless input signal IN becomes 1 V or more. The load capacity C cannot be discharged with a large current as a state. That is, when the power supply voltage Vcc is 5 V, the discharge of the capacitive load occurs at the time of 1/5 of the amplitude of the input signal IN. , The discharge of the capacitive load C starts. Therefore, input / output response characteristics deteriorate, and high-speed operation cannot be guaranteed. Therefore, the absolute value Vth of the threshold voltage needs to be scaled similarly to the power supply voltage. However, as shown in FIG. 61, when threshold voltage VT1 is reduced to threshold voltage VT0, the sub-threshold current characteristic shifts from straight line I to straight line II. Therefore, when the gate voltage becomes 0 V (Vss level), the subthreshold current increases from IL1 to IL0, and the current consumption increases. Therefore, the absolute value Vth of the threshold voltage is scaled down in the same manner as the power supply voltage. Therefore, it is expected that operating characteristics, particularly high-speed operating characteristics, will be difficult to realize.

  Therefore, a configuration for suppressing the subthreshold current without impairing the high-speed operation characteristics is described in 1993 Symposium on VLSI Circuit, Digest of Technical Papers, pp. 47-48 and pp. 83-83. Each of the 84 pages is disclosed by Horiuchi et al. And Takashima et al.

  FIG. 62 is a diagram showing a configuration of a power supply line indicated by Horiuchi and the like in the above-mentioned document. FIG. 62 shows an example of n cascaded CMOS inverters f1 to fn as a CMOS circuit. Each of inverters f1 to f4 has the same configuration as the configuration shown in FIG.

  In a path for supplying one operation power supply voltage, first power supply line 1911 is connected to first power supply node 1910 receiving power supply voltage Vcc, and second power supply line 1912 is connected in parallel to first power supply line 1911. Is arranged. The first power supply line 1911 and the second power supply line 1912 are connected by a high resistance Ra. In parallel with the resistor Ra, there is provided a p-channel MOS transistor Q1 for selectively connecting the first power supply line 1911 and the second power supply line 1912 in response to the control signal φc. A capacitor Ca having a relatively large capacitance for stabilizing the potential of second power supply line 1912 is provided between first power supply line 1911 and second power supply line 1912.

  In the transmission path of the other power supply voltage Vss (ground potential: 0 V), a third power supply line 1921 connected to a second power supply node 1920 receiving the other power supply voltage (hereinafter simply referred to as ground voltage) Vss And a fourth power supply line 1922 arranged in parallel with the third power supply line 1921. A high resistance Rb is provided between the third power supply line 1921 and the fourth power supply line 1922, and is selectively connected to the third power supply line 1921 in parallel with the resistance Rb in response to the control signal φs. An n-channel MOS transistor Q2 connecting the four power supply lines 1922 is provided. Further, a capacitor Cb having a large capacitance for stabilizing the potential of the fourth power supply line 1922 is provided between the third power supply line 1921 and the fourth power supply line 1922.

  One of the odd-numbered inverters f1, f3,... Has one operation power supply node (a power supply node receiving a high potential) connected to the first power supply line 1911 and the other power supply node (a power supply node receiving a low potential) has a fourth power supply node. Connected to power line 1922. One of the even-numbered inverters f2,... Has one operation power supply node connected to the second power supply line 1912 and the other power supply node connected to the third power supply line 1921. Next, the operation will be described.

In a DRAM, the state of its signal can be predicted in advance during standby. Also, the state of the output signal can be similarly predicted. In the configuration shown in FIG. 62, input signal IN goes low during standby and goes high during an active cycle. In the standby cycle, control signal φc is at a high level, control signal φs is at a low level, and MOS transistors Q1 and Q2 are both turned off. In this state, power supply lines 1911 and 1912 are connected via high resistance Ra, and power supply lines 1921 and 1922 are also connected via high resistance Rb. The potential VCL of the power supply line 1912 is
VCL = Vcc-Ia · Ra
And the voltage VSL of the power supply line 1922 is
VSL = Vss + Ib.Rb
It becomes. Here, Ia and Ib indicate currents flowing through the resistors Ra and Rb, respectively. Input signal IN is now at the level of ground potential Vss. In inverter f1, p-channel MOS transistor PT is on, and the output node is charged to power supply potential Vcc level on power supply line 1911. On the other hand, n channel MOS transistor NT has its source potential (potential of power supply node 1902) at intermediate potential VSL, and is set to a potential level higher than ground potential Vss. Therefore, in the n-channel MOS transistor NT, the gate-source voltage becomes a negative voltage, and as shown in FIG. 61, the sub-threshold current becomes the sub-threshold current IL2 when the gate-source voltage is -VSL. Sub-threshold current IL1 flowing when the potential of node 1902 is at ground potential Vss is made smaller. Here, the operation characteristics of the MOS transistor will be described with reference to a straight line I shown in FIG. The ON / OFF state of the n-channel MOS transistor indicates an ON state when its gate-source voltage becomes higher than the threshold voltage, and the gate-source voltage becomes lower than the threshold voltage. Is shown as off. The opposite is true for P-channel MOS transistors.

  In inverter f2, the input signal / IN (output signal of inverter f1) is at the high level of power supply potential Vcc. Therefore, in inverter f2, the p-channel MOS transistor is off and the n-channel MOS transistor is on. The p-channel MOS transistor has its source connected to power supply line 1912 and receives voltage VCL. Therefore, in inverter f2, the gate potential of the p-channel MOS transistor is higher than its source potential, and the subthreshold current is suppressed as in the case of the n-channel MOS transistor. The same applies to the subsequent inverters f3 to fn. Therefore, at the time of standby, the subthreshold current in inverters f1 to fn is suppressed, and the standby current is reduced.

When an active cycle starts, control signal φc is at a low level, control signal φs is at a high level, and MOS transistors Q1 and Q2 are both turned on. MOS transistors Q1 and Q2 have a large channel width W, and can supply a sufficient charge / discharge current to inverters f1 to fn. In this state, the potentials of power supply lines 1912 and 1922 attain the levels of power supply potential Vcc and ground potential Vss, respectively. Thus, in the active cycle, the output signal OUT is also determined according to the input signal IN.
1993 Symposium On VLSSI Circuits, Digest of Technical Papers, pp. 47-48, 83-84.

  FIG. 63 shows an operation waveform of the circuit shown in FIG. 62 and a current flowing through the power supply line. As shown in FIG. 63, in the standby cycle, both MOS transistors Q1 and Q2 are off in response to signals φs and φc, and voltage VCL on power supply line 1912 and voltage VSL on power supply line 1922 are It is an intermediate potential between the voltage Vcc and the ground potential Vss (0 V). In this state, in the inverters f1 to f4, the MOS transistors in the sub-threshold region (MOS transistors in the off state) are turned off more strongly, and the sub-threshold current is reduced.

  However, in the active cycle, control signals φs and φc are set to high level and low level, respectively, MOS transistors Q1 and Q2 are turned on, voltage VCL on power supply line 1912 is equal to power supply potential Vcc, and power supply line The voltage VSL on 1922 becomes equal to the ground potential Vss. At the start of the active cycle, power supply current Icc flows to charge power supply line 1912 (VCL charging current). Then, when input signal IN changes, inverters f1 to fn operate in response to change the signal level. , A charging / discharging current is generated and a relatively large operating current is generated.

  In the active cycle, voltage VCL is set equal to power supply potential Vcc, and on the other hand, equal to ground potential Vss of power supply voltage VSL. Therefore, in the inverters f1 to f4, the gate potential and the source potential of the off-state transistors are equal, and a large subthreshold current flows when a MOS transistor having a small absolute value Vth of the threshold voltage is used. That is, in the active cycle, before the change of the input signal IN and after the change is completed, a large subthreshold current (active DC current) flows, which causes a problem that current consumption in the active cycle increases. In particular, in a semiconductor memory device having a large storage capacity such as a 1 gigabit DRAM, when the number of MOS transistors as constituent elements increases, the sum of such active DC currents increases and becomes a value that cannot be ignored.

  Further, a sub-threshold current flows in transistors Q1 and Q2 (see FIG. 62) which are turned off in the standby cycle. When the absolute value of the threshold voltage of transistors Q1 and Q2 is increased in order to reduce the subthreshold current flowing during the standby cycle of transistors Q1 and Q2 as much as possible, the power supply line is shifted to the active cycle for the following reason. It takes a long time to recover the potentials of 1912 and 1922, and accordingly, in the case of a semiconductor memory device, there is a problem that the access time becomes long.

  That is, since the absolute values of the threshold voltages of transistors Q1 and Q2 are high at the time of transition from the standby cycle to the active cycle, the transistors Q1 and Q2 have a long time to operate in the saturation region and a long time to operate in the unsaturated region. . Therefore, as compared with the case where the absolute value of the threshold voltage is small, the current driving capability of transistors Q1 and Q2 at the time of transition from the standby cycle to the active cycle is reduced, and the potential recovery of power supply lines 1921 and 1922 is delayed. The internal circuit needs to be activated when the potentials of the power supply lines 1921 and 1922 are stabilized, so that the operation start time of the internal circuit is delayed, and in the case of a semiconductor memory device, the access time is prolonged.

  Therefore, an object of the present invention is to provide a semiconductor device that operates at high speed with low current consumption.

  Another object of the present invention is to provide a semiconductor device capable of reducing current consumption during an active cycle.

  Still another object of the present invention is to provide a semiconductor memory device that operates at high speed with low current consumption.

  A semiconductor device according to the present invention has a hierarchical power supply structure having a main power supply line and a sub power supply line, and has a standby cycle and an active cycle as operation cycles, and defines a standby cycle and an active cycle. A switching insulated gate field effect transistor that electrically connects the main power supply line and the sub power supply line, and operates in response to the operation cycle specifying signal; There is provided a threshold changing means for making the absolute value of the threshold voltage of the insulated gate field effect transistor requiring switching greater than that in a standby cycle.

  In the semiconductor device according to the present invention, the absolute value of the threshold voltage of the switching insulated gate field effect transistor that electrically connects the main power supply line and the sub power supply line during the standby cycle is increased during the standby cycle. In addition, a leakage current between the main power supply line and the sub power supply line during the standby cycle can be suppressed. In addition, during the active cycle, the absolute value of the threshold voltage of the switching insulated gate field effect transistor is reduced, so that the switching insulated gate field effect transistor has a large current driving force at the transition to the active cycle. In operation, the voltage on the sub power supply line returns to the voltage level on the main power supply line at high speed.

[Example 1]
FIG. 1 is a diagram schematically showing an overall configuration of a semiconductor memory device (DRAM) according to one embodiment of the present invention. In FIG. 1, the DRAM decodes a memory cell array 100 in which memory cells MC are arranged in a matrix of rows and columns, and an internal row address signal (X address) RA from address buffer 102, and A row selection circuit 104 for selecting a row (word line) and a column selection for decoding an internal column address signal (Y address) CA from the address buffer 102 and selecting a column (bit lines BL and / BL) in the memory cell array 100 Circuit 106 and an input / output circuit 108 for writing or reading data to or from a memory cell arranged corresponding to the intersection of the row and column selected by row selection circuit 104 and column selection circuit 106 .

  FIG. 1 representatively shows a memory cell MC arranged corresponding to the intersection of one word line WL and one bit line BL (or / BL). In the memory cell array 100, in the case of the "folded bit line configuration", the column lines are constituted by bit line pairs BL and / BL transmitting mutually complementary signals, and the memory cells arranged in one column correspond to the corresponding bit line pairs. Is connected to one bit line BL (or / BL). The memory cells MC arranged in one row are connected to the word line WL. Memory cell MC includes a memory capacitor MQ that stores information, and a memory transistor MT that connects memory capacitor MQ to corresponding bit line BL (or / BL) in response to a signal potential on corresponding word line WL.

  The DRAM further includes a control circuit 110 for generating various internal control signals according to externally applied control signals, that is, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE, and power supply node 20. The power supply voltage supply circuit 120 generates high-level power supply voltages VCL1, VCL2 and VCL3 from the one power supply voltage Vcc supplied to the power supply voltage supply circuit 120 and supplies the same to each circuit, and the other power supply voltage supplied to the other power supply node (ground node) 30 ( A ground voltage supply circuit 130 that generates low-level power supply voltages VSL1, VSL2, and VSL3 from the ground voltage Vss and supplies the low-level power supply voltages VSL1, VSL2, and VSL3 to each circuit.

  The configuration of the control circuit 110 will be described later in detail, and includes a circuit for generating a control signal related to a row selecting operation and a circuit for generating a control signal related to a column selecting operation. Row address strobe signal / RAS determines an operation cycle of the DRAM, that is, a standby cycle in an external access standby state and an active cycle in which external access is performed, and starts an operation related to row selection in the DRAM. A circuit whose activation / inactivation is determined by the row address strobe signal / RAS is hereinafter referred to as a row-related circuit.

  Column address strobe signal / CAS starts an operation (including a data input / output operation) related to column selection of DRAM when signal / RAS is activated (L level). Write enable signal / WE indicates whether data writing is performed or not, and specifies data writing at a low level and data reading at a high level. Data read timing is determined by activation of column address strobe signal / CAS, and data write timing is determined by activation of signal / WE or / CAS, whichever is later. A circuit whose activation / inactivation is determined by signal / CAS is hereinafter referred to as a column-related circuit. A structure to which output enable signal / OE is further applied may be used.

  The power supply voltage supply circuit 120 and the ground voltage supply circuit 130 will be described later in detail. The subthreshold current is suppressed by changing the impedance (resistance) of the power supply line transmitting the signal according to the operation state (operation cycle and operation period) of the DRAM.

  Next, the data input / output operation of the DRAM shown in FIG. 1 will be briefly described with reference to the operation waveform diagram shown in FIG. When external row address strobe signal / RAS is inactive at a high level, the DRAM is in a standby cycle. In this state, in memory cell array 100, bit line BL and / BL are precharged to the intermediate potential (Vcc / 2) level when word line WL is in the unselected low level. The sense amplifier activation signal SO is also at the low level in the inactive state.

  Although not shown in FIG. 1, a sense amplifier is provided for each bit line pair BL and / BL, and when activated, this sense amplifier differentially changes the potential of each bit line of the corresponding bit line pair. Amplify. The input / output data Din (and Q) is in an invalid state. In FIG. 2, it is shown as high impedance (electrically floating state) Hi-Z.

  When signal / RAS falls to a low level, an active cycle starts, and internal access of the DRAM is performed. First, the bit lines BL and / BL held at the intermediate potential are floated at the precharge potential. Address buffer 102 fetches a given address signal and generates internal row address signal RA under the control of control circuit 110. Row selecting circuit 104 decodes internal row address signal RA, and raises the potential of a word line provided corresponding to the addressed row to a high level. Data (potential of one electrode (storage node) of memory capacitor MQ) held by a memory cell connected to the selected word line WL is transmitted to corresponding bit line BL or / BL (via memory transistor MT) ). Thereby, the potential of bit line BL or / BL changes according to the held data of the transmitted memory cell. The other bit line / BL or BL of the pair holds the precharge potential (Vcc / 2).

  Next, a sense amplifier activation signal SO is activated, and a sense amplifier (not shown) operates to differentially amplify the potential of the bit line pair BL and / BL, thereby detecting and amplifying data held in the memory cell. FIG. 2 shows a case where the selected memory cell holds high-level data. When the potentials of bit lines BL and / BL are set to a high level (power supply voltage Vcc level) and a low level (ground voltage Vss level), the column interlock period ends, and the operation of the column related circuit is permitted.

  During the period in which the output signal of the column related circuit is valid, the external column address strobe signal / CAS is valid, becomes active, and goes low. In response to the low level column address strobe signal / CAS, address buffer 102 takes in the address signal and generates internal column address signal CA. Column select circuit 106 decodes internal column address signal CA and selects a corresponding column (bit line pair) in memory cell array 100. Input / output circuit 108 outputs valid data Q in response to the fall of column address strobe signal / CAS during data reading. At the time of data writing, when write enable signal / WE and column address strobe signal / CAS are both at low level, valid internal write data is generated from external write data D, and the selected memory cell ( Memory cell located at the intersection of the selected row and column).

  When data writing / reading of necessary memory cells is completed, row address strobe signal / RAS rises to an inactive high level, and an active cycle is completed. As a result, the column-related operation effective period is completed, the selected word line WL is deselected, the sense amplifier activation signal SO is also deactivated, and the bit lines BL and / BL are equalized. It is precharged to an intermediate potential. Thereafter, when column address strobe signal / CAS is deactivated and write enable signal / WE also goes high, one memory cycle is completed.

  As described above, in the DRAM, the logic level of the internal node (input signal or output signal of each circuit) during the standby cycle can be determined in advance. In the column-related operation valid period, the logic levels of the input signal and the output signal of the row-related circuit can also be determined in advance. Further, the start and completion of the standby cycle and the start and completion of the column operation effective period can be determined by signal / RAS (sense amplifier activation signal SO is generated according to signal / RAS). This embodiment utilizes these features to transmit the potential levels of the output voltages VCL1, VCL2, VSL3 and VSL1, VSL2, VSL3 of the power supply voltage supply circuit 120 and the ground voltage supply circuit 130 shown in FIG. By changing the impedance (resistance) of the power supply line (including the ground line), the sub-threshold current is reduced by changing the MOS transistor operating in the sub-threshold region to a stronger off state.

  FIG. 3 is a block diagram showing a detailed configuration of the address buffer and the control circuit shown in FIG. In FIG. 3, an address buffer 102 includes a row address buffer 101 for generating an X address (internal row address signal RA) from an externally applied address signal Ai-A0, and a Y address (internal column address signal) from an address signal Ai-A0. CA) for generating a column address buffer 103. The row address signal and the column address signal are multiplexed and applied as address signals Ai-A0. The timing at which the row address buffer 101 and the column address buffer 103 generate the X address and the Y address, respectively, are determined by an internal control signal from the control circuit 110.

  Control circuit 110 receives an external row address strobe signal / RAS to generate an internal RAS signal, a row address latch signal RAL, and a row address enable signal rade. A row address controller 202 for activating row address buffer 101 in response, and a word line drive signal RX (described later) and a sense amplifier activation signal SO in response to an internal RAS signal from / RAS buffer 200. An array controller 206 includes an interlock signal generation circuit 208 that generates an interlock signal in response to a signal (sense amplifier activation signal) from the array controller 206. An interlock signal from interlock signal generation circuit 208 determines an interlock period and a column-related operation effective period shown in FIG. 2, and enables an operation related to column selection.

  Control circuit 110 further generates an internal CAS signal, a column address latch signal CAL and a column address enable signal CAD in response to external column address strobe signal / CAS, / CAS buffer 210, and external write enable signal / WE. WE buffer 212 that generates an internal WE signal in response, column address controller 214 that controls the operation of column address buffer 103 in response to signals CAL and CADE from / CAS buffer 210, and Y from column address buffer 103. An ATD circuit 216 for detecting the address change point, and a data read system of the input / output circuit shown in FIG. Becoming trust , An internal CAS signal from the / CAS buffer 210, an internal WE signal from the / WE buffer 212, and an address change detection signal ATD from the ATD circuit 216. And a write controller 219 for generating a signal for activating the embedded system.

  In a DRAM, an address access time from the application of a column address signal to the output of valid data is defined by specifications. Therefore, ATD circuit 216 is provided for detecting the change of the column address signal. In accordance with the address change detection signal ATD from the ATD circuit 216, the operation timing of column related circuits such as a column decoder and a preamplifier (described later) is determined. Read controller 218 generates preamplifier enable signal PAE according to address change detection signal ATD from ATD circuit 216, and outputs output enable signal OEM (described later) according to signal / CAS. Write controller 219 generates a signal WDE for activating a write driver to be described later according to an internal WE signal from / WE buffer 212 and an address change detection signal ATD, and generates an internal CAS signal from / CAS buffer 210 and ATD circuit 216. And outputs a data latch signal DIL for an input buffer, which will be described later, in accordance with the address change detection signal ATD.

  The row address controller 202 causes the row address buffer 101 to latch a row address according to the row address latch signal RAL, and renders the internal row address signal (X address) valid in response to the row address enable signal RADE. The column address controller 214 causes the column address buffer 103 to perform an address latch operation when the column address latch signal CAL is activated. Then, when the column address enable signal CADE is activated, the column address controller 214 changes the internal column address signal CA (Y address). Set to the valid state.

  The interlock signal from interlock signal generation circuit 208 is applied to / CAS buffer 210 and / WE buffer 212. When the output of interlock signal generation circuit 208 is inactive and a column interlock period is designated, the internal signal generation operation of / CAS buffer 210 and / WE buffer 212 is in a standby state. ATD circuit 216 is similarly set to a standby state for generating address change detection signal ATD according to a column interlock period designation signal (inactive interlock signal) from interlock signal generation circuit 218.

  When a refresh operation is designated according to the internal RAS signal from / RAS buffer 200 and the internal CAS signal from / CAS buffer 210 (CBR mode), refresh controller 204 internally generates an internal RAS signal having a predetermined time width. Occurs and performs the necessary operations for refreshing. Refresh controller 202 determines that the refresh mode has been designated when column address strobe signal / CAS falls before the rise of row address strobe signal / RAS. When the refresh mode is designated, the column selection operation is normally prohibited (prohibition of generation of internal CAS signal and internal WE signal).

  In the configuration shown in FIG. 3, a circuit operating in association with signal / RAS, that is, a row-related circuit includes a / RAS buffer 200, a row address controller 202, a refresh controller 204, an array controller 206, an interlock signal generation circuit 208, and a row. It is an address buffer 101. The column-related circuits related to the column selection are the / CAS buffer 210, / WE buffer 212, column address controller 214, ATD circuit 216, read controller 218, write controller 219, and column address buffer 103.

  FIG. 4 is a block diagram showing a detailed configuration of the memory cell array unit and the input / output circuit shown in FIG. 4, row selection circuit 104 decodes an X address (internal row address signal RA) given from row address buffer 101 shown in FIG. 3, selects a corresponding word line in memory cell array 104, and receives a signal from array controller 206. It is constituted by a row decoder 230 for transmitting the applied word line drive signal RX onto the selected word line WL. Memory cell array 104 is activated by sense amplifier activation signal SO provided from array controller 206 (see FIG. 3), and differentially changes the signal potential of each column CL (bit line pair BL and / BL). A sense amplifier 232 for amplification is provided.

  The column selection circuit 106 shown in FIG. 1 is activated in response to a column address enable signal CDE provided from the read controller 218 or write controller 219 shown in FIG. And a column decoder 234 that decodes the applied Y address (internal column address signal CA) and generates a signal for selecting a corresponding column in memory cell array 104. Column select circuit 106 shown in FIG. 1 further includes an IO gate for connecting a corresponding column in memory cell array 104 to I / O line 236 in response to a column select signal from column decoder 234. This IO gate is not shown in FIG.

  1 is activated in response to a preamplifier enable signal PAE provided from read controller 218 shown in FIG. 3, and amplifies internal read data on I / O line 236 to read data bus. Activated in response to a preamplifier 240 transmitted to the read amplifier 245 and a main amplifier output enable signal OEM from the read controller 218 (see FIG. 3), amplifies the signal on the read data bus 245 to generate external read data Q. An output buffer 242 for outputting externally written data D in response to an input data latch signal DIL from a write controller 219 shown in FIG. 3 in response to the write driver enable signal WDE from the write controller 219 shown in FIG. It is activatable, including a write driver 246 which outputs the internal write data onto I / O line 236 according to internal write data on the write data bus 249.

  FIG. 4 further shows a Vbb generator 250, a Vcc / 2 generator 255 and a Vpp generator 256 for generating a reference voltage of the DRAM. Vbb generator 250 generates a negative voltage Vbb by a charge pump operation, and applies it to a substrate (or well) region. By applying this negative voltage Vbb to the substrate region, the following effects are achieved.

  (1) The negative voltage Vbb is applied to a p-type substrate region (well region) where an n-channel MOS transistor (insulated gate field effect transistor) is formed. Even when an undershoot is indicated in the signal applied to the external signal input terminal, injection of electrons from this input terminal into the p-type substrate region is prevented, and destruction of memory cell data due to the electron injection is prevented. (2) The PN junction capacitance formed between the high-impurity-concentration N + region of the n-channel MOS transistor and the P-substrate substrate region is reduced, and the internal operation is speeded up. (3) The substrate effect on the threshold voltage of the n-channel MOS transistor is reduced, and the circuit operation is stabilized. (4) The generation of a parasitic MOS transistor formed between the signal wiring and the substrate region is suppressed.

  Vcc / 2 generator 255 generates a potential half of power supply voltage Vcc. Intermediate potential Vcc / 2 from Vcc / 2 generator 255 is applied to the other electrode (cell plate) of the memory cell capacitor, and is used when the bit line is precharged to intermediate potential Vcc / 2 during standby. .

  Vpp generator 256 generates a high voltage Vpp higher than power supply voltage Vcc. This high voltage Vpp is used to boost the selected word line to a high voltage level.

  In the configuration shown in FIG. 4, the row-related circuits are a row decoder 230 and a sense amplifier 232. The column related circuits include a column decoder 234, a preamplifier 240, an output buffer 242, an input buffer 244, and a write driver 246. Vbb generator 250 and Vcc / 2 generator 255 always generate a predetermined voltage regardless of row-related signals and column-related signals.

  FIG. 5 is a diagram showing a generation sequence of the control signals shown in FIG. 3 and FIG. The operation of each circuit will be described below with reference to FIGS.

  In the standby cycle, external row address strobe signal / RAS is at a high level. In this state, the internal RAS signal, row address latch signal RAL, and row address enable signal RADE are all at the inactive low level. The column enable signal (interlock signal) CLE for activating the column selection operation is also at the inactive low level. Also, the column address strobe signal / CAS and the write enable signal / WE are at the high level. The column related control signals ATD, PAE, OEM, DIL and WDE are all at the inactive low level. The I / O line is precharged to a predetermined potential (Vcc-Vth) level.

  When row address strobe signal / RAS falls to a low level, an active cycle starts. In response to the fall of row address strobe signal / RAS, internal RAS signal rises to an active high level, and in response to the rise of internal RAS signal, row address latch signal RAL rises to a high level. In response to the rise of row address latch signal RAL, row address buffer 101 shown in FIG. 3 latches applied address signal Ai-A0. Then, the row address enable signal RADE is activated at a high level, and an X address (internal row address signal RA) corresponding to the latched address signal is generated from the row address buffer 101. The column enable signal CLE is kept at the inactive low level until the selection of the word line in the memory cell array 104 according to the X address, the rise of the selected word line potential to the high level, and the sensing operation by the sense amplifier 232 are completed. is there.

  After all the operations of the row-related circuits are completed and the sense amplifier 232 detects, amplifies and latches the data of the memory cell connected to the selected word line, the column enable signal CLE rises to the active high level. . When the column enable signal CLE rises to the high level, the column interlock period ends, and the column-related effective period starts.

  In the column system valid period, column address strobe signal / CAS falls, column address latch signal CAL and column address enable signal CADE are sequentially set to high level, and column address buffer 103 generates a Y address (internal column address signal CA). Is done. The ATD circuit 216 generates an address change detection signal ATD according to the Y address from the column address buffer 103, and the read controller 218 or the write controller 219 generates a column decoder enable signal CDE according to the address change detection signal ATD. FIG. 5 does not show column address latch signal CAL, column address enable signal CADE, and column decoder enable signal CDE to simplify the drawing. Column address latch signal CAL and column address enable signal CADE are generated in response to an internal CAS signal generated according to column address strobe signal / CAS, and column decoder enable signal CDE is generated in response to a rise of address transition detection signal ATD. Generated.

  In response to column decoder enable signal CDE, column decoder 234 performs a decoding operation of the Y address, and selects a column in memory cell array 104 corresponding to the Y address. As a result, the memory cell data transmitted on the selected column is transmitted to I / O line 236, and the potential of I / O line 236 changes. I / O line 236 is released from the precharge state in response to column decoder enable signal CDE and is set to an electrically floating state.

  Then, in response to the fall of address change detection signal ATD, preamplifier enable signal PAE rises to a high level, preamplifier 240 is activated, and the signal appearing on I / O line 236 is amplified to read data on read data bus 245. Communicate to The main amplifier output enable signal OEM from the read controller 218 rises to the high level, the output buffer 242 is activated, and the data on the read data bus 245 is amplified to generate and output the external data Q.

  On the other hand, at the time of data writing, input data latch signal DIL rises to a high level in response to signals / CAS and / WE, input buffer 244 latches external write data D, and is transmitted onto write data bus 249. I do. Then, in response to signals / WE and / CAS, write driver enable signal WDE rises to a high level for a predetermined period, write driver 246 is activated, and internal write data is generated from data on write data bus 249 to generate I / O. Transmit on O line 236.

  When column address strobe signal / CAS rises to a high level, a data write / read cycle for one memory cell is completed, signals OEM and DIL fall to a low level, and I / O line 236 is also precharged. It returns to the potential.

  On the other hand, when the external row address strobe signal / RAS rises to the high level, the active cycle is completed. In response to the rise of the external row address strobe signal / RAS, both the row address enable signal RADE and the column enable signal CADE are deactivated. The state becomes low level. Next, the internal RAS signal and the row address latch signal RAL go low. All the row-related control signals return to the initial state during a period from the rise of the external row address strobe signal / RAS to the high level to the fall of the internal RAS signal to the low level. During the column-related effective period, all row-related control signals maintain a constant state. The column control signal maintains the initial state during the column interlock period and changes during the column valid period. That is, in the DRAM, the logic level of both the row control signal and the column control signal in a certain operation period can be predicted. This embodiment utilizes this.

  FIG. 6 is a diagram showing the configuration of the power supply voltage supply circuit and the ground voltage supply circuit shown in FIG. FIG. 6 shows a configuration of a voltage supply circuit for a row circuit. In FIG. 6, a row-related circuit is represented by cascaded n-stage inverters FR1 to FRn. The input signal IN is a low control signal that is at a low level during a standby cycle, changes to a high level during an active cycle, and is maintained at a high level during a column valid period. The number of inverters may be one, or it may be replaced by another multi-input logic gate (this configuration will be described later).

  The inverters FR1 to FRn have a configuration of a CMOS inverter. In other words, each of inverters FR1 to FRn conducts when a signal applied to its input node is at a low level, and a p-channel MOS for transmitting a voltage applied to power supply node 900 to output nodes (O1 to On). Transistor PT and an n-channel MOS transistor NT which conducts when a signal applied to an input node is at a high level and discharges output nodes (O1 to On) to a voltage level applied to other power supply node 902.

  Power supply voltage supply circuit 120 has a first main power supply line 1 for transmitting power supply voltage Vcc supplied to first power supply node 20, and a variable power supply circuit arranged in parallel with first main power supply line 1. Includes impedance power lines 2 and 3. In the description of the claims, the power supply lines 1 and 2 are referred to as a main power supply line and a sub-power supply line, or a first to third power supply lines. It is called a variable impedance power supply line.

  The first variable impedance power supply line 2 is connected to the first main power supply line 1 via a resistor R1, and the second variable impedance power supply line 3 is connected to the first main power supply line 1 via a resistor R2. A p-channel MOS transistor Q3, which conducts in response to a control signal φc1 to connect the first main power supply line 1 and the first variable impedance power supply line 2 in parallel with the resistor R1, is provided. In parallel with the resistor R2, there is provided a p-channel MOS transistor Q4 which conducts in response to the control signal φc2 and connects the first main power supply line 1 and the second variable impedance power supply line 3 to each other. A stabilizing capacitor C1 having a relatively large capacitance between the first main power supply line 1 and the first variable impedance power supply line 2 for stably holding the potential of the second variable impedance power supply line 2 Is provided. A stabilizing capacitor C2 having a relatively large capacity between the first main power supply line 1 and the second variable impedance power supply line 3 for stably holding the potential of the second variable impedance power supply line. Is provided.

  The resistors R1 and R2 have enough resistance to cause a voltage drop in the second and third variable impedance power supply lines 2 and 3 due to the current flowing therethrough. However, in order to reduce this current consumption, a relatively large resistance value ( For example, it is set to 1 KΩ to 1 MΩ). MOS transistors Q3 and Q4 each have a large current supply capacity sufficient to supply current to the p-channel MOS transistors of inverters FR1 to FRn, and channel width W is set to a sufficiently large value. The on-resistance of the MOS transistors Q3 and Q4 is set to a value sufficiently smaller than the resistances R1 and R2, so that the voltage drop due to the on-resistance can be ignored. As the resistors R1 and R2, a MOS transistor having a large on-resistance or a MOS transistor having a large channel length L and functioning as a resistor may be used.

  Ground voltage supply circuit 130 includes a second main power supply line (hereinafter referred to as a main ground line) 4 for transmitting the other power supply voltage (ground voltage) Vss applied to second power supply node 30, and a main ground line. It includes first and second variable impedance ground lines 5 and 6 arranged in parallel with line 4. In the claims, these ground lines 4 to 6 are referred to as a second main power line, third and fourth sub power lines, and the like, but in the following description, the main ground line and the These are referred to as first and second variable impedance ground lines.

  The first variable impedance ground line 5 is connected to the main ground line 4 via a resistor R3, and the second variable impedance ground line 6 is connected to the main ground line 4 via a resistor R4. An n-channel MOS transistor Q5, which conducts in response to the control signal φs1 and connects the first variable impedance ground line 5 to the main ground line 4, is provided in parallel with the resistor R3. An n-channel MOS transistor Q6, which conducts in response to the control signal φs2 and connects the second variable impedance ground line 6 to the main ground line 4, is provided in parallel with the resistor R4. A capacitor C3 having a large capacitance for stabilizing the potential of the first variable impedance ground line 5 is provided between the main ground line 4 and the first variable impedance ground line 5. A capacitor C4 having a large capacitance for stabilizing the potential of the second variable impedance ground line 6 is provided between the main ground line 4 and the second variable impedance ground line 6. The resistors R3 and R4 have a large resistance value. That is, resistors R3 and R4 have a resistance value enough to maintain the potentials of variable impedance ground lines 5 and 6 at a voltage level higher than ground voltage Vss by the current flowing therethrough. The resistance values of the resistors R3 and R4 are on the order of 1 KΩ to 1 MΩ, like the resistors R1 and R2. MOS transistors Q5 and Q6 have sufficient current driving capability to absorb all the discharge currents of inverters FR1 to FRn, and have a sufficiently large channel width W. The ON resistances of MOS transistors Q5 and Q6 are sufficiently small and set to a value that can be ignored compared to the resistance values of resistors R3 and R4. Resistors R3 and R4 may also be realized using MOS transistors as resistance elements.

  In the inverters FR1 to FRn, one of the odd-numbered inverters FR1, FR3,... Has one power supply node 900 connected to the first variable impedance power supply line 2, and the other power supply node 902 has a second variable impedance ground line. 6 is connected. , FRn (n is assumed to be an even number), each one power supply node 900 is connected to the second variable impedance power supply line 3, and each other power supply node 902 is connected to the first variable impedance ground line. 5 is connected.

  FIG. 7 is a signal waveform diagram showing the operation of the circuit shown in FIG. The operation will be described below with reference to FIGS.

  In the standby cycle, input signal IN is at the low level of ground voltage Vss level. Control signal φc1 is at the level of ground voltage Vss, control signal φs1 is at the level of power supply voltage Vcc, and MOS transistors Q3 and Q5 are both on. Thus, voltage VCL1 on first variable impedance power supply line 2 is at the level of power supply voltage Vcc, and voltage VSL1 on first variable impedance ground line 5 is at the level of ground voltage Vss. On the other hand, control signal φs2 is at the level of ground voltage Vss (0 V), and control signal φ2 is at the level of power supply voltage Vcc. In this state, MOS transistors Q4 and Q6 are both off, and second variable impedance power supply line 3 is supplied with power supply voltage Vcc from main power supply line 1 via resistor R2. Voltage VCL2 on power supply line 3 has a voltage level lower than power supply voltage Vcc. This voltage VCL2 is represented by Vcc-Ia.R2. Ia is a current flowing through the resistor R2. On the other hand, the second variable impedance ground line 6 is connected to the main ground line 4 via a resistor R4. Therefore, the voltage on second variable impedance power supply line 6 is higher than ground voltage Vss. That is, VSL2 = Vss + Ib.R4. The current Ib is a current flowing through the resistor R4.

  In inverter FR1, p-channel MOS transistor PT is turned on in accordance with input signal IN at the level of ground voltage Vss, and output node O1 is charged to power supply voltage VCL1 level. Voltage VCL1 is at power supply voltage Vcc level, and output node O1 is at power supply voltage Vcc level. On the other hand, n-channel MOS transistor NT has input signal IN at the level of ground voltage Vss, is in an off state, and operates in a sub-threshold region. At this time, voltage VSL2 on second variable impedance power supply line 6 is at a higher voltage level than ground voltage Vss level. Therefore, the source voltage of this n-channel MOS transistor NT becomes higher than its gate voltage, the n-channel MOS transistor NT is turned off more strongly, and the subthreshold current is suppressed (see FIG. 47; VGS becomes negative).

  In inverter FR2, the voltage level of node O1 is at the level of power supply voltage Vcc. Therefore, p-channel MOS transistor PT is turned off and operates in the sub-threshold region. Voltage VCL2 on second variable impedance power supply line 3 is at a voltage level lower than power supply voltage Vcc. Therefore, p-channel MOS transistor PT (in inverter FR2) is turned off more strongly, and the subthreshold current in p-channel MOS transistor PT is suppressed. The n-channel MOS transistor of inverter FR2 receives a voltage at the level of power supply voltage Vcc at its gate, and discharges its output node O2 to the level of voltage VSL1 on first variable impedance power supply line 5. Voltage VSL1 on second variable impedance power supply line 5 is at the level of ground voltage Vss. Therefore, output node O2 attains the level of ground voltage Vss. The same operation is performed in the subsequent inverters FR3 to FRn, and the MOS transistor operating in the subthreshold region is turned off more strongly, the subthreshold current is suppressed, and the output nodes O3 to The potential of On is at the power supply voltage Vcc level or the ground voltage Vss level. Therefore, output signal OUT maintains power supply voltage Vcc level (n is an even number). In other words, the p-channel MOS transistor having its gate receiving a signal at the power supply voltage Vcc level has a source potential lower than the power supply voltage Vcc level, is turned off more strongly, and the subthreshold current is reduced. On the other hand, an n-channel MOS transistor whose gate receives a signal at the ground voltage Vss level has its source voltage set higher than the ground voltage Vss level. As a result, a stronger off state is obtained, and the subthreshold current is reduced.

  The active cycle is divided into two periods. This is a row-related signal set time period, that is, a column interlock period and a column-related effective time in which the logic levels of all row-related signals are held. In the active cycle period, control signal φs2 is set to the high level of power supply voltage Vcc level, and control signal φc2 is set to the low level of ground voltage Vss level. On the other hand, control signals φc1 and φs1 are held at the level of ground voltage Vss and the level of power supply voltage Vcc, respectively, in the row-related signal setting time zone. In this state, MOS transistors Q3 to Q6 are all turned on, and both voltages VCL1 and VCL2 on variable impedance power supply lines 2 and 3 attain power supply voltage Vcc level. Voltages VSL1 and VSL2 on variable impedance ground lines 5 and 6 are both at the level of ground voltage Vss. In this row-related set time zone, input signal IN rises from ground voltage Vss level to power supply voltage Vcc level, and the potentials of output nodes O1 to On change accordingly. With the change of the input signal IN, an operating current flows through the MOS transistor which is turned on. In a period before the input signal IN changes, a relatively large current flows due to the charging of the power supply line VCL2, and then all the MOS transistors Q3 to Q6 are turned on, so that a relatively large DC current (active DC current) flows.

  When the input signal IN rises to a high level and its voltage level becomes stable, the row-related signal setting time period is completed, and the column-related effective period starts. That is, the column interlock period ends, and the column related circuits operate. In this column system valid time, control signal φs1 is set to the level of ground voltage Vss again, and control signal φc1 is set to the level of power supply voltage Vcc. Control signals φc2 and φs2 maintain the level of ground voltage Vss and the level of power supply voltage Vcc, respectively. In this state, MOS transistors Q3 and Q5 are off, and MOS transistors Q4 and Q6 remain on. Therefore, during the column system effective time, power supply voltage Vcc is transmitted to variable impedance power supply line 2 via resistor R1, and voltage VCL1 becomes lower than power supply voltage Vcc level, while second variable impedance power supply line 2 The voltage VCL2 on 3 is maintained at the power supply voltage Vcc level by the MOS transistor Q4.

  The voltage VSL1 on the first variable impedance ground line 5 is higher than the ground voltage Vss level by the resistor R3. Voltage VSL2 on second variable impedance power supply line 6 maintains the level of ground voltage Vss. In inverter FR1, input signal IN is at the high level of power supply voltage Vcc level, and p-channel MOS transistor PT has its source potential lower than its gate potential, is turned off more strongly, and the subthreshold current is reduced. . On the other hand, n-channel MOS transistor NT is turned on, and maintains its output node O1 at the level of ground voltage Vss (= VSL2). In inverter FR2, the p-channel MOS transistor is turned on by the voltage of node O1 at ground voltage Vss level, and output node O2 is maintained at power supply voltage Vcc level (= VCL2). The source potential of the n-channel MOS transistor of the inverter FR2 is VSL1 (> Vcc), is higher than the voltage applied to the gate, is turned off more strongly, and the subthreshold current is suppressed. The same applies to the inverters FR3 to FR2 at the subsequent stage, the subthreshold current during the column effective time is suppressed, and the active DC current consumed by the row related circuit is reduced to almost the same current level as in the standby cycle.

  When the active cycle is completed, a standby cycle starts. At the start of this standby cycle, the low-related signal set to the high level returns to the original low level. In this row-related signal reset time zone, control signal φc1 is set to the level of ground voltage Vss, and control signal φs1 is set to the level of power supply voltage Vcc. Control signal φs2 maintains power supply voltage Vcc level, and control signal φc2 maintains ground voltage Vss level. In this state, MOS transistors Q3 to Q6 are all turned on again. In this state, voltages VCL1 and VCL2 are at power supply voltage Vcc level, and voltages VSL1 and VSL2 are at ground voltage Vss level. Thereby, the inverters FR1 to FRn change the potential levels of the output nodes O1 to On at high speed in response to the fall of the input signal IN from the high level to the low level, and return to the initial state.

  When the row-related signal reset time period is completed, control signal φs2 is set to ground voltage Vss level, control signal φc2 is set to power supply voltage Vcc level, MOS transistors Q4 and Q6 are turned off, and MOS transistors Q3 and Q5 are turned on. . Voltage VCL2 becomes lower than power supply voltage Vcc level, and voltage VSL2 becomes higher than ground voltage Vss level. Voltage VCL1 is at power supply voltage Vcc level, and voltage VSL1 is at ground voltage Vss level. In this state, it waits for the start of the next active cycle.

  As described above, MOS transistors Q3 to Q6 are appropriately turned on or off in accordance with the operation period, and the impedances of power supply lines 2 and 3 and ground lines 5 and 6 are changed to operate inverters FR1 to FRn. The power supply voltage level can be changed, and the subthreshold current can be reliably suppressed.

  In the above description of the operation, the input signal IN is at the low level during the standby cycle and changes to the high level during the active cycle. The signal which goes high in the standby cycle and goes low in the active cycle may be the input signal / IN shown in FIG. The operation when the input signal is at the high level during the standby cycle and changes to the low level during the active cycle will be briefly described below.

  FIG. 8 shows the voltage level of each node when a row-related circuit is formed by a CMOS inverter. The first-stage inverter includes a p-channel MOS transistor PT1 and an n-channel MOS transistor NT1, and the second-stage inverter includes a p-channel MOS transistor PT2 and an n-channel MOS transistor NT2. P-channel MOS transistor PT1 receives power supply voltage Vcc from main power supply line 1 via resistor R2 and MOS transistor Q4, and n-channel MOS transistor NT1 receives ground voltage from main ground line 4 via resistor R3 and MOS transistor Q5. Receive Vss. MOS transistor PT2 receives power supply voltage Vcc from main power supply line 1 via resistor R1 and MOS transistor Q3, and n-channel MOS transistor NT2 receives ground voltage Vss from main ground line 4 via R4 and MOS transistor Q6.

  As shown in FIG. 8A, in the standby cycle, the input signal is at a high level, MOS transistors Q4 and Q6 are turned off, and MOS transistors Q3 and Q5 are turned on. The source potential of p channel MOS transistor PT1 is VCL (<Vcc), and the source voltage of n channel MOS transistor NT1 is ground voltage Vss. The source potential of p-channel MOS transistor PT2 is at power supply voltage Vcc level, and the source potential of n-channel MOS transistor NT2 is VSL (> Vss). The input signal is at the high level of power supply voltage Vcc, n-channel MOS transistor NT1 is turned on, and its output node is at the low level of ground voltage Vss. At this time, the gate potential of the p-channel MOS transistor PT1 is higher than the source potential, so that the p-channel MOS transistor PT1 is turned off more strongly, and the subthreshold current is suppressed. The p-channel MOS transistor PT2 receives a low-level potential at its gate, turns on, and outputs a high-level signal at the power supply voltage Vcc level. Since the gate potential of the n-channel MOS transistor NT2 is lower than the source potential, the n-channel MOS transistor NT2 is turned off more strongly, and the subthreshold current is suppressed.

  As shown in FIG. 8B, in the row-related signal setting time zone, all the MOS transistors Q3 to Q6 are turned on. The source potentials of p channel MOS transistors PT1 and PT2 are at the level of power supply voltage Vcc, and the source potentials of n channel MOS transistors NT1 and NT2 are at the level of ground voltage Vss. In this state, the input signal changes from the high level to the low level, and the output signal of the inverter changes according to the change of the input signal.

  As shown in FIG. 9A, in the column-related effective period, the input signal is at the low level of the ground voltage Vss level, and the logic level of the input signal does not change during this period. In this state, MOS transistors Q3 and Q4 are off, and MOS transistors Q4 and Q6 are on. The source potential of n-channel MOS transistor NT1 attains voltage VSL (> Vcc) level, and the source potential of p-channel MOS transistor PT2 attains voltage VCL (<Vcc) level. The source potential of p channel MOS transistor PT1 is at the level of power supply voltage Vcc, and the source potential of n channel MOS transistor NT2 is at the level of ground voltage Vss. In this state, n-channel MOS transistor NT1 and p-channel MOS transistor PT2 are turned off more strongly, and the subthreshold current is suppressed. The voltage level of the output signal of each inverter is held at the power supply voltage Vcc level or the ground voltage Vss level via the ON-state MOS transistors (PT1 and NT2).

  As shown in FIG. 9B, in the row-related signal reset time period, all of the MOS transistors Q3 to Q6 are turned on, and the inverter responds to a change in the logic level of the input signal to output the low-level output signal. Change the logic level. When this state is completed, the state shifts to the standby cycle state shown in FIG.

  As described above, even when the input signal is at the high level during the standby cycle and at the low level during the active cycle, the MOS transistor operating in the sub-threshold region is turned off more strongly to suppress the sub-threshold current. Can be.

  FIG. 10 is a diagram showing a configuration of a power supply voltage and a ground voltage supply circuit for a column circuit. FIG. 10 shows an n-stage cascaded CMOS inverter as a column circuit. Each of CMOS inverters FC1 to FCm (m is an even number) includes a p-channel MOS transistor PQ and an n-channel MOS transistor NQ.

  The power supply voltage supply circuit 120 includes a main power supply line 1 connected to the first power supply node 20, a variable impedance power supply line 11 arranged in parallel with the main power supply line 1, a main power supply line 1 and a variable impedance power supply. A resistor Ra3 connecting the line 11 and a p-channel MOS transistor Q7 provided in parallel with the resistor Ra3 to conduct the current in response to the control signal φc3 and connect the main power supply line 1 to the variable impedance power supply line 11 are included. A capacitor Ca3 having a large capacitance for stabilizing the potential of variable impedance power supply line 11 is provided between main power supply line 1 and variable impedance power supply line 11. The resistance value of resistance Ra3 is made relatively large, the on-resistance of p-channel MOS transistor Q7 is made sufficiently small, and its current supply capability is made sufficiently large. As the resistor Ra3, a MOS transistor may be connected by resistance.

  The ground voltage supply circuit 130 includes a main power supply line 4 connected to the second power supply node 30, a variable impedance ground line 12 arranged in parallel with the main power supply line 4, a variable impedance ground line 12, and a main ground line. 4 and a n-channel MOS transistor Q8 provided in parallel with the resistor Rb3 and connected to the main power supply line 4 and the variable impedance power supply line 12 by conducting in response to the control signal φs3. A capacitor Cb3 for stabilizing the potential of the variable impedance ground line 12 is provided between the variable impedance ground line 12 and the main ground line 4. The resistance value of the resistor Rb3 is set to be sufficiently large, and the ON resistance of the MOS transistor Q8 is made sufficiently small and the current supply capability thereof is made sufficiently large. The input signal IN is set to a low level during a standby cycle, and changes to a high level during an active cycle (within a column-related effective period). One of the odd-numbered inverters FC1, FC3,... Has one power supply node 18 connected to the main power supply line 1 and the other power supply node 19 connected to the variable impedance ground line 12. One of the even-numbered inverters FC2,..., FCn has one power supply node (18) connected to the variable impedance power supply line 11, and the other power supply node (19) connected to the main ground line 4. Next, the operation of the circuit shown in FIG. 10 will be described with reference to the operation waveform diagram shown in FIG.

  In the standby cycle and the row-related set time zone, control signal φc3 is set to the high level of the power supply voltage level, and control signal φs3 is set to the low level of the ground voltage level. MOS transistors Q7 and Q8 are both turned off. The voltage VCL3 on the variable impedance power supply line 11 is lower than the power supply voltage Vcc by the voltage drop (Ia · Ra3) at the resistance Ra3 because the power supply voltage Vcc is supplied via the resistor Ra3. On the other hand, the variable impedance ground line 12 is connected to the ground line 4 via the resistor Rb3, and the current Ib flowing through the resistor Rb3 causes the voltage VSL3 to be higher than the ground voltage Vss by the voltage Ib · Rb3.

  Now, the input signal IN is at the low level of the ground voltage Vss level, and in the inverter FC1, the p-channel MOS transistor PQ is on and the n-channel MOS transistor NQ is off. The output of inverter FC1 is charged to power supply voltage Vcc level by p-channel MOS transistor PQ. Since the potential of the other power supply node 19 is the voltage VSL3 higher than the ground voltage Vss, the source potential of the n-channel MOS transistor NQ is higher than the gate potential and is turned off more strongly, and the subthreshold current is suppressed. Is done.

  In inverter FC2, n-channel MOS transistor (NQ) is on, and its output is discharged to the level of ground voltage Vss. The source potential of the p-channel MOS transistor (PQ) of the inverter FC2 is the voltage VCL3 on the variable impedance power supply line 11, and is lower than the gate potential. Be suppressed.

  When the row set time period, that is, the column interlock period ends, a column effective time (column effective period) starts. In this column effective time, control signal φc3 is at the level of ground voltage Vss, and control signal φs3 is at the level of power supply voltage Vcc. MOS transistors Q7 and Q8 are both turned on, and voltages VCL2 and VSL3 attain the levels of power supply voltage Vcc and ground voltage Vss, respectively. Within this column effective time, the input signal IN rises from a low level to a high level, and falls from a high level to a low level. In response to the rising and falling of input signal IN, inverters FC1 to FCn perform charging / discharging of their output nodes, and operating current Icc flows.

  When the column valid time is completed, control signal φc3 is set to power supply voltage Vcc level, control signal φs3 is set to ground voltage Vss level again, MOS transistors Q7 and Q8 are turned off, and variable impedance power supply line 11 is connected to main power supply line 1 And the variable impedance ground line 12 is connected to the main ground line 4 via the high resistance Rb3. In this standby cycle and row-related reset time zone, the input signal IN has already been reset to the low level. The operating MOS transistor is turned off more strongly, and the subthreshold current is suppressed.

  As described above, in the column related circuit, the variable impedance power supply line 11 and the variable impedance ground line 12 are connected to the power supply node 20 and the ground voltage node 30 in the low impedance state only during the column effective time during which the column related circuit operates. Operates at a high speed in response to a change in the input signal, and connects the variable impedance power supply line 11 and the variable impedance ground line 12 via the high resistances Ra3 and Rb3 during the standby cycle and the row setting time period (column interlock period). Connection to power supply node 20 and ground voltage node 30, sub-threshold current can be suppressed.

  FIG. 12 is an operation waveform diagram showing both row-related signals and column-related signals. Hereinafter, the entire operation including the row related signal and the column related signal will be described with reference to FIG.

  The row-related signals include a row-related signal / A that is at a high level during a standby cycle and changes to a low level during an active cycle, and a row-related signal B that is at a low level during a standby cycle and changes to a high level during an active cycle. Exists. Similarly, the column signal / C which goes high during the standby cycle and changes to low level during the column effective time, and the column signal / C which is low during the standby cycle and changes to high level during the column effective time Column-related signal D exists.

  In the standby cycle, external row address strobe signal / RAS (ext / RAS) attains a high level, row signal / A and column signal / C are both at a high level, and row signal B and column signal D are at a high level. Both are at low level. The interlock signal (column enable signal) / CLE is at a high level. In this state, control signals φc2 and φs1 are both at a high level, and control signals φs2 and φc1 are both at a low level. The control signal φc3 is at a high level, and the control signal φs3 is at a low level. When the external row address strobe signal / RAS falls to a low level, an active cycle starts.

  In response to the fall of external row address strobe signal / RAS, control signal φs2 changes to high level and control signal φc2 changes to low level. In the active cycle, row-related signals / A and B change respectively. The change timing of each signal is a predetermined time within the time indicated by the dashed waveform in the figure. When row-related signals / A and B change and their states are fixed to low level and high level, control signal φs1 for a voltage supply circuit provided corresponding to a circuit for generating row-related signals / A and B is generated. And φc1 change. The states of the row-related signals / A and B are determined at the latest until the interlock signal / CLE attains an active low level. Before the latest time (determined by the interlock signal / CLE) in the row-related signal setting time zone, the control signal φc1 changes to high level and the control signal φs1 changes to low level. The change timing of control signals φc1 and φs1 is set in a period between time t1 and time t2, as indicated by the broken line in the figure (according to the output determination timing of the corresponding row-related circuit). At the latest, by time t2, control signals φc1 and φs1 are set to high level and low level, respectively.

  When the low-related signal set time period is completed, the interlock signal / CLE becomes the active low level, and accordingly, the control signal φs3 becomes the high level and the control signal φc3 becomes the low level. In this column-related valid time, row-related signals / A and B are fixed at low level and high level, respectively, the subthreshold current is suppressed, and power supply current Icc due to the row-related signal almost flows in a standby cycle. It has the same value as the standby current. In the column effective time, column signals / C and D change. In a DRAM, an operation in which column-related signals / C and D change a plurality of times, such as a page mode operation, is known. During this time, the control signal φs3 is at the high level and the control signal φc3 is at the low level, and the column-related signal changes a plurality of times according to the access. During this time, the power supply current Icc is consumed by the column signal.

  When the active cycle is completed, external row address strobe signal / RAS rises to a high level, and interlock signal / CLE rises to a high level. In response to the rise of interlock signal / CLE, control signal φs3 rises to the low level, control signal φc3 rises to the high level, and the subthreshold current in column-related signal / C and D generator is suppressed. At the completion of the active cycle, column related signals / C and D have already returned to the initial state.

  On the other hand, row-related signals / A and B return to the initial state after the completion of the active cycle. The return of row signals / A and B to the initial state is performed at a predetermined timing between times t3 and t4. When the output signal of each circuit returns to the initial state, the control signal φc1 changes to low level and the control signal φs1 changes to high level. At the end time t2 of the row-related signal reset time zone, the control signal φs2 is at a low level and the control signal φc2 is at a high level. This suppresses the consumption of the sub-threshold current in the row-related signal / A and B generators.

  The configuration shown in FIG. 6 is used as the power supply for the row-related signal generation circuit, and the variable impedance power supply shown in FIG. The sub-threshold current can be minimized, and the current consumption can be significantly reduced. That is, even if a MOS transistor having a small absolute value of the threshold voltage is used, the sub-threshold current can be suppressed. A large-capacity semiconductor memory device which can be used and operates at high speed can be realized.

  FIG. 13 is a diagram showing a generation sequence of a signal for controlling on / off of a MOS transistor as a switching element provided on a power supply line and a ground line. As shown in FIG. 13, in a standby cycle in which external row address strobe signal / RAS (ext / RAS) is at a high level, control signals φs1, φc2, and φc3 are at a high level, and control signals φc1, φs2, and φs3 is at the low level. The sense amplifier activation signal SO is at a low level, and the interlock signal (column enable signal) / CLE is at a high level.

  When external row address strobe signal / RAS falls to a low level, internal RAS signal RAS rises to a high level, and an active cycle starts. In response to the fall of external row address strobe signal / RAS (ext / RAS), control signal φs2 rises to a high level, and control signal φc2 falls to a low level. Then, control signals φs1 and φc1, which change at the fastest timing, change to low level and high level, respectively, in response to the rise of internal row address strobe signal RAS. In addition, in response to the rise of internal row address strobe signal RAS, sense amplifier activation signal SO attains an active high level after a predetermined period has elapsed. In response to the activation (high level) of the sense amplifier activation signal SO, the interlock signal / CLE becomes low level, and the operation of the column circuit becomes possible. In response to the falling of interlock signal / CLE, control signals φs1 and φc1 that change at the latest timing change to low level and high level, respectively. The control signals φs1 and φc1 change during the row-related signal set period (time zone) indicated by the broken line region in FIG.

  On the other hand, control signal φs3 changes to high level and control signal φc3 changes to low level in response to the fall of interlock signal / CLE. While the interlock signal / CLE is at the low level, the column-related signal changes, and a predetermined operation is performed.

  When the active cycle is completed, external row address strobe signal / RAS (ext / RAS) rises to a high level, and interlock signal / CLE rises to a high level. Control signals φs1 and φc1, which change at the fastest timing, change to a high level and a low level, respectively, in response to the rise of interlock signal / CLE. Control signals φs3 and φc3 change to low level and high level, respectively, in response to the rise of interlock signal / CLE.

  In response to the rise of external row address strobe signal / RAS (ext / RAS), internal row address strobe signal RAS falls to a low level after a predetermined time has elapsed, and sense amplifier activation signal SO changes to a low level in response. In response to the fall of internal row address strobe signal RAS, control signals φs1 and φc1 that change at the latest timing change to high level and low level, respectively. Thereafter, control signals φs2 and φc2 change to low level and high level, respectively, in response to the fall of external row address strobe signal RAS.

  FIG. 14 is a diagram showing an example of a configuration for generating the control signal shown in FIG. 14, a control signal generation system includes an inverter 300 receiving external row address strobe signal / RAS (ext / RAS), and a fall delay circuit delaying the fall of inverter 300 to generate internal row address strobe signal RAS. 302, a sense amplifier activation signal generation circuit 304 for generating a sense amplifier activation signal SO in response to the output signal RAS of the fall delay circuit 302, and a response to the output signal of the inverter 300 and the sense amplifier activation signal SO. An interlock signal generating circuit 306 for generating an interlock signal / CLE, and an internal row address strobe signal RAS from the fall delay circuit 302 and a row in response to the interlock signal / CLE from the interlock signal generating circuit 306. System power supply impedance control signal It includes an impedance control signal generating circuit 308 to be generated.

  Row-related circuits are divided into groups according to the timing at which their output signals change. FIG. 14 shows three row-related circuits 316a, 316b, and 316c. The impedance control signal generation circuit 308 generates power supply impedance control signals φs1a, φc1a, φas1b, φc1b, and φs1c, φc1c for each of the row-related circuits 316a to 316c. Row-related power supply circuits 314a, 314b, and 314c are provided for row-related circuits 316a to 316c, respectively. Row system power supply circuit 314a is supplied with control signals φs1a and φc1a, row system power supply circuit 314b is provided with control signals φs1b and φc1b, and row system power supply circuit 314c is provided with control signals φs1c and φc1c. .

  Control signal φs2 is generated from internal row address strobe signal RAS, and control signal φc2 is generated from internal row address strobe signal RAS via inverter 310. These control signals φc2 and φs2 are commonly applied to row power supply circuits 314a to 314c. Each of row-related power supply circuits 314a to 314c changes the impedance of its own power supply line (operating power supply voltage Vcc transmission line and ground voltage Vss transmission line) in accordance with a given control signal to supply power to corresponding row-related circuits 316a to 316c. Voltages (operating power supply voltage Vcc and ground voltage Vss) are transmitted.

  Control signal φc3 is generated from interlock signal / CLE, and control signal φs3 is generated from interlock signal / CLE via inverter 312. These control signals φc3 and φs3 are applied to column related power supply circuit 320. Column-related power supply circuit 320 supplies a necessary voltage to column-related circuit 322 in accordance with applied control signals φc3 and φs3.

  Inverter 300 and fall delay circuit 302 are included in / RAS buffer 200 shown in FIG. 3, and sense amplifier activation signal generating circuit 304 is included in array controller 206 shown in FIG. Interlock signal generation circuit 306 is the same as interlock signal generation circuit 208 shown in FIG.

  Fall delay circuit 302 raises internal row address strobe signal RAS to a high level in response to the rise of the output signal of inverter 300, and outputs internal row address strobe signal RAS after a lapse of a predetermined time from the fall of the output signal of inverter 300. Fall to low level. Sense amplifier activation signal generation circuit 304 delays the rise of internal row address strobe signal RAS for a predetermined time to raise sense amplifier activation signal SO to an active high level, and causes the rise of internal row address strobe signal RAS to fall. In response, the sense amplifier activation signal SO falls to the inactive state low level.

  Interlock signal generation circuit 306 lowers interlock signal / CLE to the active low level in response to the rise of sense amplifier activation signal SO to the high level, and responds to the fall of the output signal of inverter 300. To raise the interlock signal / CLE to a high level to deactivate the interlock signal. Impedance control signal generating circuit 308 controls control signals φs1 (φs1a to φs1c) and φc1 (φc1a to φc1c) which change in the broken line region shown in FIG. 13 in response to internal row address strobe signal RAS and interlock signal / CLE, respectively. ).

  In the configuration shown in FIG. 14, fall delay circuit 302, sense amplifier activation signal 304, and interlock signal generation circuit 306 are also row-related circuits, and power supply lines (operation power supply voltage Vcc transmission line and ground voltage Vss) of these circuits are provided. The impedance of the transmission line is adjusted according to the change in the logic level of the output signal of each circuit. In the power supply of the impedance control signal generation circuit 308, the impedance of the power supply line of each control signal generation circuit is adjusted according to the change of the control signals φs1 (φs1a to φs1c) and φc1 (φc1a to φc1c). The impedance of the power supply line of inverter 310 may be adjusted according to external row address strobe signal RAS, and the impedance of the power supply line of inverter 312 may be adjusted according to interlock signal / CLE.

  Inverter 300 for external row address strobe signal / RAS (ext / RAS) may be configured to operate by receiving only power supply voltage Vcc and ground voltage Vss.

[First Modification]
Row-related signals and column-related signals are sequentially generated according to a certain operation sequence. In this case, a row-related signal and a column-related signal can be generated by utilizing a signal delay using an inverter array. In a DRAM, a multi-input logic gate is also used. Hereinafter, a method of adjusting the impedance of the power supply line when having a multi-input logic gate will be described.

  FIG. 15 is a diagram illustrating an example of a configuration of a two-input NAND circuit. 15, a two-input NAND circuit is connected in series between p-channel MOS transistors PQ1 and PQ2 connected in parallel between one power supply line 330 and output node 331, and in series between output node 331 and the other power supply line 332. N channel MOS transistors NQ1 and NQ2. Input signal INA is applied to the gates of MOS transistors PQ1 and NQ1, and input signal INB is applied to the gates of MOS transistors PQ2 and NQ2.

  Consider an operation in which the output OUT of the two-input NAND circuit is at a low level (L) during a standby cycle and changes to a high level (H) during an active cycle. In the standby cycle, since output signal OUT is at low level, MOS transistors NQ1 and NQ2 are on, and MOS transistors PQ1 and PQ2 are off. In the standby cycle, a subthreshold current flows through MOS transistors PQ1 and PQ2. Therefore, in this case, voltage Vc on power supply line 330 must be set to voltage VCL (VCL1 or VCL2) lower than power supply voltage Vcc in the standby cycle. When the output signal OUT goes high in the active cycle, at least one of the MOS transistors NQ1 and NQ2 is turned off. In this state, a subthreshold current flows via MOS transistors NQ1 and NQ2. Therefore, in this state, voltage Vs of power supply line 332 is set to a voltage higher than ground voltage Vss, and the source potential of the MOS transistor operating in the subthreshold region is increased.

  The change of the power supply voltage as described above is given by the voltages VCL2 and VSL1 from the operation waveform diagram shown in FIG. Therefore, as shown in FIG. 16, power supply voltage VCL2 is applied to one power supply line 330 of NAND circuit 335, and voltage VSL1 is applied to the other power supply line 332. With this configuration, the subthreshold current can be suppressed.

  Conversely, consider the case where the output signal OUT of the NAND circuit 335 shown in FIG. 15 is at the high level (H) in the standby cycle and changes to the low level (L) in the active cycle. In this case, MOS transistors NQ1 and NQ2 may have a sub-threshold current flowing in the standby cycle. Even if the p-channel MOS transistor PQ (PQ1 or PQ2) receives a high-level signal at its gate, no subthreshold current is generated because the output signal OUT is at the power supply voltage Vcc level. Therefore, in this standby cycle, power supply voltage Vcc is transmitted to power supply line 330, and a voltage higher than ground voltage Vss is transmitted to power supply line 332. When the output signal OUT falls to a low level in the active cycle, the sub-threshold current flows through the p-channel MOS transistor PQ1 or PQ2. Therefore, in this case, the voltage of power supply line 330 is set to a voltage level lower than power supply voltage Vcc, and the voltage on power supply line 332 is set to the level of ground voltage Vss.

  The power supply voltage sequence as described above is given by the voltages VSL1 and VSL2 from the operation waveform diagram shown in FIG. Therefore, as shown in FIG. 17, the voltage VCL1 is supplied to one power supply line 330 of the NAND circuit, and the voltage VSL2 is supplied to the other power supply line 332. Thus, the sub-threshold current in NAND circuit 335 that outputs a high-level signal in the standby cycle and outputs a low-level signal in the active cycle can be suppressed.

  FIG. 18 is a diagram showing a configuration of a two-input NOR circuit. 18, two-input NOR circuit 340 is provided in parallel between p-channel MOS transistors PQ3 and PQ4 connected in series between one power supply line 340 and output node 341, and between output node 341 and the other power supply line 342. N channel MOS transistors NQ3 and NQ4 provided. Input signal INA is applied to the gates of MOS transistors PQ3 and NQ3, and input signal INB is applied to the gates of MOS transistors PQ4 and NQ4.

  It is assumed that the output signal OUT changes to a low level during a standby cycle and changes to a high level during an active cycle. In the standby cycle, when the output signal OUT is at a low level, at least one of the input signals INA and INB is at a high level. Subthreshold current may flow in p channel MOS transistors PQ3 and PQ4. Therefore, voltage Vc on power supply line 340 is set to a voltage level lower than power supply voltage Vcc, and voltage Vs on power supply line 342 is set to the level of ground voltage Vss.

  When output signal OUT rises to a high level in the active cycle, MOS transistors PQ3 and PQ5 are both on (input signals INA and INB are both low). At this time, the sub-threshold current flows through MOS transistors NQ3 and NQ4. Therefore, voltage Vs on power supply line 342 is set to a voltage level higher than ground voltage Vss, while voltage Vc on power supply line 340 is set to power supply voltage Vcc level. It is the voltages VCL2 and VSL1 that give this voltage change. Therefore, as shown in FIG. 19, voltage VCL2 is applied to one power supply line 340 of NOR circuit 345 that outputs signal OUT which goes low in the standby cycle and goes high in the active cycle, and voltage VCL is applied to the other power supply line 342. VSL1 is provided.

  On the other hand, when the output signal OUT goes high during the standby cycle and goes low during the active cycle, the above description is reversed. In other words, in the standby cycle, the sub-threshold current flows through MOS transistors NQ3 and NQ4, while setting voltage Vs on power supply line 342 higher than the level of ground voltage Vss. In the active cycle, the sub-threshold current flows through the path of p-channel MOS transistors PQ3 and PQ4. Therefore, in this case, voltage Vc of one power supply line 340 is set lower than power supply voltage Vcc. It is the voltages VCL1 and VSL2 that give such a voltage change. Therefore, as shown in FIG. 20, a voltage VCL1 is applied to one power supply line 340 of NOR circuit 345 that outputs a high-level signal in a standby cycle and outputs a low-level signal in an active cycle, while the other power supply line 342 Is supplied with voltage VSL2.

  As described above, even in the multi-input logic circuit, the logic level of the output signal is known during the standby cycle and the active cycle, and if the logic level changes between the standby cycle and the active cycle, the sub-threshold is used. The current can be reliably suppressed. The NAND circuit and the NOR circuit are described as row circuits. In the case of a column circuit, if the logic level of the output signal OUT during the standby cycle is known, the power supply voltage level, which is the logic opposite to the output logic level, is set to the intermediate potential level (between Vcc and Vss). A configuration for adjusting may be used. This is because, in the case of a column-related circuit, the power supply line is in a low impedance state at the level of the power supply voltage Vcc and the ground voltage Vss during the column-related effective time.

  As described above, when the logic level of the input / output signal can be predicted in the active cycle and the standby cycle, the subthreshold current can be effectively suppressed even in the multi-input logic gate.

[Second Modification]
As shown in the prior art (IEEE 1993 Symposium on VLSI Circuit, Digest of Technical Papers, pp. 47-48), Horiguchi et al. All potentials can be predictable. However, there are cases where the logic level of the output signal cannot be predicted in the active cycle, such as the output signal of the address buffer, the decoder circuit and the clocked inverter. In the sense amplifier, a sub-threshold current may flow at both the high level and the low level during the standby cycle (the power supply voltage Vcc and the ground voltage Vss are turned on in response to the sense amplifier activation signal SO to be transmitted to the sense amplifier). Sub-threshold current may flow in the transistor that operates). In this case, if the above-described power supply line impedance change sequence is used, the subthreshold current may not be effectively suppressed. Hereinafter, a power supply line impedance change sequence for a circuit in which the logic level of the output signal cannot be predicted will be described.

  FIG. 21 is a diagram showing a configuration of a power supply circuit of a semiconductor device according to a second modification of the first embodiment of the present invention. FIG. 21 representatively shows three 2-input row-related circuits 450, 452, and 454. Row-related circuit 450 receives inputs INA1 and INB1, and generates output OUT1. The output signal OUT1 of the row-related circuit 450 is at a low level (L) during a standby cycle, and the logic level of the output signal is at a high level or a low level during an active cycle (shown as X in the figure). Row-related circuit 452 receives input signals INA2 and INB2 and generates output signal OUT2. The output signal OUT2 of the row-related circuit 452 goes high during the standby cycle, and goes high or low during the active cycle. Row-related circuit 454 receives input signals INA3 and INB3 and generates output signal OUT3. The output signal OUT3 of the row-related circuit 454 becomes high level or low level in the standby cycle, and also becomes high level or low level in the active cycle. As an example of the row-related circuit 454, there is a circuit such as a clocked inverter which is in an output high impedance state in a standby cycle and whose output signal is at a high level or a low level during the operation. As the row circuit 454, a sense amplifier provided for each bit line pair can be considered.

  21, a power supply voltage supply circuit 410 for supplying a high-level power supply voltage includes a main power supply line 1 coupled to a first power supply node 20, and a sub power supply connected to the main power supply line 1 via a resistor R10. And a variable impedance power supply line 403 connected to the main power supply line 1 via a resistor R12. In parallel with the resistor R10, a p-channel MOS transistor Q10 that conducts in response to the control signal φc4 and connects the main power supply line 1 and the variable impedance power supply line 402 is provided. A p-channel MOS transistor Q12 that conducts in response to the control signal φc5 and connects the main power supply line 1 and the variable impedance power supply line 403 is provided in parallel with the resistor R12. A capacitor C10 having a relatively large capacitance for stabilizing voltage VCL1 on variable impedance power supply line 402 is provided between main power supply line 1 and variable impedance power supply line 402. A capacitor C12 having a relatively large capacitance for stabilizing voltage VCL2 on variable impedance power supply line 403 is provided between main power supply line 1 and variable impedance power supply line 403. Resistors R10 and R12 have relatively large resistance values, and MOS transistors Q10 and Q12 have negligible on-resistance compared to the resistance values of resistors R10 and R12. MOS transistors Q10 and Q12 have a current supply capability capable of supplying a sufficient charging current to a row-related circuit (channel width W is increased). The resistors R10 and R12 may be configured by MOS transistors connected by resistance.

  A ground voltage supply circuit 420 for supplying a low-level power supply voltage is coupled to the other power supply node 30 to transmit a ground voltage Vss, and a variable impedance connected to the main ground line 4 and a resistor R11. It includes a ground line 405 and a variable impedance ground line 406 connected to the main ground line 4 via a resistor R13. An n-channel MOS transistor Q11 which conducts in response to the control signal φs4 and connects the main ground line 4 and the variable impedance ground line 405 is provided in parallel with the resistor R11. An n-channel MOS transistor Q13, which conducts in response to control signal φs5 and connects main ground line 4 and variable impedance ground line 406, is provided in parallel with resistor R13. A capacitor C11 having a large capacitance for stabilizing voltage VSL1 on variable impedance ground line 405 is further provided between main ground line 4 and variable impedance ground line 405. A capacitor C13 having a large capacitance for stabilizing voltage VSL2 on variable impedance ground line 406 is further provided between main ground line 4 and variable impedance ground line 406. The resistors R11 and R13 have relatively large resistance values. MOS transistors Q11 and Q13 have a large current supply capability (large channel width) capable of absorbing the discharge current from row-related circuits 450, 452, and 454. The on-resistance of MOS transistors Q11 and Q13 is set to a value that can be ignored as compared with resistors R11 and R13.

  Row-related circuit 450 has one power supply node (node receiving a high-level power supply voltage) connected to variable impedance power supply line 402 and the other power supply node (node receiving a low-level power supply voltage) connected to variable impedance ground line 406. Is done. Row-related circuit 452 has one power supply node connected to variable impedance power supply line 403, and the other power supply node connected to variable impedance ground line 405. Row-related circuit 454 has one power supply node connected to variable impedance power supply line 402 and the other power supply node connected to variable impedance ground line 405. Next, the operation of the configuration shown in FIG. 21 will be described with reference to the operation waveform diagram of FIG.

  In the standby cycle, external row address strobe signal ext / RAS is at a high level, and internal row address strobe signal RAS is at a low level. The output signal OUT1 of the row circuit 450 is low, the output signal OUT2 of the row circuit 452 is high, and the output signal OUT3 of the row circuit 454 is high or low. In this state, control signals φc4 and φs5 are at a high level, and control signals φs4 and φc5 are at a low level. MOS transistors Q10 and Q11 are both turned off, and MOS transistors Q12 and Q13 are turned on.

  The power supply voltage Vcc is supplied from the main power supply line 1 to the variable impedance power supply line 402 via the resistor R10. Therefore, voltage VCL1 becomes lower than power supply voltage Vcc level due to a voltage drop in resistor R10. Further, since variable impedance ground line 405 receives ground voltage Vss via resistor R11, voltage VSL1 becomes higher than ground voltage Vss (0 V). Variable impedance power supply line 403 receives power supply voltage Vcc via MOS transistor Q12, and voltage VCL2 attains the level of power supply voltage Vcc. Since variable impedance ground line 406 receives ground voltage Vss via MOS transistor Q13, voltage VSL2 is at the level of ground voltage Vss.

  Row-related circuit 450 receives voltage VCL1 lower than power supply voltage Vcc, and output signal OUT1 is also at a low level. Therefore, the subthreshold current flowing from the power supply node to the output node is suppressed. Row-related circuit 452 has output signal OUT2 at a high level, and the other power supply node receives voltage VSL1. Therefore, the subthreshold current flowing from the output node to the other power supply node is suppressed. Row-related circuit 454 receives voltage VCL1 at one power supply node and receives voltage VSL1 at the other power supply node. Therefore, row-related circuit 454 receives voltages Vcc and Vss via the high resistance, and regardless of the logic level of the output signal, subthreshold current flowing from one power supply node to the output node and flowing from the output node to the other power supply node. The subthreshold current is suppressed. Therefore, the sub-threshold current in the standby cycle is sufficiently suppressed.

  When the external row address strobe signal ext / RAS falls to a low level, an active cycle starts. In this active cycle, the output signals OUT1, OUT2, and OUT3 of the row circuits 450, 452, and 454 change. In FIG. 22, the change timing of the output signals OUT1 to OUT3 is set to a predetermined time within a period indicated by a bidirectional arrow. That is, the output signals OUT1 to OUT3 change at a predetermined timing during the row-related signal set period.

  In the row-related signal set period, control signal φc4 is at a low level and control signal φs4 is at a high level in accordance with internal row address strobe signal RAS rising to a high level in response to the fall of external row address strobe signal ext / RAS. It is said. The control signal φc5 maintains a low level, and the control signal φs5 maintains a high level. In this state, MOS transistors Q10-Q13 are all turned on, voltages VCL1 and VCL2 are both at power supply voltage Vcc level, and voltages VSL1 and VSL2 are both at ground voltage Vss level. An operation current Icc flows according to the operation of row-related circuits 450, 452, and 454.

  When the row-related signal set period is completed, the interlock signal, that is, the column enable signal / CLE falls to the low level, and the column-related effective period starts. In this column system effective period, control signals φc4 and φc5 are both set at a high level, and control signals φs4 and φs5 are both set at a low level. MOS transistors Q10 to Q13 are all turned off, voltages VCL1 and VCL2 are set to a voltage level lower than power supply voltage Vcc level, and voltages VSL1 and VSL3 are set to a level higher than ground voltage Vss level. During this period, the state of the row-related signal does not change. The subthreshold current is suppressed regardless of the logic levels of the output signals OUT1, OUT2, and OUT3 of the row circuits 450, 452, and 454. In this case, the voltage levels of the output signals OUT1 to OUT3 change from the power supply voltage Vcc and the ground voltage Vss level to a voltage level between the two voltages. Does not occur. Further, in the row-related circuit, it is conceivable that the voltages of the gate and the source of the MOS transistor, which is a component thereof, are at the same voltage level. However, in this case, power supply lines 402 and 403 and ground lines 405 and 406 are in a high resistance state (connected to power supply node 20 or ground voltage node 30 via the high resistance), and the active DC current flowing at that time is sufficiently small. Can be set to a value.

  When the column related valid period is completed and the memory access is completed, the external row address strobe signal ext / RAS rises to the high level, and the active cycle is completed. Column enable signal / CLE rises to a high level in response to the rise of external row address strobe signal ext / RAS. At the beginning of the standby cycle, the output signals OUT1 to OUT3 of the row circuits 450, 452, and 454 return to the initial state. In the row-related signal reset period in which the row-related signal returns to the initial state, control signals φs4 and φs5 are both set to high level, control signals φc4 and φc5 are set to low level, and MOS transistors Q10 to Q13 are all turned on. You. As a result, voltages VCL1 and VCL2 attain power supply voltage Vcc level, and voltages VSL1 and VSL2 attain ground voltage Vss level. Row-related signals are reset at a high speed, and an operating current is generated. The output signals OUT1 to OUT3 return to the initial state at a predetermined timing in the row-related signal reset period. In FIG. 22, the period during which this signal returns is indicated by a bidirectional arrow.

  When the row-related signal reset period is completed, the internal row address strobe signal RAS falls to a low level. In response to the falling of internal row address strobe signal RAS, control signal φc4 is set at a high level and control signal φs4 is set at a low level. Control signals φs5 and φc5 maintain a high level and a low level, respectively. Thereby, MOS transistors Q10 and Q11 are turned off, and MOS transistors Q12 and Q13 are turned on. Thereby, each of the row-related circuits 450, 452, and 454 has one power supply voltage (high-level power supply voltage) and the other power supply voltage (low-level power supply voltage) according to the logic levels of the respective output signals OUT1 to OUT3. The supplied sub-threshold current is suppressed.

  In a column circuit, when the logic level of the output signal is fixed to a high level or a low level in a standby cycle, one power supply voltage and the other power supply whose voltage levels are determined in accordance with the fixed logic level, respectively. It suffices if a voltage is supplied. When the column circuit is set to an output high impedance state like a clocked inverter, for example, it may be connected to a power supply line and a ground line which are set to a high resistance state in a standby cycle. For example, if the configuration shown in FIG. 10 is configured to receive voltages on power supply line 11 and ground line 12, the sub-threshold current can be sufficiently suppressed even in a circuit that is in an output high impedance state, such as a clocked inverter. be able to.

  FIG. 23 shows a configuration and operation waveforms of a circuit for generating a control signal for changing the power supply line impedance shown in FIG.

  In FIG. 23A, a control signal generating system includes an EXOR circuit 460 receiving internal row address strobe signal RAS and a column enable signal (interlock signal) / CLE, an inverter 462 for inverting the output of EXOR circuit 460, and a column. Inverter 464 for inverting enable signal / CLE is included. EXOR circuit 460 operates as a mismatch detection circuit, and outputs a high level signal when the logic levels of signals RAS and / CLE do not match. EXOR circuit 460 outputs control signal φc4. Inverter 462 outputs control signal φs4. Column enable signal / CLE is used as control signal φs5, and inverter 464 outputs control signal φc5. Next, operation of the circuit illustrated in FIG. 23A is described with reference to an operation waveform diagram illustrated in FIG.

  In the standby cycle, internal row address strobe signal RAS is at low level, and column enable signal / CLE is at high level. The control signal φc4 of the output of the EXOR circuit 460 becomes high level. Control signal φs4 attains a low level accordingly. Control signal φs5 is at a high level by column enable signal / CLE, and control signal φc5 is at a low level.

  When an active cycle starts, internal row address strobe signal RAS rises to a high level. At this time, the column enable signal / CLE is still at the high level. As a result, the control signal φc4 output from the EXOR circuit 460 goes low, and the control signal φs4 goes high. Control signals φs5 and φc5 are at high level and low level, respectively, as in the standby cycle.

  When the row-related signal set period is completed, the column enable signal / CLE falls to a low level. As a result, the control signal φc4 output from the EXOR circuit 460 goes high, and the control signal φs4 goes low. The control signal φs5 goes low and the control signal φc5 goes high in response to the fall of the column enable signal / CLE.

  When the active cycle is completed, external row address strobe signal ext / RAS rises to a high level, and in response, column enable signal / CLE rises to a high level. The control signal φs5 goes high and the control signal φc5 goes low. At the rise of column enable signal / CLE, internal row address strobe signal RAS is still at a high level, control signal φc4 output from EXOR circuit 460 is at a low level, and control signal φs4 is at a high level. When internal row address strobe signal RAS falls to a low level, control signal φc4 from EXOR circuit 460 rises to a high level, and control signal φs4 attains a low level. Thus, after the row-related signal reset period is completed, the control signal φc4 can be set at a high level and the control signal φs4 can be set at a low level.

  In the configuration of the control signal generating system shown in FIG. 23, the row-related signal set period and the row-related signal reset period are set as periods common to each row-related circuit. This configuration is merely for facilitating the control, and a configuration in which the change timing of the control signal is adjusted in accordance with the decision timing of each output signal of the row related circuit may be used.

  As described above, according to the first embodiment of the present invention, since the impedance of the power supply line and the ground line is adjusted according to the operation period or the operation cycle, the subthreshold current of each circuit can be effectively reduced. A circuit can be formed using MOS transistors having a low threshold voltage, and a semiconductor memory device that operates at high speed with low current consumption can be obtained.

  In the above embodiment, a semiconductor memory device such as a DRAM is described. However, as long as the semiconductor memory device has a standby cycle and an active cycle, and the active cycle has an output signal holding period and the holding period can be identified, The configuration of the present invention can be applied to a general semiconductor integrated circuit device.

[Example 2]
FIG. 24 is a diagram showing a configuration of a power supply circuit according to a second embodiment of the present invention. FIG. 24A shows a configuration of a power supply voltage supply circuit, and FIG. 24B shows an operation waveform thereof. 24A, the power supply voltage supply circuit conducts in response to the control signal φc with the main power supply line 1 connected to the first power supply node 20, the variable impedance power supply line 500, and the main power supply line 1 A p-channel MOS transistor Q21 connecting the variable impedance power supply line 500 to a differential amplifier (OP amplifier) 501 for comparing a voltage VCL on the variable impedance power supply line 500 with a predetermined reference voltage VP; It includes a p-channel MOS transistor Q20 which conducts in response to the output and connects main power supply line 1 and variable impedance power supply line 500 when conducting.

  The variable impedance power line 500 is one of the first and second variable impedance power lines described in the first embodiment (either a row circuit or a column circuit). The differential amplifier 501 operates using the power supply voltage Vcc and the ground voltage Vss as operating power supply voltages, receives the voltage VCL on the variable impedance power supply line 500 at its positive input (+), and receives the reference voltage VP at its negative input (-). receive. When voltage VCL is higher than reference voltage VP, differential amplifier 501 outputs a high-level signal. In the configuration shown in FIG. 24A, a high resistance connecting main power supply line 1 and variable impedance power supply line 500 is not provided. Next, the operation will be described with reference to a signal waveform diagram shown in FIG.

  When control signal φc is at a high level, p-channel MOS transistor Q21 is off. When voltage VCL is higher than reference voltage VP, the output of differential amplifier 501 is at a high level, and MOS transistor Q20 is off. The MOS transistor in the off state is in a high impedance state higher than the resistance element, and the power supply line 500 is in an electrically floating state. When the potential of the variable impedance power supply line 500 in an electrically floating state is lowered by the leak current and becomes lower than the reference voltage VP, the output of the differential amplifier 501 becomes low level, the MOS transistor Q20 is turned on, and the variable impedance is changed. The power supply line 500 and the main power supply line 1 are electrically connected. As a result, current is supplied to the variable impedance power supply line 500 from the power supply node 20, and the voltage VCL rises. When voltage VCL becomes higher than reference voltage VP level, the output of differential amplifier 501 becomes high level, MOS transistor Q20 is turned off, and variable impedance power supply line 500 is again in an electrically floating state.

  When control signal φc attains a low level, p-channel MOS transistor Q21 is turned on, and voltage VCL on variable impedance power supply line 500 attains the level of power supply voltage Vcc applied to power supply node 20 (main power supply line 1). In this state, the output of differential amplifier 501 is at a high level, and MOS transistor Q20 is off.

  By the feedback circuit of differential amplifier 501 and MOS transistor Q20, variable impedance power supply line 500 can be electrically floated while control signal φc is at a high level and voltage VCL is higher than reference voltage VP. Thus, voltage VCL can be stably generated with lower power consumption as compared with the configuration using a resistance element. At this time, by appropriately adjusting the response characteristics of the feedback circuit of the differential amplifier 501 and the MOS transistor Q20, it is possible to maintain the voltage VCL substantially at the reference voltage VP level when the variable impedance power supply line 500 is in the high impedance state. it can. In particular, when a resistance element is used, the voltage VCL at the time of high impedance of the variable impedance power supply line 500 may be set to a desired voltage level due to variation in resistance value due to variation in manufacturing parameters and variation in resistance value due to operating temperature. Although it can be considered impossible, the use of the differential amplifier 501 enables the voltage VCL to be stably held at the reference voltage VP level when the power supply line 500 has a high impedance.

  FIG. 25 is a diagram showing the configuration of a power supply circuit that generates the other power supply voltage (low-level voltage). FIG. 25A shows the configuration of the power supply circuit (ground voltage supply circuit), and FIG. Shows the operation waveforms.

  In FIG. 25 (A), the power supply circuit conducts in response to control signal φs with main ground line 4 connected to the other power supply node (ground node) 30, variable impedance ground line 505, and at the time of conduction, main ground line 4 An n-channel MOS transistor Q23 connecting the variable impedance ground line 505, a differential amplifier (OP amplifier) 506 for comparing the reference voltage Vn and the voltage VSL, and a main ground line 4 in response to the output of the differential amplifier 506. Includes n-channel MOS transistor Q22 for electrically connecting variable impedance ground line 505. Differential amplifier 506 receives reference voltage Vn at its positive input (+) and receives voltage VSL at its negative input. When the voltage VSL is lower than the reference voltage Vn, the output of the differential amplifier 506 is at a high level, and when the voltage VSL is higher than the reference voltage Vn, the output of the differential amplifier 506 is at a low level. Differential amplifier 506 operates using power supply voltage Vcc and ground voltage Vss as operating power supply voltages. Next, the operation of the power supply circuit illustrated in FIG. 25A is described with reference to an operation waveform diagram of FIG. This power supply circuit is used for both row-related circuits and column-related circuits.

  When control signal φs is at low level, MOS transistor Q23 is turned off. When the voltage VSL on the variable impedance ground line 505 is lower than the reference voltage Vn, the output of the differential amplifier 506 goes low, and the MOS transistor Q22 is turned off. As a result, the variable impedance ground line 505 is electrically floated. When the voltage VSL on variable impedance ground line 505 rises and becomes higher than reference voltage Vn due to the subthreshold current of MOS transistors Q22 and Q23 or the subthreshold current from the circuit connected to variable impedance ground line 505, the difference The output of the operational amplifier 506 becomes high level, the MOS transistor Q22 is turned on, and the variable impedance ground line 505 is connected to the main ground line 4. As a result, the voltage VSL decreases.

  When the voltage VSL becomes lower than the reference voltage Vn, the output of the differential amplifier 506 is set to a low level, the MOS transistor Q22 is turned off, and the variable impedance ground line 505 is again brought into an electrically floating state. The electrical floating state is a high impedance state higher than the electrical connection by the resistance element, and hardly generates a current. Since variable impedance ground line 505 is separated from ground node 30, current consumption can be further reduced.

  When control signal φs is at a low level, current flows from variable impedance ground line 505 to ground node 30 only when MOS transistor Q22 is on. Therefore, the current consumption when the variable impedance ground line is in the high impedance state can be further reduced as compared with the configuration using the resistance element. By appropriately setting the response characteristics of the differential amplifier 506 and the MOS transistor Q22, the voltage VSL on the variable impedance ground line 505 in the high impedance state can be set to substantially the level of the reference voltage Vn.

  When control signal φs rises to a high level, MOS transistor Q23 is turned on, variable impedance ground line 505 is set to a low impedance state, connected to ground node 30, and voltage VSL attains the level of ground voltage Vss. The output of the differential amplifier 506 becomes low level, and the MOS transistor Q22 is turned off.

  FIG. 26 is a diagram showing the overall configuration of the power supply circuit. In FIG. 26, variable impedance power supply lines 500a and 500b are provided corresponding to main power supply line 1. For the variable impedance power supply line 500a, the differential amplifier 501a for comparing the voltage VCLa on the variable impedance power supply line 500a with the reference voltage VP, and conducting in response to the output of the differential amplifier 501a, And a variable impedance power supply line 500a, and a p-channel MOS transistor Q21a which conducts in response to control signal φca and connects main power supply line 1 and variable impedance power supply line 500a.

  For the variable impedance power supply line 500b, a differential amplifier 501b that compares the voltage VSLb on the variable impedance power supply line 500b with the reference voltage VP, and conducts in response to the output of the differential amplifier 501b, are connected to the main power supply line 1. A p-channel MOS transistor Q20b connecting to variable impedance power supply line 500b and a p-channel MOS transistor Q21b which conducts in response to control signal φcb and connects main power supply line 1 to variable impedance power supply line 500b are provided.

  Variable impedance ground lines 505a and 505b are provided for main ground line 4. With respect to the variable impedance ground line 505a, the differential amplifier 506a for comparing the voltage VSLa on the variable impedance ground line 505a with the reference voltage Vn, and conducting in response to the output of the differential amplifier 506a, An n-channel MOS transistor Q22a connecting the variable impedance ground line 505a and an n-channel MOS transistor Q23a which conducts in response to the control signal φsa and connects the variable impedance ground line 505b and the main ground line 4 is provided.

  With respect to variable impedance ground line 505b, differential amplifier 506b for comparing voltage VSLb on variable impedance ground line 505b with reference voltage Vn, and conductive in response to the output of differential amplifier 506b, are connected to main ground line 4b. And a variable impedance ground line 505b, and an n-channel MOS transistor Q23b which conducts in response to control signal φsb and connects main ground line 4 and variable impedance ground line 505b. Differential amplifiers 506a and 506b receive voltages VSLa and VSLb at their positive inputs, respectively, and receive reference voltage Vn at their negative inputs.

  Differential amplifier 501a receives power supply voltage Vcc at one power supply node, and receives voltage VSLa at the other power supply node. Differential amplifier 501b receives power supply voltage Vcc at its power supply node, and receives voltage VSLb at its other power supply node. Differential amplifier 506a receives voltage VCLa at one power supply node, and receives ground voltage Vss at the other power supply node. Differential amplifier 506b receives voltage VCLb at one power supply node, and receives ground voltage Vss at the other power supply node.

  In operation, MOS transistors Q21a and Q23a are turned on and off at the same timing. Similarly, ON and OFF of MOS transistors Q21b and Q23b are controlled at the same timing. The outputs of the differential amplifiers 501a, 501b, 506a, and 506b are valid when the corresponding variable impedance power supply line or variable impedance ground line is set to a high impedance state. Differential amplifiers 501a and 501b need to output a high-level signal of power supply voltage Vcc level to turn off corresponding p-channel MOS transistors Q20a and Q20b. When MOS transistors Q20a and Q20b are turned on, it is not always necessary to output a signal at the level of ground voltage Vss. Even when the voltage level is higher than ground voltage Vss, MOS transistors Q20a and Q20b are turned on if their gate potentials are lower than their source potentials. Therefore, the other power supply node of the differential amplifiers 501a and 501b is supplied with the voltage on the variable impedance ground line which is brought into the high impedance state at the same timing. This suppresses the current in differential amplifiers 501a and 501b.

  Similarly, differential amplifiers 506a and 506b need to output a low-level signal of the level of ground voltage Vss when corresponding MOS transistors Q22a and Q22b are turned off. It is not necessary to output a signal at the power supply voltage Vcc level. MOS transistors Q22a and Q22b are turned on when the gate potential is higher than the source potential. Therefore, voltages VCLa and VCLb are applied to one power supply of differential amplifiers 506a and 506b to reduce current consumption in these differential amplifiers 506a and 506b.

  Although inverters F1 and F2 are shown as examples, this may be either a row-related circuit or a column-related circuit. That is, the power supply circuit shown in FIG. 26 can be applied to each of a row-related circuit and a column-related circuit. Further, the present invention can be applied to any of the first embodiment and its modifications.

  As described above, according to the second embodiment of the present invention, a power supply line (including a ground line) which is brought into a high impedance state is electrically floated by a feedback circuit, and a high resistance line connected by a resistance element is provided. Since the high impedance state is set higher than the state, the corresponding variable impedance power supply line (or ground line) can stably generate a voltage when the impedance is high, and the current consumption can be reduced.

[Example 3]
FIG. 27 is a diagram showing a configuration of a power supply circuit according to a third embodiment of the present invention. 27, a power supply voltage supply circuit includes a main power supply line 1 connected to power supply node 20, variable impedance power supply lines 600 and 601 provided corresponding to main power supply line 1, and another power supply node (ground node) 30. , And variable impedance ground lines 602 and 603 provided corresponding to main ground line 4. Variable impedance power supply line 600 is connected to main power supply line 1 via a p-channel MOS transistor Q33 which conducts in response to control signal φcc. Also provided between main power supply line 1 and variable impedance power supply line 600 is a p-channel MOS transistor Q31 which is turned on in response to resistance Raa and control signal / φr in parallel with p-channel MOS transistor Q33. The resistance Raa and the MOS transistor Q31 are connected in series.

  Variable impedance power supply line 601 is connected to main power supply line 1 via resistor Rab, and is connected to main power supply line 1 via MOS transistor Q33-1 which becomes conductive in response to control signal φcc. The resistances Raa and Rab have large resistance values. MOS transistor Q31 has a current supply capability of passing a current flowing through resistor Raa. The ON resistance of MOS transistor Q31 is set to a value sufficiently lower than resistance Raa. MOS transistor Q33 has an on-resistance sufficiently smaller than resistance Raa, and has a sufficiently large current supply capability. The MOS transistor Q33-1 has an on-resistance sufficiently smaller than the resistance value of the resistor Rab.

  An n-channel MOS transistor Q32 and a resistor Rba are connected in series between the variable impedance ground line 602 and the main ground line 4. MOS transistor Q32 is rendered conductive in response to control signal φr. An n-channel MOS transistor Q34 which conducts in response to control signal φss is provided in parallel with MOS transistor Q32 and resistor Rba. MOS transistor Q34 connects main ground line 4 and variable impedance ground line 602 when conductive. Variable impedance ground line 603 is connected to main ground line 4 via n-channel MOS transistor Q34-1 which conducts in response to control signal φss, and to main ground line 4 via resistor Rbb. The ON resistance of MOS transistor Q32 is set to a value sufficiently smaller than the resistance value of resistance Rba. The ON resistance of each of MOS transistors Q34 and Q34-1 is set to a value sufficiently smaller than the respective resistance values of resistors Rba and Rbb. MOS transistor Q34 has a sufficiently large current supply capability, and MOS transistor Q32 has a current supply capability sufficient to pass the current flowing through resistor Rba.

  Inverters F1 and F2 are representatively shown as an example of a circuit in which this power supply circuit supplies a power supply voltage (including a high-level and low-level power supply voltage). Further, a constant voltage generation circuit 610 generating bit line precharge voltage VBL and cell plate voltage VCP is shown. Inverter F1 has one power supply node connected to main power supply line 1 and the other power supply node connected to variable impedance ground line 602. Inverter F 2 has one power supply node connected to variable impedance power supply line 600 and the other power supply node connected to main ground line 4. The input signal IN goes low during the standby cycle. Bit line precharge voltage VBL and cell plate voltage VCP from constant voltage generating circuit 610 are supplied to memory cell array 104.

  In memory cell array 104, a configuration of a bit line precharge / equalize circuit corresponding to one memory cell MC and a pair of bit lines BL and / BL is representatively shown.

  Equalize / precharge circuit is rendered conductive in response to equalize signal EQ, and conducts in response to equalize signal EQ, with n-channel MOS transistors Qa and Qb transmitting bit line precharge voltage VBL to bit lines BL and / BL. And an n-channel MOS transistor Qc for electrically connecting bit lines BL and / BL. Cell plate voltage VCP is transmitted to cell plate CP of memory capacitor MQ included in memory cell MC. Normally, bit line precharge voltage VBL and cell plate voltage VCP are at a voltage level intermediate (1/2) between power supply voltage Vcc and ground voltage Vss. In order for this constant voltage generation circuit 610 to accurately generate an intermediate potential, the amount of voltage drop generated in resistor Rab and resistor Rbb are set to the same value. The intermediate voltage can be stably generated even when the variable impedance power supply line 601 and the variable impedance ground line 603 enter a high impedance state. Next, the operation of the circuit shown in FIG. 27 will be described with reference to a signal waveform diagram shown in FIG.

  The DRAM has a data holding mode such as a power down mode (reducing the voltage level of the power supply voltage Vcc) and a CAS before RAS refresh mode. The CAS-before-RAS refresh mode is a refresh mode designated by lowering the external column address strobe signal / CAS to a low level before the external row address strobe signal / RAS falls. In a CAS-before-RAS refresh mode usually called a CBR refresh mode, refresh is internally performed in a cycle in which the CAS-before-RAS condition is satisfied, and refresh is internally performed every predetermined time in a data holding period ( Self-refresh mode). In the power down mode, the power supply voltage Vcc is lowered and the refresh cycle is lengthened.

  During standby in the normal operation mode, the control signal φcc is set at a high level, and the control signal φss is set at a low level. In this state, MOS transistors Q33, Q33-1, Q34, and Q34-1 are off, and power lines 600 and 601 and ground lines 602 and 603 are in a high impedance state. At this time, control signal φr is at the high level and control signal / φr is at the low level, and MOS transistors Q31 and Q32 are both on. Therefore, power supply voltage Vcc is supplied to variable impedance power supply line 600 via resistor Raa and MOS transistor Q31, and voltage VCLL1 is at a voltage level lower than power supply voltage Vcc.

  On the other hand, power supply voltage Vcc is applied to variable impedance power supply line 601 via resistor Rab, so that voltage VCLL2 becomes lower than power supply voltage Vcc. In addition, variable impedance ground line 602 is connected to main ground line 4 via MOS transistor Q32 and resistor Rba in the ON state, so that voltage VSLL1 has a higher voltage level than ground voltage Vss. Further, since variable impedance ground line 603 is connected to main ground line 4 via resistor Rbb, its voltage VSLL2 is also set to a voltage level higher than ground voltage Vss. At this time, if (VCLL2 + VSLL2) / 2 is equal to Vcc / 2, constant voltages VBL and VCP can be generated stably.

  When the power down mode or the CBR refresh mode is designated, as will be described later, a row address strobe signal is internally generated and the refresh operation is performed. In a CBR active cycle in which refresh is performed, control signal φss is set to a high level, control signal φcc is set to a low level, MOS transistors Q33, Q33-1, Q34 and Q34-1 are all turned on, and a variable impedance power supply is set. Voltages VCLL1 and VCLL2 on lines 600 and 601 are at the power supply voltage Vcc level. Further, the voltages of voltages VSLL1 and VSLL2 on variable impedance ground lines 602 and 603 are also at the level of ground voltage Vss. When this CBR active cycle is completed, internal row address strobe signal RAS rises to a low level. In response to the falling of internal row address strobe signal RAS, control signal φr is set to the low level, control signal / φr is set to the high level, and MOS transistors Q31 and Q32 are turned off. Control signal φss is set to the low level again, control signal φcc is set to the high level, and MOS transistors Q33, Q33-1, Q34 and Q34-1 are all turned off. Variable impedance power supply line 601 is connected to main power supply line 1 via resistor Rab, and voltage VCLL2 falls below power supply voltage Vcc level. Similarly, variable impedance ground line 603 is connected to main ground line 4 via resistor Rbb, and its voltage VSLL2 rises above the level of ground voltage Vss. Since the power supply voltage Vcc and the ground voltage Vss are supplied to the voltages VCLL2 and VSLL2 via the resistors Rab and Rbb, respectively, the levels are stably held during the data holding period.

  On the other hand, MOS transistors Q31 and Q32 are turned off, so that variable impedance power supply line 600 and variable impedance ground line 602 are electrically floating, and have a higher resistance than the resistances of resistors Raa and Rbb. Floating state. During this time, the voltages VCLL1 and VSLL1 are in an electrically floating state, so that their voltage levels change due to discharge.

  In the standby cycle and the data holding state (excluding the refresh period), equalizing signal EQ is at the high level, and bit lines BL and / BL are held at bit line precharge potential VBL. Also at this time, since voltages VCLL2 and VSLL2 maintain a constant voltage level, bit lines BL and / BL are stably held at an intermediate potential. Similarly, cell plate voltage VCP also maintains a constant voltage level. Thus, data can be accurately held in memory cell MC. In the data holding state, the variable impedance power supply line 600 and the variable impedance ground line 602 are electrically floating, so that no current is consumed in this path, and ultra-low power consumption can be realized.

  When the data holding mode is completed, control signal φr goes high, control signal / φr goes low, and MOS transistors Q31 and Q32 are turned on. Since the voltages VCLL1 and VSLL1 change in voltage level due to leakage during the data holding mode, a reset cycle is executed again after the completion of the data holding mode. In the reset cycle, an active cycle and a standby cycle are executed a predetermined number of times (only one is shown in FIG. 28). By performing an active cycle in this reset cycle, internal row address strobe signal RAS rises to a high level, during which control signal φss is at a high level and control signal φcc is at a low level, and variable impedance power supply lines 600 and 601 and variable impedance ground Lines 602 and 603 are set to a low impedance state, and voltages VCLL1 and VCLL2 are at the power supply voltage Vcc level, and voltages VSLL1 and VSLL2 are at the ground voltage Vss level, respectively. This reset cycle is realized by toggling the external row address strobe signal ext / RAS a predetermined number of times after the completion of the data holding mode. By executing this reset cycle, voltages VCLL1 and VSLL1 each return to a predetermined voltage level.

  Upon completion of the reset cycle, normal (normal) operation cycles (active cycle and standby cycle) are executed.

  By supplying power to the constant voltage generating circuit 610 via the resistors Rab and Rbb with the above-described configuration, the voltages VBL and VCP from the constant voltage generating circuit 610 can each maintain a constant voltage level, Even in the reset cycle, the bit line precharge voltage VBL and the cell plate voltage VCP maintain the intermediate potential, and the memory cell data can be accurately refreshed.

  The internal RAS signal shown in FIG. 28 is shown to maintain a low level in the data holding state. In the data holding state, the internal row address strobe signal RAS may rise to a high level at a predetermined time interval, and a self-refresh may be performed. In this case, control signals φss and φcc are set to a high level and a low level, respectively, in each self refresh cycle.

  FIG. 29 is a diagram showing a circuit configuration for generating the control signal shown in FIG. 29, a control signal generating system includes an input buffer 650 for buffering an external row address strobe signal ext / RAS, an input buffer 652 for buffering an external column address strobe signal ext / CAS, and outputs of input buffers 650 and 652. A holding mode detection circuit 654 for detecting that a data holding mode such as a power down mode or a CBR refresh mode has been designated in response to a signal, and performing a refresh in response to a data holding mode instruction signal from the holding mode detection circuit 654. Refresh control circuit 656 for performing necessary control operations, internal RAS generating circuit 658 for generating internal RAS signal φRAS in response to an output signal of input buffer 650, internal RAS signal φRASB from refresh control circuit 656 and internal Gate circuit 660 that receives internal RAS signal φRAS from RAS generating circuit 658 to generate internal row address strobe signal RAS, and generates control signals φcc and φss in response to internal row address strobe signal RAS from gate circuit 660. Control signal generating circuit 662, control signal generating circuit 664 for generating control signals φr and / φr in response to a data holding mode instruction signal from holding mode detecting circuit 654, and data holding mode instruction from holding mode detecting circuit 654 CAS access prohibition circuit 666 for prohibiting an operation related to column selection in response to a signal, and an interlock signal generation circuit for maintaining interlock signal / CLE in an inactive state in response to an output signal of CAS access prohibition circuit 666 668. In a normal operation mode other than the data holding mode, interlock signal generation circuit 668 generates interlock signal / CLE according to internal row address strobe signal RAS from gate circuit 660.

  13, the input buffer 650 and the internal RAS generation circuit 658 correspond to the / RAS buffer 200, and the holding mode detection circuit 654 and the refresh control circuit 656 correspond to the refresh controller 204. Input buffer 652 is included in / CAS buffer 210. Refresh control circuit 656 includes a timer and an address counter, applies the output of the address counter to a row address buffer or a row decoder when a data holding mode is designated, and generates an internal RAS signal φRASB having a predetermined time width. Refresh is performed using the count value of the address counter as a row address. When the refresh is completed (CBR refresh), the refresh control circuit 656 starts a timer as described later and generates the internal RAS signal φRASB at a predetermined interval (self-refresh mode). Refresh control circuit 656 maintains internal RAS generating circuit 658 in an inactive state when the data holding mode is designated, and inhibits generation of internal RAS signal φRASA. Gate circuit 660 generates an internal row address strobe signal RAS according to internal RAS signals φRASB and φRASA. Row-related circuits operate according to the internal row address strobe signal RAS.

  Control signal generation circuit 662 sets control signal φcc to low level and control signal φss to high level when internal row address strobe signal RAS is activated (high level), and deactivates internal row address strobe signal RAS. (Low level), the control signal φcc is set to high level, and the control signal φss is set to low level. Control signal generating circuit 664 outputs a control signal when internal RAS signal φRASB from refresh control circuit 656 changes from the active state to the inactive state when the output of holding mode detecting circuit 654 is in the active state and the data holding mode is designated. φr is set to a low level, and the control signal / φr is set to a high level.

  FIG. 30 is a signal waveform diagram representing an operation of the circuit shown in FIG. Hereinafter, the operation of the circuit shown in FIG. 29 will be described with reference to the operation waveform diagram shown in FIG.

  When external column address strobe signal ext / CAS is at a low level when external row address strobe signal / RAS rises, a data holding mode is designated. In response to this data holding mode designation, refresh control circuit 656 generates internal RAS signal φRASB, and internal row address strobe signal RAS rises to a high level. During this time, CBR refresh is performed. In the CBR refresh period, the signal φcc is set to low level, and the control signal φss is set to high level. When the CBR refresh cycle is completed, control signal generation circuit 664 sets control signal φr to low level and control signal / φr to high level.

  When the CBR refresh period ends, a self-refresh period starts. In this self-refresh period, external row address strobe signal ext / RAS and external column address strobe signal ext / CAS are both set to a low level. A configuration in which only one of external row address strobe signal ext / RAS and column address strobe signal ext / CAS is set to a low level may be used. During this time, refresh control circuit 656 generates internal RAS signal φRASB at a predetermined time interval, and generates internal row address strobe signal RAS accordingly. Control signal generating circuit 662 sets control signal φcc to low level and control signal φss to high level in response to activation (high level) of internal row address strobe signal RAS.

  Control signal generating circuit 664 sets control signal φr to high level and control signal / φr to low level in response to internal RAS signal φRASB from refresh control circuit 656. As a result, the refresh is executed at predetermined time intervals. During this time, the interlock signal generation circuit 668 sets the interlock signal / CLE to a high level by the output signal of the CAS access prohibition circuit 666, and prohibits the operation of the column related circuit.

  When both external row address strobe signal ext / RAS and external column address strobe signal ext / CAS rise to a high level, the data holding mode is completed. In response to the completion of the data holding mode, control signal generating circuit 664 sets control signal φr to high level and control signal / φr to low address. When the data holding mode is completed, a reset cycle is executed. In this reset cycle, external row address strobe signal ext / RAS is set to low level a predetermined number of times. In response to activation (low level) of external row address strobe signal ext / RAS, internal RAS generating circuit 658 generates an internal RAS signal φRASA, and internal row address strobe signal RAS is activated. In response to activation of internal row address strobe signal RAS, control signal φcc is set to the low level, control signal φss is set to the high level, and the potentials of the power supply line and the ground line are restored. When the reset cycle is completed, a normal mode is performed, and an access operation is performed according to internal row address strobe signal ext / RAS and column address strobe signal ext / CAS.

  In the above description, control signals φcc and φss set variable impedance power supply line 600 and variable impedance ground line 602 to a low impedance state / high impedance state in response to activation / inactivation of internal row address strobe signal RAS. I have. Therefore, control signals φr and / φr may be fixedly set to a low level and a high level, respectively, in the data holding mode.

  This configuration can also be applied to the first embodiment. In other words, if internal row address strobe signal RAS from gate circuit 660 is used as internal row address strobe signal RAS shown in FIG. 14, the impedance of variable impedance power supply line and variable impedance ground line changes according to the operation cycle and operation period. Is realized. That is, if control signal generation circuit 662 is replaced with impedance control signal generation circuit 308 shown in FIG. 14, a configuration is realized in which the active DC current can be significantly reduced and the standby current can be further reduced. In this case, the generation of control signals φr and / φr is the same as that shown in the third embodiment for both row-related circuits and column-related circuits. That is, in both the power supply circuit for the row-related circuit and the power supply circuit for the column-related circuit, a MOS transistor is provided in series with the resistance element, and this MOS transistor is turned off in the data holding mode. As a method for generating signals φr and / φr, a gate circuit which operates as a buffer when data retention mode designating signal is activated to pass signal RAS and outputs a high level signal when data retention mode designating signal is inactive. An inverter for inverting the output of the gate circuit can be used.

  As described above, according to the third embodiment of the present invention, both the variable impedance power supply line and the variable impedance ground line which are brought into the high impedance state in the data holding mode are configured to be electrically floating. In addition, current consumption in the data holding mode can be significantly reduced.

[Example 4]
FIG. 31 is a diagram showing a chip layout of the entire DRAM. In FIG. 31, the DRAM includes four memory blocks BCK # 1 to BCK # 4. Each of memory blocks BCK # 1 to BCK # 4 is divided into 32 subarrays SBAR # 1 to SBAR # 32. In each of memory blocks BCK # 1 to BCK # 4, sense amplifier bands SA # 1 to SA # 33 are arranged to be arranged on both sides of subarray SBAR. The sense amplifiers are arranged in a so-called "alternate arrangement type shared sense amplifier arrangement".

  Row-related local circuits LCKA # 1 to LCKA # 4 are provided for each of memory blocks BCK # 1 to BCK # 4, and column-related local circuits LCKB # 1 to LCKB # 4 are provided. Further, column decoders CD # 1 to CD # 4 and row decoders RD # 1 to RD # 4 are provided for memory blocks BCK # 1 to BCK # 4, respectively. Master circuits MCK # 1 and MCK # 3 are provided on both sides of the chip, and master circuit MCK # 2 is provided at the center of the chip. Master circuit MCK # 2 generates various control signals for controlling the operations of local circuits LCKA # 1 to LCKA # 4 and LCKB # 1 to LCKB # 4. Master circuits MCK # 1 and MCK # 3 include a constant voltage generation circuit, a control signal input buffer, and the like. Pads PD for inputting and outputting data, address signals, and external control signals are arranged in an area between row-related local circuits. A so-called “lead-on-chip (LOC) arrangement” is provided.

  Each of subarrays SBAR # 1 to SBAR # 32 is divided into 16 subblocks by word line shunt regions WLSH # 1 to WLSH # 16. In word line shunt regions WLSH # 1 to WLSH # 16, the word lines are electrically connected to low resistance conductive lines. Word line drive signals from row decoders RD (RD # 1 to RD # 4) are transmitted onto the low resistance conductive lines. Thereby, the word line drive signal is transmitted at a high speed.

  Usually, local IO lines for transmitting the memory cell data selected in sub-arrays SBAR # 1 to SBAR # 32 are arranged in parallel with sense amplifier bands SA # 1 to SA # 33. These local IO lines are connected to global IO lines to input and output data. The connection between the local IO line and the global IO line is performed according to a "block selection (sub array selection)" signal. That is, the DRAM shown in FIG. 31 performs a block division operation. For example, in each of memory blocks BCK # 1 to BCK # 4, one subarray SBAR is set to the selected state, and the row selection and column selection operations are performed. The remaining unselected sub-arrays maintain the standby state. In this block division configuration, a sub-array need not be selected in each of all memory blocks BCK # 1 to BCK # 4, and a plurality of sub-arrays are activated in one memory block BCK. May be used.

  In order to perform such block division, row decoders RD # 1 to RD # 4 and column decoders CD # 1 to CD # 4 are provided corresponding to memory blocks BCK # 1 to BCK # 4, respectively, and local circuit LCKA # is provided. 1 to LCKA # 4 and LCKB # 1 to LCKB # 4. Column decoders CD # 1 to CD # 4 simultaneously select the same column line (bit line pair) of subarrays SBAR # 1 to SBAR # 32 in corresponding memory blocks BCK # 1 to BCK # 4. Row decoders RD # 1 to RD # 4 select one word line in a memory block specified by a block selection signal in subarrays SBAR # 1 to SBAR # 32. In this case, the bit line pair is connected to the corresponding local IO line in the non-selected sub-array, but the local IO line provided corresponding to the non-selected sub-array maintains the intermediate potential (precharge potential), and It is the same as the intermediate potential of the bit line of the sub-array, and no destruction of the memory cell data occurs in the unselected sub-array. Only the local IO line of the selected sub-array is connected to the global IO line.

  FIG. 32 is a diagram showing a configuration of a power supply circuit according to a fourth embodiment of the present invention. In FIG. 32, a power supply circuit is provided corresponding to each block (memory block or sub-array) as a unit to be divided and driven in the DRAM shown in FIG. FIG. 32 illustrates an example in which n unit blocks are provided and power supply circuits 700-1 to 700-n are provided. Power supply circuits 700-1 to 700-n each receive power supply voltage Vcc applied to power supply node 20 through main power supply line 1, and receive ground voltage Vss applied to ground node 30 through main ground line 4. Given through.

  A block selection circuit signal generation circuit 710 and an impedance change control signal generation circuit 720 are provided for controlling the impedances of the variable impedance power supply lines and the variable impedance ground lines of the power supply circuits 700-1 to 700-n. Block selection signal generation circuit 710 decodes a block address (usually included in the X address), generates block selection signals φB1 to φBn designating a block including the selected memory cell, and supplies power supply circuits 700-1 to 700- The block selection signals φB1 to φBn are supplied to n respectively. Impedance change control signal generation circuit 720 applies impedance change control signals φss1, φcc1 to φccn, φssn to power supply circuits 700-1 to 700-n in accordance with signals RAS and / CLE and a block selection signal from block selection signal generation circuit 710. give. Impedance change control signal generation circuit 720 applies impedance change control signals φssi and φcci to signals RAS and / CLE only to a power supply circuit provided corresponding to the block designated by the block selection signal from block selection signal generation circuit 710. Change according to. For a power supply circuit provided corresponding to an unselected block, impedance change control signal generation circuit 720 maintains the impedance change control signals φssi and φcci in a standby state. This impedance change control signal generation circuit 720 is not provided commonly to power supply circuits 700-1 to 700-n, but may be configured to be provided corresponding to each of power supply circuits 700-1 to 700-n. . The configuration in which impedance change control signal generation circuit 720 generates an impedance change control signal in accordance with the block selection signal from block selection signal generation circuit 710 is such that signals RAS and / CLE are buffered when the block selection signal is active. When the block selection signal indicates a non-selection state, a logic gate for maintaining signals RAS and / CLE in a standby state may be used. Such a logic gate can be easily realized by using an AND circuit and a NAND circuit.

  FIG. 33 is a diagram illustrating an example of a configuration of power supply circuits 700-1 to 700-n illustrated in FIG. FIG. 33 shows only the configuration of one power supply circuit. 33, power supply circuit 700-i (i = 1 to n) conducts in response to variable impedance power supply lines 731 and 732, variable impedance ground lines 733 and 734, and control signal φccia, and main power supply line 1 A p-channel MOS transistor Q40 connecting the main power supply line 1 and the variable impedance power supply line 732; a p-channel MOS transistor Q41 connecting the main power supply line 1 and the variable impedance power supply line 732 to conduct in response to the control signal φccib; A resistor R40 and a p-channel MOS transistor Q42 connected in series between line 1 and variable impedance power supply line 731; a resistor R41 and a p-channel MOS transistor connected in series between main power supply line 1 and variable impedance power supply line 732 Includes transistor Q43. The gates of p-channel MOS transistors Q42 and Q43 are supplied with a block selection signal / φBi that goes low when the corresponding block is in a selected state.

  Power supply circuit 700-i further conducts in response to control signal φssia, conducts in response to control signal φssib, and n-channel MOS transistor Q45 connecting main ground line 4 and variable impedance ground line 733. N-channel MOS transistor Q46 connecting ground line 4 to variable impedance ground line 734; resistor R42 and n-channel MOS transistor Q47 connected in series between main ground line 4 and variable impedance ground line 733; Includes a resistor R43 and an n-channel MOS transistor Q48 connected in series between line 4 and variable impedance ground line 734. The gates of n-channel MOS transistors Q47 and Q48 are supplied with a block selection signal φBi that goes high when a corresponding block is selected.

  The sub-circuit 750 is a circuit that is driven to be divided into blocks. The sub-circuit 750 is activated when the block selection signal φBi is at a high level indicating a selected state, and performs necessary operations. This sub-circuit 750 may be a row-related circuit or a column-related circuit, and is included in the local circuit shown in FIG.

  Control signals φccia, φccib, φssia, and φssib may be generated in any of the first to third embodiments. MOS transistors Q40 and Q45 are turned on and off at the same timing, and MOS transistors Q41 and Q46 are turned on and off at the same timing. Next, the operation will be briefly described.

  In the standby cycle, one of the variable impedance power supply lines 731 and 732 is set to the low impedance state, and the other variable impedance power supply line is set to the high impedance state. In the standby state, block select signal / φBi is at a high level indicating a non-selected state, and MOS transistors Q42 and Q43 are off. Therefore, the variable impedance power supply line in the high impedance state is electrically floated. As a result, the current consumption in the power supply line in the high impedance state is reduced.

  One of the variable impedance ground lines 733 and 734 is set to a low impedance state, and the other is set to a high impedance state. During standby, block selection signal φBi is at a low level in a non-selected state, and MOS transistors Q47 and Q48 are turned off. Therefore, the variable impedance ground line in the high impedance state is electrically floated and separated from the ground node 30, so that the subthreshold current in the variable impedance ground line in the high impedance state is suppressed.

  In the active cycle, when a corresponding block is designated, block select signal / φBi is at a low level, block select signal φBi is at a high level, and MOS transistors Q42, Q43, Q47 and Q48 are turned on. Thereby, variable impedance power supply lines 731 and 732 are connected to main power supply line 1 via resistors R40 and R41, and variable impedance ground lines 733 and 734 are connected to main ground line 4 via resistors R42 and R43. During the active cycle period, control signals φccia, φccib, φssia, and φssib change in the same manner as described in any of the first to third embodiments, thereby suppressing the subthreshold current. In the power supply circuit provided corresponding to the unselected block in the active cycle, block select signal / φBi is at a high level, block select signal φBi is at a low level, and MOS transistors Q42, Q43, Q47 and Q48 are turned off. is there. Control signals φccia, φccib, φssia, and φssib all maintain the same state as in the standby cycle. As described above, in the unselected memory block, the current flowing through the resistor can be suppressed by maintaining the variable impedance power supply line and the variable impedance ground line in the high impedance state in an electrically floating state, and the sub-threshold current Can be further reduced.

  The physical parameters of the MOS transistors Q40 to Q48 and the resistors R40 to R43 are the same as those described in the first to third embodiments.

  Further, in this configuration, it is conceivable that a certain block is maintained in a non-selected state for a long period of time, and the potentials of the variable impedance power supply line and the variable impedance ground line in the high impedance state change due to the leak current. However, in the DRAM, refresh is performed periodically. At this time, the block selection signals φBi and / φBi are in a selected state, so that the potentials of the variable impedance power supply line and the variable impedance ground line in the high impedance state are set. Returns to a predetermined potential level.

  Also, a configuration may be used in which the variable impedance power supply line and the variable impedance ground line in the high impedance state are electrically floated only to the non-selected blocks in the active cycle. Since the start and end of this active cycle can be detected by internal row address strobe signal RAS, when internal row address strobe signal RAS is at a high level, signals / φBi and φBi are buffered and passed, respectively, and signal RAS is passed. Is low level, signals / φBi and φBi may both be at a low level and a high level, respectively. In this case, the variable impedance power supply line and the variable impedance ground line, which are brought into a high impedance state in the standby cycle, are connected to power supply node 20 and ground node 30 via resistors, respectively.

  As described above, according to the fourth embodiment, a power supply circuit is provided for each unit block in a DRAM that is divided into blocks, and the high impedance state of the power supply circuit provided corresponding to an unselected block is determined. Since the variable impedance power supply line and the variable impedance ground line are electrically floated, the active DC current flowing during the active cycle can be significantly reduced.

[Example 5]
FIG. 34 is a diagram showing a configuration of a main part of a semiconductor device according to a fifth embodiment of the present invention. In FIG. 34, as a power supply voltage supply circuit, the semiconductor device includes a main power supply line 1 transmitting voltage Vcc from power supply node 20, a variable impedance power supply line 760 provided corresponding to main power supply line 1, and an operation cycle. A switching p-channel MOS transistor Q50a electrically connecting main power supply line 1 and variable impedance power supply line 760 in response to prescribed signal / φ is included. Operation cycle defining signal / φ defines a standby cycle and an active cycle of the semiconductor device, and is generated, for example, in accordance with row address strobe signal / RAS shown in FIG. The operation cycle defining signal / φ is at a high level during a standby cycle and at a low level during an active cycle.

  The power supply voltage supply circuit further includes a differential amplifier 761a that differentially amplifies the voltage VCL on the variable impedance power supply line 760 and the reference voltage Vref1, and a main power supply in response to an output signal of the differential amplifier 761a. Drive p-channel MOS transistor Q51a for supplying current from line 1 to variable impedance power supply line 760 is included. Differential amplifier 761a receives voltage VCL on variable impedance power supply line 760 at its positive input (+), and receives reference voltage Vref1 at its negative input (-). When voltage VCL on variable impedance power supply line 760 is higher than reference voltage Vref1, the output signal of differential amplifier 761a attains a high level, and transistor Q51a is turned off. On the other hand, when voltage VCL on variable impedance power supply line 760 is lower than reference voltage Vref1, the voltage level of the output signal of differential amplifier 761a decreases, the conductance of transistor Q51a increases, and main power supply line 1 Supplies a current to the variable impedance power supply line 760 from the power supply. That is, the differential amplifier 761a and the transistor Q51a have a function of holding the voltage VCL on the variable impedance power supply line 760 at the voltage level of the reference voltage Vref1.

  The semiconductor device also includes, as a ground voltage supply circuit, main ground line 4 transmitting voltage Vss from ground node 30, variable impedance ground line 762 provided corresponding to main ground line 4, and an operation cycle defining signal. A switching n-channel MOS transistor Q50b for electrically connecting the main ground line 4 and the variable impedance ground line 762 in response to φ, and the voltage VSL on the variable impedance ground line 762 and the reference voltage Vref2 are differentially It includes a differential amplifier 761b for amplifying, and a driving n-channel MOS transistor Q51b for discharging current from variable impedance ground line 762 to main ground line 4 in response to an output signal of differential amplifier 761b. The operation cycle defining signal φ is a signal complementary to the operating cycle defining signal / φ, and is at a low level during a standby cycle and at a high level during an active cycle. Differential amplifier 761b receives voltage VSL on variable impedance ground line 762 at its positive input (+), and receives reference voltage Vref2 at its negative input (-). That is, when the voltage VSL on the variable impedance ground line 762 is higher than the reference voltage Vref2, the output signal of the differential amplifier 761b shifts to the high level, the conductance of the transistor Q51b is increased, and The current is discharged to the ground line 4. On the other hand, when voltage VSL on variable impedance ground line 762 is lower than reference voltage Vref2, the output signal of differential amplifier 761b becomes low level, and transistor Q51b is turned off. That is, the differential amplifier 761b and the transistor Q51b have a function of holding the voltage VSL on the variable impedance ground line 762 at the voltage level of the reference voltage Vref2.

  The semiconductor device further includes a logic circuit as an internal circuit. FIG. 34 representatively shows three cascaded inverter circuits IV50, IV51 and IV52 as an example of this logic circuit. Inverter circuit IV50 includes a gate receiving input signal IN, one conduction node (source) connected to variable impedance power supply line 760, the other conduction node (drain) connected to internal output node a0, and main power supply line 1 , A gate receiving input signal IN, one conduction node (source) connected to main ground line 4, and an output node a0. On the other hand, it includes an n-channel MOS transistor NQ50 having a conduction node (drain) and a substrate region (body region) connected to main ground line 4.

  Inverter circuit IV51 includes a gate connected to output node a0 of inverter IV50, one conduction node (source) connected to main power supply line 1, another conduction node connected to output node a1, and main power supply line 1 , A gate connected to output node a0 of inverter IV50, a one-side conduction node connected to variable impedance ground line 762, and an output node a1. , And an n-channel MOS transistor NQ51 having a substrate region (body region) connected to main ground line 4. Inverter circuit IV52 includes a gate connected to output node a1 of inverter circuit IV51, one conduction node connected to variable impedance power supply line 760, another conduction node connected to output node a2, and a main power supply line 1. A substrate region (body region) to be connected, a gate connected to output node a1 of inverter circuit IV51, one conduction node connected to main ground line 4, and another conduction node connected to output node a2. Includes n-channel MOS transistor NQ52 having a substrate region (body region) connected to main ground line 4.

  That is, in inverter circuits IV50 to IV52, respective substrate regions (body regions) of p-channel MOS transistors PQ50 to PQ52 are connected to main power supply line 1, and respective substrate regions (body regions) of n-channel MOS transistors NQ50 to NQ52. Are connected to the main ground line 4. By making the source potential (potential of one conduction node) different from the potential of the substrate region (body region) during the standby cycle of the MOS transistor, the absolute value of the threshold voltage is increased by the substrate bias effect of the MOS transistor. In addition, the leakage current during the standby cycle is reduced. Next, the operation of the semiconductor device shown in FIG. 34 will be described with reference to an operation waveform diagram of FIG.

  In the standby cycle, signal φ goes low and signal / φ goes high, and both transistors Q50a and Q50b are turned off. In this state, variable impedance power supply line 760 is held at the voltage level of reference voltage Vref1 by differential amplifier 761a and transistor Q51a. This reference voltage Vref1 is at a voltage level slightly lower than voltage Vcc on main power supply line 1. On the other hand, variable impedance ground line 762 is maintained at the voltage level of reference voltage Vref2 by differential amplifiers 761b and Q51b. This reference voltage Vref2 is at a voltage level slightly higher than voltage Vss on main ground line 4.

  In the standby cycle, the input signal IN is at a high level. In this state, output node a0 is discharged to the level of voltage Vss on main ground line 4 by MOS transistor NQ50. On the other hand, the transistor PQ50 is turned off by the high-level input signal IN. Transistor PQ50 has one conduction node at the voltage level of voltage VCL on variable impedance power supply line 760, ie, reference voltage Vref1, and its substrate region (body region) at the level of voltage Vcc on main power supply line 1. That is, in p channel MOS transistor PQ50, source potential VCL becomes lower than voltage Vcc in the substrate region (body region), and the threshold voltage of transistor PQ50 becomes more negative due to the substrate bias effect (threshold voltage). Becomes larger), the transistor PQ50 is turned off more strongly, and the subthreshold current is further reduced.

  In inverter circuit IV51, since the line of internal output node a0 is at the level of voltage Vss on main ground line 4, transistor PQ51 is turned on, and transistor NQ51 is turned off. Therefore, output node a1 is charged to Vcc level on main power supply line 1 by transistor PQ51. The source potential of transistor NQ51 is voltage VSL on variable impedance ground line 762, and the potential of its substrate region (body region) is at the level of potential Vss on main ground line 4. Voltage VSL is equal to reference voltage Vref2 and is at a voltage level higher than potential Vss on main ground line 4. Therefore, also in this case, the source potential of the transistor NQ51 effectively rises due to the substrate bias effect, the gate-source thereof is placed in a reverse bias state, and the transistor NQ51 is turned off more strongly. Alternatively, this is equivalent to an increase in the threshold voltage of transistor NQ51. Thus, the sub-threshold current of transistor NQ51 is sufficiently suppressed.

  In inverter circuit IV52, similarly to inverter circuit IV50, transistor NQ52 is turned on, and transistor PQ52 is turned off. Also in this case, the source potential of transistor PQ52 and the potential of the substrate region (body region) are different, and the source potential of transistor PQ52 is effectively reduced due to the substrate bias effect (or the absolute value of the threshold voltage is reduced). And the sub-threshold current in the transistor PQ52 is suppressed.

  The substrate regions (body regions) of p-channel MOS transistors PQ50 to PQ52 are connected to main power supply line 1, and voltage VCL on variable impedance power supply line 760 is set to a voltage level of reference voltage Vref1 lower than this voltage Vcc during a standby cycle. Thus, in addition to suppressing the sub-threshold current by realizing a stronger off state by the gate-source reverse bias voltage by the reference voltage Vref1, the absolute value of the threshold voltage of the MOS transistor is further reduced by the substrate bias effect. By increasing the voltage (effectively reducing the source potentials of the p-channel MOS transistors PQ50 to PQ52), the subthreshold current can be further reduced. Similarly, by connecting the substrate regions (body regions) of n channel MOS transistors NQ50 to NQ52 to main ground line 4, voltage VSL on variable impedance ground line 762 is maintained at the voltage level of reference voltage Vref2 during the standby cycle. By doing so, the reverse bias state of the gate-source voltage of the MOS transistor, which is turned off during the standby cycle, can be further strengthened by the substrate bias effect, and the subthreshold current can be further reduced.

  In the active cycle, signal φ goes high and signal / φ goes low, transistors Q50a and Q50b are turned on, and voltage VCL on variable impedance power supply line 760 is equal to voltage Vcc level on main power supply line 1. And voltage VSL on variable impedance ground line 762 is equal to voltage Vss level on main ground line 4. In this state, the potentials of the source-substrate regions (body regions) of MOS transistors PQ50-PQ52 and NQ50-NQ52 are equalized, the substrate bias effect is eliminated, the threshold voltage is reduced, and inverter circuits IV50-PQ50 are driven at high speed. The IV 52 operates.

  MOS transistors PQ50 to PQ52 and NQ50 to NQ52, which are constituent elements of inverter circuits IV50 to IV52, may be formed in a bulk region (semiconductor substrate or well region). Therefore, these MOS transistors are realized in an SOI (semiconductor-on-insulator) structure.

  FIG. 36 is a diagram showing a schematic sectional structure of inverter circuits IV50-IV52. Since inverter circuits IV50-IV52 have the same cross-sectional structure, FIG. 36 shows only the cross-sectional structure of one inverter circuit.

In FIG. 36, an SOI structure has a semiconductor substrate 765, for example, a silicon substrate, an insulating layer 766, for example, a silicon dioxide film (SiO ₂ film) formed on semiconductor substrate 765, and an SOI structure formed on insulating layer 766. Semiconductor layer 764 to be formed. The transistor element 764 is formed in the semiconductor layer 764. The manufacturing method of the SOI structure is well known, and a semiconductor layer is formed over the insulating layer 766 using a predetermined region of the semiconductor substrate 765 (single-crystal semiconductor substrate) as a seed crystal region. On this semiconductor layer 764, a p-channel impurity region and a p-channel impurity region are formed by an ion implantation method, and an insulating film for element isolation is formed by, for example, a thermal oxidation method. Instead of this method, a method of epitaxially growing the semiconductor layer 764 on the insulating layer 766 may be used.

  P-channel MOS transistor PQ includes a low-concentration n-type impurity region 769p formed in a predetermined region on insulating layer 766, and high-concentration p-type impurity regions 767p and 768p formed on both sides of n-type impurity region 769p. Includes a gate electrode 780p formed over n-type impurity region 769p via a gate insulating film (not shown). The impurity region 767p operates as a source, and is connected to a power supply line (main power supply line or variable impedance power supply line) 783. N-type impurity region 769p forms a body region (substrate region) on which a channel region is formed when transistor PQ is turned on, and is connected to main power supply line 1. Impurity region 768p is connected to output node a.

  N-channel MOS transistor NQ includes high-concentration n-type impurity regions 767n and 768n, low-concentration p-type impurity region 769n formed between these impurity regions 767n and 768n, and a gate insulating film ( (Not shown). Impurity region 767n functions as a source region and is connected to a ground line (main ground line or variable impedance ground line) 782. Impurity region 769n forms a body region (substrate region) in which a channel is formed on the surface of transistor NQ when conductive, and is connected to main ground line 4. Impurity region 768n is connected to output node a. Gate electrodes 780p and 780n are connected to input node c (or an output node of the preceding inverter circuit).

  Each transistor element is separated from each other by insulating films 781a, 781b, and 781c.

  In the SOI structure, the semiconductor layer 764 is separated from the semiconductor substrate 765 by the insulating layer 766, so that no leak current flows from the impurity regions of the transistors NQ and PQ to the semiconductor substrate 765, and current consumption is reduced. Further, impurity regions 769n and 796p serving as body regions are separated by semiconductor layer 765 and insulating layer 766, and there is no junction capacitance between the body region and the semiconductor substrate. Therefore, transistors PQ and NQ only have a junction capacitance in the drain region and the source region, respectively, and a large junction capacitance between the well region and the substrate region existing in the transistor element formed in the ordinary bulk structure is Since it does not exist (this will be described later), the parasitic capacitance of the transistor element decreases. Therefore, the parasitic capacitance of variable impedance power supply line 760 shown in FIG. 34 is reduced, and the current consumption for charging it is reduced. Further, since the parasitic capacitances of variable impedance power supply lines 760 and 762 are small, they operate at high speed in response to voltage fluctuations of variable impedance power supply line 760 and variable impedance ground line 762 during a standby cycle to operate these variable impedance power supply lines. 760 and variable impedance ground line 762 can be maintained at the levels of predetermined voltages Vref1 and Vref2.

  When the transistors Q50a and Q50b are turned on during the transition from the standby cycle to the active cycle, the variable impedance power supply line 760 and the variable impedance ground line 762 have small parasitic capacitance when the transistors Q50a and Q50b are turned on. The variable impedance ground line 762 can be charged and discharged, and the voltages VCL and VSL of the variable impedance power supply line 760 and the variable impedance ground line 762 can be changed at high speed to the voltage Vcc on the main power supply line 1 and the voltage Vss on the main ground line 4, respectively. Can be restored to level. In other words, the recovery time Δt shown in FIG. 35 can be shortened, the operation start timing of the logic circuit can be advanced accordingly, and a high-speed semiconductor device can be realized. In addition, since the parasitic capacitance associated with the output node of each inverter circuit is reduced (because of the SOI structure of the transistor element), the output node can be driven at high speed, and a logic circuit that operates at high speed in an active cycle is realized. be able to.

  In the structure shown in FIG. 34, transistors Q50a and Q50b, Q51a and Q51b, and differential amplifiers 761a and 761b may have an SOI structure.

[Example of change]
FIG. 37 shows a configuration of a modification of the fifth embodiment of the present invention. In the semiconductor device shown in FIG. 37, one conduction node (source) of p-channel MOS transistors PQ50 to PQ52, which are components of inverter circuits IV50 to IV52 forming a logic circuit, is connected to variable impedance power supply line 760, and n One of the conduction nodes (sources) of channel MOS transistors NQ50 to NQ52 is connected to variable impedance ground line 762. Structures other than the above are the same as those shown in FIG. 34. Corresponding portions have the same reference characters allotted, and detailed description thereof will not be repeated.

  In the structure shown in FIG. 37, the sources of p-channel MOS transistors PQ50 to PQ52 are separated from main power supply line 1 during the standby cycle, and similarly, the sources (one conduction node) of n-channel MOS transistors NQ50 to NQ52 are It is separated from the main ground line 4.

  When the input signal IN is at the high level in the standby cycle, the transistor NQ50 is turned on and the transistor PQ50 is turned off. In this state, in transistor PQ50, the source and the substrate region (body region) have different potentials, the absolute value of the threshold voltage increases due to the substrate bias effect, and the subthreshold current is suppressed. On the other hand, the voltage level of the output signal of inverter IV50 is the level of voltage VSL on variable impedance ground line 762. In this case, transistor PQ51 is turned on, and transmits voltage VCL on variable impedance power supply line 760 to its output node a1. On the other hand, the gate and source of the transistor NQ51 have substantially the same voltage level. However, a voltage of the voltage Vss level on the main ground line 4 is applied to the substrate region (body region), and the threshold voltage is increased by the substrate bias effect, so that the sub-threshold current is sufficiently suppressed. Can be. Similarly, also in the next-stage inverter circuit IV52, transistor PQ52 has the same gate and source potentials at the same voltage level, but the voltage of its substrate region (body region) is at the level of voltage Vcc on main power supply line 1, and Due to the substrate bias effect, the absolute value of the threshold voltage increases, and the subthreshold current is suppressed.

  The opposite situation occurs when the input signal IN is at the low level during the standby cycle. Therefore, the sub-threshold current can be effectively suppressed regardless of whether the input signal IN is at the high level or the low level in the standby cycle. Therefore, even in a semiconductor device having a configuration in which the logic level of the input signal IN during the standby cycle cannot be predicted, the subthreshold current can be effectively suppressed, and the current consumption can be reduced accordingly.

  As described above, according to the fifth embodiment of the present invention, a transistor as a component of a logic circuit is formed in an SOI structure, and its substrate region (body region) is connected to a main power supply line or a main ground line. Therefore, in the standby cycle, the absolute value of the threshold voltage of the MOS transistor, which is a component of the logic circuit, can be made larger to reliably suppress the subthreshold current. Also, since the junction capacitance of the transistor is reduced and the parasitic capacitance of the variable impedance power supply line and the variable impedance ground line is reduced, the potential recovery of the variable impedance power supply line and the variable impedance ground line at the transition from the standby cycle to the active cycle can be performed at high speed. Can be performed.

[Example 6]
FIG. 38 is a diagram showing a configuration of a main part of a semiconductor device according to a sixth embodiment of the present invention. In the configuration shown in FIG. 38, switching p-channel conductive in response to control signal / φ between main power supply line 1 transmitting power supply voltage Vcc from first power supply node 20 and variable impedance power supply line 770 is provided. A channel MOS transistor Q60a is provided. A bias voltage VBP whose voltage level is changed according to the operation mode is applied to the substrate region (or body region) of MOS transistor Q60a. Control signal / φ goes high during a standby cycle of the semiconductor device and goes low during an active cycle. Bias voltage VBP is set to power supply voltage Vcc level during an active cycle, and is set to a voltage Vpp level higher than power supply voltage Vcc during a standby cycle.

  Between main ground line 4 transmitting ground voltage Vss from second power supply node 30 and variable impedance ground line 772, switching n-channel MOS transistor Q60b that conducts in response to control signal φ is provided. The control signal φ is a signal complementary to the control signal / φ, and goes low in the standby cycle and goes high in the active cycle. To substrate region (or body region) of switching n-channel MOS transistor Q60b, bias voltage VBN whose value is changed in accordance with an operation cycle is applied. This bias voltage VBN is set to a negative voltage Vbb level lower than the ground voltage Vss during the standby cycle, and set to the ground voltage Vss level during the active cycle.

  As a logic circuit, three-stage CMOS inverter circuits IV60, IV61 and IV62 are shown as an example. Inverter circuit IV60 has one conduction node (source) connected to variable impedance power supply line 770, its gate connected to receive input signal IN, and the other conduction node (drain) connected to internal output node a3. P-channel MOS transistor Q60p, one n-channel MOS transistor having one conduction node connected to variable impedance ground line 772, the other conduction node connected to internal output node a3, and a gate connected to receive input signal IN Includes transistor Q60n.

  Inverter circuit IV61 has a gate connected to internal output node a3, one conduction node connected to variable impedance power supply line 770, and the other conduction node connected to internal output node a4, p-channel MOS transistor Q61p, An n channel MOS transistor Q61n having its gate connected to internal output node a3, one conductive node connected to variable impedance ground line 772, and the other conductive node connected to internal output node a4. Inverter circuit IV62 has a gate connected to internal output node a4, one conduction node connected to variable impedance power supply line 770, and the other conduction node connected to internal output node a5, p-channel MOS transistor Q62p, An n channel MOS transistor Q62n having its gate connected to internal output node a4, one conduction node connected to variable impedance ground line 772, and the other conduction node connected to internal output node a5. Output signal OUT is output from internal output node a5.

  In other words, in the configuration shown in FIG. 38, inverter circuits IV60 to IV62 operate using voltage VCL on variable impedance power supply line 770 and voltage VSL on variable impedance ground line 772 as operating power supply voltages.

  The threshold voltages of transistors Q60p to Q62p are sufficiently increased (the absolute value of the threshold voltage is sufficiently reduced), and the threshold voltages of n-channel MOS transistors Q60n to Q62n are sufficiently reduced (threshold). The absolute value of the voltage is reduced). Thus, high-speed operation and low current consumption under a low power supply voltage are realized. Next, the operation of the semiconductor device shown in FIG. 38 will be described with reference to an operation waveform diagram of FIG.

  In the standby cycle, signal φ is set to the low level and signal / φ is set to the high level, and both transistors Q60a and Q60b are turned off. Bias voltage VBP is set to a high voltage Vpp level higher than power supply voltage Vcc, and bias voltage VBN is set to a negative voltage Vbb level lower than ground voltage Vss. Therefore, the transistors Q60a and Q60b have a higher absolute value of the threshold voltage due to the substrate bias effect, and are set to a stronger off state. Transistors Q60p to Q62p and Q60n to Q62n, which are components of inverter circuits IV60 to IV62, are low-threshold (the absolute value of the threshold voltage is small) transistors, and are turned on or off according to the voltage level of input signal IN. Is set to At this time, transistors Q60p to Q62p and Q60n to Q62n are low threshold transistors, and a subthreshold current flows between variable impedance power supply line 770 and variable impedance ground line 772. However, transistor Q60a between main power supply line 1 and variable impedance power supply line 770 is in a stronger off state, and the leakage current between main power supply line 1 and variable impedance power supply line 770 is sufficiently suppressed. Similarly, transistor Q60b is also in a stronger off state, and the leakage current between main ground line 4 and variable impedance ground line 772 is sufficiently suppressed. Therefore, leakage current flowing from main power supply line 1 to main ground line 4 is sufficiently suppressed, and current consumption during a standby cycle is reduced.

  When the active cycle starts, signal / RAS falls from high level to low level. In response, control signal / φ goes low, signal φ goes high, and transistors Q60a and Q60b are turned on. At this time, bias voltage VBP is set to power supply voltage Vcc level, and bias voltage VBN is set to ground voltage Vss level. As a result, transistors Q60a and Q60b have their source and substrate regions at the same voltage level, have no substrate bias effect, and are set to a low threshold state (a state in which the absolute value of the threshold voltage is small). Thus, the variable impedance power supply line 770 is supplied with current from the main power supply line 1 at high speed, and the voltage VCL returns to the power supply voltage Vcc level at high speed. Similarly, voltage VSL on variable impedance ground line 772 is discharged to main ground line 4 via transistor Q60b at high speed, and voltage VSL returns to ground voltage Vss level at high speed. Thereby, at the time of transition from the standby cycle to the active cycle, voltages VCL and VSL can be returned to power supply voltage Vcc and ground voltage Vss levels at high speed, and the operation start timing of the logic circuits (inverter circuits IV60 to IV62) is advanced. be able to.

  Inverter circuits IV60 to IV62 have transistors Q60p to Q62p and Q60n to Q62n, which are low threshold transistors, operate at high speed in accordance with input signal IN given in an active cycle, and generate output signal OUT. .

  As described above, transistors Q60a and Q60b are set to a high resistance state (stronger off state) during a standby cycle, and their threshold voltages are set to a low resistance state (low threshold state) during an active cycle. By changing, the leak current (subthreshold current) in the standby cycle is sufficiently suppressed, and the voltage levels of variable impedance power supply line 770 and variable impedance ground line 772 are recovered at a high speed at the transition from the standby cycle to the active cycle. Accordingly, a semiconductor device which operates at high speed and with low current consumption can be realized.

  FIG. 40 is a diagram showing an example of a configuration for generating the bias voltage VBP. In FIG. 40, a bias voltage generating unit generates a control signal / φ in response to a row address strobe signal / RAS, and a control signal / φ output from clock signal generator 785 is inverted. Further, it includes a level conversion section 780a for converting the high level to the high voltage Vpp level, and a selection section 780b for outputting one of the high voltage Vpp and the power supply voltage Vcc as the bias voltage VBP according to the output signal of the level conversion section 780a. Clock signal generator 785 is included in control circuit 110 shown in FIG. High voltage Vpp is generated from Vpp generator 256 shown in FIG.

  Level conversion section 780a includes an inverter 786 for inverting control signal / φ, a p-channel MOS transistor QT0 provided between a high voltage Vpp supply node and node a10, and conducting in response to the potential of node a11, A p-channel MOS transistor QT1 provided between the Vpp supply node and the node a11 and turned on in response to the potential on the node a10, and provided between the node a10 and the ground voltage Vss supply node. An n channel MOS transistor QT2 which is turned on in response to the current and an n channel MOS transistor QT3 which is provided between node a11 and the ground voltage Vss supply node and is turned on in response to an output signal of inverter circuit 786 is included.

  Selection section 780b is provided between high voltage Vpp supply node and node a12, and is turned on in response to a signal potential on node a10 of level conversion section 780a, and power supply voltage Vcc supply node and node and n-channel MOS transistor QT5 which is provided between a12 and conducts in response to the potential on node a10 of level converter 780a. The bias voltage VBP is output from the node a12. Next, the operation will be briefly described.

  In response to row address strobe signal / RAS, clock signal generator 785 generates a control signal / φ that goes high during a standby cycle and goes low during an active cycle. In the standby cycle, transistor QT2 is turned on, and transistor QT3 is turned off. Node a10 is discharged to ground voltage Vss level via transistor QT2, transistor QT1 is turned on, and the voltage level on node a11 is charged to high voltage Vpp level. The transistor QT0 is turned off by the high voltage Vpp on the node a11. Therefore, a signal at the level of ground voltage Vss is output from node a10. In this state, in the selecting section 780b, the transistor QT4 is turned on, the transistor QT5 is turned off, and the high voltage Vpp is output as the bias voltage VBP.

  In the active cycle, signal / φ is at the low level, transistor QT2 is turned off, transistor QT3 is turned on, and node all is discharged to the level of ground voltage Vss. Thereby, transistor QT0 is turned on, and node a10 is charged to the high voltage Vpp level. In selection section 780b, transistor QT4 is turned off, transistor QT5 is turned on, and bias voltage VBP at the level of power supply voltage Vcc is output from node a12.

  Signal / φ is shown as the same signal as the signal applied to the gate of transistor Q60a shown in FIG. However, the switching timing of the bias voltage VBP may be different from the on / off timing of the transistor Q60a. At the time of transition to the standby cycle, the transistor Q60a is turned off after the bias voltage VBP shifts to the high voltage Vpp level, and at the time of the active cycle, the transistor Q60a is turned on after the bias voltage VBP shifts to the power supply voltage Vcc level. May be used. Further, the voltage level of bias voltage VBP during the standby cycle may be set to a voltage level different from the high voltage Vpp level used for word line driving or the like. In the standby cycle, any voltage level can be used as long as the absolute value of the threshold voltage of transistor Q60a is sufficiently large.

  FIG. 41 shows a structure for generating bias voltage VBN shown in FIG. 41, a bias voltage generator includes a clock signal generator 795 that generates a control signal φ in response to a row address strobe signal / RAS, and a low level of a ground voltage Vss level of a control signal φ to a negative voltage Vbb level. It includes a level conversion section 790a for converting to a low level, and a selection section 790b for outputting one of negative voltage Vbb and ground voltage Vss from output node a22 as bias voltage VBN according to an output signal of level conversion section 790a. Clock signal generator 795 is included in control circuit 110 shown in FIG. Control signal φ is at a low level during a standby cycle and at a high level during an active cycle.

  Level converter 790a is connected between power supply voltage Vcc supply node and node a20 and is turned on in response to control signal φ, and transmits power supply voltage Vcc to node a20. p-channel MOS transistor QT10, p-channel MOS transistor QT11 connected between power supply voltage Vcc supply node and node a21, conducting in response to an output signal of inverter circuit 796, and transmitting power supply voltage Vcc to node a21; An n-channel MOS transistor QT12 connected between node a20 and a negative voltage Vbb supply node, rendered conductive in response to the potential on node a21, and discharging node a20 to the negative voltage Vbb level; node a21 and negative voltage Vbb Connected to the supply node, and conducts in response to the potential on node a20. And an n-channel MOS transistor QT13 discharging node a21 to the level of negative voltage Vbb. Inverter circuit 796 outputs a signal having an amplitude of power supply voltage Vcc and ground voltage Vss level.

  Selector 790b is connected between a negative voltage Vbb supply node and output node a22, and is an n-channel MOS transistor that conducts in response to the potential on node a21 of level converter 790a to transmit negative voltage Vbb to node a22. QT14, and a p-channel MOS transistor QT15 connected between ground voltage Vss supply node and node a22 to conduct in response to the potential on node a21 of level converter 790a to transmit ground voltage Vss to node a22. . The bias voltage VBN is output from the node a22. Next, the operation will be described.

  In the standby cycle, control signal / φ is at the high level, the output signal of inverter circuit 796 is at the low level, transistor QT10 is off, and transistor QT11 is on. Node a21 is charged to power supply voltage Vcc level by transistor QT11, and transistor QT12 is turned on. As a result, the node a20 is discharged to the level of the negative voltage Vbb, and the transistor QT13 is turned off. Thereby, node a21 is maintained at power supply voltage Vcc level by transistor QT11. Transistor QT14 is turned on and transistor QT15 is turned off by the signal of power supply voltage Vcc level from level conversion section 790a. Thereby, negative voltage Vbb is transmitted to node a22 through transistor QT14, and bias voltage VBN at the level of negative voltage Vbb is output.

  In the active cycle, control signal / φ goes low, transistor QT10 is turned on, and transistor QT11 is turned off. In this state, node a20 is charged to power supply voltage Vcc level by transistor QT10, transistor QT13 is turned on, and node a21 is discharged to negative voltage Vbb level. When the voltage level of node a21 decreases to the level of negative voltage Vbb, transistor QT12 is turned off. In response to a signal at the negative voltage Vbb level from level conversion section 790a, in selection section 790b, transistor QT14 is turned off and transistor QT15 is turned on. As a result, the ground voltage Vss is transmitted to the node a22, and the bias voltage VBN at the level of the ground voltage Vss is output.

  As described above, according to the sixth embodiment of the present invention, the transistor between the main power supply line and the variable impedance power supply line and the transistor between the main ground line and the variable impedance ground line are connected during the standby cycle. Because it is equivalently set to the high resistance state (state where the absolute value of the threshold voltage is large), and is set to the equivalent low resistance state (state where the absolute value of the threshold voltage is small) during the active cycle. It is possible to realize a semiconductor device which can suppress a leak current in a standby cycle and recover voltages of a variable impedance power supply line and a variable impedance ground line at a high speed at a transition to an active cycle, and operate at high speed with low current consumption. it can.

[Example 7]
FIG. 42 schematically shows a sectional structure of switching p-channel MOS transistor Q60a shown in FIG. In FIG. 42, a transistor Q60a has a bulk structure and is formed in an n-type well region 801 formed on the surface of a semiconductor substrate (semiconductor layer or well region) 800. Transistor Q60a includes p-type high-concentration impurity regions 802 and 803 formed on the surface of well region 801 with a gap therebetween, and a region between impurity regions 802 and 803 via a gate insulating film (not shown). A gate electrode layer 804 to be formed and a high-concentration n-type impurity region 805 for applying a bias voltage VBP to the well region 801 are included. Power supply voltage Vcc is applied to impurity region 802 via main power supply line 1. Impurity region 803 is connected to variable impedance power supply line 770. Control signal / φ is applied to gate electrode 804.

  Switching n-channel MOS transistor Q60b has a similar configuration. However, the conductivity type of the impurity region and the conductivity type of the well region are reversed. As shown in FIG. 42, well region 801 has a size including at least impurity regions 802, 803, and 805 for forming transistor element Q60a. Therefore, in this case, a large junction capacitance Cwell exists between the substrate 800 and the well 801. Therefore, the junction capacitance of transistor Q60a increases, the voltage of well region 801 cannot be changed at high speed by bias voltage VBP, and a large current consumption is required to maintain well region 801 at a predetermined voltage level. Problem arises. However, there is an advantage that the bias voltage VBP can be stably maintained.

  FIG. 43 shows another structure of p-channel MOS transistor Q60a shown in FIG. As shown in FIG. 43, the transistor Q60a has an SOI structure. That is, transistor Q60a is formed in a region defined by insulating films 816a and 816b on insulating layer 811 formed on semiconductor substrate 810.

  Transistor Q60a has high-concentration p-type impurity regions 812 and 814 formed adjacent to insulating films 816a and 816b, low-concentration n-type impurity region 813 formed between these impurity regions 812 and 814, A gate electrode 815 is formed over the region 813 with a gate insulating film (not shown) interposed therebetween. This impurity region 813 functions as a body region where a channel is formed when transistor Q60a is turned on. Bias voltage VBP is applied to impurity region 813. Impurity region 812 is connected to main power supply line 1 and receives power supply voltage Vcc. Impurity region 814 is connected to variable impedance power supply line 770. Control signal / φ is applied to gate electrode layer 815.

  In the structure of transistor Q60a shown in FIG. 43, insulating layer 811 is formed below impurity region 813, and semiconductor substrate 810 and impurity region 813 are separated. Therefore, there is no large junction capacitance Cwell (see FIG. 42) generated when a well structure is used, and the capacitance of impurity region 813 is small. Further, impurity region 813 is only formed corresponding to the channel region of transistor Q60a, and its size is sufficiently smaller than well region 801 shown in FIG. Therefore, when bias voltage VBP is applied to impurity region 813, the voltage level of impurity region 813 can be changed at a high speed, and the voltage level of impurity region 813 can be changed with low current consumption by the small capacitance. it can. That is, by applying the transistor having the SOI structure to the switching p-channel MOS transistor Q60a, the voltage level of the variable impedance power supply line can be changed at a high speed, and the substrate bias voltage of the transistor element can be rapidly reduced with low current consumption. It can be changed.

  Note that n-channel MOS transistor Q60b shown in FIG. 38 also has an SOI structure, similarly to the structure shown in FIG. In this case, the cross-sectional structure of transistor Q60b can be obtained by simply reversing the conductivity type shown in FIG.

  As described above, according to the seventh embodiment of the present invention, a transistor having an SOI structure is used as a transistor for connecting the main power supply line to the variable impedance power supply line and a transistor for connecting the variable impedance ground line to the main ground line. As a result, the voltage levels of the variable impedance power supply line and the variable impedance ground line can be changed at high speed, and the bias voltage of these transistors can be changed at low current consumption and at high speed. Is reduced.

Example 8
FIG. 44 is a diagram showing a configuration of a main part of a semiconductor device according to an eighth embodiment of the present invention. In the configuration shown in FIG. 44, conduction is provided between main power supply line 1 and variable impedance power supply line 820 in response to control signal / φ, and when conductive, main power supply line 1 and variable impedance power supply line 820 are electrically connected. And a voltage regulator 824 for adjusting the voltage level on variable impedance power supply line 820 during the standby cycle. Voltage regulator 824 may be formed of a high-resistance resistor, or may be formed of the differential amplifier described above with reference to FIG. 34 and a transistor driven by an output signal of the differential amplifier. Other configurations may be used.

  An n-channel MOS transistor Q60b electrically connects between main ground line 4 and variable impedance ground line 822 in response to control signal φ and electrically connects variable impedance ground line 822 and main ground line 4 when conductive. And a voltage regulator 826 for adjusting the voltage level of variable impedance ground line 822 during the standby cycle. The voltage regulator 826 has the same configuration as the voltage regulator 824.

  Bias voltages VBP and VBN are applied to substrate regions (body regions) of transistors Q60a and Q60b, respectively. The transistors Q60a and Q60b have the same configuration as those in the fifth to seventh embodiments, and realize the same functions.

  FIG. 44 shows three-stage CMOS inverter circuits IV70, IV71, and IV72 as an example of the logic circuit. The logic level of input signal IN is set to a high level in a standby cycle. According to the logic level of the standby cycle of input signal IN, the power supply line / ground line connected to the MOS transistors, which are the components of inverter circuits IV70 to IV72, are alternately changed. In inverter circuit IV70, one conduction node (source) of p channel MOS transistor Q70p is connected to variable impedance power supply line 820, and one conduction node (source) of n channel MOS transistor Q70n is connected to main ground line 4. In inverter circuit IV71, one conduction node of p channel MOS transistor Q71p is connected to main power supply line 1, and one conduction node of n channel MOS transistor Q71n is connected to variable impedance ground line 822. In inverter circuit IV72, one conduction node of p-channel MOS transistor Q72p is connected to variable impedance power supply line 820, and one conduction node of n-channel MOS transistor Q72n is connected to main ground line 4.

  In such a configuration in which the connection to the power supply line / ground line to which the MOS transistor is connected is alternately switched in accordance with the logic level of the standby cycle of the input signal, the transistors Q60a and Q60b are connected to the standby cycle. The sub-threshold current is sufficiently set by setting the high threshold state (state where the absolute value of the threshold voltage is large) at the low threshold state (state where the threshold voltage is small) in the active cycle. And the potentials of the variable impedance power supply line 820 and the variable impedance ground line 822 at the time of transition from the standby cycle to the active cycle can be recovered at high speed. When input signal IN is at a low level in the standby cycle, inverter circuit IV71 is used as a first-stage circuit.

  As described above, according to the eighth embodiment, when the logic level of the input signal in the standby cycle can be predicted, the power supply line / ground line and the variable impedance are set in accordance with the logic level of the input signal in the standby cycle. Also in a semiconductor device for switching connection between a power supply line / variable impedance ground line, a transistor provided between the main power supply line / main ground line and the variable impedance power supply line / variable impedance ground line is set to a high threshold state during a standby cycle. Since the low threshold state is set in the active cycle, a semiconductor device that operates at high speed with low current consumption can be realized.

[Example 9]
FIG. 45 is a diagram showing a configuration of a main part of a semiconductor device according to a ninth embodiment of the present invention. The semiconductor device shown in FIG. 45 is realized by combining the semiconductor device shown in FIG. 34 and the semiconductor device shown in FIG. As logic circuits, three-stage CMOS inverter circuits IV80, IV81, and IV82 are illustratively shown. In these inverter circuits IV80 to IV82, the substrate regions (body regions) of p channel MOS transistors Q80p, Q81p and Q82p are connected to main power supply line 1, and n channel MOS transistors Q80n, Q81n and Q82n are A region (body region) is connected to main ground line 4. These transistors Q80p to Q82p and Q80n to Q82n are constituted by transistors having an SOI structure. The other configuration is the same as that shown in FIG. 44, and the corresponding portions are denoted by the same reference numerals. By using transistors having an SOI structure as components, a semiconductor device which operates at high speed with low current consumption can be realized.

  In the configuration shown in FIG. 45, when the logical level of input signal IN in the standby cycle is unpredictable, one of conduction nodes (sources) of p-channel MOS transistors Q80p to Q82p in inverter circuits IV80 to IV82 has a variable impedance. One conduction node (source) of n-channel MOS transistors Q80n to Q82n is connected to variable impedance ground line 822. Also in this case, a similar effect can be achieved.

  As described above, according to the ninth embodiment, since the transistors having the SOI structure are used for all the components, the power consumption is further reduced in addition to the effects achieved by the fifth to eighth embodiments. be able to. Further, in this case, the parasitic capacitance of variable impedance power supply line 820 and variable impedance ground line 822 is reduced, and higher-speed voltage recovery can be realized.

[Example 10]
FIG. 46 is a diagram showing a configuration of a main part of a semiconductor memory device according to a tenth embodiment of the present invention. A p-channel MOS transistor Q90a that conducts in response to an operation cycle defining signal / φ is provided between main power supply line 1 and variable impedance power supply line 850, and an operation cycle is provided between main ground line 4 and variable impedance ground line 852. An n-channel MOS transistor Q90b which conducts in response to the prescribed signal φ is arranged. Operation cycle defining signal φ corresponds to internal row address strobe signal RAS shown in FIG. 30, and is activated to a high level when a memory cell selecting operation (normal operation or refresh operation) is performed. The operation cycle definition signal / φ is a signal complementary to the operation cycle definition signal φ.

  As an internal circuit, two-stage inverters IV90 and IV91 are shown as an example. Inverter IV90 receives a low level (L) signal during a standby cycle, and inverter IV91 receiving an output signal of inverter IV90 receives a high level (H) signal during a standby cycle. The internal configuration of inverters IV90 and IV91 will be described later, but is formed of a low threshold MOS transistor having a small absolute value of the threshold voltage. Inverter IV90 operates using power supply voltage Vcc on main power supply line 1 and voltage VSL on variable impedance ground line 852 as both operation power supply voltages. Inverter IV91 operates using voltage VCL on variable impedance power supply line 850 and ground voltage Vss on main ground line 4 as both operation power supply voltages. The source of the MOS transistor turned off in the standby cycle is connected to variable impedance power supply line 850 or variable impedance ground line 852.

  For the main power supply line 1 and the variable impedance power supply line 850, a Vref1 generation circuit 860 for generating a reference voltage Vref1 having a level close to the power supply voltage Vcc, and a voltage VCL on the variable impedance power supply line 850 and a Vref1 generation circuit 860 A comparison circuit 854 for comparing the output reference voltage Vref1, a p-channel MOS transistor Q95a connected between the main power supply line 1 and the variable impedance power supply line 850, and an output signal of the comparison circuit 854 in the normal operation mode. A switch circuit SWa for transmitting the signal to the gate (control electrode node) of transistor Q95a and connecting the gate of MOS transistor Q95a to main power supply line 1 in the data holding mode (sleep mode) is provided. Comparing circuit 854 is formed of, for example, a differential amplifier circuit, and receives voltage VCL on variable impedance power supply line 850 at its positive input, receives reference voltage Vref1 at its negative input, and differentially outputs these voltages VCL and Vref1. To amplify. The output signal of the comparison circuit 854 goes high when the voltage VCL is higher than the reference voltage Vref1, and goes low when the voltage VCL is lower than the reference voltage Vref1. The voltage level of the signal output from comparison circuit 854 is proportional to the difference between voltage VCL and reference voltage Vref1.

  A Vref2 generation circuit 862 that outputs a reference voltage Vref2 close to the ground voltage Vss with respect to the main ground line 4 and the variable impedance ground line 852, and a voltage VSL on the variable impedance ground line 852 and a reference voltage that the Vref2 generation circuit 862 outputs Comparison circuit 856 for comparing Vref2, n-channel MOS transistor Q95b connected between variable impedance ground line 852 and main ground line 4, and an output signal of comparison circuit 856 in the normal operation mode transmitted to the gate of MOS transistor Q95b. In the sleep mode, a switch circuit SWb for connecting the gate of MOS transistor Q95b to main ground line 4 is provided. The comparison circuit 856 is constituted by a differential amplifier circuit, and receives the voltage VSL on the variable impedance ground line 852 at its positive input and the reference voltage Vref2 at its negative input. Comparison circuit 856 outputs a signal proportional to the difference between voltage VSL and reference voltage Vref2.

  The normal operation cycle includes a standby cycle and an active cycle as shown in FIG. 30, and the sleep mode (data holding mode) includes a CBR refresh mode in which only refresh is internally performed and a self refresh mode. Next, the operation of the circuit shown in FIG. 46 will be described with reference to an operation waveform diagram of FIG. 47.

  The normal operation mode (normal mode) in which external access is possible includes a standby cycle for waiting for external access and an active cycle in which external access is actually performed and internal operation is executed (see FIG. 30). In the standby cycle, data holding mode designating signal / Sleep designating the data holding operation is at an inactive high level, and operation cycle defining signal / φ is at an inactive high level. In this state, switch circuit SWa transmits the output signal of comparison circuit 854 to the gate of MOS transistor Q95a, and switch circuit SWb transmits the output signal of comparison circuit 856 to the gate of MOS transistor Q95b. MOS transistors Q90a and Q90b are both off. Therefore, the resistance value of MOS transistor Q95a is adjusted in accordance with the output signal of comparison circuit 854, and voltage VCL on variable impedance power supply line 850 is set to the voltage of reference voltage Vref1, similarly to the operation described above with reference to FIG. Maintained at the level. On the other hand, voltage VSL on variable impedance ground line 852 is maintained at the voltage level of reference voltage Vref2 by comparison circuit 856 and MOS transistor Q95b.

  Inverter IV90 receives the low level signal, the n-channel MOS transistor as a component thereof is turned off, and the gate and source thereof are in a reverse bias state, and the subthreshold current is suppressed. In inverter IV91, the gate-source of the p-channel MOS transistor, which is a component of inverter IV91, is reverse-biased, turned off deeper, and the sub-threshold current is similarly suppressed.

  When an active cycle is entered, operation cycle defining signal / φ is set to an active low level, MOS transistors Q90a and Q90b are both turned on, variable impedance power supply line 850 is electrically connected to main power supply line 1, and Variable impedance ground line 852 is electrically connected to main ground line 4. In this state, voltage VCL is at power supply voltage Vcc level on main power supply line 1 and voltage VSL is at voltage Vss level on main ground line 4. The output signal of comparison circuit 854 is at a high level, MOS transistor Q95a is off, the output signal of comparison circuit 856 is at a low level, and MOS transistor Q95b is off. MOS transistors Q90a and Q90b are set such that, for example, gate width W is sufficiently large, on-resistance is sufficiently small, and large current driving capability is provided. Therefore, when shifting from the standby cycle to the active cycle, voltage VCL on variable impedance power supply line 850 and voltage VSL on variable impedance ground line 852 return to power supply voltage Vcc and ground voltage Vss at high speed. Thereby, inverters IV90 and IV91, which are internal circuits, operate at high speed following changes in their input signals. In particular, inverters IV90 and IV91 have low-threshold transistors as constituent elements, and high-speed operation is realized. You.

  In the data holding mode (sleep mode), switch circuit SWa connects main power supply line 1 to the gate of MOS transistor Q95a, and ground circuit SWb connects main ground line 4 to the gate of MOS transistor Q95b. Thereby, MOS transistors Q95a and Q95b have the same gate and source potential, and are turned off. The input signals of inverters IV90 and IV91 are set to the same voltage level as that of the standby cycle. In this state, voltage VCL on variable impedance power supply line 850 is maintained at a voltage level at which the leak current flowing through MOS transistors Q90a and Q95a balances the leak current flowing through inverters IV90 and IV91. At this time, if the gate width W of MOS transistor Q95a, for example, is made sufficiently smaller than that of MOS transistor Q90a, the leak current flowing through MOS transistor Q95a can be almost ignored. In this case, voltage VCL is , And the leakage current flowing through MOS transistor Q90a and the leakage current flowing through inverters IV90 and IV91 are maintained at a voltage level that is balanced.

  Similarly, voltage VSL on variable impedance ground line 852 rises to a voltage level at which the leak current flowing through MOS transistors Q90b and Q95b balances the leak current flowing through inverters IV90 and IV91. At this time, if the gate width of MOS transistor Q95b is made sufficiently smaller than the gate width of MOS transistor Q90b, the leakage current flowing through MOS transistor Q95b can be almost ignored. In FIG. 47, in the data holding mode, operation cycle defining signal / φ is shown to be maintained at a high level in an inactive state. However, in this data holding mode, as shown in FIG. 30, the refresh operation is performed at predetermined time intervals. When the refresh operation is performed in the data holding mode, the operation cycle defining signal / φ is set to the active low level, and the voltage VCL on the variable impedance power supply line 850 and the voltage VSL on the variable impedance ground line 852 are each set to the power supply voltage. Vcc and the level of the ground voltage Vss are restored. When the refresh operation is performed, no external access is performed. Therefore, even if there is a time for recovery of voltage VCL on variable impedance power supply line 850 and voltage VSL on variable impedance ground line 852, there is no access time. Is not relevant, so there is no particular problem. By simply delaying the refresh start timing and performing the refresh after the voltages VCL and VSL have been restored to the power supply voltage Vcc and the ground voltage Vss, respectively, the memory cell data can be reliably refreshed.

  At the time of transition from the data holding mode to the normal operation mode (normal mode), reset is performed to recover voltage VCL on variable impedance power supply line 850 and voltage VSL on variable impedance ground line 852 to reference voltages Vref1 and Vref2, respectively. The cycle runs. In the reset cycle, a standby cycle and an active cycle are repeatedly performed a predetermined number of times. FIG. 47 shows, as an example, a sequence in which a standby cycle, an active cycle, and a standby cycle are performed.

  When the data holding mode is completed, in the standby cycle of the reset cycle, switch circuit SWa transmits the output signal of comparison circuit 854 to the gate of MOS transistor Q95a, and switch circuit SWb transmits the output signal of comparison circuit 856 to MOS transistor Q95b. Transfer to the gate. Thereby, voltage VCL rises to the voltage level of reference voltage Vref1 by a control operation of feedback circuit of comparison circuit 854 and MOS transistor Q95a, while voltage VSL on variable impedance ground line 852 increases by comparison circuit 856 and MOS transistor Q95b. , The voltage level is restored to the voltage level of the reference voltage Vref2.

  In the reset cycle, an access cycle is executed after execution of the standby cycle. Thereby, MOS transistors Q90a and Q90b are turned on, and voltages VCL and VSL change to the levels of power supply voltage Vcc and ground voltage Vss, respectively. After the completion of the active cycle, a standby cycle is executed to prepare for the next normal mode. In this standby cycle, voltages VCL and VSL shift to reference voltages Vref1 and Vref2, respectively. The reason why the active cycle is executed in the reset cycle is to recover the voltages VCL and VSL changed in the data holding mode to the voltage levels of the predetermined reference voltages Vref1 and Vref2 at high speed. That is, the voltage recovery operation by the MOS transistors Q95a and Q95b having the reduced current driving capability is accelerated by turning on the MOS transistors Q90a and Q90b, thereby shortening the time required for the reset cycle. In the normal operation mode (normal mode), an active cycle is executed again according to an external control signal, and an access operation to a memory cell is executed. When the active cycle is completed, a standby cycle is executed.

  As described above, in the data holding mode (sleep mode), MOS transistors Q95a and Q95b are turned off more deeply than in the standby cycle, so that the leakage current (sub-current) flowing through transistors Q95a and Q95b in the data holding mode is reduced. (Threshold current) can be made sufficiently smaller than that in the standby cycle, and lower current consumption can be realized. In particular, when a data retention mode is executed using a battery as a power source in a battery-driven personal computer or the like, battery life can be extended by reducing current consumption in the data retention mode.

  Although not clearly shown in FIG. 46, comparison circuits 854 and 856 operate using power supply voltage Vcc and ground voltage Vss as both operation power supply voltages.

  FIG. 48 is a diagram showing an example of the configuration of the switch circuits SWa and SWb shown in FIG. In FIG. 48, switch circuit SWa is connected between main power supply line 1 and gate node nda of MOS transistor Q95a, and is a CMOS transmission gate 871 that is conductive when data retention mode designating signal (sleep mode designating signal) / Sleep is activated. And a CMOS transmission gate 872 connected between the output of comparison circuit 854 and gate node nda of MOS transistor Q95a, which is conductive when data holding mode designating signal Sleep is inactive.

  The data holding mode designating signal / Sleep is set to an active low level in the sleep mode (during the data holding mode), while the signal Sleep is set to an active high level in the data holding mode (the sleep mode). In the normal operation mode, signal Sleep is at a low level and signal / Sleep is at a high level. Therefore, in data holding mode, CMOS transmission gate 871 is turned on and CMOS transmission gate 872 is turned off (cut off), and gate node nda of MOS transistor Q95a receives voltage Vcc on main power supply line 1. . In the normal operation mode, signal Sleep is at a low level, signal / Sleep is at a high level, CMOS transmission gate 872 is on, and CMOS transmission gate 871 is off. In this case, the output signal from comparison circuit 854 is transmitted to gate node nda of MOS transistor Q95a.

  The switch circuit SWb is connected between the gate node ndb of the MOS transistor Q95b and the main ground line 4, and is turned on when the data holding mode designating signal / Sleep is activated. MOS transistor Q95b includes a CMOS transmission gate 874 connected between gate node nda of MOS transistor Q95b, which is conductive when signals Sleep and / Sleep are inactive. The operation of the CMOS transmission gate 873 is the same as the operation of the CMOS transmission gate 871, and the operation of the CMOS transmission gate 874 is the same as the operation of the CMOS transmission gate 872. Therefore, in the data holding mode, gate node ndb of MOS transistor Q95b is coupled to main ground line 4 via CMOS transmission gate 873. In the normal operation mode, gate node ndb of MOS transistor Q95b is coupled to the output of comparison circuit 856. Data holding mode designating signals Sleep and / Sleep are generated from sleep mode detecting circuit 870. Sleep mode detecting circuit 870 corresponds to holding mode detecting circuit 654 shown in FIG. 29, and has control signal ext. RAS and ext. In accordance with CAS, it is detected whether or not the data holding mode is designated, and when the data holding mode is designated, signals Sleep and / Sleep are activated.

  As described above, by configuring switch circuits SWa and SWb with CMOS transmission gates, even when signals Sleep and / Sleep from sleep mode detection circuit 870 have the amplitudes of power supply voltage Vcc and ground voltage Vss. The switch circuits SWa and SWb can transmit a given signal without any signal transmission loss.

  48. Instead of detecting the CBR condition, sleep mode detecting circuit 870 shown in FIG. 48 performs other conditions, for example, WCBR (write enable signal / WE and column address strobe signal / CAS fall on row address strobe signal / RAS). A configuration that detects that the sleep mode has been designated in accordance with an address signal given to a specific address signal input terminal in addition to the state in which the sleep mode has been set to a low level earlier than that may be used.

  This sleep mode detection circuit 870 operates using power supply voltage Vcc and ground voltage Vss as both operation power supply voltages. In a semiconductor memory device, for example, a negative voltage Vbb generator and a high voltage Vpp generator are provided as shown in FIG. When sleep mode detection circuit 870 has a configuration for generating such high voltage Vpp and negative voltage Vbb, a transfer composed of one MOS transistor may be used instead of the CMOS transmission gate.

  Further, a configuration is used in which high voltage Vpp is applied to gate node nda of MOS transistor Q95a in the data holding mode, and negative voltage Vbb is applied to gate node ndb of MOS transistor Q95b in the data holding mode. May be done. MOS transistors Q95a and Q95b can be turned off more strongly in the data holding mode, and the subthreshold current can be further reduced.

  As described above, according to the tenth embodiment of the present invention, the voltage on the sub power supply line (variable impedance power supply line or variable impedance ground line) is changed to the reference voltage (Vref1 or Vref2) according to the output signal of the comparison circuit during the standby cycle. ), The MOS transistor is set to an off state of a high resistance state to be in a non-conductive state, so that the leakage current of the MOS transistor in the data holding mode can be reduced from that in the standby cycle, Current consumption in the data holding mode can be reduced.

[Example 11]
FIG. 49 is a diagram showing a configuration of a main part of a semiconductor memory device according to an eleventh embodiment of the present invention. In the configuration shown in FIG. 49, p-channel MOS transistors Q97a and Q95a are connected in series between main power supply line 1 and variable impedance power supply line 852. The output signal of comparison circuit 854 is applied to the gate of MOS transistor Q95a. Data holding mode designating signal Sleep is applied to the gate of MOS transistor Q97a. N channel MOS transistors Q95b and Q97b are connected in series between main ground line 4 and variable impedance ground line 854. The output signal of comparison circuit 856 is applied to the gate of MOS transistor Q95b. Data holding mode designating signal / Sleep is applied to the gate of MOS transistor Q97b.

  In the configuration shown in FIG. 49, MOS transistors Q97a and Q97b are provided instead of switch circuits SWa and SWb. Other configurations are the same as those shown in FIG. 46, and corresponding portions are denoted by the same reference numerals.

  In the configuration shown in FIG. 49, in the normal operation mode, signal Sleep is at the level of ground voltage Vss, and signal / Sleep is at the high level of power supply voltage Vcc. Therefore, MOS transistors Q97a and Q97b are in a low-resistance conductive state, MOS transistor Q95a has one conductive terminal (source) coupled to main power supply line 1, and one conductive terminal (source) of MOS transistor Q95b has a main ground line. 4 Therefore, in the normal operation mode, the same operation as the configuration shown in FIG. 46 is realized.

  In the data holding mode, signal Sleep is at the high level of power supply voltage Vcc level, and signal / Sleep is at the low level of ground voltage Vss level. Therefore, in this state, MOS transistors Q97a and Q97b are rendered non-conductive with high resistance, and MOS transistors Q95a and Q95b are separated from main power supply line 1 and main ground line 4, respectively. In this data holding mode, MOS transistors Q97a and Q95a are connected in series between main power supply line 1 and variable impedance power supply line 852, so that their combined resistance becomes larger than that shown in FIG. Leakage current from 1 to the variable impedance power supply line 852 can be suppressed. Similarly, since MOS transistors Q95b and Q97b are connected in series between main ground line 4 and variable impedance ground line 854, their combined resistance is made larger than that shown in FIG. 46, and leakage current is further reduced. .

  In the configuration shown in FIG. 49, it is described that signals Sleep and / Sleep have amplitudes of power supply voltage Vcc and ground voltage Vss. However, the configuration may be such that signal Sleep has amplitudes of high voltage Vpp and ground voltage Vss, and signal / Sleep has amplitudes of power supply voltage Vcc and negative voltage Vbb. Such a configuration set to high voltage Vpp and negative voltage Vbb can be realized using level conversion circuits 780a and 790a shown in FIGS. By setting signal Sleep to high voltage Vpp in the data holding mode in this manner, MOS transistor Q97a is set to a stronger off state (high resistance state), and the main power supply line 1 and variable impedance power supply line 852 are reliably connected to the electric power. Can be separated. Similarly, by setting signal / Sleep to negative voltage Vbb in the data holding mode, MOS transistor Q97b can be set to a stronger off state (high resistance state) to be in a non-conductive state. The current path between the variable impedance ground lines 854 can be reliably turned off.

  As described above, according to the configuration of the eleventh embodiment of the present invention, the main power supply line 1 or main ground line 4 as the main power supply line and the variable impedance power supply line or the variable impedance ground line as the sub power supply line are connected. Two MOS transistors are provided in series between one another, and one of the MOS transistors adjusts its resistance value (or current drivability) according to the output signal of the comparison circuit, and the other MOS transistor is controlled by the data holding mode designating signals Sleep and / Sleep. Since it is configured to be set to the on state or the off state, in the data holding mode, these MOS transistors are connected in series, the resistance thereof increases, and the leak current (subthreshold current) can be further reduced. . Further, in this configuration, by setting signals Sleep and / Sleep to a voltage (Vpp or Vbb) higher than the absolute value of the voltage (Vcc or Vss) on the main power supply line, the other MOS transistor is turned off more strongly. (High resistance state), the current path between the main power supply line and the sub power supply line can be reliably set to the cutoff state, and the leak current can be further reduced.

[Example 12]
FIG. 50 is a diagram showing a configuration of a main part of a semiconductor memory device according to a twelfth embodiment of the present invention. In the configuration shown in FIG. 50, a Vref1 generating circuit 880 that generates a reference voltage Vref1 for determining the voltage level of voltage VCL on variable impedance power supply line 852 during a standby cycle, and a reference voltage Vref1 and a variable impedance voltage line 852 Is inactive in the data holding mode (sleep mode), and the generation operation and comparison operation of reference voltage Vref1 are prohibited.

  Similarly, a Vref2 generating circuit 882 for generating a reference voltage Vref2 for determining the voltage level of voltage VSL during the standby cycle of variable impedance ground line 854, and a comparing circuit 886 for comparing this reference voltage Vref2 with voltage VSL are provided. In the mode (sleep mode), it is inactive and each operation is prohibited. Structures other than the above are the same as those shown in FIG. 46. Corresponding portions are allotted with the same reference numerals, and description thereof is not repeated.

  The operation in the normal operation mode is the same as the operation described above with reference to FIGS. 46 and 47. That is, in the normal operation mode, data holding mode designating signal / Sleep is inactivated, and Vref1 generating circuit 880, Vref2 generating circuit 882, and comparing circuits 884 and 886 are activated. Switch circuits SWa and SWb transmit output signals of corresponding comparison circuits 884 and 886 to the gates of corresponding MOS transistors Q95a and Q95b, respectively. Therefore, in the standby cycle in the normal operation mode, voltage VCL on variable impedance power supply line 852 and voltage VSL on variable impedance ground line 854 are held at reference voltages Vref1 and Vref2, respectively. In the active cycle, MOS transistors Q90a and Q90b are turned on, and voltages VCL and VSL attain the levels of power supply voltage Vcc and ground voltage Vss.

  In the data holding mode (sleep mode), switch circuit SWa connects the gate of MOS transistor Q95a to main power supply line 1, and switch circuit SWb connects the gate of MOS transistor Q95b to main ground line 4. In this state, MOS transistors Q95a and Q95b are turned off, the current path is cut off, and the current consumption is reduced, similarly to the configuration of the tenth embodiment described above with reference to FIG.

  In the twelfth embodiment, further, in the data holding mode, data holding mode designating signal / Sleep is activated, and operations of Vref1 generating circuit 880, Vref2 generating circuit 882, and comparing circuits 884 and 886 are prohibited. . In the data holding mode (sleep mode), no current is consumed in these circuits, and the current consumption is reduced accordingly.

  FIG. 51 is a diagram showing an example of the configuration of the comparison circuit 884 shown in FIG. 51 includes p-channel MOS transistors 890a and 890b forming a current mirror circuit, n-channel MOS transistors 890c and 890d forming a comparison stage between voltage VCL and reference voltage Vref1, and a comparison circuit 884. And an n-channel MOS transistor 890e for controlling activation / inactivation of the semiconductor device.

  That is, MOS transistor 890a has one conduction terminal (source) connected to power supply terminal 20, and its gate and the other conduction terminal (drain) connected in common. MOS transistor 890b has one conduction terminal connected to power supply terminal 20, its gate connected to the gate and other conduction terminal of MOS transistor 890a, and the other conduction terminal connected to the other conduction terminal (drain) of MOS transistor 890d. Is done. MOS transistor 890c has the other conduction terminal connected to the gate and the other conduction terminal of MOS transistor 890a, and receives voltage VCL at its gate. MOS transistor 890d receives reference voltage Vref1 at its gate. MOS transistors 890c and 890d have one conduction terminal (source) commonly connected and coupled to ground terminal 30 via MOS transistor 890e. MOS transistor 890e receives data holding mode designating signal / Sleep at its gate.

  In the normal operation mode, data holding mode designating signal / Sleep is inactive at a high level, and MOS transistor 890e is on. In this state, a current path from power supply terminal 20 to ground terminal 30 is formed, and a comparison operation of voltages VCL and Vref1 is performed. When voltage VCL is higher than reference voltage Vref1, the conductance of MOS transistor 890c becomes larger than the conductance of MOS transistor 890d, and the amount of current flowing through MOS transistor 890c is smaller than the amount of current flowing through MOS transistor 890d. growing. The current flowing through MOS transistor 890c is supplied from power supply terminal 20 through MOS transistor 890a. A mirror current of the current flowing through MOS transistor 890a flows through MOS transistor 890b and is applied to MOS transistor 890d. Thereby, the voltage level of the other conduction node (drain) of MOS transistor 890d rises, the voltage level of the signal applied to switch circuit SWa rises, the conductance of MOS transistor Q95a (see FIG. 50) decreases, and the transistor is turned off. It becomes. When voltage VCL is lower than reference voltage Vref1, conversely, the current flowing through MOS transistor 890a becomes larger than the current flowing through MOS transistor 890c, and accordingly, the amount of current discharged by MOS transistor 890d is reduced by MOS. The current becomes larger than the current supplied from transistor 890b, and the voltage level of the signal applied from comparison circuit 884 to switch circuit SWa accordingly decreases. Thereby, the gate potential of MOS transistor Q95a shown in FIG. 50 decreases, and its conductance increases.

  In the data holding mode (sleep mode), signal / Sleep attains an inactive low level, and MOS transistor 890a is turned off. As a result, the current path from the power supply terminal 20 to the ground terminal 30 is cut off, and the comparison operation of the comparison circuit 884 is prohibited. In this state, the voltage level of the signal output from comparison circuit 884 is almost at the level of power supply voltage Vcc. In the data holding mode, the MOS transistor 890e is turned off, and the current path from the power supply terminal 20 to the ground terminal 30 of the comparison circuit 884 is cut off, thereby inhibiting the current consumption of the comparison circuit 884.

  FIG. 52 illustrates an example of a configuration of comparison circuit 886 shown in FIG. In FIG. 52, comparison circuit 886 includes n-channel MOS transistors 892a and 892b forming a current mirror circuit, p-channel MOS transistors 892c and 892d forming a comparison stage of voltages VSL and Vref2, and an active / inactive state of comparison circuit 886. Includes p-channel MOS transistor 892e for controlling inactivation. MOS transistor 892a has one conduction terminal (source) connected to ground terminal 30, and its gate and drain commonly connected. The source of MOS transistor 892b is connected to ground terminal 30, the gate is connected to the gate and drain of MOS transistor 892a, and a signal indicating the comparison result is output from the drain. MOS transistor 892c receives voltage VSL at its gate, and has its drain connected to the gate and drain of MOS transistor 892a. MOS transistor 892d receives reference voltage Vref2 at its gate, and has its drain connected to the drain of MOS transistor 892b. The sources of MOS transistors 892c and 892d are commonly connected and coupled to power supply terminal 20 via MOS transistor 892e. MOS transistor 892e receives data retention mode designating signal Sleep at its gate. The data holding mode designating signal Sleep is at an active high level in the data holding mode.

  In the normal operation mode, data holding mode designating signal Sleep is at a low level, MOS transistor 892e is turned on, and a current path from power supply terminal 20 to ground terminal 30 is formed. When voltage VSL is higher than reference voltage Vref2, the conductance of MOS transistor 892d becomes higher than the conductance of MOS transistor 892c. A mirror current of a current flowing through MOS transistor 892c is formed by MOS transistors 892a and 892b, and the formed mirror current is supplied from MOS transistor 892d. At this time, since the current supplied by MOS transistor 892d is larger than the mirror current flowing through MOS transistor 892b, the voltage level of the signal applied to switch circuit SWb rises, and MOS transistor Q95b shown in FIG. 50 is turned on. . When voltage VSL is lower than reference voltage Vref2, on the contrary, the conductance of MOS transistor 892c becomes larger than the conductance of MOS transistor 892d, and the current flowing through MOS transistor 892b becomes the current supplied from MOS transistor 892d. And the voltage level of the signal applied to the switch circuit SWb decreases.

  In the data holding mode (sleep mode), signal Sleep goes to the active high level, MOS transistor 892e is turned off, and the current path from power supply terminal 20 to ground terminal 30 is cut off. In this state, the voltage level of the signal applied from comparison circuit 886 to switch circuit SWb is substantially equal to the level of voltage Vss applied to ground terminal 30.

  FIG. 53 schematically shows a structure of reference voltage generating circuits 880 and 882 shown in FIG. 53, reference voltage generating circuit 880 includes a resistor 880a connected between power supply node 20 and node 880d, a constant current source 880b and a switching element 880c connected in series between node 880d and ground node 30. Including. Switching element 880c is turned off when data holding mode designating signal / Sleep is in a low level active state, and turned on when data holding mode designating signal / Sleep is in a high level inactive state. To form a path through which current flows. Reference voltage Vref1 is output from node 880d.

  Reference voltage generating circuit 882 includes a switching element 882c and a constant current source 882b sequentially connected in series between power supply node 20 and node 882d, and a resistance element 882a connected between node 882d and ground node 30. Switching element 882c is in an off state when data holding mode instruction signal / Sleep is in an active state and indicates a data holding mode, and is in an inactive state when data holding mode instruction signal / Sleep is in an inactive state. Operation), the switching element 882c is turned on. Reference voltage Vref2 is output from node 882d. Next, the operation will be briefly described.

  When data holding mode instruction signal / Sleep is inactive, switching elements 880c and 882c are both non-conductive. Therefore, in reference voltage generating circuit 880, no current flows through resistor 880a, and reference voltage Vref1 attains the level of power supply voltage Vcc applied on power supply node 20. Also in reference voltage generating circuit 882, no current flows through resistor 882a, and reference voltage Vref2 on node 882d attains the level of ground voltage Vss on ground node 30.

  When data holding mode instruction signal / Sleep is inactive, switching elements 880c and 882c are turned on. Therefore, in reference voltage generation circuit 880, current I (880) determined by constant current source 880b flows through resistor 880a, and reference voltage Vref1 has the voltage level of Vcc-I (880) · R (880a). . Here, R (880a) indicates the resistance value of the resistance element 880a. In reference voltage generating circuit 882 as well, constant current I (882) determined by constant current source 882b flows through resistance element 882a. Thus, the reference voltage Vref2 from the node 882d becomes I (882) · R (882a) + Vss. Here, R (882a) indicates the resistance value of the resistance element 882a.

  FIG. 54 is a diagram showing a configuration of circuits 880 and 882 for generating reference voltage shown in FIG. 53 in more detail.

  54, Vref1 generating circuit 880 has a p-channel MOS transistor Qra1 having a source connected to power supply terminal 20 and a gate connected to node na1, a source connected to node na1, and a gate connected to MOS transistor A p-channel MOS transistor Qra2 connected to the drain of Qra1, an n-channel MOS transistor Qra3 whose drain and gate are connected to the drain of MOS transistor Qra2, and whose source is coupled to ground terminal 30 via MOS transistor Qra5; , The drain of which is connected to the gate of MOS transistor Qra2 and the drain of MOS transistor Qra1, and the source of which is coupled to ground terminal 30 via n-channel MOS transistor Qra6. It includes a MOS transistor Qra4, resistors are connected in series between the power supply terminal 20 and a node na1 RRa1, ..., a RRam and RRan. Data holding mode designating signal / Sleep is applied to the gates of MOS transistors Qra5 and Qra6.

  Vref1 generating circuit 880 further includes resistors RRb1,..., RRbm and RRbn connected in series between power supply terminal 20 and node na2, a drain connected to node na2, a gate connected to the gate of MOS transistor Qra3, An n-channel MOS transistor Qra7 coupled to the drain and having its source connected to ground terminal 30 via MOS transistor Qra8 is included. Data holding mode designating signal / Sleep is applied to the gate of MOS transistor Qra8. Transistor Qra8 corresponds to switching element 880c in FIG. 53, resistors RRb1 to RRbn correspond to resistance element 880a in FIG. 53, and the remaining components correspond to constant current source 880b. Before describing the configuration and operation of Vref2 generation circuit 882, the operation of Vref1 generation circuit 880 will be described first.

  In the normal operation mode, data holding mode designating signal / Sleep is at the high level, MOS transistors Qra5, Qra6 and Qra8 are turned on, and current flows from power supply terminal 20 to ground terminal 30 in Vref1 generating circuit 880. . The current drivability of MOS transistors Qra1 and Qra2 is made sufficiently larger than the current drivability of MOS transistors Qra3 and Qra4. The voltage level of node na1 is lower than the voltage level of power supply terminal 20, and a current flows through MOS transistor Qra1. Similarly, a current flows through MOS transistor Qra2. MOS transistors Qra3 and Qra4 form a current mirror circuit, and the mirror current of MOS transistor Qra2 flows from MOS transistor Qra1 to ground terminal 30 via MOS transistor Qra4. When the voltage level of node na1 is high, the current flowing through MOS transistor Qra1 decreases. On the other hand, since the source potential of the MOS transistor Qra2 is increased, the current flowing therethrough increases. MOS transistors Qra3 and Qra4 form a current mirror circuit. When the current flowing through MOS transistor Qra2 increases, the current flowing through MOS transistor Qra4 increases accordingly, and the gate potential of MOS transistor Qra2 decreases. . Thereby, the current of MOS transistor Qra2 is further increased, and the voltage level of node na1 decreases.

  On the other hand, when the voltage level of node na1 is low, the current flowing through MOS transistor Qra1 increases. Since the source potential of the MOS transistor Qra2 is low, the supply current thereof decreases, the mirror current flowing through the MOS transistor Qra4 decreases accordingly, the gate potential of the MOS transistor Qra2 increases, and the MOS transistor Qra2 passes through the MOS transistor Qra2. And the current flowing therethrough is further reduced. Thereby, the voltage level of node na1 rises.

  By the above operation, the voltage level of node na1 is set to a constant voltage level. The current drivability of MOS transistors Qra1 and Qra2 is made sufficiently larger than the current drivability of MOS transistors Qra3 and Qra4. In this case, in the steady state, the voltage between the source and gate of MOS transistor Qra1 becomes equal to the absolute value Vthp of the threshold voltage. The current flowing from the node na1 to the ground terminal 30 is supplied from the power supply terminal 20 via resistors RRa1 to RRan. Since the voltage of the node na1 is Vcc-Vthp, the current IA flowing from the power supply terminal 20 to the ground terminal 30 via the node na1 is given by the following equation, where RA is the combined resistance of the resistors RRa1 to RRan.

IA = Vthp / RA
In the output stage, MOS transistor Qra7 forms a current mirror circuit with MOS transistor Qra3. Therefore, when the current driving capabilities of MOS transistors Qra3 and Qra7 are equal, current IA flows via transistors Qra7 and Qra8. This current IA flows through the resistors RRb1 to RRbn. Accordingly, the reference voltage Vref1 is given by the following equation, where RB is the combined resistance of the resistors RRb1 to RRbn.

Vref1 = Vcc-IA.RB = Vcc-Vthp.RB / RA
That is, reference voltage Vref1 has a voltage level lower than power supply voltage Vcc by Vthp · RB / RA. As an example, a value of about 0.15 V is used as the value of Vthp · RB / RA.

  In the data holding mode, data holding mode designating signal / Sleep goes low, MOS transistors Qra5, Qra6 and Qra8 are all turned off, and the current path from voltage terminal 20 to ground terminal 30 is cut off. In this state, reference voltage Vref1 rises to the level of power supply voltage Vcc applied to power supply terminal 20, and the reference voltage generation operation is prohibited. By turning off MOS transistors Qra5, Qra6 and Qra8 and cutting off the current path, consumption of current in Vref1 generating circuit 880 is prohibited.

  Vref2 generating circuit 882 is connected to a p-channel MOS transistor Qrb1 having a source connected to power supply terminal 20, a gate connected to node na1, a source connected to node nb1, and a drain of MOS transistor Qrb1. A MOS transistor Qrb2 having a gate connected to the drain of MOS transistor Qrb2, and a source connected to ground terminal 30 via MOS transistor Qrb5; N-channel MOS transistor having a drain connected to the gate of MOS transistor Qrb2 and the drain of MOS transistor Qrb1, and a source coupled to ground terminal 30 via MOS transistor Qrb6 Including the Qrb4. Data holding mode designating signal / Sleep is applied to the gates of MOS transistors Qrb5 and Qrb6.

  Vref2 generation circuit 882 further includes an inverter IVR for inverting data holding mode designating signal / Sleep, a gate connected to node nb1, a drain connected to node nb2, and power supply terminal 20 via MOS transistor Qrb8. , RRcm and RRcn connected in series between power supply terminal 20 and node nb1, and connected in series between ground terminal 30 and node nb2. , RRdm, and RRdn. In correspondence with the configuration of FIG. 53, resistors RRd1 to RRdn correspond to resistance element 882a, transistor Qrb8 corresponds to switching element 882c, and the remaining components correspond to constant current source 882b. Reference voltage Vref2 is output from node nb2. The configuration of the portion including MOS transistors Qrb1 to Qrb6 and resistors RRc1 to RRcn is the same as the configuration of the corresponding portion of Vref1 generation circuit 880. Therefore, the voltage level of node nb1 is Vcc-Vthp in the normal operation mode. The voltage on node nb1 is applied to the gate of MOS transistor Qrb7. In the normal operation mode, the output signal of inverter IVR is at the low level, and MOS transistor Qrb8 is on. MOS transistor Qrb7 receives the voltage on node nb1 at its gate and supplies a current of the same magnitude as MOS transistor Qrb1 (when MOS transistors Qrb1 and Qrb7 have the same size). Therefore, the current flowing through MOS transistor Qrb7 is also constant. Assuming that the current flowing through the MOS transistor Qrb7 is ID and the combined resistance of the resistors RRd1 to RRdn is RD, the reference voltage Vref2 is given by the following equation.

Vref2 = Vss + ID · RD = Vss + Vthp · RD / RC
Here, RC indicates a combined resistance of the resistors RRc1 to RRcn.

  In the data holding mode, signal / Sleep goes low, and the output signal of inverter IVR goes high. Therefore, MOS transistors Qrb5, Qrb6, and Qrb8 are turned off, and the current path flowing from power supply terminal 20 to ground terminal 30 in Vref2 generation circuit 882 is cut off. In this state, reference voltage Vref2 is at the level of voltage Vss applied to ground terminal 30.

  In the configuration shown in FIGS. 51 to 54, power supply terminal 20 and ground terminal 30 may be replaced with main power supply line 1 and main ground line 4, respectively.

[Modification Example 1]
FIG. 55 is a diagram showing a configuration of a first modification of the twelfth embodiment of the present invention. In the configuration shown in FIG. 55, p-channel MOS transistors Q97a and Q95a are connected in series between main power supply line 1 and variable impedance power supply line 852. Data holding mode designating signal Sleep is applied to the gate of MOS transistor Q97a. The output signal of comparison circuit 884 is applied to the gate of MOS transistor Q95a. Between main ground line 4 and variable impedance ground line 854, n-channel MOS transistors Q97b and Q95b are connected in series. Data holding mode designating signal / Sleep is applied to the gate of MOS transistor Q97b. The output signal of comparison circuit 886 is applied to the gate of MOS transistor Q95b. The comparison circuit 884 compares the reference voltage Vref1 output from the Vref1 generation circuit 880 with the voltage VCL on the variable impedance power supply line 852. The comparison circuit 886 compares the reference voltage Vref2 output from the Vref2 generation circuit 882 with the voltage VSL on the variable impedance ground line 854. Circuits 880, 882, 884 and 886 have a structure similar to the structure shown in FIGS. 50 to 54. When data holding mode designating signal / Sleep is activated, it is inactivated and operation is prohibited. In the configuration shown in FIG. 55 as well, the operations of circuits 880, 882, 884, and 886 are prohibited in the data holding mode, so that current consumption in the data holding mode can be reduced. The operation in the normal operation cycle is the same as the operation of the configuration shown in FIG. 49, and a description thereof will be omitted.

[Modification 2]
FIG. 56 is a diagram showing a configuration of a second modification of the twelfth embodiment of the present invention. In the configuration shown in FIG. 56, inverters IV90 and IV91 shown in FIG. 50 have a CMOS inverter configuration.

  Inverter IV90 includes a gate connected to node a10, a source connected to main power supply line 1, a drain connected to node a11, and a substrate region (well region or semiconductor layer) connected to main power supply line 1. ), A gate connected to the node a10, a drain connected to the node a11, a source connected to the variable impedance ground line 854, and a substrate connected to the variable impedance ground line 854. Includes n channel MOS transistor Q90N having a region.

  Inverter IV91 has a gate connected to node a11, a source connected to variable impedance power supply line 852, a drain connected to node a12, and a p-channel MOS having a substrate region connected to variable impedance power supply line 852. Transistor Q91P, an n-channel MOS transistor Q91N having a gate connected to node a11, a drain connected to node a12, a source connected to main ground line 4, and a substrate region connected to main ground line 4 including. The current drivability of MOS transistor Q90a is made sufficiently larger than the current drivability of MOS transistor Q95a. Similarly, the current drivability of MOS transistor Q90b is made sufficiently larger than the current drivability of MOS transistor Q95b. In the configuration shown in FIG. 56, the other configuration is the same as the configuration shown in FIG.

  In the case of the configuration shown in FIG. 56, the sources and substrate regions of MOS transistors Q90P, Q91P, Q90N and Q91N are held at the same potential. Thus, the influence of the back gate bias effect of these transistors is eliminated, and the desired constant threshold voltage is maintained in both the normal operation mode and the data holding mode. The threshold voltages of MOS transistors Q90P and Q91P are set to, for example, -0.5V, and the threshold voltages of MOS transistors Q90N and Q91N are maintained at, for example, 0.35V. In any of the operation modes, the threshold voltages of these constant threshold transistors can be stably maintained, and desired operation characteristics and current consumption characteristics can be realized.

[Modification 3]
FIG. 57 shows a configuration of a third modification of the twelfth embodiment of the present invention. The configuration shown in FIG. 57 is different from the configuration shown in FIG. 56 in the connection form of the substrate region of the MOS transistor as a component included in inverters IV90 and IV91. In the structure shown in FIG. 57, the substrate region of n-channel MOS transistor Q92N included in inverter IV90 is connected to main ground line 4. The substrate region of p-channel MOS transistor Q92P is connected to main power supply line 1 as in the case of FIG. In inverter IV91, the substrate region of p-channel MOS transistor Q93P is connected to main power supply line 1. The substrate region of n-channel MOS transistor Q93N is connected to main ground line 4. The configuration shown in FIG. 57 is electrically equivalent to the connection form of inverters IV80 to IV82 previously shown in FIG. As described above with reference to FIG. 42, the substrate region has a large junction capacitance. Therefore, the parasitic capacitance of variable impedance power supply line 852 and variable impedance ground line 854 is established by connecting the substrate region of the MOS transistor which is a component of inverters IV90 and IV91, which are internal circuits, to main power supply line 1 or main ground line 4. Can be reduced. Thus, the potential of variable impedance power supply line 852 and variable impedance ground line 854 can be recovered at high speed when the mode is shifted from the data holding mode to the normal operation mode. Further, MOS transistors Q92N and Q93P for generating a subthreshold current connect the substrate region to main ground line 4 and main power supply line 1, respectively, so that a back gate bias effect occurs in these transistors Q92N and Q93P. Transistors Q92N and Q93P can be turned off more deeply, and subthreshold current can be further reduced. Thus, current consumption in the data holding mode can be further reduced.

  In the configurations shown in FIGS. 56 and 57, MOS transistors Q95a and Q95b have switch circuits SWa and SWb connected to their gates, respectively. Instead of this configuration, the configuration of the inverter, which is the internal circuit shown in FIGS. 56 and 57, and the configuration shown in FIG. 55 may be combined.

  As described above, according to the configuration of the twelfth embodiment of the present invention, in the data holding mode, circuits 880 and 882 for generating reference voltages and comparison circuits 884 and 886 are deactivated, and these circuits are deactivated. , The current consumption in these circuits does not occur, and the current consumption in the data holding mode can be further reduced.

Example 13
FIG. 58 shows a structure of a main part of a semiconductor memory device according to a thirteenth embodiment of the present invention. In the configuration shown in FIG. 58, the voltage levels of reference voltage Vref1 and Vref2 determining voltage VCL on variable impedance power supply line 852 and voltage VSL on variable impedance ground line 854 at the time of the standby cycle are different from those of this semiconductor memory device. It can be adjusted later. In other words, tomable reference voltage generation circuit 890 for generating reference voltage Vref1 and trimmable reference voltage generation circuit 892 for generating reference voltage Vref2 have the voltage levels of reference voltages Vref1 and Vref2 generated after completion of the semiconductor memory device manufacturing process. A configuration for adjusting is provided. The detailed configuration of the trimmable reference voltage generating circuits 890 and 892 will be described later.

  As shown in FIG. 58, by making the voltage levels of the reference voltages Vref1 and Vref2 adjustable after the completion of the manufacturing process, various parameters in the manufacturing process (the deviation of the resistance value, the deviation of the threshold voltage of the transistor, the gate length, Reference voltage Vref1 and Vref2 of a desired voltage level can be generated accurately even for a shift in gate width, etc., even if the desired voltage levels of reference voltages Vref1 and Vref2 are not realized after manufacturing is completed. In this case, the reference voltage level can be adjusted, the number of semiconductor chips to be processed as defective products can be reduced, and the chip yield can be improved.

  FIG. 59 shows an example of a specific configuration of trimmable reference voltage generating circuits 890 and 892 shown in FIG. In FIG. 59, in addition to the configuration of Vref1 generation circuit 880 shown in FIG. It includes link elements LEb1 to LEbm connected in parallel with each other. Each of link elements LEa1 to LEam and LEb1 to LEbm is a low-resistance conductor and is formed of a fuse element that can be blown.

  54. In addition to the configuration of Vref2 generating circuit 882 shown in FIG. 54, trimmable reference voltage generating circuit 892 is further connected in parallel with link elements LEc1-LEcm provided in parallel with resistors RRc1-RRcm, and resistors RRd1-RRdm, respectively. Link elements LEd1 to LEdm. These link elements LEc1 to LEcm and LEd1 to LEdm are also configured by fuse elements made of fusible low-resistance conductors. In other configurations of the trimmable reference voltage generation circuits 890 and 892, the same reference numerals are given to portions corresponding to the components of the circuits 880 and 882 shown in FIG.

  Level adjustment of reference voltages Vref1 and Vref2 is performed as follows. First, a plurality of patterns for adjusting the reference voltage are prepared in advance. The plurality of voltage level adjustment patterns deal with, for example, (1) a pattern used when the variation in the resistance values of the resistors RRa1 to RRd1 is small, and (2) a case where the variation in the resistance values of these resistors is large. And (3) a pattern for coping with a large variation in parameters such as β of the transistor. Here, β is a coefficient proportional to the ratio between the gate length and the gate width of the MOS transistor, and is a factor indicating the current driving force of the MOS transistor. These patterns include the voltage level of the reference voltage detected after the completion of the manufacturing process, and information indicating the position of the link element to be blown at that time.

  After the manufacturing process of the semiconductor memory device is completed, the manufacturing parameters and the voltage levels of the reference voltages Vref1 and Vref2 are checked first. Next, various functional tests (detection of data retention characteristics and existence of defective memory cells) are performed on the semiconductor memory device. Based on the result of the function test, it is determined whether the semiconductor memory device can be repaired. When it is determined that the part can be rescued, a part to be rescued is detected. Normally, when a defective memory cell is detected in the function test, the defective memory cell is replaced by a redundant memory cell by fusing the link element. In this stage, first, the position of the link element to be blown is determined based on the function test result.

  Next, a pattern for adjusting the reference voltage is selected based on the manufacturing parameters and the voltage level information of the reference voltages Vref1 and Vref2, and the trimmable reference voltage generating circuits 890 and 892 should blow based on the selected pattern. The position of the link element is calculated.

  Next, based on the calculation result, link elements LEa1 to LEd1 are blown in trimmable reference voltage generating circuits 890 and 892. This fusing process is executed in the same step as the fusing of the link element to be blown detected based on the function test. This fusing is performed using, for example, a laser beam. By performing the level adjustment of the reference voltages Vref1 and Vref2 output from the trimmable reference voltage generation circuits 890 and 892 in the same step as the link element fusing step performed for repair or replacement in the semiconductor memory device, an additional step is performed. , The voltage levels of the reference voltages Vref1 and Vref2 can be adjusted, and an increase in the adjustment time can be suppressed.

  In determining the voltage levels of reference voltages Vref1 and Vref2, the amount of current flowing from power supply terminal 20 to ground terminal 30 during the standby cycle is also used as a determining factor for adjusting the voltage levels of reference voltages Vref1 and Vref2. Is also good. Next, voltage level adjustment in trimmable reference voltage generation circuits 890 and 892 will be described.

  The reference voltage Vref1 is given by the following equation, as described above.

Vref1 = Vcc−Vthp · RB / RA
When all of the link elements LEa1 to LEam are in the conductive state, the resistors RRa1 to RRan are all short-circuited, so that the resistance value RA becomes the minimum value. As the link elements LEa1 to LEam are selectively blown, the resistance value RA increases. Therefore, by selectively fusing link elements LEa1 to LEam, the voltage level of reference voltage Vref1 increases.

  On the other hand, when all the link elements LEb1 to LEbm are conducting, the resistance value RB between the power supply terminal 20 and the node na2 is determined by the resistance value given by the resistor RRbn and becomes the minimum value (all the resistors RRb1 to RRbm are linked). (Because it is short-circuited by the elements LEb1 to LEbm). By selectively fusing link elements LEb2 to LEbm, resistance RB between power supply terminal 20 and node na2 increases. In this case, the voltage level of the reference voltage Vref1 decreases from the above equation. By selectively fusing link elements LEa1 to LEam and LEb1 to LEbm, reference voltage Vref1 of a desired voltage level can be generated.

  Similar level adjustment is also performed in trimmable reference voltage generation circuit 892. The reference voltage Vref2 is given by the following equation, as described above.

Vref2 = Vthp · RD / RC
Here, it is assumed that the ground voltage Vss applied to the ground terminal 30 is 0V. It is also assumed that the current values flowing through transistors Qrb1 and Qrb7 are equal.

  By selectively blowing the link elements LEc1 to LEcm, the resistance value RC increases, and the voltage level of the reference voltage Vref2 decreases. On the other hand, by selectively blowing the link elements LEd1 to LEdm, the resistance value RD increases, and the voltage level of the reference voltage Vref2 increases.

  As described above, by selectively fusing link elements LEa1 to LEd1, reference voltages Vref1 and Vref2 of desired voltage levels can be generated.

  Note that trimmable reference voltage generating circuits 890 and 892 shown in FIG. 59 may be used in place of Vref1 generating circuit 880 and Vref2 generating circuit 882 in the configuration of the tenth to twelfth embodiments described above. These trimmable reference voltage generation circuits 890 and 892 may be used as the reference voltage generation circuits previously shown in FIGS. 24, 25, 26, 34 and 37.

  As described above, according to the thirteenth embodiment of the present invention, the voltage levels of reference voltages Vref1 and Vref2 for determining the voltage levels of voltages VCL and VSL of the variable impedance power supply line and the variable impedance ground line in the standby cycle are manufactured. After the process is completed, adjustment is possible, so that even if manufacturing parameters fluctuate, a reference voltage of a desired voltage level can be generated, a semiconductor memory device having a defective reference voltage level can be relieved, and the manufacturing yield can be reduced. Can be improved. Further, by adjusting the level of the reference voltage by fusing a link element connected in parallel with a resistor (a series body of resistor elements), a reference voltage of a desired voltage level can be easily produced. And the reference voltage level can be adjusted in the same step as the other rescue process such as the remedy of a defective memory cell, and the reference voltage level can be adjusted without requiring an extra level adjustment step. it can.

  Note that the resistors RRa1 to RRd1 may be formed of polysilicon resistors, or MOS transistors may be used as resistors. Further, a configuration in which a series body of one resistor is formed by a polysilicon resistor and each resistor of the other series resistor is formed by a MOS transistor may be used in the reference voltage generation circuit.

  The present invention can be applied to a semiconductor device whose operation period is defined by a control signal. In particular, by changing the impedances of the variable impedance power supply line and the variable impedance ground line in accordance with the operation cycle, the subthreshold current can be reliably suppressed, and the standby current and the active DC current can be reduced. A semiconductor device can be obtained. In addition, a subthreshold current can be reliably suppressed, and a semiconductor device with low power consumption can be realized. Further, since the subthreshold current can be reliably suppressed, a semiconductor device can be formed using a MOS transistor having a threshold voltage with a small absolute value, and the semiconductor device can operate at high speed even at a low power supply voltage. By applying this power supply circuit to a semiconductor memory device, a low-power-consumption, large-capacity semiconductor memory device that operates at a low voltage and at a high speed can be realized.

FIG. 1 is a diagram schematically showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention; FIG. 2 is an operation waveform diagram showing a memory cell selection operation of the semiconductor memory device shown in FIG. 1. FIG. 2 is a block diagram schematically showing a configuration of a buffer and a control circuit of the semiconductor memory device shown in FIG. 1. FIG. 2 is a diagram illustrating a configuration of a memory array and an input / output circuit illustrated in FIG. 1. FIG. 5 is a signal waveform diagram illustrating an operation of the circuits illustrated in FIGS. 3 and 4. FIG. 1 is a diagram illustrating a configuration of a power supply circuit according to a first embodiment of the present invention. FIG. 7 is a signal waveform diagram illustrating an operation of the power supply circuit illustrated in FIG. 6. FIGS. 7A and 7B are diagrams for explaining the operation of the power supply circuit shown in FIG. FIGS. 7A and 7B are diagrams for explaining the operation of the power supply circuit shown in FIG. FIG. 1 is a diagram showing a configuration of a power supply circuit for a column circuit according to an embodiment of the present invention. FIG. 11 is a signal waveform diagram illustrating an operation of the power supply circuit illustrated in FIG. 10. FIG. 11 is a signal waveform diagram additionally showing the operation of the power supply circuit shown in FIGS. 6 and 10. FIG. 11 is a diagram showing a sequence for generating the impedance control signals shown in FIGS. 6 and 10. FIG. 14 is a diagram showing a configuration of a control signal generation system for realizing the control signal generation sequence shown in FIG. 13. FIG. 5 is a diagram showing an example of a configuration of a multi-input NAND circuit used in a first modification of the first embodiment of the present invention. FIG. 16 is a diagram showing connection of a variable impedance power supply line and a variable impedance ground line to the two-input NAND circuit shown in FIG. FIG. 6 is a diagram showing a connection portion for supplying power to a two-input NAND circuit used as a modification in the first embodiment of the present invention. FIG. 11 is a diagram showing a configuration of a two-input NOR circuit used in a modification of the first embodiment of the present invention and a change in a logic level of an output signal. FIG. 19 is a diagram illustrating a connection configuration of power supply of the two-input NOR circuit illustrated in FIG. 18. FIG. 19 is a diagram illustrating a connection mode of power supply according to a logical level of an output signal of the two-input NOR circuit illustrated in FIG. 18. FIG. 14 is a diagram showing a configuration of a power supply circuit for a row-related circuit in a second modification of the first embodiment of the present invention. FIG. 22 is a signal waveform diagram representing an operation of the power supply circuit shown in FIG. 21. (A) shows a configuration for generating the control signal shown in FIG. 21, and (B) is a signal waveform diagram showing an operation of the circuit shown in (A). (A) shows a configuration of a power supply circuit according to a second embodiment of the present invention, and (B) shows an operation waveform thereof. FIG. 6 is a diagram illustrating a configuration of a power supply circuit according to a second embodiment of the present invention and operation waveforms thereof. FIG. 6 is a diagram illustrating an overall configuration of a power supply circuit according to a second embodiment of the present invention. FIG. 9 is a diagram illustrating a configuration of a power supply circuit according to a third embodiment of the present invention. FIG. 28 is a signal waveform diagram representing an operation of the power supply circuit shown in FIG. 27. FIG. 28 is a diagram showing a configuration for generating a control signal shown in FIG. 27. FIG. 30 is a signal waveform diagram illustrating an operation of the circuit illustrated in FIG. 29. FIG. 14 is a diagram showing an entire configuration of a DRAM to which a fourth embodiment of the present invention is applied. FIG. 11 is a diagram illustrating a configuration of a power supply circuit according to a fourth embodiment of the present invention. 33 is a diagram illustrating an example of a configuration of a power supply circuit illustrated in FIG. 32. FIG. FIG. 15 is a diagram showing a configuration of a main part of a semiconductor device according to a fifth embodiment of the present invention; FIG. 35 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. 34. FIG. 35 is a diagram showing a schematic cross-sectional structure of the inverter circuit shown in FIG. 34. FIG. 14 is a diagram showing a modification of the fifth embodiment of the present invention. FIG. 16 is a diagram showing a configuration of a main part of a semiconductor device according to a sixth embodiment of the present invention; FIG. 39 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. 38. FIG. 39 is a diagram showing an example of a configuration of a transistor substrate bias generation circuit for connecting a main power supply line and a variable impedance power supply line shown in FIG. 38. FIG. 39 is a diagram showing an example of a configuration of a circuit for generating a substrate bias voltage of a transistor connecting the variable impedance ground line and the main ground line shown in FIG. 38. FIG. 39 shows a cross-sectional structure of a transistor connecting the main power supply line and the variable impedance power supply line shown in FIG. 38. FIG. 14 is a diagram schematically showing a cross-sectional structure of a transistor for connecting a variable impedance power supply line and a main power supply line according to a seventh embodiment of the present invention. FIG. 15 is a diagram showing a configuration of a main part of a semiconductor device according to an eighth embodiment of the present invention; FIG. 21 is a diagram showing a configuration of a main part of a semiconductor device according to a ninth embodiment of the present invention; FIG. 21 is a diagram showing a configuration of a main part of a semiconductor memory device according to a tenth embodiment of the present invention; FIG. 47 is a waveform chart showing an operation of the semiconductor device shown in FIG. 46. FIG. 47 illustrates an example of the configuration of the switch circuit illustrated in FIG. 46. FIG. 21 is a diagram showing a configuration of a main part of a semiconductor memory device according to an eleventh embodiment of the present invention. FIG. 21 is a diagram showing a configuration of a main part of a semiconductor memory device according to a twelfth embodiment of the present invention. FIG. 51 is a drawing illustrating an example of the configuration of a comparison circuit that compares the reference voltage Vref1 and the voltage VCL illustrated in FIG. 50. FIG. 51 is a drawing illustrating an example of the configuration of a circuit that compares the reference voltage Vref2 and the voltage VSL illustrated in FIG. 50. FIG. 51 is a drawing illustrating roughly configuration of a reference voltage generating circuit illustrated in FIG. 50; FIG. 54 is a diagram illustrating an example of a detailed configuration of a circuit that generates reference voltages Vref1 and Vref2 illustrated in FIG. 53. FIG. 35 is a diagram showing a configuration of a first modification of the twelfth embodiment of the present invention. FIG. 33 is a diagram showing a configuration of a second modification of the twelfth embodiment of the present invention. FIG. 35 is a diagram showing a configuration of a third modification of the twelfth embodiment of the present invention. FIG. 34 is a diagram showing a configuration of a main part of a semiconductor memory device according to a thirteenth embodiment of the present invention; FIG. 59 shows a specific configuration of the trimmable reference voltage generation circuit shown in FIG. 58. FIG. 11 is a diagram illustrating a configuration of a conventional CMOS inverter. FIG. 9 is a diagram showing sub-threshold current characteristics of a MOS transistor. FIG. 9 is a diagram illustrating a configuration of a conventional variable impedance power supply line. FIG. 63 is a signal waveform diagram representing an operation of the power supply circuit shown in FIG. 62.

Explanation of reference numerals

Reference Signs List 1 main power line, 4 main ground line, 20 first power node, 30 second power node, 100 memory cell array, 102 address buffer, 104 row selection circuit, 106 column selection circuit, 108 input / output circuit, 120 power supply voltage Supply circuit, 130 ground voltage supply circuit, 110 control circuit, 2 variable impedance power lines, 3 variable impedance power lines, 5 variable impedance ground lines, 6 variable impedance ground lines, Q3, Q4 p-channel MOS transistors, Q5, Q6 n-channel MOS transistor, R1-R4 resistance element, Q7 p-channel MOS transistor, Q8 n-channel MOS transistor, Ra3, Rb3 resistance element, FR1-FRn, FC1-FCn inverter, 304 sense amplifier activation signal generation circuit, 306 interlock signal generation circuit , 308 Impedance control signal generation circuit, 314a, 314b, 314c Row power supply circuit, 320 Column power supply circuit, 352 2-input NAND circuit, 345 2-input NOR circuit, 402, 403 Variable impedance power supply line, 405, 406 Variable impedance ground Line, Q10, Q12 p-channel MOS transistor, Q11, Q13 n-channel MOS transistor, R10-R13 resistance element, 450, 452, 454 row system circuit, 500 variable impedance power supply line, 501 differential amplifier, 505 variable impedance ground line, 506 differential amplifier, 500a, 500b variable impedance power supply line, 505a, 505b variable impedance ground line, 501a, 501b, 506a, 506b differential amplifier, Q20a, Q21a, Q20b, Q 1b p-channel MOS transistor, Q22a, Q23a, Q22b, Q23b n-channel MOS transistor, 600, 601 variable impedance power supply line, 602, 603 variable impedance ground line, 610 constant voltage generation circuit, Q33, Q31 p-channel MOS transistor, Q34, Q32 n-channel MOS transistor, Raa, Rab, Rba, Rbb resistance element, 654 hold mode detection circuit, 656 refresh control circuit, 668 interlock signal generation circuit, 662 control signal generation circuit, 664 control signal generation circuit, 700-1 to 700-n power supply circuit, 710 block selection signal generation circuit, 720 impedance change control signal generation circuit, 731,732 variable impedance power supply line, 733,734 variable impedance ground line Q40-Q43 p-channel MOS transistor, Q45-Q48 n-channel MOS transistor, R40-R43 resistance element, 762a, 762b differential amplifier, Q50a, Q50b, Q60a, Q60b switching MOS transistor, PQ50-PQ52, Q80p-Q82p SOI structure p channel MOS transistor, NQ50 to NQ52, Q80n to Q82n SOI structure n channel MOS transistor, 760 variable impedance power supply line, 761a, 761b differential amplifier, 762 variable impedance ground line, 765 semiconductor substrate, 766 insulating layer, 764 semiconductor layer, Q60a, Q60b switching MOS transistor, 810 semiconductor layer, 811 insulating layer, 812, 814 impurity region, 813 substrate region (body region), 820 Variable impedance power line, 822
Variable impedance ground line, 824,826 voltage regulator, Q90a, Q95a p-channel MOS transistor, Q90b, Q95b n-channel MOS transistor, SWa, SWb switch circuit, 854,856 comparison circuit, 860 Vref1 generation circuit, 862 Vref2 generation circuit, Q97a p-channel MOS transistor, Q97b n-channel MOS transistor, IV90, IV91 inverter, 880 Vref1 generation circuit, 882 Vref2 generation circuit, 884,886 comparison circuit, 890,892 Trimmable reference voltage generation circuit.

Claims (8)

A semiconductor device having a hierarchical power supply configuration having a main power supply line and a sub power supply line, and having a standby cycle and an active cycle as operation cycles,
Provided so as to respond to an operation cycle definition signal that defines the standby cycle and the active cycle, and becomes conductive when the operation cycle definition signal specifies the active cycle, and connects the main power supply line and the sub power supply line to each other. A switching insulated gate field effect transistor electrically connected;
Threshold changing means which operates in response to the operation cycle defining signal and makes an absolute value of a threshold voltage of the switching insulated gate field effect transistor at the time of the standby cycle larger than that at the time of the active cycle. A semiconductor device.   2. The semiconductor device according to claim 1, wherein said switching insulated gate field effect transistor is formed in a semiconductor layer formed on an insulating layer. The threshold changing means,
When the operation cycle defining signal indicates the standby cycle, the absolute value of the bias voltage applied to the substrate region where the channel is formed when the switching insulated gate field effect transistor is turned on is set to be greater than that in the active cycle. 3. The semiconductor device according to claim 1, further comprising means for increasing the size. The main power supply line has a first main power supply line for transmitting a first logic voltage, and a second main power supply line for transmitting a second logic voltage, and the sub power supply line is Having first and second sub power supply lines arranged corresponding to the first and second main power supply lines, respectively;
A first insulated gate field effect transistor electrically connecting the first sub power supply line to an internal output node in response to an input signal; and a first insulated gate field effect transistor in response to the input signal 4. A logic gate including a second insulated gate field effect transistor that conducts complementarily to the effect transistor and electrically connects the second sub power supply line to the internal output node. The semiconductor device according to any one of the above. The main power supply line includes a first main power supply line transmitting a first logic voltage, and a second main power supply line transmitting a second logic voltage, and the sub power supply line includes: First and second sub power supply lines arranged corresponding to the first and second main power supply lines, respectively; and the first sub power supply line and an internal output node are responsive to an input signal. A first insulated gate field effect transistor that electrically connects the second main power supply line and the second main power supply line with the first insulated gate field effect transistor in response to the input signal. 4. The semiconductor device according to claim 1, further comprising a logic gate including a second insulated gate field effect transistor electrically connecting to an internal output node.   The absolute value of the threshold voltage of the switching insulated gate field effect transistor is made larger than the absolute value of the threshold voltage of the first and second insulated gate field effect transistors included in the logic gate. The semiconductor device according to claim 4.   The first and second insulated gate field effect transistors included in the logic gate are formed in a semiconductor layer formed on an insulating layer, and when the first and second insulated gate field effect transistors are turned on. 7. The semiconductor device according to claim 4, wherein a substrate region where a channel is formed is connected to each of said first and second main power supply lines.   9. The semiconductor device according to claim 8, further comprising a plurality of cascade-connected logic gates alternately coupled to said main power supply line and said sub-power supply line, each of which performs predetermined logic processing on an output signal of a preceding circuit and outputs the processed signal. The semiconductor device according to 1.

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