JP2004240299A - Hash function processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a high speed round processing in a hash function using less number of hardware resources than in the past. <P>SOLUTION: This hash function processor 10 achieves the round processing in an SHA1 algorithm using four registers 101-104 storing feedback data and one register 105 storing an intermediate result of calculation. Input data W and a constant K are read one clock cycle prior to an original reading timing, and two-stage pipeline treatment is performed by first and second operation parts 161, 162, and the resister 105, thus to achieve the high speed round processing in the hash function in apparently one clock cycle per round. By using one of the registers storing the feedback data as the register storing the intermediate result in common, the number of the registers can be reduced compared to the past. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a hash function processing device, and more particularly, to obtain a fixed-length value (hash value) that is difficult to reverse-transform from arbitrary-length data in order to protect security in the field of information communication and the like. The present invention relates to a hash function processing device.
[0002]
[Prior art]
In recent years, broadband IP (Internet Protocol) infrastructures represented by FTTH (Fiber To The Home) and ADSL (Asymmetric Digital Subscriber Line) have become widespread in homes and the like. Along with this, demands for security techniques, such as prevention of message tampering, have been increasing even on IP transmission paths that require high speed. As a typical example of the message tampering prevention technique, for example, a method using a hash function is known. The hash function is a function for obtaining a fixed-length value (hereinafter, referred to as a hash value) unique to a message of an arbitrary length. The hash value obtained by using the hash function has extremely high randomness. That is, different hash values are obtained with extremely high probability for different messages. A hash function having such characteristics can be used as a means for detecting tampering of a message.
[0003]
Conventionally, as a hash function processing device, for example, an arithmetic circuit described in Patent Document 1 is known. Patent Literature 1 describes an arithmetic circuit that performs an iterative process (hereinafter, referred to as a round process) in The SecureHash Algorithm, which is a type of hash function. This arithmetic circuit performs a round process at high speed by performing a two-stage pipeline process.
[0004]
[Patent Document 1]
JP 2002-287635 A
[0005]
[Problems to be solved by the invention]
However, the above-mentioned conventional arithmetic circuit includes five registers for storing feedback data and one or more registers for storing intermediate results of the operation in order to perform a round process in the hash function. As described above, this arithmetic circuit has a problem that the circuit scale increases and the cost increases.
[0006]
Therefore, an object of the present invention is to provide a hash function processing device that executes round processing in a hash function at high speed using less hardware resources.
[0007]
Means for Solving the Problems and Effects of the Invention
A first invention is a hash function processing device that performs iterative processing defined by a hash function on input data, the first to fourth registers storing feedback data, and input data having a predetermined length. An input data supply unit for supplying, a constant value supply unit for supplying a constant value determined by a hash function, a value of a fourth register, input data supplied from the input data supply unit, and a constant value supply unit. A first arithmetic processing unit that performs a predetermined arithmetic processing on the supplied constant value, an intermediate value storage register that stores an arithmetic result of the first arithmetic processing unit, and a first to a fourth register. A second arithmetic processing unit for performing predetermined arithmetic processing on the value and the value of the intermediate value storage register, wherein the first and second arithmetic processing units operate in parallel and store the intermediate value. Register is the first operation The first register takes in the operation result of the second operation processing unit, the second register takes in the value of the first register, and the third register takes in the operation result of the first register. An operation of acquiring a value obtained by cyclically shifting the value of the second register, an operation of acquiring the value of the third register by the fourth register, an operation of acquiring the next input data by the input data supply unit, and an operation of supplying a constant value. The operation in which the unit takes in the next constant value is performed in parallel within one clock cycle.
According to the first aspect, the first and second arithmetic circuits operate in parallel, the output of the first arithmetic circuit is written to the intermediate value storage register, and the input of the second arithmetic circuit is the intermediate value. It is supplied from a value storage register or the like. Thus, two-stage pipeline processing is performed by the first and second arithmetic circuits and the intermediate value storage register. Further, in order to supply data to the pipeline at an appropriate timing, input data and a constant value used in the repetitive processing are acquired one clock cycle before the timing at which the data should be acquired. Therefore, the iterative process in the hash function can be executed at a high speed with one clock cycle per round in appearance. In addition to this, the number of registers for storing feedback data can be reduced, and iterative processing in the hash function can be executed at high speed using fewer hardware resources than in the past.
[0008]
In a second aspect based on the first aspect, the first arithmetic processing unit includes a fourth register value, input data supplied from the input data supply unit, and a constant value supplied from the constant value supply unit. And is added.
[0009]
In a third aspect based on the first aspect, the second arithmetic processing section performs a predetermined logical operation on the values of the second to fourth registers, and outputs the operation result and the value of the intermediate value storage register. And a value obtained by cyclically shifting the value of the first register.
[0010]
A fourth invention is characterized in that in any one of the first to third inventions, the hash function is SHA1 (The Secure Hash Algorithm 1).
According to the second to fourth aspects, the repetitive processing in the SHA1 algorithm can be executed at a high speed with one clock cycle per apparently one round.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a logic circuit diagram of the hash function processing device according to the first embodiment of the present invention. The hash function processing device 10 illustrated in FIG. 1 performs a round process in The Secure Hash Algorithm 1 (hereinafter, referred to as SHA1), which is a kind of a hash function. SHA1 is a function for obtaining a 160-bit hash value from input data of an arbitrary length. In the SHA1 algorithm, input data is divided into 512 bits in order from the beginning. The input data divided into 512 bits is further divided into 16 words (one word is 32 bits), and a predetermined logical operation is performed on the 16 words to obtain 80 words. Then, the following processing (hereinafter, referred to as 80 round processing) is sequentially performed using the obtained 80 words as one unit (hereinafter, referred to as block data).
[0012]
In the 80 round process, variables A, B, C, D and E of 32 bits are used. Before performing the 80 round processing on each block data, the variables A to E have predetermined initial values As to Es (when the block data is the first block data) or the 80 round processing on the block data so far. One of the obtained values of the variables A to E (if not the first block data) is set. Then, the operation shown in the following equation (1) is performed 80 times while increasing the variable i by 1 from 0 to 79 in order. At the same time, the value of the variable D is stored in the variable E, and the value of the variable D is stored in the variable D. The value of the variable C is substituted into the variable C by a value obtained by cyclically shifting the value of the variable B to the left by 30 bits, and the value of the variable A is substituted into the variable B.
E = (A << 5) + Fi (B, C, D) + E + Wi + Ki (1)
Here, in the above equation (1), <<<< represents a left cyclic shift, and Fi, Wi, and Ki represent a logical operation in the i-th operation, 32-bit input data, and a 32-bit constant value, respectively. . The details of the SHA1 algorithm are described, for example, in the United States Department of Commerce: “Secure Hash Standard”, National Institute of Standards and Technology, Federal Information Processing Standard (180S, 1917, FIPS. It is described in.
[0013]
The hash function processing device 10 illustrated in FIG. 1 includes registers 101 to 107 and 111 to 115, adders 121 to 129, selectors 130 to 139, cyclic shift operation blocks 141 and 142, and logical operation blocks 151 to 154. . Among these, the adders 126 and 127 constitute the first arithmetic processing unit 161. The adders 128 and 129, the selector 130, the cyclic shift operation block 141, and the logical operation blocks 151 to 154 constitute a second operation processing unit 162.
[0014]
The data width of each of the signal lines shown in FIG. 1 is 32 bits except for the output signal HV of 160 bits. In FIG. 1, control signals and control circuits for controlling round processing in the SHA1 algorithm are omitted for simplification of the drawing. This notation is also applied to FIG. 3 described later.
[0015]
In FIG. 1, registers 101 to 104 store feedback data used in round processing in the SHA1 algorithm. The registers 101 to 104 are also referred to as a first register R1, a second register R2, a third register R3, and a fourth register R4, respectively. The register 105 stores intermediate data when performing round processing in the SHA1 algorithm. The register 106 stores 32-bit input data Wi processed in the round process in the SHA1 algorithm. The input data Wi is either data obtained by dividing original input data to be subjected to hash processing into 32 bits, or data obtained by cyclically shifting the exclusive OR of these four data to the left by one bit. The register 107 stores a predetermined constant value Ki for each round in the round processing in the SHA1 algorithm. Each of the registers 111 to 115 stores a value obtained by performing the 80 round process on the block data so far in the SHA1 algorithm.
[0016]
The adder 121 adds the value of the register 101 and the value of the register 111. The adder 122 adds the value of the register 102 and the value of the register 112. The adder 123 adds the value of the register 103 and the value of the register 113. The adder 124 adds the value of the register 104 and the value of the register 114. The adder 125 adds the value of the register 104 and the value of the register 115. The adder 126 adds the value of the register 106 and the value of the register 107. The adder 127 adds the value of the register 104 and the output of the adder 126. The adder 128 adds the output of the selector 130 and the output of the cyclic shift operation block 141. The adder 129 adds the value of the register 105 and the output of the adder 128.
[0017]
The selector 131 selects and outputs an appropriate value from the initial value As before the round processing in the SHA1 algorithm and the output of the adder 121. The selector 132 selects and outputs an appropriate value from the initial value Bs before the start of the round process in the SHA1 algorithm and the output of the adder 122. The selector 133 selects and outputs an appropriate value from the initial value Cs before the start of the round processing in the SHA1 algorithm and the output of the adder 123. The selector 134 selects and outputs an appropriate value from the initial value Ds before the round processing in the SHA1 algorithm and the output of the adder 124. The selector 135 selects and outputs an appropriate value from the initial value Es before the start of the round process in the SHA1 algorithm and the output of the adder 125.
[0018]
The selector 136 selects and outputs an appropriate value from the value of the register 111 and the output of the adder 129. The selector 137 selects and outputs an appropriate value from the value of the register 112 and the value of the register 101. The selector 138 selects and outputs an appropriate value from the value of the register 113 and the output of the cyclic shift operation block 142. The selector 139 selects and outputs an appropriate value from the value of the register 114, the value of the register 115, and the value of the register 103. The selector 130 selects and outputs an appropriate value from the outputs of the logical operation blocks 151 to 154.
Note that the selectors 130 to 139 select and output appropriate values so that round processing and the like described later can be performed correctly.
[0019]
The cyclic shift operation blocks 141 and 142 perform a cyclic shift operation according to the SHA1 algorithm. More specifically, the cyclic shift operation block 141 cyclically shifts the input to the left by 5 bits. The cyclic shift operation block 142 cyclically shifts the input to the left by 30 bits. Note that the shift direction in the cyclic shift operation blocks 141 and 142 is the left direction when the bits included in the input are arranged such that the left side is higher.
[0020]
The logical operation blocks 151 to 154 perform any one of four types of predetermined logical operations in the round processing in the SHA1 algorithm. Specifically, the logical operation block 151 performs a logical operation in the 0th to 19th rounds. The logical operation block 152 performs a logical operation in the 20th to 39th rounds. The logical operation block 153 performs a logical operation in the 40th to 59th rounds. The logical operation block 154 performs a logical operation in the 60th to 79th rounds. More specifically, the value of the register 102 is X, the value of the register 103 is Y, the value of the register 104 is Z, and the logical operations of logical sum, logical product, negation, and exclusive logical sum are respectively and and or , Not and xor, the logical operation block 151 performs a logical operation of “(XandY) or ((notX) andZ)”.
The logical operation blocks 152 and 154 perform a logical operation of “XxorYxorZ”. The logical operation block 153 performs a logical operation of “(XandY) or (XandZ) or (YandZ)”. Note that the hash function processing device 10 may not include the logical operation block 154, and the logical operation block 152 may perform the logical operation in the 60th to 79th rounds.
[0021]
The hash function processing device 10 first performs pre-hash processing on input data, then performs round processing, and finally performs post-hash processing. In the pre-hash process, a process of setting an appropriate value to a register before handling the first block data is performed. In the round processing, processing of the 0th to 78th rounds in the SHA1 algorithm and round end processing are performed on each block data. In the round end processing, (a) processing of the 79th round in the SHA1 algorithm, (b) processing of adding the value obtained this time and the value obtained up to the previous time, and (c) before processing the next block data A process of setting an appropriate value to each register is performed. However, round end processing is not performed on the last block data. In the post-hash process, the processes (a) and (b) are performed.
[0022]
FIG. 2 is a diagram showing how the values of the registers 101 to 107 and 111 to 115 are changed by the pre-hash processing, the round processing, and the post-hash processing. In FIG. 2, a minus sign indicates that the value of the register is indefinite, and an arrow indicates that the value of the register is the same as the previous clock cycle. This notation is also applied to FIG. 4 described later.
[0023]
Hereinafter, the operation of the hash function processing device 10 will be described with reference to FIG. In the following description, capturing two registers A and B with a certain value in the same clock cycle may be referred to as register A and B simultaneously capturing a value.
[0024]
(1) Hash preprocessing
The hash preprocessing is performed in two clock cycles in a state where the registers 111 to 115 store the initial values (As to Es in FIG. 2) determined by the SHA1 algorithm. In the first clock cycle, the register 104 takes in the value of the register 115 (Es in FIG. 2). At the same time, the registers 101 to 103 take in the values of the registers 111 to 113 (As to Cs in FIG. 2), respectively. At the same time, registers 106 and 107 take in input data and constant values (W0 and K0 in FIG. 2) used in the 0th round, respectively, provided from the outside.
[0025]
Next, in the second clock cycle, the register 105 takes in the output of the adder 127 ((Es + W0 + K0) in FIG. 2). At the same time, the register 104 takes in the value of the register 114 (Ds in FIG. 2). At the same time, the registers 106 and 107 take in input data and constant values (W1 and K1 in FIG. 2) used in the first round supplied from the outside.
[0026]
(2) Round processing
The processing of the 0th to 78th rounds is performed in one clock cycle per round (that is, 79 clock cycles for each block data). In the processing of the 0th to 78th rounds, the register 104 takes in the value of the register 103 in each clock cycle. At the same time, the register 103 takes in the output of the cyclic shift operation block 142. At the same time, the register 102 captures the value of the register 101. At the same time, the register 101 takes in the output of the adder 129. At the same time, the register 105 takes in the output of the adder 127. At the same time, registers 106 and 107 take in the next input data and constant value respectively given from outside. However, in the process of the 78th round, the registers 106 and 107 may take in arbitrary values.
[0027]
As an example, the processing of the fifth round shown in FIG. 2 will be described. When the values obtained in the processing of the 0th to 4th rounds are E0, D0, C0, B0, and A0, respectively, the values of the registers 101 to 104 are A0 to D0 when the processing of the fourth round is completed. , The value of the register 105 is (E0 + W5 + K5), the value of the register 106 is W6, and the value of the register 107 is K6. Therefore, in the processing of the fifth round, the register 104 captures the value C0 of the register 103. At the same time, the register 103 takes in a value obtained by cyclically shifting the value B0 of the register 102 to the left by 30 bits (in FIG. 2, described as B0 before cyclic shift; hereinafter, the same notation is used). At the same time, the register 102 takes in the value A0 of the register 101. At the same time, the register 101 takes in the output E1 of the adder 129. Here, E1 is a value obtained by substituting A0 to E0 for A to E, W5 for Wi, and K5 for Ki in equation (1). At the same time, the register 105 takes in the output (D0 + W6 + K6) of the adder 127. At the same time, the registers 106 and 107 take in the next input data W7 and the next constant value K7, respectively.
[0028]
On the other hand, the round termination processing is performed over four clock cycles for each block data. In the first clock cycle, the register 115 takes in the output of the adder 125 (Em in FIG. 2). At the same time, the register 104 takes in the value of the register 103 (D15 in FIG. 2). At the same time, the register 103 takes in the output of the cyclic shift operation block 142 (C15 in FIG. 2). At the same time, the register 102 takes in the value of the register 101 (B15 in FIG. 2). At the same time, the register 101 takes in the output of the adder 129 (A15 in FIG. 2).
[0029]
Next, in the second clock cycle, the registers 111 to 114 take in the outputs (Am to Dm in FIG. 2) of the adders 121 to 124, respectively. Note that the registers 101 to 104 may take in an arbitrary value, and here it is assumed that the register holds the value of the immediately preceding clock cycle.
[0030]
Next, in the third clock cycle, the registers 101 to 103 take in the values (Am to Cm in FIG. 2) of the registers 111 to 113, respectively. At the same time, the register 104 takes in the value of the register 115 (Em in FIG. 2). At the same time, registers 106 and 107 take in input data and constant values (W0 and K0 in FIG. 2) used in the 0th round, respectively, provided from the outside.
[0031]
Next, in the fourth clock cycle, the register 105 takes in the output of the adder 127 ((Em + W0 + K0) in FIG. 2). At the same time, the register 104 takes in the value of the register 114 (Dm in FIG. 2). At the same time, the registers 106 and 107 take in input data and constant values (W1 and K1 in FIG. 2) used in the first round supplied from the outside. Note that the input data taken into the register 106 in the third and fourth clock cycles is data included in the next block data.
[0032]
(3) Hash post-processing
Post-hash processing is performed over two clock cycles. In the first clock cycle, the register 115 takes in the output of the adder 125 (Ee in FIG. 2). At the same time, the register 104 takes in the value of the register 103 (D15 in FIG. 2). At the same time, the register 103 takes in the output of the cyclic shift operation block 142 (C15 in FIG. 2). At the same time, the register 102 takes in the value of the register 101 (B15 in FIG. 2). At the same time, the register 101 takes in the output of the adder 129 (A15 in FIG. 2).
[0033]
Next, in the second clock cycle, the registers 111 to 114 take in the outputs (Ae to De in FIG. 2) of the adders 121 to 124, respectively. Note that the registers 101 to 104 may take in an arbitrary value, and here it is assumed that the register holds the value of the immediately preceding clock cycle.
[0034]
When the second clock cycle is completed, the values (Ae to Ee in FIG. 2) stored in the registers 111 to 115 are hash values to be obtained. Therefore, a hash value for the entire input data can be obtained by reading the values of the registers 111 to 115 using means (not shown).
[0035]
Before the second clock cycle is completed, the output of the register 115 and the adders 121 to 124 (the output signal HV shown in FIG. 1) matches the hash value to be obtained. Therefore, a 160-bit register is provided outside the hash function processing apparatus 10, and the provided register takes in the output signal HV at this time, whereby a hash value for the entire input data can be obtained.
[0036]
Hereinafter, the effects provided by the hash function processing device 10 will be described. As shown in Expression (1), in round processing in the SHA1 algorithm, input data and constant values do not depend on feedback data. Therefore, the operation shown in Expression (1) can be decomposed into two operations as shown in Expressions (2) and (3) below. However, in equations (2) and (3), Q is a 32-bit variable.
Q = E + Wi + Ki (2)
E = (A << 5) + Fi (B, C, D) + Q (3)
[0037]
Correspondingly, the hash function processing device 10 includes a first arithmetic processing unit 161 that performs the arithmetic processing shown in Expression (2) and a second arithmetic processing unit 162 that performs the arithmetic processing shown in Expression (3). And a register 105 for storing the output of the first arithmetic processing unit 161. The first arithmetic processing unit 161 and the second arithmetic processing unit 162 operate in parallel, and the output of the second arithmetic processing unit 162 is supplied from the register 105 or the like. Thus, the first arithmetic processing unit 161, the second arithmetic processing unit 162, and the register 105 perform two-stage pipeline processing. Further, in order to supply data to the pipeline at an appropriate timing, the input data Wi and the constant value Ki used in each round are read one clock cycle before the timing at which they should be read.
[0038]
In addition, the hash function processing device 10 includes four registers 101 to 104 for storing feedback data and one register 105 for storing an intermediate result of an operation in order to perform round processing in the SHA1 algorithm. . That is, the hash function processing device 10 also uses one of the five registers for storing the feedback data as the register for storing the intermediate result of the operation. Therefore, according to the hash function processing device 10, it is possible to perform the same pipeline processing as that of the related art using a smaller number of registers than in the related art.
[0039]
As described above, according to the hash function processing device according to the present embodiment, the round processing in the SHA1 algorithm can be executed at a high speed with one clock cycle per round apparently using less hardware resources than in the past. Can be.
[0040]
(Second embodiment)
FIG. 3 is a logic circuit diagram of the hash function processing device according to the second embodiment of the present invention. The hash function processing device 20 shown in FIG. 3 is obtained by changing a part of a circuit included in the hash function processing device 10 according to the first embodiment. The hash function processing device 20 shown in FIG. 3 includes registers 201 to 207 and 211 to 215, adders 221 to 229, selectors 230 to 239, cyclic shift operation blocks 241 and 242, and logical operation blocks 251 to 254. . Among them, the adders 226 and 227 constitute a first arithmetic processing unit 261. The adders 228 and 229, the selector 230, the cyclic shift operation block 241, and the logical operation blocks 251 to 254 constitute a second operation processing unit 262.
[0041]
The circuit configuration of the hash function processing device 20 is different from the circuit configuration of the hash function processing device 10 according to the first embodiment in the following four points. First, the selector 236 selects and outputs an appropriate value from the value of the register 211, the output of the adder 229, and the output of the adder 221. Second, the selector 237 selects and outputs an appropriate value from the value of the register 212, the value of the register 201, and the output of the adder 222. Third, the selector 238 selects and outputs an appropriate value from the value of the register 213, the output of the cyclic shift operation block 242, and the output of the adder 223. The selector 239 selects and outputs an appropriate value from the value of the register 214, the value of the register 215, the value of the register 203, and the output of the adder 225.
[0042]
The hash function processing device 20 first performs pre-hash processing, then performs round processing, and finally performs post-hash processing on input data, similarly to the hash function processing device 10 according to the first embodiment. . The contents of these three processes are the same as those of the hash function processing device 10. FIG. 4 is a diagram showing how the values of the registers 201 to 207 and 211 to 215 change by these three processes. Hereinafter, the operation of the hash function processing device 20 will be described with reference to FIG.
[0043]
(1) Hash preprocessing
The pre-hash processing in the hash function processing device 20 is the same as the processing in the hash function processing device 10 according to the first embodiment.
[0044]
(2) Round processing
The processes in the 0th to 78th rounds in the hash function processing device 20 are the same as those in the hash function processing device 10 according to the first embodiment. The processing of the 0th to 78th rounds is performed in one clock cycle per round (that is, 79 clock cycles for each block data).
[0045]
On the other hand, the round termination processing is performed by taking two clock cycles for each block data. In the first clock cycle, both registers 204 and 215 capture the output of adder 225 (Em in FIG. 4). At the same time, the register 214 takes in the output of the adder 224 (Dm in FIG. 4). At the same time, the register 203 takes in the output (C15 in FIG. 4) of the cyclic shift operation block 242. At the same time, the register 202 takes in the value of the register 201 (B15 in FIG. 4). At the same time, the register 201 takes in the output of the adder 229 (A15 in FIG. 4). At the same time, the registers 206 and 207 take in input data and constant values (W0 and K0 in FIG. 4) which are used from the outside in the 0th round, respectively.
[0046]
Next, in the second clock cycle, the registers 201 and 211 both take in the output of the adder 221 (Am in FIG. 4). At the same time, both the registers 202 and 212 take in the output of the adder 222 (Bm in FIG. 4).
At the same time, both the registers 203 and 213 take in the output of the adder 223 (Cm in FIG. 4). At the same time, the register 204 takes in the value of the register 214 (Dm in FIG. 4). At the same time, the register 205 takes in the output of the adder 227 ((Em + W0 + K0) in FIG. 4). At the same time, the registers 206 and 207 fetch input data and constant values (W1 and K1 in FIG. 4) used in the 0th round, respectively, provided from the outside. The input data taken into the register 206 in the first and second clock cycles is data included in the next block data.
[0047]
(3) Hash post-processing
Post-hash processing is performed over two clock cycles. In the first clock cycle, registers 214 and 215 capture the outputs of adders 224 and 225 (De and Ee in FIG. 4). At the same time, the register 203 takes in the output (C15 in FIG. 4) of the cyclic shift operation block 242. The register 202 takes in the value of the register 201 (B15 in FIG. 4). At the same time, the register 201 takes in the output of the adder 229 (A15 in FIG. 4). The register 204 may take in an arbitrary value. Here, it is assumed that the register 204 takes in the output of the adder 225.
[0048]
Next, in the second clock cycle, the registers 211 to 213 take in the outputs (Ae to Ce in FIG. 4) of the adders 221 to 223, respectively. The registers 201 to 204 may take in arbitrary values. Here, it is assumed that the register 204 takes in the value of the register 214 and the registers 201 to 203 take in the outputs of the adders 221 to 223, respectively.
[0049]
When the second clock cycle is completed, the values (Ae to Ee in FIG. 4) stored in the registers 211 to 215 are hash values to be obtained. Therefore, by reading the values of the registers 211 to 215 using means (not shown) (or by reading the value of the output signal HV in the second clock cycle of the post-hash processing by an externally provided register), A hash value for the whole can be obtained.
[0050]
As described above, the hash function processing device 20 can correctly execute the round process in the SHA1 algorithm, despite being different from the hash function processing device 10 according to the first embodiment in the above-described four points. Further, the hash function processing device 10 according to the first embodiment performs the round termination process over four clock cycles, whereas the hash function processing device 20 performs the round termination process over two clock cycles. .
[0051]
From the above, according to the hash function processing device according to the present embodiment, in addition to the effects achieved by the hash function processing device according to the first embodiment, the number of clock cycles required for round termination processing is reduced, and round processing is performed. There is an effect that execution can be performed at higher speed.
[0052]
Note that the hash function processing device of the present invention may be any device that performs the processes of the 0th to 78th rounds by the above-described pipeline process, and may constitute a modified example other than the devices described in the above embodiments. it can. For example, regarding the hash function processing device 10 according to the first embodiment, the timings for setting the initial values As to Es in the registers 111 to 115, the registers 101 to 104 in the pre-hash processing, the round end processing, and the post-hash processing Various designs are possible for the update timing, the update timing of the registers 111 to 115, the values set in the registers that can take in arbitrary values, and the like. The same applies to the hash function processing device 20 according to the second embodiment.
[0053]
Further, in each of the above embodiments, SHA1 is used as the hash function, but it goes without saying that another algorithm may be used as the hash function.
[Brief description of the drawings]
FIG. 1 is a logic circuit diagram of a hash function processing device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a state where a value of a register included in the hash function processing device according to the first embodiment of the present invention changes.
FIG. 3 is a logic circuit diagram of a hash function processing device according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating a state where a value of a register included in a hash function processing device according to a second embodiment of the present invention changes.
[Explanation of symbols]
10, 20 ... Hash function processing device
101-107, 111-115, 201-207, 211-215 ... registers
121-129, 221-229 ... adder
130-139, 230-239 ... selector
141, 142, 241, 242 ... cyclic shift operation block
151-154, 251-254 ... Logical operation block
161, 261: first arithmetic processing unit
162, 262: second arithmetic processing unit

Claims (4)

A hash function processing device that performs iterative processing defined by a hash function on input data,
First to fourth registers for storing feedback data;
An input data supply unit for supplying input data of a predetermined length,
A constant value supply unit that supplies a constant value determined by a hash function,
A first arithmetic processing unit that performs predetermined arithmetic processing on the value of the fourth register, input data supplied from the input data supply unit, and a constant value supplied from the constant value supply unit When,
An intermediate value storage register for storing a calculation result by the first calculation processing unit;
A second arithmetic processing unit that performs predetermined arithmetic processing on the values of the first to fourth registers and the value of the intermediate value storage register;
The first and second arithmetic processing units operate in parallel, and the intermediate value storage register fetches the operation result by the first arithmetic processing unit, and the first register performs the second arithmetic operation. An operation of capturing the operation result by the processing unit, an operation of the second register capturing the value of the first register, and an operation of the third register capturing a value obtained by cyclically shifting the value of the second register. An operation in which the fourth register acquires the value of the third register, an operation in which the input data supply unit acquires the next input data, and an operation in which the constant value supply unit acquires the next constant value. A hash function processing device, wherein the hash function processing is performed in parallel within one clock cycle. The first arithmetic processing unit adds the value of the fourth register, input data supplied from the input data supply unit, and a constant value supplied from the constant value supply unit. The hash function processing device according to claim 1, wherein The second operation processing unit performs a predetermined logical operation on the values of the second to fourth registers, and calculates the operation result, the value of the intermediate value storage register, and the value of the first register. The hash function processing device according to claim 1, wherein a value obtained by cyclically shifting is added. The hash function processing device according to any one of claims 1 to 3, wherein the hash function is SHA1 (The Secure Hash Algorithm 1).

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