JP2004240298A - Hash function processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a high speed round processing in a hash function using less number of hardware resources. <P>SOLUTION: In the round processing in an MD5 algorithm, input data and constant values are not dependent on feed back data. Considering this point, two-stage pipeline processing is performed by first and second processing parts 361 and 362, and a register 305. To supply the pipeline with data at an appropriate timing, the input data X and constant value T are read one clock cycle prior to the timing originally to read. The two-stage pipeline processing enables high speed round processing in the hash function apparently in one clock cycle per round. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a hash function processing device, and more particularly, to obtain a fixed-length value (hash value) that is difficult to reverse-transform from arbitrary-length data in order to protect security in the field of information communication and the like. The present invention relates to a hash function processing device.
[0002]
[Prior art]
In recent years, broadband IP (Internet Protocol) infrastructures represented by FTTH (Fiber To The Home) and ADSL (Asymmetric Digital Subscriber Line) have become widespread in homes and the like. Along with this, demands for security techniques, such as prevention of message tampering, have been increasing even on IP transmission paths that require high speed. As a typical example of the message tampering prevention technique, for example, a method using a hash function is known. The hash function is a function for obtaining a fixed-length value (hereinafter, referred to as a hash value) unique to a message of an arbitrary length. The hash value obtained by using the hash function has extremely high randomness. That is, different hash values are obtained with extremely high probability for different messages. A hash function having such characteristics can be used as a means for detecting tampering of a message.
[0003]
Conventionally, as a processing device for a hash function, for example, a processing device described in Patent Literature 1 is known. In this processing device, a circuit unit divided into a plurality of stages is configured by interposing a register in a flow direction of processing data processed by a plurality of stages of arithmetic units. In addition, this processing apparatus performs at least the following steps while performing a calculation process in the calculator using the output data from the rotation processing unit and the feedback data of one cycle before using the bit replacement process for the input data by the rotation processing unit. The present invention is characterized in that arithmetic processing on input data of a cycle and output data from a set number of parts are performed in an overlapping manner.
[0004]
[Patent Document 1]
JP-A-2002-72879
[0005]
[Problems to be solved by the invention]
However, in the above-described conventional processing apparatus, two clock cycles are required per round at the highest speed in order to perform the repetition processing (hereinafter, round processing) in the hash function. For this reason, the conventional processing apparatus is not suitable for applications requiring high-speed processing. Further, in order to realize the overlap processing, it is necessary to divide the pipeline processing into a plurality of stages, and a large number of hardware resources such as registers are required. As described above, the above-described conventional processing apparatus also has a problem that the circuit scale is increased and the cost is increased.
[0006]
Therefore, an object of the present invention is to provide a hash function processing device that executes round processing in a hash function at high speed with one clock cycle per round. Another object of the present invention is to provide a hash function processing device that executes round processing in a hash function at high speed using a small amount of hardware resources.
[0007]
Means for Solving the Problems and Effects of the Invention
A first invention is a hash function processing device that performs iterative processing defined by a hash function on input data, the first to fourth registers storing feedback data, and input data having a predetermined length. An input data supply unit for supplying, a constant value supply unit for supplying a constant value determined by the hash function, a value of the first register, input data supplied from the input data supply unit, and a constant value supply unit. A first arithmetic processing unit that performs a predetermined arithmetic processing on the supplied constant value, an intermediate value storage register that stores an arithmetic result of the first arithmetic processing unit, and a second to a fourth register. A second arithmetic processing unit for performing predetermined arithmetic processing on the value and the value of the intermediate value storage register, wherein the first and second arithmetic processing units operate in parallel and store the intermediate value. Register is the first operation An operation of taking in the operation result by the control unit, an operation of the second register taking in the operation result of the second operation processing unit, an operation of taking in the value of the second register by the third register, and the first and fourth registers. Of the third register, the operation of the input data supply unit to acquire the next input data, and the operation of the constant value supply unit to acquire the next constant value within one clock cycle. Are performed in parallel.
According to the first aspect, the first and second arithmetic circuits operate in parallel, the output of the first arithmetic circuit is written to the intermediate value storage register, and the input of the second arithmetic circuit is the intermediate value. It is supplied from a value storage register or the like. Thus, two-stage pipeline processing is performed by the first and second arithmetic circuits and the intermediate value storage register. Further, in order to supply data to the pipeline at an appropriate timing, input data and a constant value used in the repetitive processing are acquired one clock cycle before the timing at which the data should be acquired. Therefore, the iterative process in the hash function can be executed at a high speed with one clock cycle per round in appearance.
[0008]
A second invention is a hash function processing device that performs iterative processing defined by a hash function on input data, the first to third registers storing feedback data, and a predetermined length of input data. An input data supply unit for supplying, a constant value supply unit for supplying a constant value determined by the hash function, a value of the first register, input data supplied from the input data supply unit, and a constant value supply unit. A first arithmetic processing unit that performs a predetermined arithmetic processing on the supplied constant value, an intermediate value storage register that stores an arithmetic result of the first arithmetic processing unit, and a first to a third register. A second arithmetic processing unit for performing predetermined arithmetic processing on the value and the value of the intermediate value storage register, wherein the first and second arithmetic processing units operate in parallel and store the intermediate value. Register is the first operation The second register takes in the operation result of the second operation processing unit, the third register takes in the value of the second register, and the first register takes the value of the second register. The operation of capturing the value of the third register, the operation of the input data supply unit acquiring the next input data, and the operation of the constant value supply unit acquiring the next constant value are performed in parallel within one clock cycle. It is characterized by being performed.
According to the second aspect, the first and second arithmetic circuits operate in parallel, the output of the first arithmetic circuit is written to the intermediate value storage register, and the input of the second arithmetic circuit is intermediate. It is supplied from a value storage register or the like. Thus, two-stage pipeline processing is performed by the first and second arithmetic circuits and the intermediate value storage register. Further, in order to supply data to the pipeline at an appropriate timing, input data and a constant value used in the repetitive processing are acquired one clock cycle before the timing at which the data should be acquired. Therefore, the iterative process in the hash function can be executed at a high speed with one clock cycle per round in appearance. In addition to this, the number of registers for storing feedback data can be reduced, and iterative processing in the hash function can be executed at high speed using a small amount of hardware resources.
[0009]
In a third aspect based on the first or second aspect, the first arithmetic processing unit is configured to receive the value of the first register, the input data supplied from the input data supply unit, and the input data supplied from the constant value supply unit. And a constant value.
[0010]
In a fourth aspect based on the first aspect, the second arithmetic processing section performs a predetermined logical operation on the values of the second to fourth registers, and stores the arithmetic result and the value of the intermediate value storage register. Is cyclically shifted by a predetermined number of bits and then added to the value of the second register.
[0011]
In a fifth aspect based on the second aspect, the second arithmetic processing unit performs a predetermined logical operation on the values of the first to third registers, and calculates a result of the arithmetic operation with the value of the intermediate value storage register. Is cyclically shifted by a predetermined number of bits and then added to the value of the second register.
[0012]
According to a sixth aspect, in any one of the first to fifth aspects, the hash function is MD5 (Message Digest 5).
According to the third to sixth aspects, the repetitive processing in the MD5 algorithm can be executed at a high speed with one clock cycle per round in appearance.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a logic circuit diagram of the hash function processing device according to the first embodiment of the present invention. The hash function processing device 10 illustrated in FIG. 1 performs a round process in Message Digest 5 (hereinafter, referred to as MD5), which is a type of hash function. MD5 is a function for obtaining a 128-bit hash value from input data of an arbitrary length. In the MD5 algorithm, input data is divided into 512 bits at a time from the beginning. Then, the following processing (hereinafter, referred to as 64 round processing) is sequentially performed on each divided input data (hereinafter, referred to as block data).
[0014]
In the 64-round process, variables A, B, C, and D of 32 bits are used. Before performing the 64-round processing on each block data, the variables A to D have predetermined initial values As to Ds (when the block data is the first block data) or the variables A to D in the 64-round processing on the block data so far. One of the obtained values of the variables A to D (when the data is not the first block data) is set. Then, the operation shown in the following equation (1) is performed 64 times while the variable i is sequentially increased from 0 to 63 in steps of one.
α = β + ((α + Fi (β, γ, Δ) + Xi + Ti) <<<< Si) (1)
Here, in the equation (1), <<<< indicates a left cyclic shift, and Fi, Xi, Ti, and Si represent a logical operation, a 32-bit input data, a 32-bit constant value, and a logical operation in the i-th operation, respectively. Indicates the shift number. Α to Δ are A, B, C, and D in order when the remainder j obtained by dividing i by 4 is 0, and D, A, B, and in order when j is 1. If it is C and j is 2, then it is C, D, A, B in order, and if j is 3, it is B, C, D, A in order.
[0015]
Hereinafter, the i-th operation using Expression (1) is referred to as an i-th round process. After the 63rd round of processing is completed for each block data, the values of the variables A to D are added to the values of the variables A to D obtained by the 64 round processing on the block data so far. When 64 rounds of processing are performed on all block data included in the input data, the result obtained by the final addition becomes the hash value to be obtained. The details of the MD5 algorithm are described in, for example, R. Rivest, "The MD5 Message Digest Algorithm", IETF RFC 1321, 1992. It is described in.
[0016]
The hash function processing device 10 shown in FIG. 1 includes registers 101 to 107 and 111 to 114, adders 121 to 128, selectors 131 to 139, a cyclic shift operation block 141, and logical operation blocks 151 to 154. Among them, the adders 125 and 126 constitute the first arithmetic processing unit 161. Further, the adders 127 and 128, the selector 139, the cyclic shift operation block 141, and the logical operation blocks 151 to 154 constitute a second operation processing unit 162.
[0017]
The data width of each of the signal lines shown in FIG. 1 is 32 bits except for the output signal HV of 128 bits. In FIG. 1, control signals and control circuits for controlling round processing in the MD5 algorithm are omitted for simplification of the drawing. This notation is also applied to FIGS. 3, 5, and 7 described below.
[0018]
In FIG. 1, registers 101 to 104 store feedback data used in round processing in the MD5 algorithm. The registers 101 to 104 are also referred to as a first register R1, a fourth register R4, a third register R3, and a second register R2, respectively. The register 105 stores intermediate data when performing round processing in the MD5 algorithm. The register 106 stores the input data Xi divided into 32 bits each, which is processed by the round processing in the MD5 algorithm. The register 107 stores a predetermined constant value Ti for each round in the round processing in the MD5 algorithm. Each of the registers 111 to 114 stores a value obtained by 64-round processing on the block data so far in the MD5 algorithm.
[0019]
The adder 121 adds the value of the register 101 and the value of the register 111. The adder 122 adds the value of the register 102 and the value of the register 112. The adder 123 adds the value of the register 103 and the value of the register 113. The adder 124 adds the value of the register 104 and the value of the register 114. The adder 125 adds the value of the register 106 and the value of the register 107. The adder 126 adds the value of the register 101 and the output of the adder 125. The adder 127 adds the value of the register 105 and the output of the selector 139. The adder 128 adds the value of the register 104 and the output of the cyclic shift operation block 141.
[0020]
The selector 131 selects and outputs an appropriate value from the initial value As before the round process in the MD5 algorithm and the output of the adder 121. The selector 132 selects and outputs an appropriate value from the initial value Ds before the start of the round process in the MD5 algorithm and the output of the adder 122. The selector 133 selects and outputs an appropriate value from the initial value Cs before the start of the round process in the MD5 algorithm and the output of the adder 123. The selector 134 selects and outputs an appropriate value from the initial value Bs before the start of the round processing in the MD5 algorithm and the output of the adder 124.
[0021]
The selector 135 selects and outputs an appropriate value from the value of the register 111, the value of the register 102, and the value of the register 103. The selector 136 selects and outputs an appropriate value from the value of the register 112 and the value of the register 103. The selector 137 selects and outputs an appropriate value from the value of the register 113 and the value of the register 104. The selector 138 selects and outputs an appropriate value from the value of the register 114 and the output of the adder 128. The selector 139 selects and outputs an appropriate value from the outputs of the logical operation blocks 151 to 154. The selectors 131 to 139 select and output appropriate values so that round processing and the like described later can be performed correctly.
[0022]
The cyclic shift operation block 141 performs a cyclic shift operation according to the MD5 algorithm. More specifically, the cyclic shift operation block 141 cyclically shifts the input to the left by a value designated for each round in the round processing in the MD5 algorithm. Note that the shift direction in the cyclic shift operation block 141 is the left direction when the bits included in the input are arranged such that the left side is higher.
[0023]
The logical operation blocks 151 to 154 perform any one of four types of predetermined logical operations in the round processing in the MD5 algorithm. Specifically, the logical operation block 151 performs a logical operation in the 0th to 15th rounds. The logical operation block 152 performs a logical operation in the 16th to 31st rounds. The logical operation block 153 performs a logical operation in the 32nd to 47th rounds. The logical operation block 154 performs a logical operation in the 48th to 63rd rounds. More specifically, the value of the register 104 is X, the value of the register 103 is Y, the value of the register 102 is Z, and the logical operations of logical sum, logical product, negation, and exclusive logical sum are respectively, and, or , Not and xor, the logical operation block 151 performs a logical operation of “(XandY) or ((notX) andZ)”. The logical operation block 152 performs a logical operation of “(XandZ) or (Yand (notZ))”. The logical operation block 153 performs a logical operation “XxorYxorZ”. The logical operation block 154 performs a logical operation of “Yxor (Xor (notZ))”.
[0024]
The hash function processing device 10 first performs pre-hash processing on input data, then performs round processing, and finally performs post-hash processing. In the pre-hash process, a process of setting an appropriate value to a register before handling the first block data is performed. In the round processing, the processing of the 0th to 62nd rounds in the MD5 algorithm and the round end processing are performed on each block data. In the round end processing, (a) processing of the 63rd round in the MD5 algorithm, (b) processing of adding the value obtained this time to the value obtained up to the previous time, and (c) before processing the next block data A process of setting an appropriate value to each register is performed. However, round end processing is not performed on the last block data. In the post-hash process, the processes (a) and (b) are performed.
[0025]
FIG. 2 is a diagram illustrating how the values of the registers 101 to 107 and 111 to 114 are changed by the pre-hash processing, the round processing, and the post-hash processing. In FIG. 2, a minus sign indicates that the value of the register is indefinite, and an arrow indicates that the value of the register is the same as the previous clock cycle. This notation is also applied to FIGS. 4, 6 and 8 described later.
[0026]
Hereinafter, the operation of the hash function processing device 10 will be described with reference to FIG. In the following description, capturing two registers A and B with a certain value in the same clock cycle may be referred to as register A and B simultaneously capturing a value.
[0027]
(1) Hash preprocessing
The hash preprocessing is performed in two clock cycles in a state where the registers 111 to 114 store initial values (As and Ds to Bs in FIG. 2) determined by the MD5 algorithm. In the first clock cycle, the registers 101 to 104 take in the values of the registers 111 to 114 (As and Ds to Bs in FIG. 2), respectively. At the same time, registers 106 and 107 fetch input data and constant values (X0 and T0 in FIG. 2) used in the 0th round provided from the outside, respectively.
[0028]
Next, in the second clock cycle, the register 105 takes in the output of the adder 126 ((As + X0 + T0) in FIG. 2). At the same time, the register 101 takes in the value of the register 102 (Ds in FIG. 2). At the same time, registers 106 and 107 take in input data and constant values (X1 and T1 in FIG. 2) used in the first round, respectively, provided from the outside.
[0029]
(2) Round processing
The processing of the 0th to 62nd rounds is performed by taking one clock cycle per round (that is, by taking 63 clock cycles for each block data). In the processing of the 0th to 62nd rounds, each of the registers 101 and 102 takes in the value of the register 103 in each clock cycle. At the same time, the register 103 captures the value of the register 104. At the same time, the register 104 captures the output of the adder 128. At the same time, the register 105 captures the output of the adder 126. At the same time, registers 106 and 107 take in the next input data and constant value respectively given from outside. However, in the processing of the 62nd round, the registers 106 and 107 may take in arbitrary values.
[0030]
As an example, the processing of the fourth round shown in FIG. 2 will be described. When the values obtained in the processing of the 0th to third rounds are A0, D0, C0, and B0 in order, the value of the registers 101 and 102 is D0 and the value of the register 103 when the processing of the third round is completed. Is C0, the value of the register 104 is B0, the value of the register 105 is (A0 + X4 + T4), the value of the register 106 is X5, and the value of the register 107 is T5. Therefore, in the processing of the fourth round, both the registers 101 and 102 take in the value C0 of the register 103. At the same time, the register 103 takes in the value B0 of the register 104. At the same time, the register 104 takes in the output A1 of the adder 128. Here, A1 is a value obtained by substituting A0 to D0 for α to Δ, X4 for Xi, and T4 for Ti in equation (1). At the same time, the register 105 takes in the output (D0 + X5 + T5) of the adder 126. At the same time, the registers 106 and 107 take in the next input data X6 and the next constant value T6, respectively.
[0031]
On the other hand, the round termination processing is performed over four clock cycles for each block data. In the first clock cycle, the register 111 takes in the output of the adder 121 (Am in FIG. 2). At the same time, registers 102 and 103 take in the values of registers 103 and 104, respectively (D15 and C15 in FIG. 2). At the same time, the register 104 takes in the output of the adder 128 (B15 in FIG. 2). Note that the register 101 may take in an arbitrary value. Here, it is assumed that the value of the register 103 is taken in.
[0032]
Next, in the second clock cycle, the registers 112 to 114 take in the outputs (Dm to Bm in FIG. 2) of the adders 122 to 124, respectively. Note that the registers 101 to 104 may take in an arbitrary value, and here it is assumed that the register holds the value of the immediately preceding clock cycle.
[0033]
Next, in the third clock cycle, the registers 101 to 104 take in the values (Am and Dm to Bm in FIG. 2) of the registers 111 to 114, respectively. At the same time, registers 106 and 107 fetch input data and constant values (X0 and T0 in FIG. 2) used in the 0th round provided from the outside, respectively.
[0034]
Next, in the fourth clock cycle, the register 105 takes in the output of the adder 126 ((Am + X0 + T0) in FIG. 2). At the same time, the register 101 takes in the value of the register 102 (Dm in FIG. 2). At the same time, registers 106 and 107 take in input data and constant values (X1 and T1 in FIG. 2) used in the first round, respectively, provided from the outside. Note that the input data taken into the register 106 in the third and fourth clock cycles is data included in the next block data.
[0035]
(3) Hash post-processing
Post-hash processing is performed over two clock cycles. In the first clock cycle, the register 111 takes in the output of the adder 121 (Ae in FIG. 2). At the same time, registers 102 and 103 take in the values of registers 103 and 104, respectively (D15 and C15 in FIG. 2). At the same time, the register 104 takes in the output of the adder 128 (B15 in FIG. 2). Note that the register 101 may take in an arbitrary value. Here, it is assumed that the value of the register 103 is taken in.
[0036]
Next, in the second clock cycle, the registers 112 to 114 take in the outputs (De to Be in FIG. 2) of the adders 122 to 124, respectively. Note that the registers 101 to 104 may take in an arbitrary value, and here it is assumed that the register holds the value of the immediately preceding clock cycle.
[0037]
At the time when the second clock cycle is completed, the values (Ae and De to Be in FIG. 2) stored in the registers 111 to 114 are hash values to be obtained. Therefore, a hash value for the entire input data can be obtained by reading the values of the registers 111 to 114 using means (not shown).
[0038]
Before the second clock cycle is completed, the outputs of the register 111 and the adders 122 to 124 (the output signal HV shown in FIG. 1) match the hash value to be obtained. Therefore, a 128-bit register is provided outside the hash function processing device 10, and the provided register takes in the output signal HV at this time, whereby a hash value for the entire input data can be obtained.
[0039]
Hereinafter, the effects provided by the hash function processing device 10 will be described. As shown in Expression (1), in round processing in the MD5 algorithm, input data and constant values do not depend on feedback data. Therefore, the operation shown in Expression (1) can be decomposed into two operations as shown in Expressions (2) and (3) below. However, in equations (2) and (3), Q is a 32-bit variable.
Q = α + Xi + Ti (2)
α = β + ((Q + Fi (β, γ, Δ)) <<<< Si) (3)
[0040]
Correspondingly, the hash function processing device 10 includes a first arithmetic processing unit 161 that performs the arithmetic processing shown in Expression (2) and a second arithmetic processing unit 162 that performs the arithmetic processing shown in Expression (3). And a register 105 for storing the output of the first arithmetic processing unit 161. Further, the first arithmetic processing unit 161 and the second arithmetic processing unit 162 operate in parallel, and the input of the second arithmetic processing unit 162 is supplied from the register 105. Thus, the first arithmetic processing unit 161, the second arithmetic processing unit 162, and the register 105 perform two-stage pipeline processing. Also, in order to supply data to the pipeline at an appropriate timing, the input data Xi and the constant value Ti used in each round are read one clock cycle before the timing at which they should be read. Furthermore, the hash function processing device 10 also has a path for directly writing the value of the register 103 to the register 101 without passing through the register 102 so that data is correctly supplied during the round processing.
[0041]
As described above, according to the hash function processing device according to the present embodiment, the round processing of the MD5 algorithm can be executed at a high speed in one clock cycle per apparently by performing two-stage pipeline processing. Can be.
[0042]
(Second embodiment)
FIG. 3 is a logic circuit diagram of the hash function processing device according to the second embodiment of the present invention. The hash function processing device 20 shown in FIG. 3 is obtained by changing a part of a circuit included in the hash function processing device 10 according to the first embodiment. The hash function processing device 20 includes registers 201 to 207 and 211 to 214, adders 221 to 228, selectors 231 to 239, a cyclic shift operation block 241, and logical operation blocks 251 to 254. Among them, the adders 225 and 226 constitute the first arithmetic processing unit 261. The adders 227 and 228, the selector 239, the cyclic shift operation block 241, and the logical operation blocks 251 to 254 constitute a second operation processing unit 262.
[0043]
The circuit configuration of the hash function processing device 20 is different from the circuit configuration of the hash function processing device 10 according to the first embodiment in the following four points. First, the selector 235 selects and outputs an appropriate value from the value of the register 211, the value of the register 202, the value of the register 203, the output of the adder 221, and the output of the adder 222. . Second, the selector 236 selects and outputs an appropriate value from the value of the register 212, the value of the register 203, and the output of the adder 222. Third, the selector 237 selects and outputs an appropriate value from the value of the register 213, the value of the register 204, and the output of the adder 223. Fourth, the selector 238 selects and outputs an appropriate value from the value of the register 214, the output of the adder 228, and the output of the adder 224. The other components of the hash function processing device 20 are the same as those of the hash function processing device 10, and a description thereof will be omitted.
[0044]
The hash function processing device 20 first performs pre-hash processing, then performs round processing, and finally performs post-hash processing on input data, similarly to the hash function processing device 10 according to the first embodiment. . The contents of these three processes are the same as those of the hash function processing device 10. FIG. 4 is a diagram showing how the values of the registers 201 to 207 and 211 to 214 are changed by these three processes. Hereinafter, the operation of the hash function processing device 20 will be described with reference to FIG.
[0045]
(1) Hash preprocessing
The pre-hash processing in the hash function processing device 20 is the same as the processing in the hash function processing device 10 according to the first embodiment.
[0046]
(2) Round processing
The processes in the 0th to 62nd rounds in the hash function processing device 20 are the same as those in the hash function processing device 10 according to the first embodiment. The processing of the 0th to 62nd rounds is performed by taking one clock cycle per round (that is, by taking 63 clock cycles for each block data).
[0047]
On the other hand, the round termination processing is performed by taking two clock cycles for each block data. In the first clock cycle, both the registers 201 and 211 take in the output of the adder 221 (Am in FIG. 4). At the same time, the registers 202 and 203 take in the values (D15 and C15 in FIG. 4) of the registers 203 and 204, respectively. At the same time, the register 204 takes in the output of the adder 228 (B15 in FIG. 4). At the same time, the registers 206 and 207 respectively take in the input data and the constant values (X0 and T0 in FIG. 4) used in the 0th round given from the outside.
[0048]
Next, in the second clock cycle, the registers 201, 202, and 212 all take in the output (Dm in FIG. 4) of the adder 222. At the same time, both the registers 203 and 213 take in the output of the adder 223 (Cm in FIG. 4). At the same time, both registers 204 and 214 take in the output of adder 224 (Bm in FIG. 4). At the same time, the register 205 takes in the output of the adder 226 ((Am + X0 + T0) in FIG. 4). At the same time, the registers 206 and 207 fetch input data and constant values (X1 and T1 in FIG. 4) used in the first round, respectively, provided from the outside. The input data taken into the register 206 in the first and second clock cycles is data included in the next block data.
[0049]
(3) Hash post-processing
Post-hash processing is performed over two clock cycles. In the first clock cycle, the register 211 takes in the output of the adder 221 (Ae in FIG. 4). At the same time, the registers 202 and 203 take in the values (D15 and C15 in FIG. 4) of the registers 203 and 204, respectively. At the same time, the register 204 takes in the output of the adder 228 (B15 in FIG. 4). Note that the register 201 may take in an arbitrary value. Here, it is assumed that the register 201 takes in the output of the adder 221.
[0050]
Next, in the second clock cycle, the registers 212 to 214 take in the outputs (De to Be in FIG. 4) of the adders 222 to 224, respectively. The registers 201 to 204 may take in arbitrary values. Here, the register 201 takes in the output of the adder 222, and the registers 202 to 204 take in the outputs of the adders 222 to 224, respectively. I do.
[0051]
When the second clock cycle is completed, the values (Ae to De in FIG. 4) stored in the registers 211 to 214 are hash values to be obtained. Therefore, by reading the values of the registers 211 to 214 using means (not shown) (or by reading the value of the output signal HV in the second clock cycle of the post-hash processing by an externally provided register), A hash value for the whole can be obtained.
[0052]
As described above, the hash function processing device 20 can correctly execute the round process in the MD5 algorithm, despite being different from the hash function processing device 10 according to the first embodiment in the above-described four points. Further, the hash function processing device 10 according to the first embodiment performs the round termination process over four clock cycles, whereas the hash function processing device 20 performs the round termination process over two clock cycles. .
[0053]
From the above, according to the hash function processing device according to the present embodiment, in addition to the effects achieved by the hash function processing device according to the first embodiment, the number of clock cycles required for round termination processing is reduced, and round processing is performed. There is an effect that execution can be performed at higher speed.
[0054]
(Third embodiment)
FIG. 5 is a logic circuit diagram of the hash function processing device according to the third embodiment of the present invention. The hash function processing device 30 shown in FIG. 5 is obtained by changing a part of a circuit included in the hash function processing device 10 according to the first embodiment. The hash function processing device 30 includes registers 302 to 307 and 311 to 314, adders 321 to 328, selectors 331 to 334 and 336 to 339, a cyclic shift operation block 341, and logical operation blocks 351 to 354. Among them, the adders 325 and 326 constitute a first arithmetic processing unit 361. The adders 327 and 328, the selector 339, the cyclic shift operation block 341, and the logical operation blocks 351 to 354 constitute a second operation processing unit 362.
[0055]
The circuit configuration of the hash function processing device 30 is different from the circuit configuration of the hash function processing device 10 according to the first embodiment in the following three points. First, the register 101 and the selector 135 of the hash function processing device 10 are deleted in the hash function processing device 20. Second, the selector 336 selects and outputs an appropriate value from the value of the register 311, the value of the register 312, and the value of the register 303. Third, the adder 321 adds the value of the register 302 and the value of the register 311. The other components of the hash function processing device 30 are the same as those of the hash function processing device 10, and the description thereof is omitted here. Note that, in the present embodiment, the registers 302 to 304 are referred to as a first register R1, a third register R3, and a second register R2, respectively.
[0056]
The hash function processing device 30 performs a pre-hash process on input data, then performs a round process, and finally performs a post-hash process on the input data, similarly to the hash function processing device 10 according to the first embodiment. . The contents of these three processes are the same as those of the hash function processing device 10. FIG. 6 is a diagram showing how the values of the registers 302 to 307 and 311 to 314 are changed by these three processes. Hereinafter, the operation of the hash function processing device 30 will be described with reference to FIG.
[0057]
(1) Hash preprocessing
The hash preprocessing is performed over two clock cycles in a state where the registers 311 to 314 store the initial values (As and Ds to Bs in FIG. 6) determined by the MD5 algorithm. In the first clock cycle, unlike the first embodiment, the register 302 takes in the value of the register 311 (As in FIG. 6). At the same time, registers 303 and 304 take in the values (Cs and Bs in FIG. 6) of registers 313 and 314, respectively. At the same time, the registers 306 and 307 respectively take in the input data and the constant values (X0 and T0 in FIG. 6) used from the outside in the 0th round.
[0058]
Next, in the second clock cycle, the register 305 takes in the output of the adder 326 ((As + X0 + T0) in FIG. 6). At the same time, unlike the first embodiment, the register 302 takes in the value of the register 312 (Ds in FIG. 6). At the same time, registers 306 and 307 take in input data and constant values (X1 and T1 in FIG. 6) used in the first round, respectively, provided from the outside.
[0059]
(2) Round processing
The processing of the 0th to 62nd rounds is performed by taking one clock cycle per round (that is, by taking 63 clock cycles for each block data). The processes of the 0th to 62nd rounds by the hash function processing device 30 are the same as the processes by the hash function processing device 10 according to the first embodiment, except that the register corresponding to the register 101 does not exist. That is, in each clock cycle, the register 302 takes in the value of the register 303. At the same time, the register 303 captures the value of the register 304. At the same time, the register 304 captures the output of the adder 328. At the same time, the register 305 takes in the output of the adder 326. At the same time, registers 306 and 307 respectively take in the next input data and constant value given from outside. However, in the process of the 62nd round, the registers 306 and 307 may take in arbitrary values.
[0060]
On the other hand, the round termination processing is performed over four clock cycles for each block data. In the first clock cycle, the register 311 takes in the output of the adder 321 (Am in FIG. 6). At the same time, registers 302 and 303 take in the values (D15 and C15 in FIG. 6) of registers 303 and 304, respectively. At the same time, the register 304 takes in the output of the adder 328 (B15 in FIG. 6).
[0061]
Next, in the second clock cycle, the registers 312 to 314 take in the outputs (Dm to Bm in FIG. 6) of the adders 322 to 324, respectively. Note that the registers 302 to 304 may take in an arbitrary value, and here it is assumed that the register holds the value of the immediately preceding clock cycle.
[0062]
Next, in the third clock cycle, the register 302 takes in the value of the register 311 (Am in FIG. 6). At the same time, registers 303 and 304 take in the values (Cm and Bm in FIG. 6) of registers 313 and 314, respectively. At the same time, the registers 306 and 307 respectively take in the input data and the constant values (X0 and T0 in FIG. 6) used from the outside in the 0th round.
[0063]
Next, in the fourth clock cycle, the register 305 takes in the output of the adder 326 ((Am + X0 + T0) in FIG. 6). At the same time, the register 302 takes in the value of the register 312 (Dm in FIG. 6). At the same time, registers 306 and 307 take in input data and constant values (X1 and T1 in FIG. 6) used in the first round, respectively, provided from the outside. Note that the input data taken into the register 306 in the third and fourth clock cycles is data included in the next block data.
[0064]
(3) Hash post-processing
Post-hash processing is performed over two clock cycles. In the first clock cycle, the register 311 takes in the output of the adder 321 (Ae in FIG. 6). At the same time, registers 302 and 303 take in the values (D15 and C15 in FIG. 6) of registers 303 and 304, respectively. At the same time, the register 304 takes in the output of the adder 328 (B15 in FIG. 6).
[0065]
Next, in the second clock cycle, the registers 312 to 314 take in the outputs (De to Be in FIG. 6) of the adders 322 to 324, respectively. Note that the registers 302 to 304 may take in an arbitrary value, and here it is assumed that the register holds the value of the immediately preceding clock cycle.
[0066]
At the time when the second clock cycle is completed, the values (Ae and De to Be in FIG. 6) stored in the registers 311 to 314 are hash values to be obtained. Therefore, by reading the values of the registers 311 to 314 using means (not shown) (or by an external register taking in the value of the output signal HV in the second clock cycle of the post-hash processing), A hash value for the whole can be obtained.
[0067]
As described above, the hash function processing device 30 can correctly execute the round process in the MD5 algorithm, despite being different from the hash function processing device 10 according to the first embodiment in the above-described three points. In addition, the register corresponding to the register 101 is removed from the hash function processing device 30.
[0068]
As described above, according to the hash function processing device according to the present embodiment, in addition to the effect provided by the hash function processing device according to the first embodiment, there is an effect that the circuit scale can be reduced.
[0069]
(Fourth embodiment)
FIG. 7 is a logic circuit diagram of the hash function processing device according to the fourth embodiment of the present invention. A hash function processing device 40 shown in FIG. 7 is obtained by changing a part of a circuit included in a hash function processing device 30 according to the third embodiment. The hash function processing device 40 includes registers 402 to 407 and 411 to 414, adders 421 to 428, selectors 431 to 434 and 436 to 439, a cyclic shift operation block 441, and logical operation blocks 451 to 454. Among them, the adders 425 and 426 constitute a first arithmetic processing unit 461. The adders 427 and 428, the selector 439, the cyclic shift operation block 441, and the logical operation blocks 451 to 454 form a second operation processing unit 462.
[0070]
The circuit configuration of the hash function processing device 40 is different from the circuit configuration of the hash function processing device 30 according to the third embodiment in the following three points. First, the selector 436 selects and outputs an appropriate value from the value of the register 411, the value of the register 412, the value of the register 403, and the output of the adder 421. Second, the selector 437 selects and outputs an appropriate value from the value of the register 413, the value of the register 404, and the output of the adder 423. Third, the selector 438 selects and outputs an appropriate value from the value of the register 414, the output of the adder 428, and the output of the adder 424. The other components of the hash function processing device 40 are the same as those of the hash function processing device 30, and a description thereof will not be repeated.
[0071]
The hash function processing device 40 performs a pre-hash process on input data, then performs a round process, and finally performs a post-hash process on the input data, similarly to the hash function processing device 30 according to the third embodiment. . The contents of these three processes are the same as those of the hash function processing device 30. FIG. 8 is a diagram showing how the values of the registers 402 to 407 and 411 to 414 change by these three processes. Hereinafter, the operation of the hash function processing device 40 will be described with reference to FIG.
[0072]
(1) Hash preprocessing
The pre-hash processing in the hash function processing device 40 is the same as the process in the hash function processing device 30 according to the third embodiment.
[0073]
(2) Round processing
The processes in the 0th to 62nd rounds in the hash function processing device 40 are the same as those in the hash function processing device 30 according to the third embodiment. The processing of the 0th to 62nd rounds is performed by taking one clock cycle per round (that is, by taking 63 clock cycles for each block data).
[0074]
On the other hand, the round termination processing is performed by taking two clock cycles for each block data. In the first clock cycle, both registers 402 and 411 take in the output of adder 421 (Am in FIG. 8). At the same time, the register 412 takes in the output of the adder 422 (Dm in FIG. 8). At the same time, the register 403 takes in the value of the register 404 (C15 in FIG. 8). At the same time, the register 404 takes in the output of the adder 428 (B15 in FIG. 8). At the same time, registers 406 and 407 fetch input data and constant values (X0 and T0 in FIG. 8) used in the 0th round provided from the outside, respectively.
[0075]
Next, in the second clock cycle, the register 402 takes in the value of the register 412 (Dm in FIG. 4). At the same time, the registers 403 and 413 both take in the output of the adder 423 (Cm in FIG. 8). At the same time, the registers 404 and 414 both take in the output of the adder 424 (Bm in FIG. 8). At the same time, the register 405 takes in the output of the adder 426 ((Am + X0 + T0) in FIG. 8). At the same time, registers 406 and 407 fetch input data and constant values (X1 and T1 in FIG. 8) used in the first round, respectively, provided from outside. Note that the input data taken into the register 406 in the first and second clock cycles is data included in the next block data.
[0076]
(3) Hash post-processing
Post-hash processing is performed over two clock cycles. In the first clock cycle, registers 411 and 412 take in the outputs (Ae and De in FIG. 8) of adders 421 and 422, respectively. At the same time, the register 403 takes in the value of the register 404 (C15 in FIG. 8). At the same time, the register 404 takes in the output of the adder 428 (B15 in FIG. 8). The register 402 may take in an arbitrary value. Here, it is assumed that the register 402 takes in the output of the adder 421.
[0077]
Next, in the second clock cycle, the registers 413 and 414 take in the outputs of the adders 423 and 424 (Ce and Be in FIG. 8), respectively. Registers 402 to 404 may capture any value, where register 402 captures the value of register 412 and registers 403 and 404 capture the output of adders 423 and 424, respectively.
[0078]
At the time when the second clock cycle is completed, the values (Ae and De to Be in FIG. 8) stored in the registers 411 to 414 are the hash values to be obtained. Therefore, by reading the values of the registers 411 to 414 using means (not shown) (or by an external register taking in the value of the output signal HV in the second clock cycle of the post-hash processing), A hash value for the whole can be obtained.
[0079]
As described above, the hash function processing device 40 can correctly execute the round process in the MD5 algorithm, despite being different from the hash function processing device 30 according to the third embodiment in the above-described four points. The hash function processing device 30 according to the third embodiment performs the round termination process over four clock cycles, whereas the hash function processing device 40 performs the round termination process over two clock cycles. .
[0080]
From the above, according to the hash function processing device according to the present embodiment, in addition to the effect provided by the hash function processing device according to the third embodiment, the number of clock cycles required for round termination processing is reduced, and round processing is performed. There is an effect that execution can be performed at higher speed. That is, in addition to the effects provided by the hash function processing device according to the first embodiment, there is an effect that the circuit scale can be reduced and round processing can be executed at higher speed.
[0081]
The hash function processing device of the present invention may be any device that performs the processes of the 0th to 62nd rounds by the above-described pipeline process, and may constitute a modified example other than the devices described in the above embodiments. it can. For example, regarding the hash function processing device 10 according to the first embodiment, the timings for setting the initial values As to Ds in the registers 111 to 114, the registers 101 to 104 in the pre-hash processing, the round end processing, and the post-hash processing , The timing of updating the registers 111 to 114, the value set in the register that may take in an arbitrary value, and the like can be variously designed. The same applies to the hash function processing devices according to the second to fourth embodiments.
[0082]
Further, in each of the above embodiments, the MD5 algorithm is used as the hash function, but it goes without saying that another algorithm may be used as the hash function.
[Brief description of the drawings]
FIG. 1 is a logic circuit diagram of a hash function processing device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a state where a value of a register included in the hash function processing device according to the first embodiment of the present invention changes.
FIG. 3 is a logic circuit diagram of a hash function processing device according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating a state where a value of a register included in a hash function processing device according to a second embodiment of the present invention changes.
FIG. 5 is a logic circuit diagram of a hash function processing device according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating a state in which the value of a register included in a hash function processing device according to a third embodiment of the present invention changes.
FIG. 7 is a logic circuit diagram of a hash function processing device according to a fourth embodiment of the present invention.
FIG. 8 is a diagram illustrating a state in which a value of a register included in a hash function processing device according to a fourth embodiment of the present invention changes.
[Explanation of symbols]
10, 20, 30, 40 ... hash function processing device
101-107, 111-114, 201-207, 211-214, 302-307, 311-314, 402-407, 411-414 ... registers
121-128, 221-228, 321-328, 421-428 ... adders
131-139, 231-239, 331-334, 336-339, 431-434, 436-439 ... selector
141, 241, 341, 441... Cyclic shift operation block
151-154, 251-254, 351-354, 451-454 ... Logic operation block
161, 261, 361, 461: first arithmetic processing unit
162, 262, 362, 462: second arithmetic processing unit

Claims (6)

A hash function processing device that performs iterative processing defined by a hash function on input data,
First to fourth registers for storing feedback data;
An input data supply unit for supplying input data of a predetermined length,
A constant value supply unit that supplies a constant value determined by a hash function,
A first arithmetic processing unit that performs predetermined arithmetic processing on the value of the first register, the input data supplied from the input data supply unit, and the constant value supplied from the constant value supply unit When,
An intermediate value storage register for storing a calculation result by the first calculation processing unit;
A second arithmetic processing unit that performs predetermined arithmetic processing on the values of the second to fourth registers and the value of the intermediate value storage register;
The first and second arithmetic processing units operate in parallel, and the intermediate value storage register fetches the operation result by the first arithmetic processing unit, and the second register performs the second arithmetic operation. An operation of capturing a calculation result by the processing unit, an operation of capturing the value of the second register by the third register, an operation of capturing the value of the third register by the first and fourth registers, A hash function, wherein the operation of the input data supply unit to obtain the next input data and the operation of the constant value supply unit to obtain the next constant value are performed in parallel within one clock cycle. Processing equipment. A hash function processing device that performs iterative processing defined by a hash function on input data,
First to third registers for storing feedback data;
An input data supply unit for supplying input data of a predetermined length,
A constant value supply unit that supplies a constant value determined by a hash function,
A first arithmetic processing unit that performs predetermined arithmetic processing on the value of the first register, the input data supplied from the input data supply unit, and the constant value supplied from the constant value supply unit When,
An intermediate value storage register for storing a calculation result by the first calculation processing unit;
A second arithmetic processing unit that performs predetermined arithmetic processing on the values of the first to third registers and the value of the intermediate value storage register;
The first and second arithmetic processing units operate in parallel, and the intermediate value storage register fetches the operation result by the first arithmetic processing unit, and the second register performs the second arithmetic operation. An operation of taking in the operation result by the processing unit, an operation of taking in the value of the second register by the third register, an operation of taking in the value of the third register by the first register, A hash function processing device, wherein the operation of the unit to obtain the next input data and the operation of the constant value supply unit to obtain the next constant value are performed in parallel within one clock cycle. The first arithmetic processing unit adds a value of the first register, input data supplied from the input data supply unit, and a constant value supplied from the constant value supply unit, The hash function processing device according to claim 1 or 2, wherein The second arithmetic processing unit performs a predetermined logical operation on the values of the second to fourth registers, and calculates a result of adding the operation result and the value of the intermediate value storage register by a predetermined number of bits. 2. The hash function processing device according to claim 1, wherein the value of the second register is added after the cyclic shift. The second arithmetic processing unit performs a predetermined logical operation on the values of the first to third registers, and calculates an addition result of the operation result and the value of the intermediate value storage register by a predetermined number of bits. 3. The hash function processing device according to claim 2, wherein after cyclically shifting, the value is added to the value of the second register. The hash function processing device according to claim 1, wherein the hash function is MD5 (Message Digest 5).

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