JP2004235662A - Semiconductor device and electronic device provided with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for performing heating treatment in an atmosphere containing halogen without damaging the effect of channel dope. <P>SOLUTION: A catalytic element, which promotes crystallization to an amorphous silicon film containing an impurity element for controlling a threshold value is added, and a crystalline silicon film is obtained by the heating treatment. Next, the heating treatment is performed in the atmosphere containing the halogen to perform gettering on the catalytic element. In this case, a chemical equilibrium is formed to the impurity element by mixing a compound gas containing the impurity element for controlling the threshold value in the atmosphere, to prevent the impurity element from escaping into a gaseous phase. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The invention disclosed in this specification relates to a method for manufacturing a semiconductor device using a thin film semiconductor having crystallinity. In particular, the present invention relates to a structure of an insulating gate thin film transistor (TFT).

  In recent years, a technique for manufacturing a TFT using a crystalline silicon film (particularly, a material called a polycrystalline silicon film, a polycrystalline silicon film, a polysilicon film, or the like) over a substrate having an insulating surface has been developed. A TFT using such a material has an advantage that a high-speed operation is possible as compared with a TFT using an amorphous silicon film (also referred to as an amorphous silicon film).

  Therefore, a monolithic panel on which a pixel matrix circuit and a driver circuit are mounted on the same substrate, and a system-on-panel structure integrally formed with a logic circuit (memory, amplifier, CPU, etc.) for performing signal processing are also being actively studied. ing. For example, the driver circuit and the logic circuit are composed of a composite circuit based on a CMOS circuit (inverter circuit) in which an N-type TFT and a P-type TFT are complementarily combined.

  The TFTs constituting the various circuits as described above are turned on when a specific voltage (referred to as threshold or threshold voltage) is applied to the gate electrode, and turned off when the voltage is lower than that. It is a switching element. Therefore, precise control of the threshold voltage is very important for accurate operation of the circuit.

  However, the threshold voltage of the TFT may shift (shift) to the minus side or the plus side due to an unspecified factor in the manufacturing process. This may be due to the influence of mobile ions due to contamination, or due to a work function difference around the gate of the TFT or an interface charge.

  Such a shift in the threshold voltage impairs the function as a switching element and has an adverse effect such as an increase in power consumption. However, it is possible to solve the problem due to the contamination by improving the process or the like. However, since the problem due to the work function difference or the like is determined by the material, there is a case where the structure is unavoidable.

  A technique proposed as a solution in such a case is a channel doping method. In the channel doping method, an impurity element imparting one conductivity (typically, P, As, B, or the like) is added to at least a channel formation region of a TFT, and a threshold voltage is intentionally shifted to perform control. It is a technology to do. Therefore, in order to control the threshold voltage to a desired value, it is necessary to control the amount of the impurity element extremely precisely.

  The impurity element may be added in advance to a film forming gas for forming an amorphous silicon film or a crystalline silicon film, or may be added by ion implantation after crystallization. Alternatively, a method in which a crystalline silicon film is processed into an island shape and then selectively added only to a portion to be a channel formation region can be used.

[Process leading to the invention]
The present inventors have conducted intensive studies to obtain excellent TFT characteristics, and as a result, have invented a crystalline silicon film having extremely excellent crystallinity. The necessary conditions for forming the crystalline silicon film will be briefly described below.

  First, an amorphous silicon film is formed on a substrate having high heat resistance (for example, a quartz substrate), and crystallized using the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652 disclosed by the present inventors. The technique described in this publication is a technique in which a catalytic element (typically, nickel) that promotes crystallization is added to an amorphous silicon film, and crystallization is performed by heat treatment.

  After the crystalline silicon film is obtained, a heat treatment is performed in an atmosphere containing a halogen element to getter the catalytic element. This gettering step utilizes the gettering effect of the metal element by the halogen element. Note that the above heat treatment is preferably performed at a temperature exceeding 700 ° C. in order to sufficiently obtain the gettering effect by the halogen element.

In the gettering step, the catalyst element remaining in the crystalline silicon film is gettered by being combined with a halogen element, becomes a volatile halide, and is removed to the atmosphere and removed. Then, the concentration of the catalyst element in the crystalline silicon film is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less (preferably, the spin density or less) by the catalyst element gettering step. Note that the impurity concentration in this specification is defined by the minimum value of the measurement value obtained by SIMS analysis.

  The crystalline silicon film formed as described above is composed of a crystal structure in which a plurality of rod-shaped or flat rod-shaped crystals are aggregated, and when viewed microscopically, the growth direction of the rod-shaped crystals is directed to a specific direction. There is a characteristic in having the property. Further, the heat treatment in the gettering step significantly improves the crystallinity inside the crystal.

  However, while various TFTs have been experimentally manufactured using the crystalline silicon film, the present inventors have recognized that a serious problem occurs when the channel doping method described in the conventional example is applied. The problem is a phenomenon in which the impurity elements (B, P, As, etc.) added near the surface layer of the crystalline silicon film are depleted when the catalytic element is removed in the gettering step. This phenomenon is also reported in "IBM Technical Disclosure Bulletin: vol. 1, No. 5, 1973".

  That is, the concentration of the impurity element in the region where the channel is formed (near the surface of the active layer) is greatly reduced, so that the effect of channel doping cannot be obtained. Therefore, precise control of the threshold voltage becomes impossible.

  The above problem was first recognized when a conventional channel doping method was applied to the above-described method for forming a crystalline silicon film, and was not recognized by anyone in the past. That is, an object of the present invention is to solve a completely new problem that no one has recognized as described above.

  Specifically, an object is to provide a technique for performing heat treatment in an atmosphere containing a halogen element without depleting impurity elements such as phosphorus and boron existing near the surface of the crystalline silicon film. I do.

A source region, a drain region, a crystalline silicon film on which an LDD region and a channel forming region are formed on a substrate having an insulating surface, a gate insulating film formed on the channel forming region, A gate electrode formed on an insulating film; and a sidewall formed in contact with a side surface of the gate electrode. A silicide layer is formed on a surface of the gate electrode, the source region, and the drain region. It is characterized by having.
A source region, a drain region, a crystalline silicon film on which an LDD region and a channel forming region are formed on a substrate having an insulating surface, a gate insulating film formed on the channel forming region, A gate electrode formed on an insulating film, and a sidewall formed in contact with a side surface of the gate electrode, wherein the LDD region is disposed below the sidewall; A silicide layer is formed on the surface of the region and the drain region.

  A source region, a drain region, a crystalline silicon film on which an LDD region and a channel forming region are formed on a substrate having an insulating surface, a gate insulating film formed on the channel forming region, A gate electrode formed on an insulating film, and a sidewall formed in contact with a side surface of the gate electrode, wherein the LDD region is disposed below the sidewall; Cobalt silicide is formed on the surface of the region and the drain region.

  A source region, a drain region, a crystalline silicon film on which an LDD region and a channel forming region are formed on a substrate having an insulating surface, a gate insulating film formed on the channel forming region, A gate electrode formed on an insulating film, and a sidewall formed in contact with a side surface of the gate electrode, wherein the LDD region is arranged below the sidewall, and the source region and the drain A feature is that silicide of titanium, cobalt, tungsten, tantalum, or molybdenum is formed on a surface of the region.

  The substrate having the insulating surface is a quartz substrate.

  In the above configuration, the gate electrode is made of silicon.

  In the above structure, the source region and the drain region have N-type conductivity.

  In the above structure, the crystalline silicon film is characterized in that the amorphous silicon film is crystallized by holding a catalyst element that promotes crystallization and performing a heat treatment.

  The above structure is an electronic device including the semiconductor device.

The configuration of the invention disclosed in this specification is:
Forming an amorphous silicon film containing an impurity element of group 13 or 15;
Transforming the amorphous silicon film into a crystalline silicon film by performing a heat treatment;
Performing a heat treatment in an atmosphere containing a halogen element,
In a method for manufacturing a semiconductor device having at least
The atmosphere containing the halogen element contains a compound gas containing the impurity element.

Further, the configuration of another invention is as follows.
Holding a catalytic element that promotes crystallization of the amorphous silicon film in the amorphous silicon film containing an impurity element of group 13 or 15,
Performing a heat treatment to transform all or at least a part of the amorphous silicon film into a crystalline silicon film;
A step of performing a heat treatment in an atmosphere containing a halogen element to remove or reduce the catalyst element from the silicon film;
In a method for manufacturing a semiconductor device having at least
The atmosphere containing the halogen element contains a compound gas containing the impurity element.

Further, the configuration of another invention is as follows.
Adding an impurity element of group 13 or 15 to the amorphous silicon film;
Holding a catalyst element for promoting crystallization of the amorphous silicon film with respect to the amorphous silicon film;
Performing a heat treatment to transform all or at least a part of the amorphous silicon film into a crystalline silicon film;
A step of performing a heat treatment in an atmosphere containing a halogen element to remove or reduce the catalyst element from the silicon film;
In a method for manufacturing a semiconductor device having at least
The atmosphere containing the halogen element contains a compound gas containing the impurity element.

  In the present invention, when the catalyst element gettering step is performed in an atmosphere containing a halogen element, a compound gas (preferably the halogen element and the halogen element) containing a group 13 or 15 impurity element (an impurity element for controlling a threshold value) is used. Compound gas with an impurity element) in the processing atmosphere.

  Thus, a state of chemical equilibrium with the impurity element is formed between the processing atmosphere and the surface to be processed.

  By doing so, the chemical reaction of the impurity element in the vicinity of the silicon film surface can be suppressed, and the removal of the impurity element for controlling the threshold value from the silicon film can be effectively suppressed.

  In addition, examples of the impurity for controlling the threshold value typically used in the channel doping method include boron (B), which is a Group 13 element, phosphorus (P), and arsenic (As), which are Group 15 elements. In addition, aluminum (Al) and gallium (Ga) can be used as the group 13 element, and antimony (Sb) can be used as the group 15 element. These are selectively used depending on the conductivity type of the TFT or depending on which side of the threshold voltage is to be shifted, the plus side or the minus side.

As the compound gas containing the impurity element for controlling the threshold value, diborane (B ₂ H ₆ ), boron trifluoride (BF ₃ ), boron trichloride (BCl ₃ ), Aluminum (AlCl ₃ ), gallium trichloride (GaCl ₃ ), or the like can be used. In addition, phosphine (PH ₃ ), phosphorus trifluoride (PF ₃ ), phosphorus trichloride (PCl ₃ ), arsine (AsH ₃ ), arsenic trifluoride (AsF ₃ ), and arsenic trichloride (AsCl ₃ ) are used as Group 15 elements. ), Stippin (SbH ₃ ), antimony trichloride (SbCl ₃ ), and the like.

  By utilizing the present invention, heat treatment in an atmosphere containing a halogen element can be performed without impairing the effect of channel doping. Therefore, precise threshold control can be performed in a semiconductor device requiring such a special process.

  An amorphous silicon film containing a Group 13 or Group 15 impurity element used for threshold control is formed over a substrate having an insulating surface. Then, a heat treatment is performed on the amorphous silicon film while holding a catalyst element for promoting crystallization to obtain a crystalline silicon film.

  Next, the catalyst element remaining in the crystalline silicon film is removed or reduced by a heat treatment in an atmosphere containing a halogen element. At that time, a compound gas containing an impurity element added to the amorphous silicon film is introduced into a processing atmosphere.

  At this time, a chemical equilibrium state is formed between the processing atmosphere and the surface to be processed (crystalline silicon film) for the impurity element, so that the impurity element is effectively prevented from being separated from the crystalline silicon film. Can be suppressed.

  As a result, heat treatment in an atmosphere containing a halogen element can be performed without impairing the effect of channel doping.

  In this embodiment, an example of a manufacturing process for manufacturing an active matrix substrate in which a CMOS circuit and a pixel matrix circuit are provided over the same substrate will be described with reference to FIGS. Note that this embodiment is an example, and the present invention is not limited to this manufacturing process.

  In FIG. 1A, reference numeral 101 denotes a quartz substrate. Instead of a quartz substrate, a ceramic substrate or a silicon substrate having a 0.5 to 5 μm thick insulating film formed on the surface can be used. Since a low-grade silicon substrate used for a solar cell is inexpensive, it is effective when used for an application that does not require the use of a light-transmitting substrate, such as a reflective display device.

  Reference numeral 102 denotes an amorphous silicon film, which is adjusted so that the final film thickness (thickness in consideration of film reduction after thermal oxidation) is 10 to 75 nm (preferably 15 to 45 nm). The amorphous silicon film 102 may be formed by a low pressure thermal CVD method or a plasma CVD method.

At this time, in this embodiment, a predetermined amount of boron is contained in the amorphous silicon film 102 by introducing diborane (B ₂ H ₆ ) into the deposition gas. The reason for adding boron is to shift the threshold voltage to the plus side by about 1 V as a whole (for shifting to the minus side, phosphorus or arsenic may be used). The content must be determined experimentally in advance, but in this case, the content is adjusted to be 2 ppm.

  Next, the amorphous silicon film 102 is crystallized. In this embodiment, a technique described in Japanese Patent Application Laid-Open No. 8-78329 is used as a crystallization means. First, a thin oxide film (not shown) is formed on the surface of the amorphous silicon film 102. Next, a mask insulating film 103 for selecting a region to be added with a catalytic element (hereinafter, nickel is taken as an example in this embodiment) is formed.

  After the formation of the mask insulating film 103, a solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film is applied by a spin coating method to form a nickel-containing layer 104. In addition, as a catalyst element, in addition to nickel, cobalt (Co), iron (Fe), tin (Sn), lead (Pb), palladium (Pd), platinum (Pt), copper (Cu), and gold (Au) For example, an element which promotes crystallization of silicon can be used. (Fig. 1 (A))

Next, when the step of adding nickel is completed, an inert atmosphere after removal of the mask insulating film 103, O ₂ 500 to 700 ° C. in an atmosphere or an H ₂ atmosphere, typically at a temperature of 550 to 650 ° C. 4 to 8 The amorphous silicon film 102 is crystallized by applying heat treatment for a long time. At this time, the crystallization of the amorphous silicon film 102 proceeds preferentially from the added regions 105 and 106 to which nickel has been added, and lateral growth regions 107 and 108 grown substantially parallel to the substrate 101 are formed. (FIG. 1 (B))

  After the heat treatment for crystallization is completed, the mask insulating film 104 is removed. Next, a heat treatment is performed in an atmosphere containing a halogen element at a temperature exceeding 700 ° C., preferably 800 to 1000 ° C. (typically 950 ° C.) for 0.1 to 6 hours (typically 0.5 to 1 hour) to obtain a nickel getter. Perform the ring process (first time). In the present invention, at this time, a compound gas containing an impurity element (boron in this embodiment) for controlling the threshold value is introduced into the atmosphere. (Fig. 1 (C))

In this embodiment, the above heat treatment is performed in an oxygen atmosphere containing 0.5 to 10% by volume of hydrogen chloride (HCl) and 0.1 to 10% by volume of boron trichloride (BCl ₃ ). At this time, it is important to maintain a chemical equilibrium state between the processing atmosphere and the surface to be processed for boron so that boron is not released from the silicon film.

Note that an example in which HCl gas is used as a compound containing a halogen element has been described, but HF, NF ₃ , HBr, Cl ₂ , ClF ₃ , BCl ₃ , BF ₃ , F ₂ , One or more compounds selected from compounds containing halogen such as Br ₂ can be used.

Further, in the case of this embodiment, B ₂ H ₆ , BF _3, or the like can be used as the compound gas containing the impurity element for controlling the threshold value, in addition to BCl ₃ . When phosphorus is used for threshold control, PH ₃ , PF ₃ , and PCl ₃ may be used. When arsenic is used, AsH ₃ , AsF ₃ , and AsCl ₃ may be used.

  In this step, nickel remaining in the crystalline silicon film (the amorphous component remaining after the above-mentioned crystallization step is completely crystallized by this heat treatment) is gettered by the action of chlorine, and volatile nickel chloride is formed. And escapes into the gas phase.

In the gettering step of FIG. 1D, a thermal oxidation reaction proceeds on the surface of the silicon film, so that an oxide film 109 having an increased thickness is formed on the silicon film. However, this oxide film 109 does not serve as a blocking layer that prevents the release of nickel chloride. The oxide film 109 also has an effect of preventing silicon atoms from becoming compounds such as dichlorosilane (SiH ₂ Cl ₂ ) and being separated.

Then, the concentration of nickel in the lateral growth regions 107 and 108 is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less (preferably, spin density or less) by the catalyst element gettering step. Further, similar SIMS analysis has confirmed that the halogen element used for the gettering process remains in the lateral growth regions 107 and 108 at a concentration of 1 × 10 ¹⁵ to 1 × 10 ²⁰ atoms / cm ³ .

  It is also considered that during the gettering step, boron intentionally added for controlling the threshold becomes boron trichloride and escapes. However, since it is kept in a state of chemical equilibrium with boron trichloride contained in the processing atmosphere, the release of boron from the silicon film can be effectively suppressed.

  Next, after removing the oxide film 109, patterning is performed to form island-like semiconductor layers (active layers) 110 to 112 including only lateral growth regions as shown in FIG. Then, a silicon oxide film 113 to be a gate insulating film later is formed thereon. The thickness of the silicon oxide film 113 may be adjusted to a finally required thickness in consideration of the thickness of a thermal oxide film formed in a subsequent thermal oxidation step.

  Next, as shown in FIG. 2A, a catalyst element gettering step (second time) is performed again. The conditions described above can be used as they are. At this time, a thermal oxidation reaction proceeds at the interface between the active layers 110 to 112 and the silicon oxide film 113, and the total thickness of the silicon oxide film 113 increases by the formed thermal oxide film (not shown).

  Further, by performing the heat treatment in the halogen atmosphere and then performing the heat treatment in a nitrogen atmosphere at 950 ° C. for about 1 hour, the film quality of the silicon oxide film 113 is improved and an extremely good semiconductor / insulating film interface is realized. Is done.

  The crystalline silicon film formed through the above-described steps has a crystal structure in which a plurality of rod-shaped or flat rod-shaped crystals are grown in a direction substantially parallel to each other. Each rod-shaped crystal has a structure partitioned by crystal grain boundaries extending substantially in parallel with each other.

  After the active layers 110 to 112 having the above-described crystal structure are obtained, an aluminum film (not shown) containing 0.2 wt% of scandium is formed, and becomes a prototype of a gate electrode later. An electrode pattern is formed. Note that tantalum, tungsten, molybdenum, silicon, or the like can be used instead of the aluminum film. Then, by anodizing the surface of the pattern, gate electrodes 114 to 116 and anodic oxide films 117 to 119 are formed. (FIG. 2 (B))

  Next, the silicon oxide film 113 is etched in a self-aligned manner using the gate electrodes 114 to 116 as a mask. The etching may be performed by a dry etching method using CHF3 gas. By this step, gate insulating films 120 to 122 remaining only immediately below the gate electrode are formed.

Next, after a resist mask 123 is formed so as to cover a region to be a P-channel TFT, impurity ions imparting N-type conductivity are added. The impurity ions may be added by an ion implantation method or a plasma doping method. Since the concentration at this time (represented by n ⁻ ) becomes the concentration of the LDD region later (about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ ), the optimum value is experimentally obtained in advance and precise control is performed. Need to do. Thus, n ⁻ regions 124 to 127 are formed. (Fig. 2 (C))

After the n ^- regions 124 to 127 are formed, the resist mask 123 is removed, and a resist mask 128 is formed to cover the N-channel TFT. Then, a addition of the impurity ions for imparting P-type, p ^- to form a region 129,130. Since these p ⁻ regions 129 and 130 also have the concentration of the LDD region later (about 5 × 10 ¹⁸ to 5 × 10 ¹⁹ atoms / cm ³ ), it is necessary to perform precise control. (FIG. 2 (D))

After forming n ⁻ regions 124 to 127 and p ⁻ regions 129 and 130 as described above, resist mask 128 is removed. Then, a silicon oxide film (not shown) is formed to a thickness of 0.5 to 2 μm, and sidewalls 131 to 133 are formed by an etch back method. (FIG. 2 (E))

Next, a resist mask 134 is formed so as to cover the P-channel TFT again, and an impurity ion adding process for imparting N-type is performed. This time, it is added at a concentration (represented by n ⁺ ) higher than the aforementioned addition concentration n ⁻ . This concentration is adjusted so that the sheet resistance of the source / drain region is 500 Ω or less (preferably 300 Ω or less).

  By this step, a source region 135, a drain region 136, and a low-concentration impurity region (particularly, the drain region side is called an LDD region) 137 of the N-channel TFT constituting the CMOS circuit are formed. Further, a channel formation region 138 is formed immediately below the gate electrode. At the same time, a source region 139, a drain region 140, a low-concentration impurity region 141, and a channel formation region 142 of the N-channel pixel TFT forming the pixel matrix circuit are formed. (FIG. 3 (A))

  Next, the resist mask 134 is removed, and a resist mask 143 is formed to cover the N-channel TFT. Then, a source region 144, a drain region 145, and a low-concentration impurity region 146 of a P-channel TFT forming a CMOS circuit are added by adding a p-type impurity ion at a higher concentration (represented by p +) than the first time. , A channel formation region 147 is formed. (FIG. 3 (B))

  As described above, all the active layers are completed. After the step of adding all the impurity ions is completed, the resist mask 143 is removed, and then the impurity ions are activated by a heat treatment such as furnace annealing, laser annealing, lamp annealing, or the like. Note that the damage of the active layer during the ion implantation is recovered at the same time.

  Next, a titanium (Ti) film 148 is formed to a thickness of 20 to 50 nm, and a heat treatment by lamp annealing is performed. At this time, the silicon film in contact with the titanium film 148 is silicided, and titanium silicides 149 to 151 are formed in the source / drain regions. Note that cobalt (Co), tungsten (W), tantalum (Ta), molybdenum (Mo), or the like can be used instead of titanium.

  After the silicidation is completed, the titanium film 148 is patterned to form island patterns 152 to 154 on the source / drain regions. The island-shaped patterns 152 to 154 are patterns for preventing the titanium silicides 149 to 151 from being lost when a contact hole connecting the source / drain region and the wiring is formed later.

  Next, a silicon oxide film is formed as a first interlayer insulating film 155 to a thickness of 0.3 to 1 μm, and contact holes are formed to form source wirings 156 to 158 and drain wirings 159 and 160. Thus, the state shown in FIG. 3D is obtained.

  When the state shown in FIG. 3D is obtained, a second interlayer insulating film 161 made of an organic resin film is formed to a thickness of 0.5 to 3 μm. As the organic resin film, polyimide, acrylic, polyamide, polyimide amide or the like is used. The advantages of the organic resin film are (1) that the film formation method is simple, (2) that the film thickness can be easily increased, (3) that the parasitic capacitance can be reduced because the relative dielectric constant is low, (4) ) Excellent flatness.

  Then, a black mask 162 made of a light-shielding film is formed to a thickness of 100 nm on the interlayer insulating film 161 (above the pixel TFT). Although a titanium film is used as the black mask in this embodiment, a resin film containing a black pigment may be used.

  After the formation of the black mask 162, an organic resin film is again formed as the third interlayer insulating film 163 to a thickness of 0.1 to 0.3 μm. Then, contact holes are formed in the second interlayer insulating film 161 and the third interlayer insulating film 163, and the pixel electrode 164 is formed to a thickness of 120 nm. Note that an auxiliary capacitor 165 can be formed between the black mask 162 and the pixel electrode 164. (FIG. 3 (E))

  Finally, the entire substrate is heated in a hydrogen atmosphere to hydrogenate the entire device, thereby compensating for dangling bonds (unbonded bonds) in the film (especially in the active layer). Through the above steps, an active matrix substrate having a CMOS circuit and a pixel matrix circuit arranged on the same substrate can be manufactured.

  In the plurality of TFTs manufactured as described above, boron (channel-doped) added to the channel formation region functions effectively, so that a designed threshold voltage can be secured.

  Here, the effect of the present invention will be described with reference to the electrical characteristics of the TFT shown in FIG. The electrical characteristics of a TFT are graphs in which the horizontal axis represents the gate voltage (Vg) and the vertical axis represents the logarithm of the drain current (Id), and is representative data also called Id-Vg characteristics. Since an N-channel TFT is shown in FIG. 6, the off state is generally shown when the gate voltage is -6V to 0V, and the on state is shown when the gate voltage is 0V to 6V. Therefore, the Id-Vg characteristic indicates a state where the drain current increases near 0 V and switches from the off state to the on state or vice versa.

  However, to be precise, it is considered that the on / off state has been switched when the gate voltage matches the threshold voltage. That is, the voltage at which the drain current of the Id-Vg characteristic rises does not always match the threshold voltage. However, if the Id-Vg characteristic shifts to the left or right as a whole, the threshold voltage shifts accordingly, so the relative shift of the threshold voltage is evaluated by the shift of the rising voltage of the Id-Vg characteristic. it can.

  FIG. 6A shows the electrical characteristics when the present invention is applied, and the threshold voltage is about 0.3 V. FIG. 6B shows the electrical characteristics when the present invention is not applied, and the threshold voltage is about -0.5V. FIG. 6C shows the electrical characteristics in the case of the conventional process without channel doping, and the threshold voltage is about -0.7V.

  The present inventors adjusted the impurity concentration of channel doping so as to shift the threshold voltage of the TFT manufactured by the conventional process by 1 V to the plus side. That is, the fact that the threshold voltage of about -0.7 V in FIG. 6C becomes 0.3 V in FIG. 6A indicates that the effect of channel doping appears in the characteristics of FIG. 6A. It is shown that. In the case of FIG. 6B to which the present invention is not applied, the threshold voltage is -0.5 V, which indicates that the effect of channel doping has almost disappeared. The above results clearly show that the present invention is very effective.

  As described above, by applying the present invention, heat treatment can be performed in an atmosphere containing a halogen element without impairing the effect of channel doping. That is, it is possible to perform precise threshold value control while obtaining the effects obtained by the heat treatment (such as improvement in the crystallinity of the silicon film).

Note that the TFT manufactured in the steps described in this embodiment has extremely high performance, and can obtain electrical characteristics comparable to or superior to those of an IGFET formed on a single crystal silicon wafer. For example, the sub-threshold coefficient (S value) is as small as 60 to 100 mV / decade for both N-type TFT and P-type TFT, and the field-effect mobility (μ _FE ) is 200 to 650 cm ² / Vs (typically, N-type TFT). large 250 ~300cm ² / Vs), and 100 ~300cm ² / Vs in the P-type TFT (typically 150 ~200cm ² / Vs).

  This embodiment shows an example in which the present invention is applied to a high-temperature polysilicon technology. Note that the case of manufacturing an N-channel TFT will be described for simplicity, but it is easy to apply to a known single-gate CMOS circuit or dual-gate CMOS circuit.

  In FIG. 4A, reference numeral 401 denotes a quartz substrate, and 402 denotes an active layer formed of a crystalline silicon film. The crystalline silicon film is obtained by crystallizing an amorphous silicon film by a heat treatment at 600 ° C. for 24 to 48 hours. Needless to say, in this embodiment, when an amorphous silicon film is formed, boron is added as an impurity element for controlling a threshold value. (FIG. 4A)

  Next, heat treatment is performed at 1000 ° C. for 30 minutes in an atmosphere containing 3% of hydrogen chloride and 7% of diborane in an oxygen atmosphere. By this heat treatment, a thermal oxide film 403 functioning as a gate insulating film later is formed to a thickness of 50 nm. (FIG. 4 (B))

  It is already known that the film quality of a thermal oxide film (gate insulating film) can be improved by including a halogen element in a processing atmosphere. Also, in this case, the impurity element for controlling the threshold value is gettered by the halogen element. Therefore, it is important to maintain a chemically balanced atmosphere by applying the present invention.

  Next, a polysilicon film having N-type conductivity is formed, and a pattern is formed to form a gate electrode 404. After the gate electrode 404 is formed, the exposed gate insulating film 403 is removed with a hydrofluoric acid-based etchant, and P ions are implanted to form N-type regions 405 and 406. (FIG. 4 (C))

  Next, sidewalls 407 are formed by using an etch back method, and P ions are implanted again. Through this step, a source region 408, a drain region 409, a low-concentration impurity region 410, and a channel formation region 411 are defined. These impurity regions are activated by thermal annealing or laser annealing. (FIG. 4 (D))

  When the state of FIG. 4D is obtained, a cobalt film is formed and lamp annealing is performed to form cobalt silicides 412 to 414. This technique is already known as the salicide process.

  Next, an interlayer insulating film 415 made of a silicon oxide film is formed, a contact hole is formed, and a source wiring 416 and a drain wiring 417 are formed. Finally, a hydrogenation process is performed to complete the silicon gate type TFT shown in FIG.

  In the first and second embodiments, diborane is introduced as one of the film forming gases for the amorphous silicon film to contain boron. However, the plasma doping method without ion implantation or mass separation is used. Means for adding ions may be used.

  In that case, if ion implantation is performed on the crystalline silicon film, the crystalline silicon film becomes amorphous again. Therefore, it is preferable to add the crystalline silicon film before the crystallization step. Alternatively, the semiconductor layer can be selectively added only to a region to be a channel formation region using a mask.

  The present invention can be applied to various electro-optical devices. For example, if a liquid crystal is interposed between the active matrix substrate and the counter substrate described in the first embodiment, an active matrix liquid crystal display device is obtained. In that case, the pixel electrode is formed of a translucent material to provide a transmissive liquid crystal display device, and the pixel electrode is formed of a light reflective material to provide a reflective liquid crystal display device.

  Further, by slightly changing the structure of the active matrix substrate, an active matrix EL display device, an active matrix EC display device, or the like can be easily manufactured.

  The present invention is applied to all semiconductor devices including (1) a step of adding an impurity element for controlling a threshold value to a channel formation region, and (2) a step of performing heat treatment in an atmosphere containing a halogen element as a manufacturing process. can do.

  Therefore, the present invention can be applied not only to a semiconductor circuit formed on a substrate having an insulating surface but also to a semiconductor circuit constituted by an IGFET (insulated gate field effect transistor) formed on a silicon wafer. .

In this specification, a “semiconductor device” refers to any device that functions using a semiconductor, and the following devices are included in the category of the semiconductor device.
(1) Single element such as TFT and IGFET.
(2) A semiconductor circuit using the single element of (1). (3) An electro-optical device composed of (1) and (2).
(4) An electronic device including (2) and (3).

  In this embodiment, various electronic devices will be described as examples of a semiconductor device to which the present invention can be applied with reference to FIGS. As a semiconductor device using the present invention, a (digital) video camera, a (digital) still camera, a head-mounted display, a car navigation, a personal computer, a portable information terminal (a mobile computer, a mobile phone, and the like) are exemplified. Further, the present invention can be applied to a portable information terminal equipped with a PHS (Personal Handyphone System), which has recently been in the spotlight.

  FIG. 5A illustrates a mobile computer (mobile computer), which includes a main body 2001, a camera unit 2002, an image receiving unit 2003, operation switches 2004, and a display device 2005. The present invention can be applied to the display device 2005 and internal circuits.

  FIG. 5B illustrates a head-mounted display, which includes a main body 2101, a display device 2102, and a band portion 2103. The present invention can be applied to the display device 2102.

  FIG. 5C illustrates a car navigation system, which includes a main body 2201, a display device 2202, operation switches 2203, and an antenna 2204. The present invention can be applied to the display device 2202 and internal circuits.

  FIG. 5D illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display device 2304, operation switches 2305, and an antenna 2306. The present invention can be applied to the display device 2304, a high-frequency circuit for communication, and the like.

  FIG. 5E illustrates a video camera, which includes a main body 2401, a display device 2402, an audio input portion 2403, operation switches 2404, a battery 2405, and an image receiving portion 2406. The present invention can be applied to the display device 2402.

  As described above, the applicable range of the present invention is extremely wide, and it can be applied to display media in all fields. In addition, as long as the product requires a semiconductor circuit such as an IC or an LSI, the application is not limited.

FIG. 4 illustrates a manufacturing process of an active matrix substrate. FIG. 4 illustrates a manufacturing process of an active matrix substrate. FIG. 4 illustrates a manufacturing process of an active matrix substrate. 4A to 4C illustrate a manufacturing process of a silicon gate type TFT. FIG. 3 illustrates an example of an electronic device. FIG. 4 illustrates electric characteristics of a TFT.

Claims (9)

A crystalline silicon film in which a source region, a drain region, and an LDD region and a channel formation region are formed over a substrate having an insulating surface;
A gate insulating film formed on the channel formation region, a gate electrode formed on the gate insulating film,
A sidewall formed in contact with a side surface of the gate electrode,
A semiconductor device, wherein a silicide layer is formed on surfaces of the gate electrode, the source region, and the drain region. A crystalline silicon film in which a source region, a drain region, and an LDD region and a channel formation region are formed over a substrate having an insulating surface;
A gate insulating film formed on the channel formation region, a gate electrode formed on the gate insulating film,
A sidewall formed in contact with a side surface of the gate electrode,
The LDD region is arranged below the sidewall,
A semiconductor device, wherein a silicide layer is formed on surfaces of the gate electrode, the source region, and the drain region. A crystalline silicon film in which a source region, a drain region, and an LDD region and a channel formation region are formed over a substrate having an insulating surface;
A gate insulating film formed on the channel formation region, a gate electrode formed on the gate insulating film,
A sidewall formed in contact with a side surface of the gate electrode,
The LDD region is arranged below the sidewall,
A semiconductor device, wherein cobalt silicide is formed on surfaces of the gate electrode, the source region, and the drain region. A crystalline silicon film in which a source region, a drain region, and an LDD region and a channel formation region are formed over a substrate having an insulating surface;
A gate insulating film formed on the channel formation region, a gate electrode formed on the gate insulating film,
A sidewall formed in contact with a side surface of the gate electrode,
The LDD region is arranged below the sidewall,
A semiconductor device, wherein a silicide of titanium, cobalt, tungsten, tantalum or molybdenum is formed on surfaces of the source region and the drain region. In any one of claims 1 to 4,
A semiconductor device, wherein the substrate having an insulating surface is a quartz substrate. In any one of claims 1 to 5,
The semiconductor device, wherein the gate electrode is made of silicon. In any one of claims 1 to 6,
A semiconductor device, wherein the source region and the drain region have N-type conductivity. In any one of claims 1 to 7,
A semiconductor device, wherein the crystalline silicon film is crystallized by holding a catalytic element for promoting crystallization with respect to an amorphous silicon film and performing heat treatment. In any one of claims 1 to 8,
An electronic device including the semiconductor device.

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