JP2004235200A

JP2004235200A - Semiconductor apparatus and its manufacturing method

Info

Publication number: JP2004235200A
Application number: JP2003018563A
Authority: JP
Inventors: Takeshi Mitsushima; 猛光嶋
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2003-01-28
Filing date: 2003-01-28
Publication date: 2004-08-19

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the situation in which the film remainder of a conductive film to be a capacitance upper electrode is generated on the sides of a capacitance lower electrode and a wiring. <P>SOLUTION: A semiconductor apparatus has the capacitance lower electrode 111a and the leading-out wiring 111b formed on a first insulating film 110 formed on a semiconductor substrate 100 by the same process, a capacitance insulating film 112a formed on the lower electrode 111a and formed in a region inner than a region in which the lower electrode 111a is formed, and the capacitance upper electrode 113a formed on the insulating film 112a and formed in a region inner than a region in which the insulating film 112a is formed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
半導体集積回路の高性能化の進展により、デジタル論理回路のみならずアナログ信号処理回路又は電源供給系回路等の半導体集積回路中に大容量の静電容量素子を組み込む必要性が高まってきている。
【０００３】
一般に用いられている静電容量素子としては、半導体基板中のｐｎ接合容量を利用するもの、金属若しくは導電性多結晶シリコン等よりなる電極と結晶性半導体基板との間に膜厚が薄いシリコン酸化膜等を介在させたＭＯＳ型容量素子、又は２層の導電性多結晶シリコン膜間に膜厚が薄いシリコン酸化膜等を介在させた２層ポリシリコン型容量素子等が知られている。これらは、電極の一方又は双方として半導体基板中の不純物拡散層又は導電性の多結晶シリコン膜を用いているので電気抵抗が高く、また、半導体基板中の空乏層の厚さ又は形状が印加される電界の強度によって変化するので容量値が電圧に対して一定ではない等の問題があった。
【０００４】
このような観点から、上下電極が金属膜で形成された平行平板型の金属−絶縁膜−金属（ＭＩＭ）型容量素子が求められるようになった。ＭＩＭ型容量素子は、トランジスタ等の半導体素子を作った後に半導体集積回路の上下配線層に配設することが容易であり、通常の多層配線プロセスに対して工程をわずかに付加することによって実現できるため、設計の自由度が大きく、製造コストが低い等のメリットが多い。
【０００５】
以下、ＭＩＭ型容量素子を有する従来の半導体装置について図４（ａ）〜（ｄ）及び図５（ａ）〜（ｃ）を参照しながら説明する。
【０００６】
図４（ａ）に示すように、半導体基板１１の上に絶縁膜１２を堆積した後、該絶縁膜１２の上に下部電極用の第１の金属膜１３を堆積する。次に、該第１の金属膜１３に対してフォトエッチングを行って容量下部電極１３ａを形成すると同時に、容量下部電極の第１の引き出し配線１３ｂを形成する。
【０００７】
次に、図４（ｂ）に示すように、プラズマＣＶＤ法により、絶縁膜１２の上に容量下部電極１３ａ及び第１の引き出し配線１３ｂを覆うように、シリコン酸化膜よりなる容量絶縁膜１４を堆積した後、図４（ｃ）に示すように、容量絶縁膜１４の上にＡｌ／Ｔｉ膜よりなる上部電極用の第２の金属膜１５としてＡｌ／Ｔｉ膜を堆積する。次に、図４（ｄ）に示すように、フォトリソグラフィーによりレジストパターンを形成した後、該レジストパターンをマスクに第２の金属膜１５に対して反応性イオンエッチング（以下、ＲＩＥという）を行って容量上部電極１５ａを形成する。
【０００８】
次に、図５（ａ）に示すように、容量絶縁膜１４及び容量上部電極１５ａの上にシリコン酸化膜よりなる層間絶縁膜１６を形成した後、図５（ｂ）に示すように、層間絶縁膜１６に対してレジストパターンをマスクにエッチングを行って第１のスルーホール１７ａ及び第２のスルーホール１７ｂを形成する。
【０００９】
次に、図５（ｃ）に示すように、スパッタ法により、容量上部電極１５ａ、第１の引き出し配線１３ｂ及び層間絶縁膜１６の上に、アルミニウム合金膜よりなる第３の金属膜を堆積した後、該第３の金属膜をＲＩＥによりパターニングして容量上部電極１５ａの第２の引き出し配線１８ａ及び第１の引き出し配線１３ｂと接続する第３の引き出し配線１８ｂを形成する。このようにすると、ＭＩＭ型容量素子を有する従来の半導体装置が完成する（例えば特許文献１）。
【００１０】
【特許文献１】
特開平８−３０６８６２号公報（第５−６頁、図１、図２）
【００１１】
【発明が解決しようとする課題】
ところで、従来の半導体装置の製造方法においては、容量下部電極１３ａを形成した後に容量上部電極用の第２の金属膜１５を堆積するため、第２の金属膜１５に対してＲＩＥを行った際に、容量下部電極１３ａ及び第１の引き出し配線１３ｂの側方に容量の絶縁膜１４を介して第２の金属膜１５の膜残りが生じる。その結果、容量下部電極１３ａと容量上部電極１５ａとの間に寄生容量が発生するため、ＭＩＭ型容量素子の容量精度が低下する。また、第１の引き出し配線１３ｂの側方に第２の金属膜１５の膜残りが生じると、第１の引き出し配線１３ｂと隣り合う他の配線とがショートする可能性もある。
【００１２】
前記に鑑み、本発明は、容量下部電極及び配線の側方に、容量上部電極となる導電膜の膜残りが発生する事態を防止することを目的とする。
【００１３】
【課題を解決するための手段】
上記の目的を達成するために、本発明に係る第１の半導体装置は、基板上に形成された第１の層間絶縁膜の上に同一の工程により形成された容量下部電極及び配線と、容量下部電極の上であって該容量下部電極が形成されている領域よりも内側の領域に形成された容量絶縁膜と、容量絶縁膜の上であって該容量絶縁膜が形成されている領域よりも内側の領域に形成された容量上部電極とを備えている。
【００１４】
本発明に係る第１の半導体装置によると、容量下部電極及び配線となる下層導電膜、容量絶縁膜となる絶縁膜並びに容量上部電極となる上層導電膜を堆積した後に、順次パターニングを行って容量上部電極、容量絶縁膜及び容量下部電極をそれぞれ形成することが容易になるので、容量下部電極及び配線の側方に上層導電膜の膜残りが発生する事態を防止することができる。
【００１５】
本発明に係る第１の半導体装置は、容量下部電極、配線、容量絶縁膜及び容量上部電極を覆うように形成された第２の層間絶縁膜と、第２の層間絶縁膜に形成され、容量上部電極の上面と連通する第１のスルーホールと、第２の層間絶縁膜に形成され、配線の上面と連通する第２のスルーホールとを備えていてもよい。
【００１６】
この場合、第１のスルーホールと第２のスルーホールとは、同一の工程により形成されてもよいし、異なる工程により形成されてもよい。
【００１７】
また、本発明に係る第２の半導体装置は、基板上に形成された能動素子を覆うように形成された第１の層間絶縁膜と、第１の層間絶縁膜の上に形成された導電膜と、導電膜の上に形成された第２の層間絶縁膜と、第２の層間絶縁膜の上であって能動素子の上方に形成された容量下部電極と、容量下部電極の上であって該容量下部電極が形成されている領域よりも内側の領域に形成された容量絶縁膜と、容量絶縁膜の上であって該容量絶縁膜が形成されている領域よりも内側の領域に形成された容量上部電極とを備えている。
【００１８】
本発明に係る第２の半導体装置によると、容量下部電極及び配線となる下層導電膜、容量絶縁膜となる絶縁膜並びに容量上部電極となる上層導電膜を堆積した後に、順次パターニングを行って容量上部電極、容量絶縁膜及び容量下部電極をそれぞれ形成することが容易になるので、容量下部電極及び配線の側方に上層導電膜の膜残りが発生する事態を防止することができる。また、容量素子と能動素子との間に導電膜が介在していることにより、能動素子に電圧を印加してもその電圧の影響が容量素子に及ばないため、能動素子の上方に容量素子を形成しても寄生容量等は変化しないので、容量素子の上方に容量素子を配置することが可能になる。従って、半導体装置のレイアウト上の自由度が向上するので、半導体装置の微細化が可能になる。
【００１９】
本発明に係る第２の半導体装置において、容量下部電極、配線、容量絶縁膜及び容量上部電極を覆うように形成された第３の層間絶縁膜と、第３の層間絶縁膜に形成され、容量上部電極の上面と連通する第１のスルーホールと、第３の層間絶縁膜に形成され、配線の上面と連通する第２のスルーホールとを備えていてもよい。
【００２０】
この場合、第１のスルーホールと第２のスルーホールとは、同一の工程により形成されてもよいし、異なる工程により形成されてもよい。
【００２１】
本発明に係る第１又は第２の半導体装置が第１のスルーホール及び第２のスルーホールを備えている場合、第１のスルーホールと第２のスルーホールとは異なる工程により形成されることが好ましい。
【００２２】
このようにすると、層間絶縁膜における容量上部電極の上側部分の膜厚及び配線の上側部分の膜厚に応じて適切なエッチングを行うことができるため、相対的に膜厚が薄い層間絶縁膜における容量上部電極の上側部分に対するエッチングが過度に行われて容量上部電極が膜減りする事態が防止される。従来においては容量上部電極及び容量絶縁膜に突き抜けが発生するおそれがあったが、これを防ぐことができる。また、上部電極及び配線のそれぞれのデザインルールに適した開口径でスルーホールを形成することができるので、回路設計の自由度が増加する。
【００２３】
本発明に係る第１又は第２の半導体装置において、第１のスルーホールの径は第２のスルーホールの径よりも大きいことが好ましい。
【００２４】
このようにすると、第１のスルーホールのアスペクト比が小さくなるので、スルーホール形成の際に容量上部電極に溜まる電子が減少して上部電極に対するダメージを抑制できると共に、第２のスルーホールの径は小さいので配線との位置ずれが生じる事態を防止することができる。
【００２５】
また、上記の目的を達成するために、本発明に係る第１の半導体装置の製造方法は、基板上に形成された第１の層間絶縁膜の上に第１の導電膜を形成する工程と、第１の導電膜の上に絶縁膜を形成する工程と、絶縁膜の上に第２の導電膜を形成する工程と、第２の導電膜をパターニングして容量上部電極を形成する工程と、絶縁膜をパターニングして容量絶縁膜を形成する工程と、第１の導電膜をパターニングして容量下部電極及び配線を形成する工程とを備え、容量絶縁膜は、容量下部電極が形成される領域よりも内側の領域に形成され、容量上部電極は、容量絶縁膜が形成される領域よりも内側の領域に形成されるものである。
【００２６】
本発明に係る第１の半導体装置の製造方法によると、容量下部電極及び配線となる下層導電膜、容量絶縁膜となる絶縁膜並びに容量上部電極となる上層導電膜を堆積した後に、順次パターニングを行って容量上部電極、容量絶縁膜及び容量下部電極をそれぞれ形成することが容易になるので、容量下部電極及び配線の側方に上層導電膜の膜残りが発生する事態を防止することができる。
【００２７】
本発明に係る第１の半導体装置の製造方法は、容量下部電極及び配線を形成する工程よりも後に、容量下部電極、配線、容量絶縁膜及び容量上部電極を覆うように第２の層間絶縁膜を形成する工程と、第２の層間絶縁膜に容量上部電極の上面と連通する第１のスルーホールを形成する工程と、第２の層間絶縁膜に配線の上面と連通する第２のスルーホールを形成する工程とを備えていてもよい。
【００２８】
この場合、第１のスルーホールと第２のスルーホールとは、同一の工程により形成されてもよいし、異なる工程により形成されてもよい。
【００２９】
本発明に係る第１の半導体装置の製造方法において、第２の導電膜をパターニングする工程、絶縁膜をパターニングする工程及び第１の導電膜をパターニングする工程は、いずれもレジストパターンをマスクにして行われることが好ましい。
【００３０】
このようにすると、各工程においてレジストパターンをマスクにしてパターニングする際に、該レジストパターンはすでにパターンニングされた領域を覆っているため、該パターニングされた領域にダメージを与えることを防止することができる。
【００３１】
また、本発明に係る第２の半導体装置の製造方法は、基板上に形成された能動素子を覆うように第１の層間絶縁膜を形成する工程と、第１の層間絶縁膜の上に第１の導電膜を形成する工程と、第１の導電膜の上に第２の層間絶縁膜を形成する工程と、第２の層間絶縁膜の上に第２の導電膜を形成する工程と、第２の導電膜の上に絶縁膜を形成する工程と、絶縁膜の上に第３の導電膜を形成する工程と、第３の導電膜をパターニングして容量上部電極を形成する工程と、絶縁膜をパターニングして容量絶縁膜を形成する工程と、第２の導電膜をパターニングして容量下部電極及び配線を形成する工程とを備え、容量下部電極は、前記能動素子の上方に形成され、容量絶縁膜は、容量下部電極が形成される領域よりも内側の領域に形成され、容量上部電極は、容量絶縁膜が形成される領域よりも内側の領域に形成されるものである。
【００３２】
本発明に係る第２の半導体装置の製造方法によると、容量下部電極及び配線となる下層導電膜、容量絶縁膜となる絶縁膜並びに容量上部電極となる上層導電膜を堆積した後に、順次パターニングを行って容量上部電極、容量絶縁膜及び容量下部電極をそれぞれ形成することが容易になるので、容量下部電極及び配線の側方に上層導電膜の膜残りが発生する事態を防止することができる。また、容量素子と能動素子との間に導電膜が介在していることにより、能動素子に電圧を印加してもその電圧の影響が容量素子に及ばないため、能動素子の上方に容量素子を形成しても寄生容量等は変化しないので、容量素子の上方に容量素子を配置することが可能になる。従って、半導体装置のレイアウト上の自由度が向上するので、半導体装置の微細化が可能になる。
【００３３】
本発明に係る第２の半導体装置の製造方法は、容量下部電極及び配線を形成する工程よりも後に、容量下部電極、配線、容量絶縁膜及び容量上部電極を覆うように第３の層間絶縁膜を形成する工程と、第３の層間絶縁膜に容量上部電極の上面と連通する第１のスルーホールを形成する工程と、第３の層間絶縁膜に配線の上面と連通する第２のスルーホールを形成する工程とを備えていてもよい。
【００３４】
この場合、第１のスルーホールと第２のスルーホールとは、同一の工程により形成されてもよいし、異なる工程により形成されてもよい。
【００３５】
本発明に係る第２の半導体装置の製造方法において、第３の導電膜をパターニングする工程、絶縁膜をパターニングする工程及び第２の導電膜をパターニングする工程は、いずれもレジストパターンをマスクにして行われることが好ましい。
【００３６】
このようにすると、各工程においてレジストパターンをマスクにしてパターニングする際、該レジストパターンはすでにパターンニングされた領域を覆っているため、該パターニングされた領域にダメージを与えることを防止することができる。
【００３７】
本発明に係る第１又は第２の半導体装置の製造方法は、容量下部電極はアルミ合金を含み、容量下部電極及び配線を形成する工程の後に、容量上部電極及び容量下部電極に対して熱処理を行う工程を備えることが好ましい。
【００３８】
このようにすると、下部電極及び配線となる第１の導電膜をパターニングをした後に上部電極及び下部電極に対して熱処理を行うため、下部電極をパターニングする前に熱処理が行われている場合に下部電極表面に析出する金属が原因となるパターニング後の膜残りが発生する事態を防止することができる。
【００３９】
本発明に係る第１又は第２の半導体装置の製造方法において、第１のスルーホールと第２のスルーホールとは異なる工程によって形成されることが好ましい。
【００４０】
このようにすると、層間絶縁膜における容量上部電極の上側部分の膜厚及び配線の上側部分の膜厚に応じて適切なエッチングを行うことができるため、相対的に膜厚が薄い層間絶縁膜における容量上部電極の上側部分に対するエッチングが過度に行われて容量上部電極が膜減りする自体が防止される。従来においては容量上部電極及び容量絶縁膜に突き抜けが発生するおそれがあったが、これを防ぐことができる。また、上部電極及び配線のそれぞれのデザインルールに適した開口径でスルーホールを形成することができるので、回路設計の自由度が増加する。
【００４１】
本発明に係る第１又は第２の半導体装置の製造方法において、第１のスルーホールの径は第２のスルーホールの径よりも大きいことが好ましい。
【００４２】
このようにすると、第１のスルーホールのアスペクト比が小さくなるので、スルーホール形成の際に容量上部電極に溜まる電子が減少して上部電極に対するダメージを抑制できると共に、第２のスルーホールの径は小さいので配線との位置ずれが生じる事態を防止することができる。
【００４３】
【発明の実施の形態】
（第１の実施形態）
以下、本発明の第１の実施形態に係る半導体装置の製造方法について、図１（ａ）〜（ｄ）及び図２（ａ）〜（ｄ）を参照しながら説明する。
【００４４】
図１（ａ）に示すように、スパッタ法により、半導体基板１００上に堆積された第１の絶縁膜１１０の上に、Ｔｉ／ＴｉＮ／ＡｌＣｕ／ＴｉＮ／Ｔｉよりなり、膜厚が約６００ｎｍであって容量下部電極及び配線となる第１の金属膜１１１を堆積した後、ＳｉＨ_４、Ｎ_２Ｏ及びＡｒよりなる反応ガスを用いるプラズマＣＶＤ法により、該第１の金属膜１１１の上にシリコン酸化膜よりなる容量用の第２の絶縁膜１１２を２０〜１００ｎｍの厚さに堆積する。次に、スパッタ法により、第２の絶縁膜１１２の上に、Ｔｉ／ＴｉＮ／ＡｌＣｕよりなり、膜厚が約２００ｎｍであって容量上部電極となる金属膜１１３を堆積する。
【００４５】
次に、図１（ｂ）に示すように、フォトリソグラフィーによりレジストパターンを形成した後、該レジストパターンをマスクに第２の金属膜１１３に対して反応性イオンエッチング（以下、ＲＩＥという）を行って容量上部電極１１３ａを形成する。尚、容量上部電極１１３ａを形成した際には、該容量上部電極１１３ａに対して熱処理は行わず、後述する容量下部電極１１１ａを形成した後に一括して行う。
【００４６】
次に、図１（ｃ）に示すように、フォトリソグラフィーによりレジストパターンを形成した後、該レジストパターンをマスクに第２の絶縁膜１１２に対してＲＩＥを行って容量絶縁膜１１２ａを形成する。このとき、容量絶縁膜１１２ａは、該容量絶縁膜１１２ａが形成される領域よりも内側の領域に容量上部電極１１３ａが収まるように形成される。このようにして、容量絶縁膜１１２ａに対してレジストパターンをマスクにエッチングを行って容量絶縁膜１１２ａを形成するので、そのエッチングの際には容量上部電極１１３ａはレジストパターンに覆われるため、エッチングの際のイオン、ラジカルの影響を直接受けることがなくなってダメージを受けることがない。
【００４７】
次に、図１（ｄ）に示すように、フォトリソグラフィーによりレジストパターンを形成した後、該レジストパターンをマスクに第１の金属膜１１１に対してＲＩＥを行って容量下部電極１１１ａと容量下部電極用の第１の引き出し配線１１１ｂとを同時に形成する。このとき、容量下部電極１１１ａは、該容量下部電極１１１ａが形成される領域よりも内側の領域に容量絶縁膜１１２ａが収まるように形成される。このようにして、レジストパターンをマスクに第１の金属膜１１１に対してエッチングを行って容量下部電極１１１ａを形成するので、そのエッチングの際には容量絶縁膜１１２ａはレジストパターンに覆われるため、エッチングの際のイオン、ラジカルの影響を直接受けることがなくなって下部容量絶縁膜１１２ａがダメージを受けることがない。
【００４８】
その後、水素雰囲気において、４００℃で約５分間の熱処理を行って水分を蒸発させることにより、水分を起因として発生する容量上部電極１１３ａ及び容量下部電極１１１ａの腐食を防ぐと共に、容量上部電極１１３ａ及び容量下部電極１１１ａの上に膜を堆積した場合にかかる応力を緩和する。このように、容量下部電極１１１ａ及び第１の引き出し配線１１１ｂとなる第１の金属膜１１１に対してパターニングした後に容量上部電極１１３ａ及び容量下部電極１１１ａに対して熱処理を行う。これにより、第１の金属膜１１１がアルミ合金よりなる場合は、容量下部電極１１１ａ及び第１の引き出し配線１１１ｂをパターニングする前に第１の金属膜１１１に対して熱処理が行われると、第１の金属膜の表面に析出する金属が原因となって発生するパターニング後の膜残りを防止することができる。ここで、アルミ合金とはアルミニウムと他の金属との合金のことであり、第１の金属膜１１１が例えばアルミニウムと銅との合金である場合には、容量下部電極１１１ａ及び第１の引き出し配線１１１ｂがパターニングされた後に熱処理が行われるので、パターニング前に第１の金属膜１１１に対して熱処理が行われると第１の金属膜１１１の表面に析出するＣｕが原因となって発生するエッチングの際の膜残りを防止することができる。
【００４９】
このように、図１（ａ）〜（ｄ）に示したように、容量下部電極１１１ａ及び第１の引き出し配線１１１ｂとなる第１の金属膜１１１、容量絶縁膜１１２ａとなる第２の絶縁膜１１２並びに容量上部電極１１３ａとなる第２の金属膜１１３を堆積した後に、順次パターニングを行って容量上部電極１１３ａ、容量絶縁膜１１２ａ並びに容量下部電極１１１ａ及び第１の引き出し配線１１１ｂとをそれぞれ形成するので、容量下部電極１１１ａ及び第１の引き出し配線１１１ｂの側方に、第２の金属膜１１３の膜残りが発生する事態を防止することができる。その結果、容量下部電極１１１ａと容量上部電極１１３ａとの間に第２の金属膜１１３の膜残りにより寄生容量は発生しないので、ＭＩＭ型容量素子の容量精度の低下を防止することができる。また、第１の引き出し配線１１１ｂの側方に発生する膜残りが原因となって第１の引き出し配線１１１ｂとその隣合う配線とがショートする事態を防止することができる。
【００５０】
次に、図２（ａ）に示すように、プラズマＣＶＤ法により、第１の絶縁膜１１０の上に、容量下部電極１１１ａ及び第１の引き出し配線１１１ｂ、容量絶縁膜１１２ａ並びに容量上部電極１１３ａを覆うように、シリコン酸化膜を例えば２０００ｎｍの厚さに堆積した後、ＣＭＰ法によりシリコン酸化膜を平坦化して層間絶縁膜１１４を形成する。
【００５１】
次に、図２（ｂ）に示すように、フォトリソグラフィーによりレジストパターンを形成した後、該レジストパターンをマスクに層間絶縁膜１１４に対してＲＩＥを行って、容量上部電極１１３ａの上面と連通する第１のスルーホール１１１５ａを形成する。
【００５２】
次に、図２（ｃ）に示すように、フォトリソグラフィーによりレジストパターンを形成した後、該レジストパターンをマスクに層間絶縁膜１１４に対してＲＩＥを行って、第１の引き出し配線１１１ｂの上面と連通する第２のスルーホール１１５ｂを形成する。
【００５３】
ところで、層間絶縁膜１１４における容量上部電極１１３ａの上側部分の膜厚は、第１の引き出し配線１１１ｂの上側部分の膜厚に比べて、おおよそ容量絶縁膜１１２ａ及び容量上部電極１１３ａの膜厚の合計分の厚さだけ薄くなる。従って、第１のスルーホール１１５ａ及び第２のスルーホール１１５ｂを同時に形成する場合は、第１のスルーホール１１５ａを形成する際のエッチングが過度になってしまうので、容量上部電極１１３ａが膜減りする事態が発生する。従来においては、容量上部電極１１３ａ及び容量絶縁膜１１２ａに突き抜けが発生してＭＩＭ型容量素子の形成ができなくなる可能性もあった。
【００５４】
しかしながら、本実施形態では、上記のように、第１のスルーホール１１５ａと第２のスルーホール１１５ｂとは異なる工程で形成されるため、層間絶縁膜１１４における容量上部電極１１３ａ及び第１の引き出し配線１１１ｂのそれぞれの上側部分の膜厚に応じて適切なエッチングを行うことができるので、容量上部電極１１３ａが膜減りすることを防止すると共に、ＭＩＭ型容量素子の形成ができなくなることを防ぐことができる。また、容量上部電極１１３ａ及び第１の引き出し配線１１１ｂのそれぞれのデザインルールに適した開口径でスルーホールを形成することができるので、回路設計の自由度が増加する。
【００５５】
また、第１のスルーホール１１５ａは、その径が第２のスルーホール１１５ｂの径よりも大きくなるように形成される。これにより、容量上部電極１１３ａの上面に対する第１のスルーホール１１５ａのアスペクト比は小さくなるので、スルーホールを形成する際に容量上部電極１１３ａに溜まる電子が減少して容量上部電極１１３ａに対するダメージを小さくできると共に、第２のスルーホール１１５ｂの径は小さいので、第１の引き出し配線１１１ｂとの位置ずれを防止することができる。また、第１の引き出し配線１１１ｂの上面に対する第２のスルーホール１１５ｂのアスペクト比は大きくなるが、配線の性質上、電子が溜まっても第１の引き出し配線１１１ｂに与えるダメージは少ない。尚、ここでいう径とは、第１のスルーホール１１５ａ又は第２のスルーホール１１５ｂの平面形状が方形である場合には対角線の長さを示し、第１のスルーホール１１５ａ又は第２のスルーホール１１５ｂの平面形状が円形である場合には直径を示す。
【００５６】
次に、図２（ｄ）に示すように、メタルＣＶＤ法により、層間絶縁膜１１４、第１のスルーホール１１５ａ及び第２のスルーホール１１５ｂの上にＴｉＮ膜とＷ膜とを順次堆積した後、ＣＭＰ法により層間絶縁膜１１４の上に堆積されたＴｉＮ膜及びＷ膜を除去すると、ＴｉＮ／Ｗよりなる第１のコンタクト１１６ａ及び第２のコンタクト１１６ｂが形成される。次に、スパッタ法により、層間絶縁膜１１４、第１のコンタクト１１６ａ及び第２のコンタクト１１６ｂの上にＴｉ／ＴｉＮ／ＡｌＣｕ／ＴｉＮ／Ｔｉよりなり、膜厚が約８００ｎｍである金属膜を堆積する。次に、フォトリソグラフィーによりレジストパターンを形成した後、該レジストパターンをマスクに上記金属膜に対してＲＩＥを行って第２の引き出し配線１１７ａ及び第３の引き出し配線１１７ｂを形成する。このようにすると、本発明の第１の実施形態に係るＭＩＭ型容量素子を有する半導体装置が完成する。
【００５７】
（第２の実施形態）
以下、本発明の第２の実施形態に係る半導体装置の製造方法について、図３（ａ）〜（ｃ）を参照しながら説明する。
【００５８】
図３（ａ）に示すように、半導体基板２００の上にリソグラフィー技術及びエッチング技術とを用いて分離２０１を形成する。次に、高密度プラズマＣＶＤ法により、半導体基板２００及び分離２０１の上にシリコン酸化膜を堆積した後、ＣＭＰ法により、該シリコン酸化膜を平坦化する。次に、半導体基板２００の上にゲート絶縁膜とポリシリコン膜とメタルシリサイド膜とを形成した後、リソグラフィー技術及びエッチング技術を用いてゲート電極２０２を形成する。
【００５９】
次に、図３（ｂ）に示すように、ＣＶＤ法により、半導体基板２００の上に、分離２０１及びゲート電極２０２を覆うようにボロンリンガラス膜２０３を堆積した後、ＣＭＰ法により、ボロンリンガラス膜２０３を平坦化する。次に、スパッタ法により、ボロンリンガラス膜２０３の上に全面に渡ってＴｉ／ＴｉＮ／ＡｌＣｕ／ＴｉＮ／Ｔｉよりなり、膜厚が約６００ｎｍである金属膜２０４を堆積する。このように、金属膜２０４をボロンリンガラス膜２０３の上に全面に渡って堆積することにより、半導体基板２００又はゲート電極２０２からの電気的な影響は金属膜２０４によって遮断される。
【００６０】
次に、第１の実施形態と同様にして、図３（ｃ）に示すように、第１の絶縁膜２１０、容量下部電極２１１ａ、第１の引き出し配線２１１ｂ、容量絶縁膜２１２ａ、容量上部電極２１３ａ、層間絶縁膜２１４、第１のコンタクト２１６ａ、第２のコンタクト２１６ｂ、第２の引き出し配線２１７ａ及び第３の引き出し配線２１７ｂを形成する。このようにすると、本発明の第３の実施形態に係るＭＩＭ型容量素子を有する半導体装置が完成する。
【００６１】
このように、ＭＩＭ型容量素子とゲート電極２０２との間に金属膜２０４が介在していることにより、ゲート電極２０２に電圧を印加してもその電圧の影響がＭＩＭ型容量素子に及ばないため、ゲート電極２０２の上方にＭＩＭ型容量素子を形成しても寄生容量は発生しているが変化しないので、ゲート電極の上方に容量素子を配置することが可能になる。従って、半導体装置のレイアウト上の自由度が向上するため、半導体基板２００の面積を有効活用できるので、半導体装置の微細化が可能になる。
【００６２】
尚、上記第１の実施形態では、ＭＩＭ型容量素子及び引き出し配線に寄生容量が発生することを懸念してＭＩＭ型容量素子の下方には、他のゲート電極又は引き出し配線等の能動素子を形成していなかったが、本実施形態のように、ＭＩＭ型容量素子及び引き出し配線層に発生する寄生容量が一定となるように半導体装置を製造するので、ゲート電極２０２等の能動素子の上方にＭＩＭ型容量素子を配置することが可能になる。従って、半導体装置のレイアウト上の自由度が向上するので、半導体装置の微細化が可能になる。
【００６３】
また、以上の第１及び第２の実施形態において、第１の絶縁膜１１０及び２１０はシリコン酸化膜又はシリコン酸窒化膜でもよい。また、層間絶縁膜１１４及び２１４はシリコン酸窒化膜でもよい。
【００６４】
【発明の効果】
上述の通り、本発明に係る半導体装置によると、容量下部電極及び配線となる下層導電膜、容量絶縁膜となる絶縁膜並びに容量上部電極となる上層導電膜を堆積した後に、順次パターニングを行って容量上部電極、容量絶縁膜及び容量下部電極をそれぞれ形成することが容易になるので、容量下部電極及び配線の側方に上層導電膜の膜残りが発生する事態を防止することができる。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は本発明の第１の実施形態に係る半導体装置の製造方法を示す断面図である。
【図２】（ａ）〜（ｄ）は本発明の第１の実施形態に係る半導体装置の製造方法を示す断面図である。
【図３】（ａ）〜（ｃ）は本発明の第２の実施形態に係る半導体装置の製造方法を示す断面図である。
【図４】（ａ）〜（ｄ）は従来の半導体装置の製造方法を示す断面図である。
【図５】（ａ）〜（ｃ）は従来の半導体装置の製造方法を示す断面図である。
【符号の説明】
１００、２００半導体基板
１１０、２１０第１の絶縁膜
１１１第１の金属膜
１１１ａ、２１１ａ容量下部電極
１１１ｂ第１の引き出し配線
１１２第２の絶縁膜
１１２ａ、２１２ａ容量絶縁膜
１１３第２の金属膜
１１３ａ、２１３ａ容量上部電極
１１４、２１４層間絶縁膜
１１５ａ第１のスルーホール
１１５ｂ第２のスルーホール
１１６ａ、２１６ａ第１のコンタクト
１１６ｂ、２１６ｂ第２のコンタクト
１１７ａ、２１７ａ第２の引き出し配線
１１７ｂ、２１７ａ第３の引き出し配線
２０１分離
２０２ゲート電極
２０３ボロンリンガラス膜
２０４金属膜[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art With the advancement of the performance of semiconductor integrated circuits, there is an increasing need to incorporate large-capacity capacitive elements into semiconductor integrated circuits such as analog signal processing circuits or power supply circuits as well as digital logic circuits.
[0003]
A commonly used capacitance element utilizes a pn junction capacitance in a semiconductor substrate, and a thin silicon oxide film between an electrode made of metal or conductive polycrystalline silicon and a crystalline semiconductor substrate. A MOS capacitor having a film or the like or a two-layer polysilicon capacitor having a thin silicon oxide film or the like between two conductive polycrystalline silicon films is known. These use an impurity diffusion layer or a conductive polycrystalline silicon film in the semiconductor substrate as one or both of the electrodes, so that the electric resistance is high, and the thickness or shape of the depletion layer in the semiconductor substrate is applied. There is a problem that the capacitance value is not constant with respect to the voltage because it varies depending on the strength of the electric field.
[0004]
From such a viewpoint, a parallel plate type metal-insulating film-metal (MIM) type capacitive element in which upper and lower electrodes are formed of metal films has been demanded. The MIM-type capacitance element can be easily disposed in upper and lower wiring layers of a semiconductor integrated circuit after a semiconductor element such as a transistor is manufactured, and can be realized by adding a few steps to a normal multilayer wiring process. Therefore, there are many advantages such as a high degree of freedom in design and a low manufacturing cost.
[0005]
Hereinafter, a conventional semiconductor device having an MIM type capacitive element will be described with reference to FIGS. 4 (a) to 4 (d) and FIGS. 5 (a) to 5 (c).
[0006]
As shown in FIG. 4A, after an insulating film 12 is deposited on a semiconductor substrate 11, a first metal film 13 for a lower electrode is deposited on the insulating film 12. Next, photo-etching is performed on the first metal film 13 to form the capacitor lower electrode 13a, and at the same time, a first lead-out wiring 13b for the capacitor lower electrode is formed.
[0007]
Next, as shown in FIG. 4B, a capacitive insulating film 14 made of a silicon oxide film is formed on the insulating film 12 so as to cover the capacitive lower electrode 13a and the first lead-out wiring 13b by the plasma CVD method. After the deposition, as shown in FIG. 4C, an Al / Ti film is deposited on the capacitance insulating film 14 as the second metal film 15 for the upper electrode made of the Al / Ti film. Next, as shown in FIG. 4D, after forming a resist pattern by photolithography, reactive ion etching (hereinafter, referred to as RIE) is performed on the second metal film 15 using the resist pattern as a mask. To form a capacitor upper electrode 15a.
[0008]
Next, as shown in FIG. 5A, after an interlayer insulating film 16 made of a silicon oxide film is formed on the capacitor insulating film 14 and the capacitor upper electrode 15a, as shown in FIG. The first through hole 17a and the second through hole 17b are formed by etching the insulating film 16 using the resist pattern as a mask.
[0009]
Next, as shown in FIG. 5C, a third metal film made of an aluminum alloy film was deposited on the capacitor upper electrode 15a, the first lead-out wiring 13b, and the interlayer insulating film 16 by a sputtering method. After that, the third metal film is patterned by RIE to form a third extraction wiring 18b connected to the second extraction wiring 18a and the first extraction wiring 13b of the capacitor upper electrode 15a. By doing so, a conventional semiconductor device having an MIM type capacitive element is completed (for example, Patent Document 1).
[0010]
[Patent Document 1]
JP-A-8-306862 (pages 5-6, FIGS. 1 and 2)
[0011]
[Problems to be solved by the invention]
By the way, in the conventional method of manufacturing a semiconductor device, the RIE is performed on the second metal film 15 in order to deposit the second metal film 15 for the upper capacitor electrode after forming the lower capacitor electrode 13a. Then, a film residue of the second metal film 15 occurs on the side of the capacitor lower electrode 13a and the first lead-out wiring 13b via the capacitor insulating film 14. As a result, a parasitic capacitance is generated between the capacitance lower electrode 13a and the capacitance upper electrode 15a, so that the capacitance accuracy of the MIM type capacitance element is reduced. In addition, if a film residue of the second metal film 15 occurs on the side of the first lead-out line 13b, there is a possibility that the first lead-out line 13b and another line adjacent thereto are short-circuited.
[0012]
In view of the above, an object of the present invention is to prevent a situation in which a film residue of a conductive film serving as a capacitor upper electrode occurs on the side of a capacitor lower electrode and a wiring.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a first semiconductor device according to the present invention includes a capacitor lower electrode and a wiring formed in the same process on a first interlayer insulating film formed on a substrate; A capacitor insulating film formed in a region above the lower electrode and inside a region where the capacitor lower electrode is formed; and a capacitor insulating film formed in a region above the capacitor insulating film and in which the capacitor insulating film is formed. And a capacitor upper electrode formed in the inner region.
[0014]
According to the first semiconductor device of the present invention, after depositing a lower conductive film serving as a capacitor lower electrode and a wiring, an insulating film serving as a capacitor insulating film, and an upper conductive film serving as a capacitor upper electrode, patterning is sequentially performed by performing patterning. Since the upper electrode, the capacitor insulating film, and the capacitor lower electrode can be easily formed, it is possible to prevent a situation in which a film residue of the upper conductive film occurs on the side of the capacitor lower electrode and the wiring.
[0015]
A first semiconductor device according to the present invention includes a second interlayer insulating film formed so as to cover a capacitor lower electrode, a wiring, a capacitor insulating film and a capacitor upper electrode, and a second interlayer insulating film formed on the second interlayer insulating film. A first through-hole communicating with the upper surface of the upper electrode and a second through-hole formed in the second interlayer insulating film and communicating with the upper surface of the wiring may be provided.
[0016]
In this case, the first through-hole and the second through-hole may be formed in the same step or may be formed in different steps.
[0017]
Further, a second semiconductor device according to the present invention includes a first interlayer insulating film formed so as to cover an active element formed on a substrate, and a conductive film formed on the first interlayer insulating film. A second interlayer insulating film formed on the conductive film, a capacitor lower electrode formed on the second interlayer insulating film and above the active element, and a capacitor lower electrode formed on the capacitor lower electrode. A capacitor insulating film formed in a region inside the region where the capacitor lower electrode is formed; and a capacitor insulating film formed in a region on the capacitor insulating film and inside the region where the capacitor insulating film is formed. And a capacitor upper electrode.
[0018]
According to the second semiconductor device of the present invention, after depositing a lower conductive film serving as a capacitor lower electrode and a wiring, an insulating film serving as a capacitor insulating film, and an upper conductive film serving as a capacitor upper electrode, patterning is sequentially performed by performing patterning. Since the upper electrode, the capacitor insulating film, and the capacitor lower electrode can be easily formed, it is possible to prevent a situation in which a film residue of the upper conductive film occurs on the side of the capacitor lower electrode and the wiring. In addition, since a conductive film is interposed between the capacitive element and the active element, even if a voltage is applied to the active element, the effect of the voltage does not reach the capacitive element. Even if it is formed, the parasitic capacitance and the like do not change, so that the capacitor can be arranged above the capacitor. Therefore, the degree of freedom in the layout of the semiconductor device is improved, so that the semiconductor device can be miniaturized.
[0019]
In the second semiconductor device according to the present invention, a third interlayer insulating film formed so as to cover the capacitor lower electrode, the wiring, the capacitor insulating film, and the capacitor upper electrode; and a capacitor formed in the third interlayer insulating film, A first through hole communicating with the upper surface of the upper electrode and a second through hole formed in the third interlayer insulating film and communicating with the upper surface of the wiring may be provided.
[0020]
In this case, the first through-hole and the second through-hole may be formed in the same step or may be formed in different steps.
[0021]
When the first or second semiconductor device according to the present invention has the first through hole and the second through hole, the first and second through holes are formed by different processes. Is preferred.
[0022]
By doing so, appropriate etching can be performed according to the film thickness of the upper portion of the capacitor upper electrode and the film thickness of the upper portion of the wiring in the interlayer insulating film. This prevents a situation in which the upper portion of the capacitor upper electrode is excessively etched and the film of the capacitor upper electrode is reduced. In the related art, there is a risk that penetration may occur in the capacitor upper electrode and the capacitor insulating film, but this can be prevented. Further, since the through hole can be formed with an opening diameter suitable for each design rule of the upper electrode and the wiring, the degree of freedom in circuit design is increased.
[0023]
In the first or second semiconductor device according to the present invention, the diameter of the first through hole is preferably larger than the diameter of the second through hole.
[0024]
By doing so, the aspect ratio of the first through hole is reduced, so that electrons accumulated in the capacitor upper electrode during formation of the through hole are reduced, and damage to the upper electrode can be suppressed, and the diameter of the second through hole can be reduced. Is small, it is possible to prevent a situation in which positional deviation from the wiring occurs.
[0025]
In order to achieve the above object, a first method for manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive film on a first interlayer insulating film formed on a substrate. Forming an insulating film on the first conductive film, forming a second conductive film on the insulating film, and forming a capacitor upper electrode by patterning the second conductive film. Forming a capacitor insulating film by patterning the insulating film, and forming a capacitor lower electrode and a wiring by patterning the first conductive film, wherein the capacitor lower electrode is formed. The capacitor upper electrode is formed in a region inside the region, and the capacitor upper electrode is formed in a region inside the region where the capacitor insulating film is formed.
[0026]
According to the first method of manufacturing a semiconductor device according to the present invention, after depositing a lower conductive film serving as a capacitor lower electrode and a wiring, an insulating film serving as a capacitor insulating film, and an upper conductive film serving as a capacitor upper electrode, patterning is performed sequentially. This facilitates the formation of the capacitor upper electrode, the capacitor insulating film, and the capacitor lower electrode, respectively, so that the film remaining of the upper conductive film on the side of the capacitor lower electrode and the wiring can be prevented.
[0027]
In the first method for manufacturing a semiconductor device according to the present invention, the second interlayer insulating film is formed so as to cover the lower capacitor electrode, the wiring, the capacitor insulating film, and the upper capacitor electrode after the step of forming the lower capacitor electrode and the wiring. Forming a first through hole communicating with the upper surface of the capacitor upper electrode in the second interlayer insulating film; and forming a second through hole communicating with the upper surface of the wiring in the second interlayer insulating film. And a step of forming
[0028]
In this case, the first through-hole and the second through-hole may be formed in the same step or may be formed in different steps.
[0029]
In the first method for manufacturing a semiconductor device according to the present invention, the step of patterning the second conductive film, the step of patterning the insulating film, and the step of patterning the first conductive film are all performed using the resist pattern as a mask. It is preferably performed.
[0030]
In this manner, when patterning is performed using the resist pattern as a mask in each step, the resist pattern covers the already-patterned region, thereby preventing the patterned region from being damaged. it can.
[0031]
In a second method of manufacturing a semiconductor device according to the present invention, a step of forming a first interlayer insulating film so as to cover an active element formed on a substrate; and a step of forming a first interlayer insulating film on the first interlayer insulating film. Forming a first conductive film, forming a second interlayer insulating film on the first conductive film, forming a second conductive film on the second interlayer insulating film, Forming an insulating film on the second conductive film, forming a third conductive film on the insulating film, patterning the third conductive film to form a capacitor upper electrode; Patterning an insulating film to form a capacitive insulating film; and patterning a second conductive film to form a capacitive lower electrode and a wiring, wherein the capacitive lower electrode is formed above the active element. The capacitor insulating film is formed in a region inside the region where the capacitor lower electrode is formed, and Department electrode is to be formed in a region inside the region the capacitor insulating film is formed.
[0032]
According to the second method of manufacturing a semiconductor device according to the present invention, after depositing a lower conductive film serving as a capacitor lower electrode and a wiring, an insulating film serving as a capacitor insulating film, and an upper conductive film serving as a capacitor upper electrode, patterning is performed sequentially. This facilitates the formation of the capacitor upper electrode, the capacitor insulating film, and the capacitor lower electrode, respectively, so that the film remaining of the upper conductive film on the side of the capacitor lower electrode and the wiring can be prevented. In addition, since a conductive film is interposed between the capacitive element and the active element, even if a voltage is applied to the active element, the effect of the voltage does not reach the capacitive element. Even if it is formed, the parasitic capacitance and the like do not change, so that the capacitor can be arranged above the capacitor. Therefore, the degree of freedom in the layout of the semiconductor device is improved, so that the semiconductor device can be miniaturized.
[0033]
In the second method for manufacturing a semiconductor device according to the present invention, the third interlayer insulating film is formed so as to cover the lower capacitor electrode, the wiring, the capacitor insulating film, and the upper capacitor electrode after the step of forming the lower capacitor electrode and the wiring. Forming a first through hole communicating with the upper surface of the capacitor upper electrode in the third interlayer insulating film; and forming a second through hole communicating with the upper surface of the wiring in the third interlayer insulating film. And a step of forming
[0034]
In this case, the first through-hole and the second through-hole may be formed in the same step or may be formed in different steps.
[0035]
In the second method for manufacturing a semiconductor device according to the present invention, the step of patterning the third conductive film, the step of patterning the insulating film, and the step of patterning the second conductive film all use the resist pattern as a mask. It is preferably performed.
[0036]
In this manner, when patterning is performed using the resist pattern as a mask in each step, the resist pattern covers the already-patterned region, so that damage to the patterned region can be prevented. .
[0037]
In the first or second method for manufacturing a semiconductor device according to the present invention, the capacitor lower electrode includes an aluminum alloy, and after the step of forming the capacitor lower electrode and the wiring, heat treatment is performed on the capacitor upper electrode and the capacitor lower electrode. Preferably, the method includes a step of performing the step.
[0038]
With this configuration, since the heat treatment is performed on the upper electrode and the lower electrode after patterning the lower electrode and the first conductive film to be the wiring, the lower heat treatment is performed before the lower electrode is patterned. It is possible to prevent a situation in which a film residue after patterning due to a metal deposited on the electrode surface occurs.
[0039]
In the first or second method for manufacturing a semiconductor device according to the present invention, it is preferable that the first through-hole and the second through-hole are formed by different processes.
[0040]
By doing so, appropriate etching can be performed according to the film thickness of the upper portion of the capacitor upper electrode and the film thickness of the upper portion of the wiring in the interlayer insulating film. Excessive etching of the upper portion of the capacitor upper electrode is prevented, and the film of the capacitor upper electrode is reduced. In the related art, there is a risk that penetration may occur in the capacitor upper electrode and the capacitor insulating film, but this can be prevented. Further, since the through hole can be formed with an opening diameter suitable for each design rule of the upper electrode and the wiring, the degree of freedom in circuit design is increased.
[0041]
In the first or second method for manufacturing a semiconductor device according to the present invention, the diameter of the first through hole is preferably larger than the diameter of the second through hole.
[0042]
With this configuration, the aspect ratio of the first through hole is reduced, so that electrons accumulated in the capacitor upper electrode during the formation of the through hole are reduced, so that damage to the upper electrode can be suppressed and the diameter of the second through hole can be reduced. Is small, it is possible to prevent a situation in which a positional deviation from the wiring occurs.
[0043]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (d) and 2 (a) to 2 (d).
[0044]
As shown in FIG. 1A, on a first insulating film 110 deposited on a semiconductor substrate 100 by a sputtering method, the first insulating film 110 is made of Ti / TiN / AlCu / TiN / Ti and has a thickness of about 600 nm. After depositing a first metal film 111 serving as a capacitor lower electrode and a wiring, ₄ , N ₂ By a plasma CVD method using a reaction gas consisting of O and Ar, a second insulating film 112 for capacitance made of a silicon oxide film is deposited on the first metal film 111 to a thickness of 20 to 100 nm. Next, a metal film 113 made of Ti / TiN / AlCu, having a thickness of about 200 nm and serving as a capacitor upper electrode is deposited on the second insulating film 112 by a sputtering method.
[0045]
Next, as shown in FIG. 1B, after forming a resist pattern by photolithography, reactive ion etching (hereinafter, referred to as RIE) is performed on the second metal film 113 using the resist pattern as a mask. Thus, a capacitor upper electrode 113a is formed. When the capacitor upper electrode 113a is formed, heat treatment is not performed on the capacitor upper electrode 113a, but is performed collectively after forming the capacitor lower electrode 111a described later.
[0046]
Next, as shown in FIG. 1C, after forming a resist pattern by photolithography, RIE is performed on the second insulating film 112 using the resist pattern as a mask to form a capacitive insulating film 112a. At this time, the capacitor insulating film 112a is formed such that the capacitor upper electrode 113a fits in a region inside the region where the capacitor insulating film 112a is formed. In this manner, since the capacitor insulating film 112a is etched by using the resist pattern as a mask to form the capacitor insulating film 112a, the capacitor upper electrode 113a is covered with the resist pattern during the etching. It will not be directly affected by ions or radicals at the time and will not be damaged.
[0047]
Next, as shown in FIG. 1D, after forming a resist pattern by photolithography, RIE is performed on the first metal film 111 using the resist pattern as a mask to form a capacitor lower electrode 111a and a capacitor lower electrode. And the first lead-out wiring 111b are formed at the same time. At this time, the capacitor lower electrode 111a is formed such that the capacitor insulating film 112a fits in a region inside the region where the capacitor lower electrode 111a is formed. In this manner, the first metal film 111 is etched using the resist pattern as a mask to form the capacitor lower electrode 111a. Since the capacitor insulating film 112a is covered with the resist pattern during the etching, The lower capacitance insulating film 112a is not directly affected by ions and radicals at the time of etching and is not damaged.
[0048]
Thereafter, in a hydrogen atmosphere, a heat treatment is performed at 400 ° C. for about 5 minutes to evaporate moisture, thereby preventing corrosion of the capacitor upper electrode 113a and the capacitor lower electrode 111a generated due to moisture, and preventing the capacitor upper electrode 113a and the capacitor upper electrode 113a from being corroded. The stress applied when a film is deposited on the capacitor lower electrode 111a is reduced. After patterning the capacitor lower electrode 111a and the first metal film 111 serving as the first lead-out wiring 111b, heat treatment is performed on the capacitor upper electrode 113a and the capacitor lower electrode 111a. Thus, when the first metal film 111 is made of an aluminum alloy, if the first metal film 111 is subjected to a heat treatment before patterning the capacitor lower electrode 111a and the first extraction wiring 111b, the first Can be prevented from remaining after patterning caused by the metal deposited on the surface of the metal film. Here, the aluminum alloy is an alloy of aluminum and another metal. When the first metal film 111 is, for example, an alloy of aluminum and copper, the capacitor lower electrode 111a and the first lead wiring Since the heat treatment is performed after the patterning of the first metal film 111b, if the heat treatment is performed on the first metal film 111 before the patterning, the etching that occurs due to Cu precipitated on the surface of the first metal film 111 is performed. In this case, film residue can be prevented.
[0049]
As described above, as shown in FIGS. 1A to 1D, the first metal film 111 serving as the capacitor lower electrode 111a and the first lead-out wiring 111b, and the second insulating film serving as the capacitor insulating film 112a After depositing the second metal film 113 serving as the capacitor 112 and the capacitor upper electrode 113a, patterning is sequentially performed to form the capacitor upper electrode 113a, the capacitor insulating film 112a, the capacitor lower electrode 111a, and the first lead wiring 111b, respectively. Therefore, it is possible to prevent a situation in which the second metal film 113 remains on the side of the capacitor lower electrode 111a and the first lead-out wiring 111b. As a result, no parasitic capacitance occurs due to the remaining of the second metal film 113 between the capacitance lower electrode 111a and the capacitance upper electrode 113a, so that a decrease in capacitance accuracy of the MIM type capacitance element can be prevented. In addition, it is possible to prevent a situation in which the first lead-out wiring 111b and a wiring adjacent thereto are short-circuited due to a film residue generated on the side of the first lead-out wiring 111b.
[0050]
Next, as shown in FIG. 2A, a capacitor lower electrode 111a, a first lead wiring 111b, a capacitor insulating film 112a, and a capacitor upper electrode 113a are formed on the first insulating film 110 by a plasma CVD method. After a silicon oxide film is deposited to a thickness of, for example, 2000 nm so as to cover the silicon oxide film, the silicon oxide film is planarized by a CMP method to form an interlayer insulating film 114.
[0051]
Next, as shown in FIG. 2B, after forming a resist pattern by photolithography, RIE is performed on the interlayer insulating film 114 using the resist pattern as a mask to communicate with the upper surface of the capacitor upper electrode 113a. A first through hole 1115a is formed.
[0052]
Next, as shown in FIG. 2C, after forming a resist pattern by photolithography, RIE is performed on the interlayer insulating film 114 using the resist pattern as a mask, and the upper surface of the first lead-out wiring 111b is formed. A communicating second through-hole 115b is formed.
[0053]
Incidentally, the film thickness of the upper portion of the capacitor upper electrode 113a in the interlayer insulating film 114 is approximately the sum of the film thicknesses of the capacitor insulating film 112a and the capacitor upper electrode 113a compared to the film thickness of the upper portion of the first lead-out wiring 111b. It becomes thinner by the thickness of a minute. Therefore, when the first through-hole 115a and the second through-hole 115b are formed at the same time, the etching when forming the first through-hole 115a becomes excessive, so that the film of the capacitor upper electrode 113a is reduced. Things happen. Conventionally, punch-through may occur in the capacitor upper electrode 113a and the capacitor insulating film 112a, making it impossible to form an MIM-type capacitor.
[0054]
However, in the present embodiment, as described above, since the first through hole 115a and the second through hole 115b are formed in different steps, the capacitor upper electrode 113a and the first lead-out wiring in the interlayer insulating film 114 are formed. Since appropriate etching can be performed in accordance with the thickness of each upper portion of 111b, it is possible to prevent the capacity upper electrode 113a from being reduced in film thickness and to prevent the MIM-type capacitive element from being unable to be formed. it can. Further, since a through hole can be formed with an opening diameter suitable for each design rule of the capacitor upper electrode 113a and the first lead wiring 111b, the degree of freedom in circuit design is increased.
[0055]
The first through hole 115a is formed such that its diameter is larger than the diameter of the second through hole 115b. As a result, the aspect ratio of the first through hole 115a with respect to the upper surface of the capacitor upper electrode 113a is reduced, so that the electrons accumulated in the capacitor upper electrode 113a when forming the through hole are reduced, and damage to the capacitor upper electrode 113a is reduced. In addition, since the diameter of the second through hole 115b is small, it is possible to prevent the first through wiring 115b from being displaced from the first lead wiring 111b. Although the aspect ratio of the second through-hole 115b to the upper surface of the first lead-out line 111b increases, even if electrons are accumulated, damage to the first lead-out line 111b is small due to the nature of the line. Here, the diameter refers to the length of a diagonal line when the planar shape of the first through-hole 115a or the second through-hole 115b is a square, and indicates the length of the first through-hole 115a or the second through-hole 115a. When the plane shape of the hole 115b is circular, the diameter indicates the diameter.
[0056]
Next, as shown in FIG. 2D, after a TiN film and a W film are sequentially deposited on the interlayer insulating film 114, the first through hole 115a, and the second through hole 115b by a metal CVD method. When the TiN film and the W film deposited on the interlayer insulating film 114 are removed by the CMP method, a first contact 116a and a second contact 116b made of TiN / W are formed. Next, a metal film made of Ti / TiN / AlCu / TiN / Ti and having a thickness of about 800 nm is deposited on the interlayer insulating film 114, the first contact 116a, and the second contact 116b by a sputtering method. . Next, after forming a resist pattern by photolithography, RIE is performed on the metal film using the resist pattern as a mask to form a second lead wiring 117a and a third lead wiring 117b. By doing so, the semiconductor device having the MIM type capacitance element according to the first embodiment of the present invention is completed.
[0057]
(Second embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.
[0058]
As shown in FIG. 3A, a separation 201 is formed on a semiconductor substrate 200 by using a lithography technique and an etching technique. Next, after a silicon oxide film is deposited on the semiconductor substrate 200 and the separation 201 by high-density plasma CVD, the silicon oxide is planarized by CMP. Next, after forming a gate insulating film, a polysilicon film, and a metal silicide film on the semiconductor substrate 200, a gate electrode 202 is formed by using a lithography technique and an etching technique.
[0059]
Next, as shown in FIG. 3B, a boron phosphorus glass film 203 is deposited on the semiconductor substrate 200 by the CVD method so as to cover the separation 201 and the gate electrode 202, and then the boron phosphorus glass film is deposited by the CMP method. The glass film 203 is flattened. Next, a metal film 204 made of Ti / TiN / AlCu / TiN / Ti and having a thickness of about 600 nm is deposited on the entire surface of the boron phosphorus glass film 203 by sputtering. In this manner, by depositing the metal film 204 over the entire surface of the boron-phosphorus glass film 203, electrical influence from the semiconductor substrate 200 or the gate electrode 202 is cut off by the metal film 204.
[0060]
Next, similarly to the first embodiment, as shown in FIG. 3C, the first insulating film 210, the lower capacitor electrode 211a, the first lead-out wiring 211b, the capacitor insulating film 212a, and the upper capacitor electrode 213a, an interlayer insulating film 214, a first contact 216a, a second contact 216b, a second lead wiring 217a, and a third lead wiring 217b are formed. Thus, the semiconductor device having the MIM type capacitance element according to the third embodiment of the present invention is completed.
[0061]
Since the metal film 204 is interposed between the MIM-type capacitance element and the gate electrode 202, even if a voltage is applied to the gate electrode 202, the voltage does not affect the MIM-type capacitance element. Even if an MIM-type capacitance element is formed above the gate electrode 202, the parasitic capacitance is generated but does not change, so that the capacitance element can be arranged above the gate electrode. Accordingly, the degree of freedom in the layout of the semiconductor device is improved, and the area of the semiconductor substrate 200 can be effectively used, so that the semiconductor device can be miniaturized.
[0062]
In the first embodiment, an active element such as another gate electrode or a lead-out line is formed below the MIM-type capacitance element because of concern that parasitic capacitance may occur in the MIM-type capacitance element and the lead-out line. However, since the semiconductor device is manufactured such that the MIM-type capacitance element and the parasitic capacitance generated in the lead-out wiring layer are constant as in this embodiment, the MIM-type capacitance element and the MIM-type capacitor are disposed above the active element such as the gate electrode 202. It becomes possible to arrange the type capacitance element. Therefore, the degree of freedom in the layout of the semiconductor device is improved, so that the semiconductor device can be miniaturized.
[0063]
In the first and second embodiments, the first insulating films 110 and 210 may be a silicon oxide film or a silicon oxynitride film. Further, the interlayer insulating films 114 and 214 may be silicon oxynitride films.
[0064]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, after depositing the lower conductive film serving as the capacitor lower electrode and the wiring, the insulating film serving as the capacitor insulating film, and the upper conductive film serving as the capacitor upper electrode, patterning is performed sequentially. Since each of the capacitor upper electrode, the capacitor insulating film, and the capacitor lower electrode can be easily formed, it is possible to prevent a situation in which an upper conductive film remains on the side of the capacitor lower electrode and the wiring.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIGS. 3A to 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
4A to 4D are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
FIGS. 5A to 5C are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
100, 200 semiconductor substrate
110, 210 First insulating film
111 first metal film
111a, 211a Lower electrode of capacitor
111b First extraction wiring
112 Second insulating film
112a, 212a Capacitive insulating film
113 Second metal film
113a, 213a Capacitor upper electrode
114, 214 interlayer insulating film
115a 1st through hole
115b 2nd through hole
116a, 216a First contact
116b, 216b Second contact
117a, 217a Second lead-out wiring
117b, 217a Third extraction wiring
201 Separation
202 Gate electrode
203 Boron phosphorus glass film
204 metal film

Claims

A capacitor lower electrode and a wiring formed by the same process on a first interlayer insulating film formed on a substrate;
A capacitor insulating film formed in a region above the capacitor lower electrode and inside a region where the capacitor lower electrode is formed;
A capacitor upper electrode formed on the capacitor insulating film and in a region inside the region where the capacitor insulating film is formed.

A second interlayer insulating film formed so as to cover the capacitor lower electrode, the wiring, the capacitor insulating film, and the capacitor upper electrode;
A first through hole formed in the second interlayer insulating film and communicating with an upper surface of the capacitor upper electrode;
2. The semiconductor device according to claim 1, further comprising: a second through hole formed in the second interlayer insulating film and communicating with an upper surface of the wiring. 3.

A first interlayer insulating film formed so as to cover the active element formed on the substrate;
A conductive film formed on the first interlayer insulating film;
A second interlayer insulating film formed on the conductive film;
A capacitor lower electrode formed on the second interlayer insulating film and above the active element;
A capacitor insulating film formed in a region above the capacitor lower electrode and inside a region where the capacitor lower electrode is formed;
A capacitor upper electrode formed on the capacitor insulating film and in a region inside the region where the capacitor insulating film is formed.

A third interlayer insulating film formed to cover the capacitor lower electrode, the wiring, the capacitor insulating film, and the capacitor upper electrode;
A first through hole formed in the third interlayer insulating film and communicating with an upper surface of the capacitor upper electrode;
4. The semiconductor device according to claim 3, further comprising: a second through hole formed in the third interlayer insulating film and communicating with an upper surface of the wiring.

The method according to claim 2, wherein the first through hole and the second through hole are formed by different processes.

The semiconductor device according to claim 2, wherein a diameter of the first through hole is larger than a diameter of the second through hole.

Forming a first conductive film on the first interlayer insulating film formed on the substrate;
Forming an insulating film on the first conductive film;
Forming a second conductive film on the insulating film;
Patterning the second conductive film to form a capacitor upper electrode;
Patterning the insulating film to form a capacitive insulating film;
Patterning the first conductive film to form a capacitor lower electrode and a wiring,
The capacitor insulating film is formed in a region inside a region where the capacitor lower electrode is formed,
The method of manufacturing a semiconductor device, wherein the capacitor upper electrode is formed in a region inside a region where the capacitor insulating film is formed.

After the step of forming the capacitor lower electrode and the wiring,
Forming a second interlayer insulating film so as to cover the capacitor lower electrode, the wiring, the capacitor insulating film, and the capacitor upper electrode;
Forming a first through hole communicating with the upper surface of the capacitor upper electrode in the second interlayer insulating film;
Forming a second through-hole in the second interlayer insulating film, the second through-hole communicating with the upper surface of the wiring.

8. The method according to claim 7, wherein the step of patterning the second conductive film, the step of patterning the insulating film, and the step of patterning the first conductive film are all performed using a resist pattern as a mask. The manufacturing method of the semiconductor device described in the above.

Forming a first interlayer insulating film so as to cover the active element formed on the substrate;
Forming a first conductive film on the first interlayer insulating film;
Forming a second interlayer insulating film on the first conductive film;
Forming a second conductive film on the second interlayer insulating film;
Forming an insulating film on the second conductive film;
Forming a third conductive film on the insulating film;
Patterning the third conductive film to form a capacitor upper electrode;
Patterning the insulating film to form a capacitive insulating film;
Forming a capacitor lower electrode and a wiring by patterning the second conductive film,
The capacitor lower electrode is formed above the active element,
The capacitor insulating film is formed in a region inside a region where the capacitor lower electrode is formed,
The method of manufacturing a semiconductor device, wherein the capacitor upper electrode is formed in a region inside a region where the capacitor insulating film is formed.

After the step of forming the capacitor lower electrode and the wiring,
Forming a third interlayer insulating film so as to cover the capacitor lower electrode, the wiring, the capacitor insulating film, and the capacitor upper electrode;
Forming a first through hole in the third interlayer insulating film communicating with the upper surface of the capacitor upper electrode;
11. The method of manufacturing a semiconductor device according to claim 10, further comprising: forming a second through hole communicating with an upper surface of the wiring in the third interlayer insulating film.

11. The method according to claim 10, wherein the step of patterning the third conductive film, the step of patterning the insulating film, and the step of patterning the second conductive film are all performed using a resist pattern as a mask. The manufacturing method of the semiconductor device described in the above.

The capacitor lower electrode includes an aluminum alloy,
After the step of forming the capacitor lower electrode and the wiring,
The method of manufacturing a semiconductor device according to claim 7, further comprising: performing a heat treatment on the capacitor upper electrode and the capacitor lower electrode.

12. The method according to claim 8, wherein the first through hole and the second through hole are formed by different processes.

The method according to claim 8, wherein a diameter of the first through hole is larger than a diameter of the second through hole.