JP2004234791A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the efficiency and speed of a series of operation for an accessing processing. <P>SOLUTION: In the semiconductor memory device being an amplification type cross point memory, a reset switch Trst short-circuiting a common node electrode NE to ground any time is provided, the common node electrode NE is kept in a state of being separated from a bit line BL, the reset switch Trst is transited from on to off and from off to on. Thereby, potential variation of a floating node at the time of holding data in a cross point type ferroelectric memory is prevented, while in an amplification type memory having a sense transistor Ts, timing control of data read-out operation from a memory cell can be simplified remarkably. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory.
[0002]
[Prior art]
Semiconductor memories, particularly FeRAMs using ferroelectrics, are attracting attention as easy-to-use devices having both high-speed access and nonvolatile storage, and are expected to have a large capacity.
FeRAM is small in size, has low power consumption, and is resistant to impact. If the unit cost per bit is reduced due to the increase in capacity, it is promising as a recording medium for voice and images.
Also, with the miniaturization of semiconductor processing dimensions, instead of directly driving bit lines with memory cells, weak signals generated from small memory cells are temporarily received by the gate of the FET as a sense transistor, and bit Attention has been paid to amplification type semiconductor memories that drive lines.
For example, in the following document, the present applicant proposes an amplification type and cross-point type semiconductor memory device in which a plurality of ferroelectric capacitors are shared by one gain FET, and there is almost no area overhead due to the installation of a gain circuit. .
[Patent Document 1] JP-A-2002-197857
[0003]
FIG. 7 shows a circuit configuration example of such a semiconductor memory device, that is, an amplification type memory having a built-in sense transistor. FIG. 7 shows only one memory unit MU constituting the memory array. Actually, a plurality of such memory units MU are repeatedly arranged in the bit line BL direction and the word line WL direction to form a memory array.
[0004]
The memory unit MU in FIG. 7 includes a plurality (here, four examples) of ferroelectric capacitors C1, C2, C3, and C4 connected to the common node electrode NE. Each of the capacitors C1, C2, C3, and C4 is a memory cell that stores different data.
One end of each of the capacitors C1, C2, C3, C4 is connected to the common node electrode NE. The other ends are connected to the plate lines PL1, PL2, PL3, and PL4, respectively, and are controlled by the plate lines PL1 to PL4.
[0005]
Further, a read access transistor Tr, a write access transistor Tw, and a sense transistor Ts, each of which is constituted by an FET, are provided.
The sense transistor Ts is a depletion-type N-channel MOS-FET, and its gate is connected to the common node electrode NE. Further, one of the source / drain is connected to the fixed voltage source Vcc, and the other is connected to the bit line BL via the read access transistor Tr.
In the read access transistor Tr, one of a source and a drain is connected to the sense transistor Ts, and the other is connected to the bit line BL. The gate is connected to the read word line WLr, so that the read access transistor Tr is on / off controlled by the read word line WLr.
In the write access transistor Tr, one of a source and a drain is connected to the common node electrode NE, and the other is connected to the bit line BL. The gate is connected to the write word line WLw, so that the write access transistor Tw is on / off controlled by the write word line WLw.
[0006]
A voltage is applied to each of the plate lines PL (PL1 to PL4) and each of the word lines WL (WLr, WLw) by a drive circuit (not shown) according to a predetermined operation sequence at the time of writing and reading.
[0007]
At the time of data reading, for example, at the time of reading data from the capacitor C1, for example, the read word line WLr is selected, and the plate line PL1 is driven with the plate lines PL2 to PL4 fixed at 0V.
As a result, charges are released from the capacitor C1 to the common node electrode NE. At this time, the write word line WLw is off, and the common node electrode NE is disconnected from the bit line BL. That is, the charge from the cell capacitor C1 does not directly drive the bit line BL, but drives only the gate electrode of the sense transistor Ts. At this time, since the read access transistor Tr is on because the read word line WLr is selected, the sense transistor Ts drives the bit line BL according to the voltage applied to its gate. Then, data can be read out by sensing the potential of the bit line BL driven in this manner with a sense amplifier (not shown).
[0008]
On the other hand, at the time of data writing, write word line WLw is selected, and write access transistor Tw is turned on. The read access transistor Tr is turned off. Then, since the common node electrode NE is connected to the bit line BL, the bit line BL and the plate line are driven to required states, respectively, so that the bit line BL and the plate A voltage is applied as a potential difference of the line PL (x), and data is written.
[0009]
In such an amplification type semiconductor memory including the sense transistor Ts, it is not necessary for the capacitor C to directly drive the bit line BL when reading data. Therefore, a large signal can be obtained even with a small capacitor, which is suitable for miniaturization.
[0010]
[Problems to be solved by the invention]
By the way, the above-mentioned amplification type cross point memory has two access transistors (Tr, Tw) respectively corresponding to reading and writing. However, as understood from the configuration of FIG. 7, when it is desired to set the common node electrode NE to a desired potential, the only option is to supply the potential from the bit line BL via the write access transistor Tw. For this reason, it is necessary to drive the write access transistor Tw in a timely manner even at the time of reading, and there is a problem that access becomes complicated.
[0011]
FIG. 8 shows an example of operation timing at the time of reading. One data read from a certain memory cell is executed by the respective operations at timings R1 to R8 in FIG.
In this operation example, a case of reading data from capacitor C1 connected to plate line PL1 will be described as an example.
[0012]
Timing R1: With the bit line BL equalized to 0 V, first, a high-level pulse is applied to the write word line WLw to turn on the write access transistor Tw. Thus, the common node electrode NE which has been at an unstable potential in a floating state is once connected to the ground level. At this point, the plate lines PL1 to PL4 are all connected to the ground level.
Timing R2: The pulse to the write word line WLw is turned off, and the common node electrode NE returns to the floating state again.
Timing R3: A pulse is generated on the plate line PL selected for reading data from the capacitor C1. As a result, different signals ((1) or (2)) are generated at the common node electrode NE depending on the polarization state of the ferroelectric capacitor C1.
Timing R4: The read word line WLr is set to the high level, and the read access transistor Tr is turned on. As a result, the sense transistor Ts raises the potential of the bit line BL with the driving ability according to the potential of the common node electrode NE connected to its gate ((3) or (4)).
Timing R5: A sense amplifier (not shown) connected to the bit line BL senses a signal (bit line potential (3) or (4)), latches the value, and outputs it.
Timing R6: The read word line WLr is set to the low level, the read access transistor Tr is turned off, and the bit line BL is reset to the ground level again.
Timing R7: A pulse is again applied to the write word line WLw, and the write access transistor Tw is turned on. Thereby, the common node electrode NE is reset to the ground level again. As a result, Vcc is applied between the selection plate line PL1 and the common node electrode NE. As a result, "0" is written to all of the read memory cells.
Timing R8: The selected plate line PL1 returns to 0 V, and the write word line WLw is also set to low level.
[0013]
In such a series of operations, two reset operations are performed before and after data reading in order to stabilize the floating node NE of the capacitor.
This is an indispensable operation for removing unnecessary electric charges that become noise before reading, and for preventing unnecessary voltage from being continuously applied to the capacitor after reading.
However, in the amplification type memory as shown in FIG. 7, two pulses need to be applied to the write word line WLw for this operation, and the pulse timing and the operation timing of the bit line BL and the read word line WLr are appropriate. It had to be controlled in a proper order.
Therefore, there has been a problem that the reading operation is particularly complicated and the reading speed is reduced.
[0014]
[Means for Solving the Problems]
Therefore, an object of the present invention is to make a series of operations at the time of access more efficient and faster in a semiconductor memory device.
[0015]
Therefore, in the semiconductor memory device according to the present invention, in which the memory units are repeatedly arranged in each direction along the bit line and the word line to form a memory array, each of the memory units is mutually reciprocal. A plurality of memory cells each including a ferroelectric capacitor storing an independent value; a common node electrode for generating a read signal corresponding to a value stored in the plurality of memory cells; An access transistor to be turned off, one of a source / drain connected to a fixed voltage node, the other connected to the access transistor, a gate connected to the common node electrode, and a read signal generated at the common node electrode. A sense transistor that drives the bit line via the access transistor; So that and a reset means for short-circuiting the electrode and the ground node.
[0016]
In this case, when reading data from the memory cell, the common node electrode is electrically disconnected from the bit line.
When reading data from the memory cell, the reset means causes the common node electrode and the ground node to transition from a short-circuited state to a non-short-circuited state, and further to transition from a non-short-circuited state to a short-circuited state.
A reset control signal line wired in the same direction as the word line; wherein the reset means connects the common node electrode and the ground node in response to a reset control signal supplied from the reset control signal line. Control the connection state.
Further, the fixed voltage node and the ground node are arranged in parallel with the word line using a diffusion layer.
[0017]
That is, in the present invention, in the amplification type cross point memory, reset means for appropriately short-circuiting the common node electrode to the ground is provided, and when reading data from the memory unit, the common node electrode is kept disconnected from the bit line. The reset means is changed from ON (short-circuit state) to OFF (non-short-circuit state) and from OFF (non-short-circuit state) to ON (short-circuit state).
This not only prevents the potential fluctuation of the floating node when data is held in the cross-point type ferroelectric memory, but also significantly simplifies the read operation timing control, especially in the amplification type.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows a configuration of a memory unit MU of the amplification type cross-point memory according to the embodiment, and FIG. 2 shows a configuration in which the memory unit MU is repeatedly arranged in each direction of the bit line BL and the word line WL. 4 shows a memory array that has been used.
[0019]
In FIG. 1, the memory unit MU includes a plurality (here, four examples) of ferroelectric capacitors C1, C2, C3, and C4 connected to the common node electrode NE. Each of the capacitors C1, C2, C3, and C4 is a memory cell that stores different data.
One end of each of the capacitors C1, C2, C3, C4 is connected to the common node electrode NE. The other ends are connected to the plate lines PL1, PL2, PL3, and PL4, respectively, and are controlled by the plate lines PL1 to PL4.
[0020]
Further, a read access transistor Tr, a write access transistor Tw, and a sense transistor Ts, each of which is constituted by an FET, are provided. Further, a reset switch Trst using an FET is also provided.
[0021]
The sense transistor Ts is a depletion-type N-channel MOS-FET, and its gate is connected to the common node electrode NE. Further, one of the source / drain is connected to the fixed voltage source Vcc, and the other is connected to the bit line BL via the read access transistor Tr.
In the read access transistor Tr, one of a source and a drain is connected to the sense transistor Ts, and the other is connected to the bit line BL. The gate is connected to the read word line WLr, so that the read access transistor Tr is on / off controlled by the read word line WLr.
In the write access transistor Tr, one of a source and a drain is connected to the common node electrode NE, and the other is connected to the bit line BL. The gate is connected to the write word line WLw, so that the write access transistor Tw is on / off controlled by the write word line WLw.
[0022]
In the reset switch Trst, one of a source and a drain is connected to the common node electrode NE, and the other is connected to the ground GND (ground node). Further, the gate is connected to the reset control line RST, so that the reset switch Trst is turned on / off by the reset control line RST. When the reset switch Trst is turned on, the common node electrode NE is short-circuited to the ground.
[0023]
FIG. 2 shows a memory array in which a plurality of memory units MU having such a configuration are arranged, for example. That is, as shown in FIG. 2, a plurality of memory units MU11, MU12... Are repeatedly arranged in the bit line BL direction and the word line WL direction as the memory unit MU having the configuration of FIG.
[0024]
Each memory unit arranged in the word line WL direction shares a read word line WLr and a write word line WLw.
For example, in the unit row MR1 including the memory units MU11, MU12, and MU13, the read word line WLr1 is connected to the gate of the read access transistor Tr of each of these memory units (MU11, MU12,...), And the write word line WLw1 is connected to the gate of the write access transistor Tw of each memory unit (MU11, MU12,...).
Similarly, the read word line WLr2 and the write word line WLw2 become the word lines WL corresponding to the unit row MR2 including the memory units MU21, MU22, and MU23.
[0025]
Further, the reset control line RST is provided in parallel with the word line WL, and each memory unit arranged in the word line WL direction shares the reset control line RST.
For example, in the unit row MR1, the reset control line RST1 is connected to the gate of the reset switch Trst of each of these memory units (MU11, MU12,...).
Similarly, the reset control line RST2 becomes the reset control line RST corresponding to the unit row MR2 including the memory units MU21, MU22, and MU23.
[0026]
The bit lines BL (BL1, BL2,...) Are arranged perpendicular to the word lines WL.
Each memory unit arranged in the direction of the bit line BL shares the bit line BL. For example, in the memory units MU11 and MU21, the bit line BL1 is connected to the read access transistor Tr and the write access transistor Tw.
Each of the bit lines BL (BL1, BL2,...) Is applied with a voltage by the sense amplifier 2 (2-1, 2-2,...) At the time of writing, and a potential is detected at the time of reading.
[0027]
Also, as shown in FIG. 1, each of the capacitors C1 to C4 in each of the memory units MU is connected to the plate line PL.
For example, in the memory units MU11, MU12, MU13,... Of the unit row MR1, the capacitors C1 to C4 are connected to the plate lines PL11 to PL14, respectively.
In the memory units MU21, MU22, MU23,... Of the unit row MR2, the capacitors C1 to C4 are connected to plate lines PL21 to PL24, respectively.
[0028]
Each word line WL, plate line PL, and reset control line RST are applied with a voltage corresponding to an address to be accessed and writing / reading by drive circuits DRV1 and DRV2, respectively.
For example, when the unit row MR1 is selected and accessed, the word lines WLr1 and WLw1, the reset control line RST1, and the plate lines PL11 to PL14 corresponding to the unit row MR1 are operated by the drive circuit (DRV1). At this time, the common node electrode NE and the plate line PL (PL21 to PL24) of the unselected unit row, for example, the unit row MR2, are both grounded by the drive circuit DRV2, and hold data in a stable state.
[0029]
As shown in FIGS. 1 and 2, in the case of this example, each memory unit MU is provided with a reset switch Trst for short-circuiting the common node electrode NE and the ground.
FIG. 3 shows an example of operation timing at the time of data reading in such an amplification type cross point memory. One-time data reading from a certain memory cell is executed by the respective operations at timings R1 to R6 in FIG.
In this operation example, it is assumed that the unit row MR1 is selected, and a case of reading data from the capacitor C1 connected to the plate line PL11 will be described as an example.
[0030]
Timing R1: The reset control line RST1 is turned off, and the common node electrode NE, which has been grounded so far, is brought into a floating state. Also, the bit line BL, which has been equalized to 0 V, is removed from the equalization to be in a floating state. All the plate lines PL11 to PL14 are connected to the ground level.
Timing R2: A pulse is generated on the selected plate line PL11. As a result, different signals ((1) or (2)) are generated at the common node electrode NE depending on the polarization state of the ferroelectric capacitor C1.
Timing R3: The read word line WLr1 of the selected unit row MR1 is set to a high level. As a result, the read access transistor Tr of the memory unit MU (MU11, MU12,...) In the unit row MR1 is turned on, and the sense transistor Ts is driven according to the potential of the common node electrode NE connected to its gate. The potential of the bit line BL is raised by the ability ((3) or (4)).
Timing R4: The sense amplifier 2 (2-1, 2-2,...) Senses the signal ((3) or (4)), latches the value, and outputs it.
Timing R5: The read word line WLr is set to low level, the read access transistor Tr is turned off, and the bit line BL is equalized to the ground level again. At the same time, the reset control line RST1 also returns to the ON state, and the common node electrode NE is grounded to the ground level. As a result, Vcc is applied between the selection plate line P11 and the common node electrode NE. As a result, "0" is written to all of the read cells.
-Timing R6: The selection plate line PL11 is returned to 0V.
[0031]
As described above, during data reading, the reset control line RST changes from on to off, and then returns from off to on. Thus, the common node electrode NE can be appropriately grounded before and after reading regardless of the operation of the bit line BL. Therefore, the timing operation of grounding the common node electrode NE via the bit line BL becomes unnecessary, and the need to drive the write access transistor Tw during reading is eliminated. Therefore, the sequence is simplified and the reading speed is increased.
[0032]
Subsequently, a layout example of the amplification type cross point memory provided with the reset switch Trst and the reset control line RST will be described.
FIG. 4 shows a layout example when viewed in a plane direction, and FIG. 5 shows a cross-sectional structure along the line AA.
Since this layout example corresponds to the circuit configuration of FIG. 6, the circuit configuration of FIG. 6 will be described first.
[0033]
In the memory array of FIG. 6, memory units MU1, MU2, and MU3 are shown, but each of these memory units MU has the same configuration as that of FIG. 1 or FIG.
However, sixteen (C1 to C16) capacitors C as memory cells are provided in one memory unit MU.
Each of the memory units MU1, MU2, MU3,... Is connected to a bit line BL (BL1, BL2, BL3,...) Via a write access transistor Tw and a read access transistor Tr.
[0034]
In this case, a write word line WLw1, a read word line WLr1, and a reset control line RST1 are provided corresponding to the memory units MU1, MU3 (and MU5, MU7,..., Not shown), and the memory unit MU2 ( MU4, MU6 (not shown), a write word line WLw2, a read word line WLr2, and a reset control line RST2 are provided.
The plate lines PL1 to PL16 are provided in common to the respective memory units MU1, MU2, MU3,... And are connected to the capacitors C1 to C16, respectively.
[0035]
In the case of such a configuration, in each memory unit MU adjacent in the word line direction, the corresponding word line WL (WLw, WLr) and the reset control line RST are alternately different. By operating the WL and the reset control line RST simultaneously, a circuit equivalent to FIG. 2 is obtained.
That is, when MU1, MU2, MU3... Are one unit row MR1 in FIG. 2, the write word lines WLw1 and WLw2, the read word lines WLr1 and WLr2, and the reset control lines RST1 and RST2 in FIG. , May be driven in common.
[0036]
In the layout examples of FIGS. 4 and 5, first, as can be seen from FIG. 5, the common node electrode NE and each of the plate lines PL1 to PL16 are formed with the ferroelectric film FER interposed therebetween. Each memory cell (capacitor) is formed as a ferroelectric film FER at the intersection of PL1 to PL16.
[0037]
4, the read word line WLr (WLr1, WLr2), the write word line WLw (WLw1, WLw2), and the reset control line RST (RST1, RST2) are connected to the bit lines BL (BL1, BL2, BL3,...). 5), the read word line WLr (WLr1, WLr2), the write word line WLw (WLw1, WLw2), and the reset control line RST (RST1), as can be seen particularly from the sectional structure of FIG. , RST2) are also wired as the corresponding transistors, ie, the read access transistor Tr, the write access transistor Tw, and the gate electrode of the reset switch Trst. Therefore, a read access transistor Tr, a write access transistor Tw, and a reset switch Trst are formed at the intersection of each of the read word line WLr, the write word line WLw, and the reset control line RST with the active region (ACT). Have been.
[0038]
The common node electrode NE is connected to the gate SG of the sense transistor Ts via the contact hole CT1. Further, the common node electrode NE is connected to the shared diffusion layer region AC1 of the write access transistor Tw and the reset switch Trst via the contact hole CT2.
The power supply line VCC (fixed voltage node line) connected to the sense transistor Ts and the ground node line GND connected to the reset switch Trst are both scanned in the same direction as the word lines WL (WLr, WLw) using a diffusion layer. ing.
[0039]
By adopting such a layout, all the transistors and wirings are compactly housed under the cell capacitors without increasing the number of steps, and there is no area overhead.
[0040]
Further, in this example, the sense transistors Ts of the memory units MU adjacent to each other in the word line direction, for example, the memory units MU1 and MU2 are dispersedly arranged on the left and right sides of the drawing with a power supply line (VCC) forming one end of the diffusion layer. Accordingly, read word lines (WLr1 and WLr2), write word lines (WLw1 and WLw2), and reset lines (RST1 and RST2) are also distributed.
By performing such an arrangement, the area of the sense transistor Ts can be made large as shown in the figure, and its driving capability can be increased to increase the read speed.
Further, since the ground node wiring (GND) can be shared with the memory units MU of another unit row (not shown) adjacent in the bit line direction, the area efficiency is improved.
[0041]
As described in the description of the circuit in FIG. 6 corresponding to this layout, each pair (WLr1 and WLr1) of the read word line, the write word line, and the reset line provided on the left and right of the power supply line (VCC) is provided. WLr2, WLw1 and WLw2, and RST1 and RST2) operate simultaneously on the left and right sides to form a circuit equivalent to FIG.
However, it is also possible to operate these left and right signal line pairs individually to form a so-called “folded bit line configuration”.
The details of the folded bit line configuration in the cross-point type ferroelectric memory are described in, for example, Japanese Patent Application No. 11-158632 previously proposed by the present applicant. By adding Ts, the reset switch Trst, the power supply wiring VCC, and the ground wiring GND, a layout with almost no increase in area can be realized.
[0042]
While the embodiments of the present invention have been described above, various modifications of the present invention are possible within the scope of the gist.
[0043]
【The invention's effect】
As can be understood from the above description, according to the present invention, in a semiconductor memory device as an amplifying cross-point memory, reset means for appropriately shorting the common node electrode to ground is provided, and when reading data from the memory unit, The node electrode is kept disconnected from the bit line, and the reset means is changed from the short-circuited state to the non-short-circuited state and from the non-short-circuited state to the short-circuited state. As a result, it is possible to prevent the potential of the floating node from fluctuating when data is retained in the cross-point ferroelectric memory. Further, the fact that the common node electrode can be appropriately short-circuited to the ground by the reset means can significantly simplify the timing control of the data read operation from the memory cell, especially in an amplification type memory having a sense transistor. A series of operations at the time of access can be made more efficient and faster.
[0044]
Further, a reset control signal line for controlling the reset means to a short-circuit state and a non-short-circuit state is arranged in the same direction as the word line.
Further, the wiring of the fixed voltage node and the wiring of the ground node are wired in parallel with the word lines using a diffusion layer.
With such a layout, all of the transistors and wirings are compactly housed under the cell capacitors without increasing the number of processes, so that area overhead does not occur.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a configuration example of a memory unit according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of a configuration example of a memory array according to an embodiment;
FIG. 3 is an explanatory diagram of a read operation timing according to the embodiment;
FIG. 4 is an explanatory diagram of a layout example according to the embodiment;
FIG. 5 is an explanatory diagram of an AA cross section of a layout example according to the embodiment;
FIG. 6 is an explanatory diagram of a configuration of a memory array corresponding to a layout example of the embodiment;
FIG. 7 is an explanatory diagram of a conventional amplification type memory.
FIG. 8 is an explanatory diagram of a conventional read operation timing.
[Explanation of symbols]
2-1 2-2 Sense amplifier, MU, MU11, MU12 Memory unit WL word line WLw1, WLw2 Write word line WLr1, WLr2 Read word line BL , BL1, BL2 ... bit line, PL, PL11, PL12 ... plate line, Ts sense transistor, Tr read access transistor Tw write access transistor, Trst reset switch, RST, RST1, RST2 ... reset Control line, NE common node electrode

Claims (5)

In a semiconductor memory device in which a memory array is configured by a plurality of memory units being repeatedly arranged in each direction along a bit line and a word line,
Each of the above memory units
A plurality of memory cells each including a ferroelectric capacitor that stores a mutually independent value;
A common node electrode from which a read signal corresponding to a value stored in the plurality of memory cells is generated;
An access transistor that is turned on / off by the potential of the word line;
One of the source / drain is connected to the fixed voltage node, the other is connected to the access transistor, the gate is connected to the common node electrode, and the bit is passed through the access transistor based on the read signal generated at the common node electrode. A sense transistor for driving the line,
A semiconductor memory device comprising: reset means for short-circuiting the common node electrode and a ground node. 2. The semiconductor memory device according to claim 1, wherein when reading data from said memory cell, said common node electrode is electrically disconnected from said bit line. The reset means causes the common node electrode and the ground node to transition from a short-circuited state to a non-short-circuited state and to transition from a non-short-circuited state to a short-circuited state when reading data from the memory cell. The semiconductor memory device according to claim 1. A reset control signal line wired in the same direction as the word line;
2. The semiconductor memory device according to claim 1, wherein said reset means controls a connection state between said common node electrode and said ground node in accordance with a reset control signal supplied from said reset control signal line. . 2. The semiconductor memory device according to claim 1, wherein said fixed voltage node and said ground node are arranged in parallel with said word line using a diffusion layer.

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