JP2004229434A - Dc-dc converter, integrated circuit and flat display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce ripples by further improving conversion efficiency as compared with prior art, particularly in a charge-pump type DC-DC converter related to the DC-DC converter, an integrated circuit and a flat display device. <P>SOLUTION: A switch circuit 5 that charges a capacitor 4 and a switch circuit 6 that outputs a terminal voltage of the biased capacitor 4 are on/off-controlled, by shifting the timings of the on/off controls. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DC-DC converter, an integrated circuit, and a flat display device, and is particularly applicable to a charge pump type DC-DC converter, an integrated circuit using the DC-DC converter, and the like. The present invention uses a charge-pump type DC-DC converter by performing on / off control of a switch circuit that charges or discharges a capacitor and a switch circuit that outputs a terminal voltage of a biased capacitor at a shifted timing. Therefore, the conversion efficiency can be improved and the ripple can be reduced as compared with the related art.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in a liquid crystal display device which is a flat display device applied to a portable terminal device such as a PDA and a mobile phone, a driving circuit of the liquid crystal display panel is integrated on a glass substrate which is an insulating substrate constituting the liquid crystal display panel. Are provided.
[0003]
In such a liquid crystal display device, a power supply circuit is formed using a charge-pump type DC-DC converter as disclosed in, for example, JP-A-2002-191168. To generate the necessary power.
[0004]
FIG. 10 is a connection diagram showing a basic configuration of this type of DC-DC converter. As shown in FIG. 11, the DC-DC converter 1 inputs a clock CK whose signal level switches at a predetermined cycle to the buffer circuit 3 via the inverter circuit 2, and outputs the clock signal of the main capacitor 4 by the output of the buffer circuit 3. The potential at one end is changed. Further, the charge switch circuit 5 including a MOS (Metal Oxide Semiconductor) transistor is controlled on / off by the clock CK, and the potential of the other end of the main capacitor 4 is set by the power supply voltage VDD.
[0005]
Thus, the DC-DC converter 1 sets one end of the main capacitor 4 to the potential of the power supply VDD, and biases this potential by driving the buffer circuit 3 so that the power supply voltage VDD is boosted by the main capacitor 4. During a period in which the other end of the main capacitor 4 is not charged by the charge switch circuit 5, the out switch circuit 6 including a MOS transistor or the like is switched on to output the voltage V0 boosted by the main capacitor 4. Has been done. The output voltage V0 obtained through the out-switch circuit 6 is determined, and the supply of the clock CK is controlled to maintain the output voltage V0 at a predetermined voltage.
[0006]
[Patent Document 1]
JP-A-2002-191168 [0007]
[Problems to be solved by the invention]
By the way, in the DC-DC converter shown in FIG. 10, the charge switch circuit 5 and the out switch circuit 6 are on / off controlled complementarily by the common clock CK, so that the transistors constituting these switch circuits 5, 6 During the transition period, both are temporarily kept in the ON state, thereby causing a transient short-circuit state.
[0008]
As a result, a conversion loss occurs in this type of DC-DC converter, and there is a problem that power consumption increases when viewed as a whole device. Further, there is a problem that a ripple occurs in the output voltage V0 due to such a transient short-circuit state, and this ripple may adversely affect the operation of other circuits.
[0009]
The present invention has been made in consideration of the above points. In using a charge pump type DC-DC converter, a DC-DC converter capable of improving conversion efficiency and reducing ripples as compared with the related art. An object is to propose a DC converter, an integrated circuit using the DC-DC converter, and a flat display device.
[0010]
[Means for Solving the Problems]
In order to solve this problem, the invention according to claim 1 is applied to a DC-DC converter, and after setting the second switch circuit to an off state by setting the first to third control clocks, , The first switch circuit is turned on, the first switch circuit is turned off, the drive circuit starts the capacitor bias, and then the second switch circuit is turned off. Set the circuit to the ON state.
[0011]
According to the invention of claim 2, the DC-DC converter is applied to an integrated circuit that generates a power supply for internal operation from an input power supply supplied from outside by a built-in DC-DC converter, and After setting the second switch circuit to the OFF state by setting the control clock, the bias of the capacitor by the drive circuit is stopped, then the first switch circuit is switched to the ON state, and the first switch circuit is turned OFF. After switching to the state, the bias of the capacitor is started by the drive circuit, and then the second switch circuit is set to the ON state.
[0012]
In the invention according to claim 3, the present invention is applied to a flat display device in which a display unit having pixels arranged in a matrix and a drive circuit for driving the pixels of the display unit are integrally formed on a substrate. A drive circuit generates a power supply for internal operation from an input power supply externally supplied by a built-in DC-DC converter, and the DC-DC converter generates a second power supply by setting first to third control clocks. After the switch circuit is set to the off state, the bias of the capacitor by the drive circuit is stopped, then the first switch circuit is switched to the on state, and the first switch circuit is switched to the off state. , And then the second switch circuit is set to the ON state.
[0013]
According to the configuration of the first aspect, applied to a DC-DC converter, the first switch circuit for charging the capacitor and the second switch circuit for outputting the terminal voltage of the biased capacitor are shifted in timing. By performing the on / off control, a transient short-circuit state of the first and second switch circuits can be effectively avoided. Thus, when using the charge pump type DC-DC converter, Conversion efficiency can be improved and ripple can be reduced.
[0014]
According to this configuration, the present invention is applied to an integrated circuit that generates a power supply for internal operation from an input power supply externally supplied by a built-in DC-DC converter. The power consumption can be reduced by improving the conversion efficiency of the converter, and the performance can be improved by reducing the ripple.
[0015]
According to the configuration of the third aspect, the present invention is applied to a flat display device in which a display unit having pixels arranged in a matrix and a drive circuit for driving the pixels of the display unit are integrally formed on a substrate. As compared with the related art, the conversion efficiency of the DC-DC converter can be improved to reduce the power consumption, and the ripple can be reduced to improve the performance.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.
[0017]
(1) Configuration of First Embodiment FIG. 2 is a block diagram showing an image display unit according to the mobile terminal device according to the embodiment of the present invention. The mobile terminal device is, for example, a mobile phone, a PDA, or the like, and displays a desired image on the image display unit 11. Therefore, in the image display unit 11, the image data D1 is stored in an image memory built in the image processing circuit 12, and the image data D1 is sequentially output to the liquid crystal display device 13. Further, in synchronization with the output of the image data D1, a master clock MCK, a vertical synchronization signal VSYNC, and a horizontal synchronization signal HSYNC are output.
[0018]
In this portable terminal device, the image data D1, the master clock MCK, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC are input by the built-in liquid crystal display device 13, and an image is displayed by the liquid crystal display device 13. Here, the liquid crystal display device 13 is a flat display device in which a display unit 14 having pixels arranged in a matrix and a drive circuit 15 for driving the pixels of the display unit 14 are integrally formed on a glass substrate. It is. In this embodiment, the pixels of the display section 14 are composed of a liquid crystal cell, a polysilicon TFT for switching the liquid crystal cell, and an auxiliary capacitor.
[0019]
On the other hand, the drive circuit 15 inputs the master clock MCK, the vertical synchronizing signal VSYNC, and the horizontal synchronizing signal HSYNC to the timing generator (TG) 17 via the interface (IF) 16, and outputs timing signals of various operation references here. Generate. The DC-DC converter (DDC) 21 operates according to a predetermined timing signal generated by the timing generator 17, and converts the power supply VDD supplied to the liquid crystal display device 13 to the power supplies VDD2, VVSS2, HVSS2 or the like is generated.
[0020]
Similarly, the vertical drive circuit 18 is operated by a predetermined timing signal generated by the timing generator 17, and outputs a selection signal for selecting a line of the display unit 14. The reference voltage generation circuit 19 generates a reference voltage necessary for the processing of the horizontal drive circuit 20, and the horizontal drive circuit 20 sets the gradation of the corresponding pixel of the display unit 14 by the gradation data based on the image data D1.
[0021]
FIG. 3 is a connection diagram showing a configuration related to one power supply VDD2 of the DC-DC converter 21. Here, the converter unit 31 is a charge-pump type DC-DC converter, operates based on the clock CK, and outputs a predetermined power supply VDD2. The comparison circuit 32 outputs a comparison result between the potential VA of the power supply VDD2 output from the converter unit 31 and a predetermined reference potential VB to the latch 33, and the latch 33 latches the comparison result and sends it to the AND circuit 34. Output. The AND circuit 34 controls the operation of the converter unit 31 on and off by gating the clock CK based on the latch result of the latch 33. Accordingly, the DC-DC converter 21 is configured to maintain the output voltage VDD2 at a predetermined voltage by feedback control based on the comparison result of the comparison circuit 32.
[0022]
Here, as shown in FIG. 4, the comparison circuit 32 is configured so that the input line and the output line of the comparison circuit main body 47 can be cut off by the switch circuits 41, 42 and 43 operated by the control signal SCC. The supply of the power supplies VCC and VSS to the comparison circuit main body 47 is stopped by the switch circuits 44 and 45 operated by the signal SC.
[0023]
The comparison circuit 32 is set such that the signal levels of the power supply control signal SC and the control signal SCC are switched in conjunction with each other, whereby the switch circuits 41 to 43 are switched off to compare the potentials VA and VB. During the non-period, the switch circuits 44 and 45 are switched off so that no power is supplied, thereby further reducing power consumption.
[0024]
In the DC-DC converter 21 (FIG. 3), the comparison result by the comparison circuit 32 is latched by the latch 33 and input to the AND circuit 34. The AND circuit 34 gates the clock CK and outputs the output voltage of the converter unit 31. VDD2 is maintained at a predetermined voltage.
[0025]
That is, as shown in FIG. 5, in the DC-DC converter 21, the converter unit 31 operates by the clock CK to gradually increase the output voltage VDD2 (FIGS. 5A and 5B). In the DC-DC converter 21, the power supply control signal SC and the control signal SCC rise at regular time intervals, and a comparison result is obtained by the comparison circuit 32 (FIGS. 5C and 5D). The control signal SD of the converter unit 31 which is latched by the latch 33 and gates the AND circuit 34 rises (FIG. 5E). As a result, the operation of the DC-DC converter 21 is stopped, and the output voltage VDD2 gradually decreases. Further, the control signal SD falls due to the rise of the power supply control signal SC and the control signal SCC after a certain time interval, whereby the converter unit 31 starts operating and the output voltage VVSS2 is prevented from lowering. As a result, in this embodiment, the power consumption can be reduced as compared with the case where the voltage of the operating power supply is monitored by always operating the comparison circuit.
[0026]
FIG. 1 is a connection diagram showing a configuration of the converter unit 31 in comparison with FIG. In the configuration shown in FIG. 1, the same components as those in FIG. 10 are denoted by the corresponding reference numerals, and redundant description will be omitted. The converter unit 31 controls the charge switch circuit 5 and the out-switch circuit 6 using transistors with control clocks CCK and OCK different from the clock CK as an operation reference.
[0027]
Here, as shown in FIG. 6, the control clock OCK used to control the out-switch circuit 6 is set so as to rise before the clock CK and fall with a delay from the clock CK (see FIG. 6). 6 (A) and (C)). The control clock CCK used for controlling the charge switch circuit 5 is set so as to rise with a delay with respect to the clock CK and to fall before the clock CK (FIGS. 6A and 6B). ).
[0028]
Thus, in this embodiment, after the out-switch circuit 6 is set to the off state at time t1, the clock CK rises to lower the potential at both ends of the main capacitor 4, and then the charge switch circuit 5 is turned on at time t3. In this state, the end of the main capacitor 4 on the side of the charge switch circuit 5 is charged by the power supply VDD, and a potential difference between the power supply VSS and VDD is formed at both ends of the main capacitor 4.
[0029]
In addition, a potential difference is formed in this manner, the charge switch circuit 5 is turned off at time t4, and then the clock CK falls at time t5, thereby biasing the potential difference of the main capacitor 4 by the power supply VDD, and subsequently By setting the out-switch circuit 6 to the ON state at time t6, the high-potential-side terminal voltage of the main capacitor 4 thus biased is output, and the power supply voltage VDD2 obtained by boosting the power supply voltage VDD is thereby output. Is output.
[0030]
At this time, in the converter section 31, the signal levels of the control clocks OCK and CCK are switched before and after the clock CK, so that the out-switch circuit 6 is turned off, and then the charge switch circuit 5 is turned off. Can be set to the on state, and conversely, after setting the charge switch circuit 5 to the off state, the out switch circuit 6 can be set to the on state, whereby the transients of these two switch circuits 5, 6 can be set. The short circuit state can be prevented, the conversion loss can be reduced, the conversion efficiency can be increased, and the occurrence of ripple can be prevented.
[0031]
As shown in FIGS. 7 and 8, in the power supply control signal SC and the control signal SCC, a predetermined reference signal S1 is delayed by a delay circuit (D) 51 in a timing generator 17 to generate a delayed reference signal S2. The OR circuit 52 and the AND circuit 53 process the reference signal S1 and the delay reference signal S2 to generate the signal. Similarly, in the clocks CK, CCK, and OCK, similarly, in the timing generator 17, the master clock MCK is sequentially delayed by delay circuits (D) 55 and 56, and the output of the delay circuit 55 is output as the clock CK. The clocks OCK and CCK are generated by processing the output of 56 and the master clock MCK by the OR circuit 57 and the AND circuit 58.
[0032]
As a result, in this embodiment, the switch circuit 5 is switched to the ON state by the clock OCK, which is the first control clock, and sets the one end of the capacitor 4 to a predetermined potential by charging or discharging. The buffer circuit 3 changes the voltage at the other end of the capacitor 4 according to the clock CK as the second control clock, and sets the potential at the other end of the capacitor 4 set to a predetermined potential by the first switch circuit. Is configured as a drive circuit that biases The switch circuit 6 is turned on by a clock CCK that is a third control clock, and constitutes a second switch circuit that outputs the potential of the other end of the capacitor 4 biased by the drive circuit. I have.
[0033]
(2) Operation of the First Embodiment In the configuration described above, in this portable terminal device (FIG. 2), image data D1 relating to an image obtained by accessing a homepage, and image data D1 obtained through an imaging unit are obtained. Is stored in an image memory built in the image processing circuit 12, and the image data D1 stored in the image memory is input to the liquid crystal display device 13 together with a synchronization signal and the like. Further, the image data D1 is converted into a drive signal corresponding to the gradation of each pixel by the horizontal drive circuit 20 and output to the display unit 14, and by the selection of the line by the vertical drive circuit 18, the drive signal The image data D1 is supplied to the pixels, whereby an image based on the image data D1 is displayed on the display unit 14.
[0034]
In displaying an image based on the image data D1 in this manner, an operation power supply VDD2 and the like necessary for the operation of the drive circuit are generated from the input power supply VDD by the DC-DC converter 21 which is a power supply circuit. That is, in the DC-DC converter 21 (FIG. 3), the converter unit 31 operates by the clock CK to generate the operating power supply VDD2 from the input power supply VDD, and to change the voltage VA of the operating power supply VDD2 at regular time intervals. A predetermined reference voltage VB is compared with the comparison circuit 32 and held in the latch 33. In the DC-DC converter 21, when the voltage of the operating power supply VDD2 is high based on the comparison result, the clock CK is gated based on the latch result and the supply of the clock CK to the converter unit 31 is stopped and controlled. This prevents the voltage of the operation power supply VDD2 from rising. Conversely, when the voltage of the operation power supply VDD2 is low, the clock CK is supplied to the converter section 31 by the gate of the clock CK based on the latch result, and the converter section 31 operates to thereby operate. The voltage effect of VDD2 is prevented.
[0035]
Thus, in this embodiment, the power consumption can be reduced as compared with the case where the voltage of the operating power supply is constantly monitored by the comparison circuit.
[0036]
In the converter section 31 operated in this manner by the clock CK (FIG. 1), the charge switch circuit 5 is switched to the ON state, the other end of the capacitor 4 is charged by the power supply VDD, and one end of the capacitor 4 is connected to the power supply VDD. After that, the charge switch circuit 5 is turned off, and the voltage at the other end of the capacitor 4 is raised by the buffer circuit 3, so that the voltage at the other end charged by the power supply VDD is biased. Then, the biased voltage is output via the out-switch circuit 6, thereby generating a power supply VDD2 obtained by boosting the power supply VDD.
[0037]
In the converter section 31, the switch circuits 5 and 6 are set so as to switch the operation by shifting the timing by the control clocks CCK and OCK, respectively, so that a transient short-circuit state of the two switch circuits 5 and 6 is caused. This is effectively avoided, the conversion efficiency is improved accordingly, and the ripple is further reduced. As a result, when viewed as a whole of the liquid crystal display device 13, power consumption is reduced and performance is improved.
[0038]
Further, the timing of these two switch circuits 5 and 6 is set so that the timing is also different in the buffer circuit 3 that is used to bias the capacitor 4, thereby also preventing a transient abnormal current from flowing out. Can be prevented, and the conversion efficiency can be improved accordingly.
[0039]
(3) Effects of the First Embodiment According to the above configuration, the switch circuit for charging the capacitor and the switch circuit for outputting the terminal voltage of the biased capacitor are on-off controlled by shifting the timing. In using the charge pump type DC-DC converter, the conversion efficiency can be improved and the ripple can be reduced as compared with the related art.
[0040]
Thus, in this liquid crystal display device, power consumption can be reduced and performance can be improved.
[0041]
Further, since a transient short-circuit state can be prevented, the driving frequency can be increased, and accordingly, the DC-DC converter can be reduced in size and weight, and further, the liquid crystal display device can be reduced in size and weight. it can.
[0042]
(4) Second Embodiment FIG. 9 is a connection diagram showing a converter unit applied to a second embodiment of the present invention. As the converter section 61, instead of the inverter circuit 2 and the buffer circuit 3 described with reference to FIG. 1, a series circuit of four-stage CMOS inverter circuits 62 to 65 each including an NMOS transistor and a PMOS transistor is applied. The converter unit 61 inputs a master clock MCK to a built-in reference signal generation circuit 67, and generates clocks XCK, OCK, and CCK necessary for the operation of each unit using the master clock MCK.
[0043]
That is, the reference signal generation circuit 67 sequentially delays the master clock MCK by the delay circuits (D) 68 and 69, outputs the output of the delay circuit 68 as the clock XCK via the inverter circuit 72, and outputs the output of the delay circuit 69. Clocks OCK and CCK are generated by processing the master clock MCK with an OR circuit 70 and an AND circuit 71.
[0044]
Even if an inverter circuit is connected in an even number of stages as in this embodiment and the capacitor 4 is driven by a buffer circuit configuration, a clock necessary for the operation of each section is generated by a built-in reference signal generation circuit. Also, the same effect as in the first embodiment can be obtained.
[0045]
(5) Other Embodiments In the above-described embodiment, a case has been described in which one end of a capacitor is set to a predetermined voltage by charging, and the predetermined potential is boosted by a bias. However, the present invention is not limited to this. For example, when one end of a capacitor is set to a predetermined voltage by discharging and this predetermined voltage falls by a bias, such as when a negative power supply is generated, the present invention can be widely applied.
[0046]
Further, in the above-described embodiment, the case where the present invention is applied to the display device in which the display portion and the driving circuit formed of the liquid crystal are formed over the substrate has been described. The present invention can be widely applied to an integrated circuit that generates a power supply for internal operation.
[0047]
Further, in the above-described embodiment, a case where a pixel is driven by a liquid crystal cell has been described. However, the present invention is not limited to this, and can be widely applied to a flat display device including a pixel with various display means.
[0048]
【The invention's effect】
As described above, according to the present invention, a charge-pump type DC-DC converter is provided by performing on / off control of a switch circuit for charging a capacitor and a switch circuit for outputting a terminal voltage of a biased capacitor at staggered timing. In use, the conversion efficiency is improved and the ripple is reduced as compared with the related art.
[Brief description of the drawings]
FIG. 1 is a connection diagram showing a converter unit according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a portable terminal device using the converter unit of FIG. 1;
3 is a connection diagram showing a DC-DC converter in the portable terminal device of FIG.
FIG. 4 is a connection diagram showing a comparison circuit in the DC-DC converter of FIG. 3;
FIG. 5 is a time chart for explaining the operation of the DC-DC converter of FIG. 3;
FIG. 6 is a time chart for explaining the operation of the converter unit in FIG. 1;
FIG. 7 is a block diagram illustrating a configuration of a timing generator that generates various operation reference signals of the DC-DC converter of FIG. 3;
8 is a time chart for explaining the operation of the timing generator of FIG. 7;
FIG. 9 is a connection diagram illustrating a converter unit according to a second embodiment of the present invention.
FIG. 10 is a connection diagram showing a conventional DC-DC converter.
FIG. 11 is a time chart for explaining the DC-DC converter of FIG. 10;
[Explanation of symbols]
1, 21 DC-DC converter, 2 inverter circuit, 3 buffer, 4 capacitor, 5, 6 switch circuit, 11 image display unit, 13 image display device, 31 ... Converter part, 32 ... Comparison circuit, 33 ... Latch

Claims (3)

A capacitor,
A first switch circuit that is turned on by a first control clock and sets one end of the capacitor to a predetermined potential by charging or discharging;
A drive circuit that changes the voltage at the other end of the capacitor according to a second control clock, and biases the potential at the other end of the capacitor set to the predetermined potential by the first switch circuit;
A second switch circuit that is turned on by a third control clock and outputs a potential at the other end of the capacitor biased by the drive circuit;
By setting the first to third control clocks,
After setting the second switch circuit to the off state, stopping the bias of the capacitor by the drive circuit, and subsequently switching the first switch circuit to the on state;
A DC-DC converter, wherein after the first switch circuit is turned off, a bias of the capacitor is started by the drive circuit, and then the second switch circuit is set to an on state. An integrated circuit that generates power for internal operation from input power supplied from the outside by a built-in DC-DC converter,
The DC-DC converter includes:
A capacitor,
A first switch circuit that is turned on by a first control clock and sets one end of the capacitor to a predetermined potential by charging or discharging;
A drive circuit that changes the voltage at the other end of the capacitor according to a second control clock, and biases the potential at the other end of the capacitor set to the predetermined potential by the first switch circuit;
A second switch circuit that is turned on by a third control clock and outputs a potential at the other end of the capacitor biased by the drive circuit;
By setting the first to third control clocks,
After setting the second switch circuit to the off state, stopping the bias of the capacitor by the drive circuit, and subsequently switching the first switch circuit to the on state;
An integrated circuit, wherein after the first switch circuit is turned off, the bias of the capacitor is started by the drive circuit, and then the second switch circuit is set on. In a flat display device in which a display portion in which pixels are arranged in a matrix and a driving circuit for driving the pixels in the display portion are formed integrally on a substrate,
The driving circuit includes:
A power supply for internal operation is generated from an input power supply externally supplied by a built-in DC-DC converter,
The DC-DC converter includes:
A capacitor,
A first switch circuit that is turned on by a first control clock and sets one end of the capacitor to a predetermined potential by charging or discharging;
A drive circuit that changes the voltage at the other end of the capacitor according to a second control clock, and biases the potential at the other end of the capacitor set to the predetermined potential by the first switch circuit;
A second switch circuit that is turned on by a third control clock and outputs a potential at the other end of the capacitor biased by the drive circuit;
By setting the first to third control clocks,
After setting the second switch circuit to the off state, stopping the bias of the capacitor by the drive circuit, and subsequently switching the first switch circuit to the on state;
The flat display device according to claim 1, wherein after the first switch circuit is turned off, the bias of the capacitor is started by the drive circuit, and then the second switch circuit is set on.

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