JP2004228407A - Solid state imaging element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging element capable of preventing light leakage into an adjacent light receiving area even when pixels are further fined, and also to provide a method for manufacturing the solid state imaging element. <P>SOLUTION: In the solid state imaging element 30 constituted of arraying a plurality of light receiving areas 11 on the surface side of a substrate 1, a trench 9 whose inside is hollow is formed between the light receiving areas 11 as an element separation area 16. The trench 9 is formed from the rear face of the substrate 1 to the surface side and reached to an insulating film 20 formed on the substrate 1. A p-type impurity diffusion layer 10 is formed on the periphery of a sidewall of the element separation area 16. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device and a method of manufacturing the same, and more particularly, to a solid-state imaging device having a plurality of light receiving regions arranged on a surface side of a substrate and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the demand for increasing the number of pixels and reducing the size of a solid-state imaging device, miniaturization of pixels has been progressing. In such a solid-state imaging device that has been miniaturized in this manner, light (incident light) incident on each pixel arranged and formed on the surface side of the substrate via an on-chip lens or an in-layer lens is received by an adjacent pixel. The phenomenon of leaking into the region occurs. This phenomenon is caused by the fact that the incident light is diffracted at the edge of the light-shielding film that covers the periphery of each pixel, so that the diffracted light having a large incident angle with respect to the substrate surface (the angle formed with the normal to the substrate surface) It is due to the birth. As the size of the module of the solid-state imaging device advances and the exit pupil distance decreases, the angle of incidence of incident light on the substrate increases, and therefore, it is considered that the angle of incidence of such diffracted light also increases. .
[0003]
Therefore, a configuration has been proposed in which between each pixel provided on the front surface side of the semiconductor substrate, a trench is formed by processing the semiconductor substrate from the front side, and an element isolation layer is formed by filling the trench with an insulating film. (See Patent Document 1 below). In this case, silicon oxide is preferably used as the insulating film. This is because, in addition to the fact that the refractive index of silicon oxide is extremely small even in an insulating film (N = 1.46), since an element other than oxygen is not included extra, a substrate of an impurity element causing dark current is generated. Because there is no problem of diffusion into.
[0004]
[Patent Document 1]
JP-A-2002-57318
[0005]
In the solid-state imaging device provided with the element isolation layer having such a configuration, the above-described diffracted light is totally reflected at the interface between the insulating film embedded in the trench and the semiconductor substrate (that is, the side wall of the element isolation layer). Accordingly, it is possible to prevent the diffracted light from leaking into adjacent pixels. In addition, since adjacent pixels are insulated by an insulating film serving as an element isolation layer, leakage of charges to adjacent pixels can be prevented.
[0006]
[Problems to be solved by the invention]
However, the above-described solid-state imaging device has the following problems. That is, even when silicon oxide (n = 1.46) having a small refractive index is used as an insulating film forming an element isolation layer, a semiconductor substrate (n = 3.4) made of, for example, single crystal silicon can be used. , That is, the critical angle of total reflection at the side wall of the element isolation layer is only about 25.4 °. Therefore, if the incident angle of the above-mentioned diffracted light further increases in accordance with the demand for miniaturization of the pixel, the incident angle of the diffracted light with respect to the side wall of the element isolation layer (the angle formed with the normal line of the side wall of the element isolation layer) becomes larger. It is expected that the reflection critical angle will be less than 25.4 °. For this reason, in the solid-state imaging device having such a configuration, it is difficult to prevent light leakage when pixels are further miniaturized, and further prevent color mixing due to light leakage.
[0007]
In addition, the miniaturization of pixels requires finer trenches. However, it is a very difficult process to fill an insulating film in a trench, which is further miniaturized and has a narrower opening width. Become.
[0008]
Moreover, in order to obtain the solid-state imaging device, it is necessary to form an insulating film after forming the trench and to polish and remove an extra insulating film on the semiconductor substrate. There is also a problem that it will increase.
[0009]
Therefore, the present invention provides a solid-state imaging device capable of preventing light from leaking into an adjacent light receiving region even when the pixel size is further reduced, and a method for manufacturing the solid-state imaging device. The purpose is to do.
[0010]
[Means for Solving the Problems]
The solid-state imaging device of the present invention for achieving such an object is a solid-state imaging device in which a plurality of light-receiving regions are arranged and formed on the surface side of the substrate, and in particular, a trench whose inside is kept hollow, It is characterized in that it is provided between the light receiving regions as an element isolation region.
[0011]
In the solid-state imaging device having such a configuration, the critical angle of total reflection at the interface between the substrate and the hollow portion (that is, the side wall of the device isolation region) is minimized by using the trench whose inside is kept hollow as the device isolation region. Is set. Here, the critical angle for total reflection is the minimum value of the incident angle that can be totally reflected by the element isolation side wall among the incident angles with respect to the element isolation region side wall. For this reason, as compared with the configuration in which the inside of the trench is buried with the insulating film, the range of the incident angle totally reflected on the side wall of the element isolation region is expanded. Therefore, even when incident light having a larger incident angle with respect to the substrate surface is incident on the light receiving region, the light can be totally reflected on the side wall of the element isolation region, and is arranged with the element isolation region interposed therebetween. Light is prevented from leaking into the light receiving region.
[0012]
Further, in the method for manufacturing a solid-state imaging device according to the present invention, the step of arranging a plurality of light receiving regions on the surface side of the substrate, Forming an element isolation region in which the interior of the trench is kept hollow. Preferably, the trench is formed by forming an insulating film on the surface of the substrate and then performing pattern etching using the insulating film as a stopper.
[0013]
In the manufacturing method having such a configuration, by forming the trench from the rear surface side of the substrate, a trench whose front surface side of the substrate is closed is formed. For this reason, it is possible to prevent the influence of the trench formation from affecting the members provided above the substrate and the processes such as film formation and patterning performed on the surface of the substrate. In particular, in the case where a trench is formed by pattern etching using the insulating film as a stopper after forming the insulating film on the substrate, a trench that is closed on the surface side of the substrate with the insulating film and penetrates the surface side of the substrate is formed. In addition, the insulating film can be kept flat without loosening the insulating film in the hollow trench.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a solid-state imaging device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. Here, an embodiment in which the present invention is applied to an interline transfer type CCD solid-state imaging device will be described.
[0015]
<Solid-state image sensor>
1 to 4 show schematic configuration diagrams of a solid-state imaging device according to an embodiment to which the present invention is applied. 1 is a schematic plan view of the solid-state imaging device, FIG. 2 is an enlarged plan view of a portion A in FIG. 1, FIG. 3 is a sectional view taken along line xx 'in FIG. 2, and FIG. It is -y 'sectional drawing.
[0016]
The solid-state imaging device 30 shown in FIG. 1 is an inter-transfer-type CCD solid-state imaging device, and is configured as follows. That is, in the solid-state imaging device 30, photoelectric conversion / charge storage regions (hereinafter, referred to as light receiving regions) 11 for converting incident light into electrons and storing the electrons are arranged in a matrix on the front surface side of the substrate 1. I have. Each part where these light receiving areas 11 are arranged becomes each pixel. Further, a vertical transfer area 13 is arranged on the side of the light receiving area 11 in the horizontal direction (the left and right direction in the drawing) via the reading area 12. The vertical transfer region 13 extends in the vertical direction (vertical direction in the drawing) along the light receiving region 11, and a horizontal transfer electrode 14 is arranged so as to be connected to the final stage. The output unit 15 is arranged so as to be connected to the last stage. An element isolation region 16 is arranged between each light receiving region 11 and the vertical transfer region 13.
[0017]
As shown in the enlarged view of FIG. 2, on the substrate 1 in the vertical transfer region 13, transfer electrodes 21 (21a, 21b) having a two-layer structure are stacked at respective ends via an insulating film (not shown). In this state, they are arranged alternately along the vertical direction. The transfer electrodes 21a-21a and the transfer electrodes 21b-21b arranged in the horizontal direction are connected between the light receiving regions 11 arranged in the vertical direction. In this connection portion, the second-layer transfer electrode 21b is stacked on the first-layer transfer electrode 21a. Although not shown here, the transfer electrodes 21 arranged at the last stage in the vertical direction of the vertical transfer area 13 are connected to the transfer electrodes of the horizontal transfer area.
[0018]
Further, as shown in FIGS. 3 and 4, the internal structure of the substrate 1 in the solid-state imaging device 30 is such that a first P-type semiconductor that becomes an overflow barrier deep inside the N-type substrate 1 made of, for example, single crystal silicon A well region (Pwell) 2 is formed, and an N-type semiconductor well region (Nwell) 3 is formed above the surface of the substrate 1. An N-type impurity diffusion layer 4 is formed on the surface side of the N-type semiconductor well region 3, and a P-type impurity diffusion layer 5 is formed thereon. Thus, a light receiving region 11 having a signal charge generation region from the P-type impurity diffusion layer 5 to the P-type semiconductor well region (Pwell) 2 is formed.
[0019]
Further, a read region 12 having a MOS structure is provided adjacent to each light receiving region 11, and the above-described vertical transfer region 13 is provided beside the light receiving region 11 via the read region 12 (see FIG. 4). ). The readout region 12 includes the N-type semiconductor well region 3 on the front surface side of the substrate 1 and the readout electrode 21 provided thereon with an insulating film 20 interposed therebetween. Further, the vertical transfer region 13 is constituted by an N-type transfer channel region 7 provided on the surface layer of the substrate 1 and a transfer electrode 21 provided thereon with an insulating film 20 interposed therebetween. The read electrode 21 and the transfer electrode 21 may be formed integrally. Note that a second P-type semiconductor well region 8 is formed below the transfer channel region 7.
[0020]
Further, in the substrate 1, the above-described element isolation region 16 is provided at a position between the light receiving regions 11. The element isolation region 16 is arranged at a position surrounding the light receiving region 11 except for the side where the readout region 12 is arranged (see plan views in FIGS. 1 and 2). However, the arrangement state of the element isolation region 16 is not limited to the position shown in the plan views of FIGS. 1 and 2, and is at least vertically arranged at a position other than between the light receiving region 11 and the readout region 12. It is provided between the light receiving regions 11 provided. Further, a transfer electrode 21 is also provided above the element isolation region 16.
[0021]
In particular, the element isolation region 16 is characterized by comprising the trench 9 whose inside is kept hollow. The trench 9 has a width of about 0.1 μm to 0.2 μm.
[0022]
The trench 9 is arranged at a position at least as deep as the P-type semiconductor well region (Pwell) 2, and is provided, for example, from the back side to the front side of the substrate 1.
[0023]
FIG. 5 is an enlarged view of a portion A in FIG. As shown in FIG. 5, it is preferable that the element isolation region 16 is provided to penetrate the substrate 1 so as to reach the insulating film 20 covering the surface of the substrate 1. In this case, as will be described in more detail in a later manufacturing method, by forming the insulating film 20 using a material serving as a stopper in the etching of the substrate 1, the element in which the trench 9 is closed by the insulating film 20 having a flat surface is provided. An isolation region 16 is provided. Therefore, for example, when the substrate 1 is made of single-crystal silicon, an insulating film 20 in which a silicon oxide film 20a, a silicon nitride film 20b, and a silicon oxide film 20c are stacked in this order is provided on the substrate 1, and the silicon nitride film 20b is used as a stopper. The trenches 9 are provided by pattern-etching the substrate 1 from the back side.
[0024]
As described above, the trench 9 is preferably disposed at a position at least as deep as the P-type semiconductor well region (Pwell) 2, but does not have to penetrate the surface side of the substrate 1. Alternatively, it may be provided with a depth of about several μm from the surface side of the substrate 1.
[0025]
The element isolation region 16 having such a configuration comes into contact with the inner wall of the trench at a portion in contact with the inner wall of the trench, particularly at a depth position substantially equal to the P-type semiconductor well region (Pwell) 2 corresponding to the maximum light-receiving depth. If the portion is hollow, the interior of the trench need not be completely hollow. Therefore, if such a state is maintained, for example, the insulating film 20 may enter the inside of the trench 9 constituting the element isolation region 16 with the bottom surface side slackened.
[0026]
Then, as shown in FIGS. 3 and 4, a P-type impurity diffusion layer 10 is provided at a position surrounding the side surface of the element isolation region 16. The P-type impurity diffusion layer 10 is provided around the side wall of the element isolation region 16 from the first P-type semiconductor well region 2 serving as an overflow barrier to the surface of the substrate 1. However, in addition to this portion, the P-type impurity diffusion layer 10 may be provided around the sidewall of the element isolation region 16 on the back surface side of the substrate 1 with respect to the first P-type semiconductor well region 2.
[0027]
The interlayer insulating film 22 is provided on the substrate 1 having the inside as described above so as to cover the transfer electrodes 21a and 21b formed via the insulating film 20. On the interlayer insulating film 22, a light-shielding film 23 made of aluminum, tungsten, or the like is provided so as to open the light receiving region 11. Further, a reflow film 24 covering the entire surface and a high-refractive-index film 25 whose surface is flattened are formed in this order. The reflow film 24 has irregularities according to the steps of the underlying layers, and the reflow film 24 and the high-refractive-index film 25 form an inner-layer lens 26 on the light receiving region 11. Thereby, it becomes possible to condense the light to the light receiving region 11 and improve the sensitivity. Further, although not shown here, it is assumed that a filter layer and an on-chip lens are provided on the high refractive index film 25.
[0028]
In the solid-state imaging device 30 configured as described above, the element isolation region 16 including the trench 9 whose inside is kept hollow is provided between the light receiving regions 11. In such an element isolation region 16, since the refractive index n of the hollow portion is almost the minimum value of n = 1, the total reflection criticality at the interface between the substrate 1 and the hollow portion (that is, the side wall of the element isolation region 16). Corners are set to minimum. Here, the total reflection critical angle is defined as the angle of incidence between the normal line of the light receiving surface (here, the side wall of the element isolation region 16) and the incident light, and the light receiving surface (the side wall of the element isolation region 16). Is the minimum value of the incident angle that allows total reflection. When the substrate 11 is made of single-crystal silicon, its critical angle for total reflection is 17.1 °.
[0029]
For this reason, such an element isolation region 16 has a smaller element isolation layer (total reflection critical angle 25.4 °) than the element isolation layer in which the trench 9 is filled with an insulating film as described in the related art. The range of the incident angle totally reflected by the side wall of the region 16 is widened. Therefore, even when incident light having a larger incident angle with respect to the surface of the substrate 1 is incident on the light receiving region 11, the light can be totally reflected on the side wall of the element isolation region 16. As a result, the miniaturization of the solid-state imaging device 30 progresses to further reduce the exit pupil distance, thereby increasing the incident angle with respect to the surface of the substrate 1. Even when the angle of incidence of the diffracted light on the side wall of the light-receiving element 16 becomes small, it is possible to prevent light from leaking into the light-receiving area 11 disposed with the element isolation area 16 interposed therebetween, thereby suppressing the occurrence of color mixing. it can.
[0030]
In the solid-state imaging device 30, when the trench 9 forming the element isolation region 16 is provided so as to reach the insulating film 20 provided on the substrate 1, the trench 9 ( That is, the element isolation region 16) is arranged. Therefore, the distance between the element isolation region 16 and the transfer electrode 21 thereabove can be further reduced, and leakage of light from the space to the adjacent light receiving region 11 can be suppressed. Become.
[0031]
In addition, the element isolation region 16 can also prevent the charge from leaking into the adjacent display region 11.
[0032]
In the solid-state imaging device 30, a P-type impurity diffusion layer 10 is provided around the side wall of the element isolation region 16. Therefore, even if a dark current is generated on the surface of the substrate 11 at the interface with the trench 9, the dark current can be absorbed by the holes in the P-type impurity diffusion layer 10. The P-type impurity diffusion layer 10 does not need to be a specially provided layer as long as the P-type impurity concentration around the side wall of the element isolation region 16 is sufficient to absorb dark current.
[0033]
The solid-state imaging device 30 described above may be configured as shown in FIG. 6, for example. That is, the solid-state imaging device 30 includes a support frame 51 and a semiconductor thin film portion 52 supported in a state of being stretched in the support frame 51. The semiconductor thin film portion 52 has a configuration in which each region of the solid-state imaging device described with reference to FIGS. 2 to 4, that is, the light receiving region 11, the readout region 12, the vertical transfer region 13, and the element isolation region 16 are arranged. I do. In this case, the semiconductor thin film portion 52 becomes the substrate 1 described above.
[0034]
With such a configuration, the element isolation region 16 arranged along the vertical transfer region 13 keeps the inside of the trench 9 hollow, and the trench 9 is formed in the substrate 1 (that is, the semiconductor thin film 52). Even if it communicates with the back surface, the support frame 51 can prevent the substrate 1 from being bent at the trench 9 portion.
[0035]
In the solid-state imaging device 30 having such a configuration, only the portion where the element isolation region 16 is provided may be provided in the semiconductor thin film 52 portion. Therefore, the horizontal transfer area 14 and the output unit 15 described with reference to FIG. 1 may be provided on the front side of the support frame 51.
[0036]
In addition, by employing a configuration in which a support substrate is bonded to the back surface of the substrate 1, the substrate can be prevented from being bent at the trench 9 portion. Even in this case, the same effect as in the above-described embodiment can be obtained by keeping a predetermined portion (a portion having the same depth as the light receiving region 11) in the trench 9 hollow.
[0037]
<Method of manufacturing solid-state imaging device>
Next, a method for manufacturing the solid-state imaging device having the above-described configuration will be described with reference to FIGS.
[0038]
First, a P-type impurity is introduced into a predetermined depth of a substrate 1 made of single-crystal silicon by ion implantation to form a first P-type semiconductor well region 2 serving as an overflow barrier.
[0039]
Next, an N-type transfer channel region 7 and a second P-type semiconductor well region 8 therebelow are formed in the vertical transfer region 13 in the surface layer of the substrate 1 by ion implantation.
[0040]
Thereafter, an insulating film 20 is formed on the substrate 1 by laminating the silicon oxide film 20a, the silicon nitride film 20b, and the silicon oxide film 20c in this order (see FIG. 5).
[0041]
Next, a P-type impurity is diffused by ion implantation over a region where the element isolation region 16 is to be formed and a region outside the region including the region, thereby forming a P-type impurity diffusion layer 10. At this time, the diffusion depth of the P-type impurity may be set from the surface of the substrate 1 to the first P-type semiconductor well region 2 as a guide.
[0042]
After the above steps are performed in the same procedure as in the related art, pattern etching is performed from the back surface side of the substrate 1 so that the arrangement shape surrounding the light receiving region 11 from three directions excluding the side where the readout region 12 is arranged. A trench 9 is formed. Note that these three directions are the three directions except the surface on the side where the readout area 12 is arranged when the readout area 12 is rectangular when the substrate 1 is viewed in a plan view. . For this reason, when the reading area 12 is not rectangular when the substrate 1 is viewed in a plan view, the directions are all other directions except for the surface on which the reading area 12 is arranged. In forming the trench 9, etching is performed using the silicon nitride film 20b constituting the insulating film 20 as a stopper (see FIG. 5). In addition, the trench 9 having a width of about 0.1 μm to 0.2 μm is formed by performing etching under a condition with good anisotropy.
[0043]
Here, in the formation of the trench 9, the substrate 1 is sufficiently thinned in advance by etching or polishing the substrate 1 from the back side, so that the line width is sufficiently narrow (0.1 μm to 0 μm). (About 2 μm) is preferably formed in an anisotropic shape. When thinning the substrate 1, first, a resist pattern surrounding a region where the trench 9 is formed is provided on the back surface of the substrate 1, and the substrate 1 is etched from the back surface using the resist pattern as a mask. Thus, the region where the trench 9 is formed is thinned. As a result, the thinned substrate 1 portion (semiconductor thin film portion 52) is supported inside the support frame 51 as shown in FIG. 6, and then the semiconductor thin film portion 52 is subjected to pattern etching from the back surface side. Thereby, the trench 9 having a favorable anisotropic shape is formed.
[0044]
After the above, the transfer electrode 21a of the first layer is formed on the insulating film 20 and the transfer electrode 21b of the second layer is formed via the insulating film 20 in the same procedure as the conventional method. Thereafter, an N-type impurity diffusion layer 4 and a P-type impurity diffusion layer 5 thereon are formed in the openings of the transfer electrodes 21a and 21b in the surface layer of the substrate 1 to form the light receiving region 11. Next, a light-shielding film 23 having an opening for exposing the light-receiving region 11 is formed, and a reflow film 24, a high-refractive-index film 25, and, if necessary, further upper-layer members (filters, on-chip lenses, etc.) By forming, the solid-state imaging device 30 having the above-described configuration is completed.
[0045]
According to the above-described manufacturing method, the trench 9 that becomes the element isolation region 16 is formed from the back surface side of the substrate 1, thereby forming the trench 9 in which the front surface side of the substrate 1 is closed. At this time, in particular, by performing pattern etching using the insulating film 20 (specifically, the silicon nitride film 20b) formed on the substrate 1 as a stopper, the trench 9 penetrating to the surface side of the substrate 1 can be formed, and the insulating film can be formed. The insulating film 20 can be kept flat without loosening the insulating film 20 into the hollow trench. Therefore, it is possible to prevent the formation of the trench 9 from affecting the steps such as film formation and patterning performed on the insulating film 20 in the subsequent steps. As a result, each component formed on the insulating film 20 can be accurately formed on the flat insulating film 20.
[0046]
Moreover, since the inside of the trench 9 is kept hollow, the number of manufacturing steps can be reduced as compared with the conventional method of filling the trench 9 with an insulating film. When the trench 9 is filled with an insulating film, the accuracy of the filling is a problem, but such a problem does not occur.
[0047]
In the above procedure, immediately after the formation of the insulating film 20, the trench 9 to be the element isolation region 16 is formed. However, the formation of the trench 9 may be performed in any step after the formation of the insulating film 20, and more specifically, after the formation of the silicon nitride film 20 b constituting the insulating film 20. The same effect as described above can be obtained.
[0048]
When there is no problem of loosening of the insulating film 20 into the trench 9 or when there is no problem in forming each component on the loosened insulating film 20, the surface side of the substrate 1 may be used. After the trench 9 is formed by the above etching, the steps after the formation of the insulating film 20 may be performed.
[0049]
When the trench 9 is not penetrated on the front surface side of the substrate 1, that is, when the substrate 1 is pattern-etched from the rear surface side to form the trench 9, the substrate 1 is left at the bottom of the trench 9 on the front surface side. 9 may be formed in any step.
[0050]
Further, in the above-described embodiment, the embodiment in which the present invention is applied to the interline transfer type CCD solid-state imaging device has been described. However, the present invention is not limited to the application to such a solid-state imaging device, but includes a frame transfer type CCD solid-state imaging device, a frame interline transfer type CCD solid-state imaging device, and a full frame transfer type CCD solid-state imaging device. The present invention can be applied to a device, and further to a solid-state imaging device using a CMOS sensor, and similar effects can be obtained.
[0051]
In the above-described embodiment, the configuration in which the element isolation region 11 is provided only in the portion surrounding the light receiving region 11 from three directions excluding the side where the readout region 12 is arranged has been described. However, the element isolation region 11 may further extend below the second P-type semiconductor well region 8 in the vertical transfer region 13. With such a configuration, it is also possible to prevent light from leaking from below the second P-type semiconductor well region 8 to the light receiving region of an adjacent pixel.
[0052]
【The invention's effect】
As described above, according to the solid-state imaging device of the present invention, the critical angle of total reflection on the side wall of the element isolation region can be minimized by using the trench whose inside is kept hollow as the element isolation region. . Therefore, even when the miniaturization of the solid-state imaging device is advanced and the exit pupil distance is further reduced, even when incident light having a smaller incident angle is incident on the light receiving region of each pixel with respect to the side wall of the element isolation region. This allows the incident light to be totally reflected on the side wall of the element isolation region, preventing light from leaking into the light receiving region disposed across the element isolation region, and enabling imaging with reduced color mixing. become.
[0053]
According to the method for manufacturing a solid-state imaging device of the present invention, the trench can be formed in a state in which the front surface of the substrate is closed by forming the trench from the back surface of the substrate. For this reason, it is possible to prevent the influence of the trench formation from affecting the members provided above the substrate and the processes such as film formation and patterning performed on the surface of the substrate. In particular, by forming a trench by pattern etching using the insulating film formed on the surface side of the substrate as a stopper, the insulating film is not loosened in the hollow trench, that is, while keeping the surface of the insulating film flat, By forming a penetrated trench on the front surface side of the substrate, an element isolation region reaching a higher position can be formed. For this reason, it is possible to obtain a solid-state imaging device that can maintain the formation accuracy of each member on the substrate and can more reliably prevent light leakage by element separation.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a solid-state imaging device to which the present invention is applied.
FIG. 2 is an enlarged plan view of a portion A in FIG.
FIG. 3 is a sectional view taken along the line xx ′ in the enlarged plan view of FIG. 2;
FIG. 4 is a sectional view taken along the line yy ′ in the plan view of FIG.
FIG. 5 is an enlarged sectional view of a portion A in FIG. 3;
FIG. 6 is a schematic sectional view showing another example of the solid-state imaging device to which the present invention is applied.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 9 ... Trench, 10 ... P-type impurity diffusion layer, 11 ... Light receiving area, 16 ... Element isolation area, 20 ... Insulating film, 30 ... Solid-state image sensor

Claims (7)

A solid-state imaging device in which a plurality of light receiving regions are arranged and formed on the front surface side of the substrate,
A solid-state imaging device, wherein a trench whose interior is kept hollow is provided as an element isolation region between the light receiving regions. The solid-state imaging device according to claim 1,
The solid-state imaging device according to claim 1, wherein the trench is formed from a back surface of the substrate toward a front surface. The solid-state imaging device according to claim 2,
The solid-state imaging device according to claim 1, wherein the trench reaches an insulating film provided on the substrate. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a P-type impurity diffusion layer is provided around a side wall of the element isolation region. A step of arranging and forming a plurality of light receiving regions on the surface side of the substrate,
Forming a trench from the back side of the substrate between the light receiving regions of the substrate or between regions where the light receiving region is to be formed, and forming an element isolation region in which the inside of the trench is kept hollow. A method for manufacturing a solid-state imaging device, comprising: The method for manufacturing a solid-state imaging device according to claim 5,
The method for manufacturing a solid-state imaging device, wherein the trench is formed by forming an insulating film on a surface of the substrate and then performing pattern etching using the insulating film as a stopper. The method for manufacturing a solid-state imaging device according to claim 5,
Before or after the step of forming the element isolation region, a step of forming a P-type impurity diffusion region in the substrate around the element isolation region or at a position covering a region where the element isolation region is to be formed. Of manufacturing a solid-state imaging device.

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