JP2004228369A - Semiconductor device and method of blowing out fuse - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent conductive layers at both ends of a fuse from being melted by its heat generation when the fuse is heated and blown out by current supply heating. <P>SOLUTION: The fuse 11 is connected with a first semiconductor layer 2 and a second semiconductor layer 3 both having higher heat conductivity than that of a first insulating layer 32. Since the heat generated at a time of blown-out of the fuse is radiated to a substrate 1 side as well via the first semiconductor layer 2 and second semiconductor layer 3, the conductive layers 41 are hardly soluble. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a fuse and a method for blowing the fuse.
[0002]
[Prior art]
In some cases, a fuse is incorporated in a semiconductor device. Such a fuse is used, for example, in a trimming circuit for adjusting the resistance value by fusing the fuse when adjusting the characteristics of the manufacturing variation of the output voltage in the driver IC of the LCD. The trimming circuit includes a circuit using a fuse such as polysilicon and a circuit using a Zener zap diode.
In particular, a trimming circuit using a fuse such as polysilicon can form a fuse in the same process as forming a polysilicon layer such as a gate electrode or a resistor of a transistor in an IC, and can use an existing device. There are advantages such as the fact that the fuse can be blown by the current flow, and the characteristics can be adjusted with a simple configuration in which the fuse is inserted into the current path to be cut off.
[0003]
A case of adjusting the resistance value in a trimming circuit that blows a fuse by energizing heating will be described below with reference to FIGS. 7 and 8. FIG. 7 is a circuit diagram illustrating a configuration example of a trimming circuit. The series resistor R of the present trimming circuit includes a reference resistor R0 (resistance value: r0), a trimming resistor R1 (resistance value: r1), and a resistor R2 (resistance value: r2). A first fuse element F1 and a second fuse element F2 of polysilicon are connected in parallel to the trimming resistors R1 and R2, respectively. The trimming pad PD1 is connected to the midpoint between the reference resistor R0 and the trimming resistor R1, the trimming pad PD2 is connected to the midpoint between the trimming resistors R1 and R2, and the other of the trimming resistors R2. Is connected to a trimming pad PD3.
[0004]
FIG. 8 is a plan view and a cross-sectional view of the first fuse element F1. SiO on the semiconductor substrate 101 ₂ Is formed, and a fuse 111 made of conductive polysilicon is formed on the first insulating film 132. The fuse 111 has a wide electrode side, which is both ends. On the other hand, the fuse fusing portion F at the center is formed in a narrow taper shape in order to increase the current density and generate heat to cause fusing. The fuse 111 is formed so as to be gradually widened from the fuse fusing portion F to both ends in order to disperse the electric field concentration at both ends of the fuse.
[0005]
Then, for example, SiO ₂ Of the insulating film 133 is formed. The second insulating film 133 has a first contact hole 121a and a second contact hole 121b formed at both ends of the fuse 111. A first conductive layer 141a and a second conductive layer 141b of, for example, Al (aluminum) are provided in the first contact hole 121a and the second contact hole 121b of the second insulating film 133, respectively, and the first electrode and the second electrode are respectively provided. Is composed.
[0006]
In the present trimming circuit, for example, in order to make the characteristics close to an ideal value according to the characteristic measurement result, the fuse element is blown by energizing and heating, and the resistance of the fuse circuit is changed to adjust the resistance. Specifically, as shown in FIG. 7, the fuse is not blown when the value of the resistor R can be kept at r0, but when the value of the resistor R is made larger than r0, the first fuse element F1 Alternatively, the second fuse element F2 is blown. When the first fuse element F1 is blown, a predetermined current is supplied from the trimming pad PD1 and the trimming pad PD2. As a result, the current density increases at the fuse fusing portion F and heat is generated, and the fuse is blown at this portion to be in a cutoff state. As a result, the value of the resistor R changes to (r0 + r1). Similarly, when the second fuse element F2 is blown by a predetermined energization from the trimming pad PD2 and the trimming pad PD3, the value of the resistor R changes to (r0 + r2). Further, when both the first fuse element F1 and the second fuse element F2 are blown, the value of the resistor R changes to (r0 + r1 + r2). That is, by controlling the present trimming circuit, the value of the resistor R can be changed from r0 to any one of (r0 + r1), (r0 + r2), and (r0 + r1 + r2).
[0007]
A semiconductor device having a fuse such as the above-described trimming circuit is required to be able to fuse the fuse with high yield and high reliability. In addition, with recent miniaturization of semiconductor devices, miniaturization of fuses is also required. In order to respond to such a request, various methods have been conventionally proposed (for example, see Patent Document 1).
[0008]
[Patent Document 1]
JP-A-7-122646 (P.3-4, FIGS. 1 and 2)
[0009]
[Problems to be solved by the invention]
According to the conventionally proposed fuse, for example, by setting the fuse shape to a predetermined shape, the distance between the pair of electrodes can be reduced, and a high yield of the fuse fusing and a miniaturization of the device shape have been enabled. .
[0010]
However, in the related art, when the distance between the conductive layers at both ends of the fuse is reduced for miniaturization, heat generated at the time of fuse blowing may be conducted to the conductive layer, and the conductive layer may be melted. For example, the melted conductive layer may be short-circuited by contact with the conductive layer of an adjacent fuse, for example, and a fuse may fail to blow. In order to prevent the conductive layer from melting, it is necessary to increase the distance between the conductive layers through which the fuse is energized, and it has not been possible to achieve sufficient miniaturization. In addition, when the distance between the conductive layers to which the fuse is energized is increased, there is a case where the heat generated in the portion where the fuse can be blown is insufficient and the fuse is blown poorly. As described above, conventionally, it has been difficult to achieve both the yield or reliability and miniaturization. This problem occurs not only in the trimming circuit but also when the fuse is blown by energizing heating.
[0011]
Accordingly, an object of the present invention is to provide a semiconductor device capable of preventing the conductive layer at both ends of the fuse from being melted and preventing the fuse from being blown, and improving the yield or the reliability, and a method of blowing the fuse. . Another object of the present invention is to provide a semiconductor device which can reduce the size of the conductive layer at both ends of the fuse and can be miniaturized.
[0012]
[Means for Solving the Problems]
The present invention provides a substrate of a first conductivity type semiconductor, a first insulating layer formed on a surface region of the substrate, and a first insulating layer formed on one side of the first insulating layer and formed on a surface region of the substrate. A first semiconductor layer of one conductivity type semiconductor and a first semiconductor layer formed on the other side of the first insulating layer opposite to the one side and formed in a surface region of the substrate to form a PN junction between the first semiconductor layer and the substrate; A conductive layer having a second semiconductor layer of a two-conductivity type semiconductor and a portion formed by bridging the first insulating layer and the first semiconductor layer and the second semiconductor layer and having a high current density and capable of being blown by heating; A fuse, a first conductive layer connected to one end of the fuse and the first semiconductor layer, a second conductive layer connected to the other end of the fuse, and a second conductive layer formed on the fuse. An insulating layer, wherein the first semiconductor layer and the second The thermal conductivity of the conductor layer is a semiconductor device higher than the first insulating layer.
[0013]
The fuse of the semiconductor device according to the present invention is energized by a pair of the first conductive layer and the second conductive layer connected to the fuse, and the fuse which can be blown is heated and blown. The heat generated by the fuse is conducted to the first conductive layer and the second conductive layer and is then dissipated.
In the semiconductor device of the present invention, the first semiconductor layer and the second semiconductor layer are formed on the substrate 1, and the fuse is connected to the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the second semiconductor layer have higher thermal conductivity than the first insulating layer. Therefore, the heat generated by the fuse can be radiated from the first semiconductor layer and the second semiconductor layer to the substrate together with the heat radiated from the first conductive layer and the second conductive layer.
Therefore, the heat which is conducted to the first conductive layer and the second conductive layer and stored therein can be reduced. Further, even in the case of miniaturization such as reducing the distance between the first conductive layer and the second conductive layer, it is possible to prevent the first conductive layer and the second conductive layer from melting.
[0014]
The present invention is the above-described method for fusing a semiconductor device, wherein the first conductive layer and the second conductive layer are energized so that a reverse bias is applied to the junction between the substrate and the second semiconductor layer. This is a fuse blowing method in which the fuse is blown by heating.
[0015]
According to the method for blowing a fuse of a semiconductor device of the present invention, the first conductive layer and the second conductive layer have a reverse bias at the junction between the substrate of the first conductive type semiconductor and the second semiconductor layer of the second conductive type semiconductor. Therefore, the current to the fuse does not flow to the substrate. Since no current flows through the substrate, the yield or reliability can be improved.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment which is an example of the present invention will be described with reference to FIGS. Note that, in the drawings, portions denoted by the same reference numerals indicate the same items. As for the embodiment of the present invention, the case where the resistance is adjusted as shown in FIG.
[0017]
<First embodiment>
FIG. 1 shows the structure of the fuse of the semiconductor device according to the first embodiment of the present invention. FIG. 1 is a plan view and a sectional view of the first fuse element F1 of FIG.
[0018]
The first embodiment includes a substrate 1, a first insulating layer 32, a first semiconductor layer 2, a second semiconductor layer 3, a fuse 11, a first conductive layer 41a, a second conductive layer 41b, and a second insulating layer 33. .
[0019]
In the first embodiment, the substrate 1 uses an n-type Si semiconductor. The first insulating layer 32 is made of SiO ₂ And is located in the surface region of the substrate 1. On both sides of the first insulating layer 32, a first fuse contact region A and a second fuse contact region B are formed. The first semiconductor layer 2 is an n-type semiconductor, and is located on one side of the first insulating layer 32 in the surface region of the substrate 1 in the first fuse contact region A. The second semiconductor layer 2 is a p-type semiconductor that forms a PN junction with the n-type semiconductor substrate 1. The second semiconductor layer 2 is formed of the second fuse contact region B on the other side facing the first semiconductor layer 2. Located in the surface area.
[0020]
The fuse 11 is made of conductive polysilicon and is formed so as to bridge the first insulating layer 32, the first semiconductor layer 2, and the second semiconductor layer 3, and has a portion having a high current density and capable of being blown by heating. The polysilicon used for the fuse 11 has good processing accuracy, and ₂ This is preferable because the adhesion to the first insulating layer 32 is good. The polysilicon fuse 11 is formed as a p-type semiconductor. At the time of ion implantation, the first semiconductor layer 2 and the second semiconductor layer 3 are provided with the p-type semiconductor bonding layer 4, and the first semiconductor layer 2 and the second semiconductor layer 2 are formed. Connect to semiconductor layer 3.
[0021]
The first conductive layer 41a is connected to one end of the fuse 11 and the first semiconductor layer 2 to form a first electrode. The second conductive layer 41b is connected to one end of the fuse 11 to which the first conductive layer 41a is connected and the other end to form a second electrode. Second insulating layer 33 is located on fuse 11. The first semiconductor layer 2 and the second semiconductor layer 3 are formed on a Si substrate 1 having a thermal conductivity of 50.0 W / m · K. The first insulating layer 32 is made of SiO 2 having a thermal conductivity of 1.63 W / m · K. ₂ Is used. Thus, the first semiconductor layer 2 and the second semiconductor layer 3 have higher thermal conductivity than the first insulating layer 32.
[0022]
Further, in the semiconductor device of the present embodiment, SiO 2 having a lower thermal conductivity than the Si substrate 1 is provided on the substrate 1 side of the fusing portion F of the fuse 11. ₂ Is provided.
[0023]
As described above, the semiconductor device according to the present embodiment includes the first semiconductor layer 2 and the second semiconductor layer 3 on the substrate 1 unlike the related art. In the conventional fuse, since the fuse body is formed on the insulating layer of the substrate, heat generated when the fuse is blown hardly conducts to the substrate side, and heat is mainly radiated from the conductive layer connected to the fuse. On the other hand, the fuse 11 according to the present embodiment is connected to the first semiconductor layer 2 and the second semiconductor layer 3 having higher thermal conductivity than the first insulating layer 32 on the substrate 1. Therefore, the heat generated when the fuse is blown can be radiated from the first semiconductor layer 2 and the second semiconductor layer 3 to the substrate 1 together with the heat radiated from the first conductive layer 41a and the second conductive layer 41b. That is, the amount of heat stored in the first conductive layer 41a and the second conductive layer 41b is smaller than in the related art.
[0024]
Therefore, the first conductive layer 41a and the second conductive layer 41b are prevented from melting, the yield or reliability can be improved, and the distance between the first conductive layer 41a and the second conductive layer 41b can be reduced. As a result, miniaturization becomes possible. As described above, the semiconductor device of the present embodiment can achieve both improvement in yield or reliability and miniaturization, which have been contradictory in the related art.
[0025]
Further, the semiconductor device of the present embodiment has a structure in which SiO 2 is provided on the substrate 1 side of the fusing portion F of the fuse 11. ₂ Is provided. SiO for forming the first heat dissipation prevention layer 31 ₂ Has a thermal conductivity of 1.63 W / m · K, the thermal conductivity of Si forming the substrate 1 is 50.0 W / m · K, and the first heat radiation preventing layer 31 has a thermal conductivity that is lower than that of the substrate 1. Low. For this reason, the first heat dissipation prevention layer 31 prevents the heat generated at the fusing portion F of the fuse 11 from being conducted to the substrate 1 side. Accordingly, heat radiation required for fusing the fuse 11 can be prevented, and a fusing defect of the fuse 11 can be prevented.
As described above, the first heat dissipation prevention layer 32 is preferably thicker in order to prevent heat dissipation required for fusing the fuse 11. For example, SiO ₂ In this case, the thickness is preferably 600 to 800 nm. If the thickness is less than 600 nm, heat radiation may not be sufficiently prevented. If the thickness exceeds 800 nm, high integration may be impaired due to the influence of steps. Further, in the present embodiment, the heat radiation preventing layer has insulating SiO 2. ₂ However, as long as the thermal conductivity is lower than that of the substrate 1, the presence or absence of the insulating property does not matter. Note that, as in the present embodiment, both the first heat dissipation preventing layer 32 and the first insulating layer 32 are made of SiO having low thermal conductivity and excellent insulating properties. ₂ In the case where is used, it may be integrally provided with a thickness exhibiting a necessary insulating property and a heat radiation preventing function.
[0026]
The semiconductor device of the present embodiment includes the first semiconductor layer 2 and the second semiconductor layer 3 on the substrate at both ends of the fuse 11, and includes the first heat dissipation prevention layer 31 at the fusing portion F of the fuse 11. With such a configuration, it is possible to prevent both the melting of each conductive layer and the fusing failure of the fuse 11, and to further improve the yield or the reliability.
[0027]
The method for manufacturing the semiconductor device according to the first embodiment described above will be described with reference to FIG. 1 and FIGS.
First, as shown in FIG. 3A, an n-type Si semiconductor ₂ Is formed. SiO ₂ The first heat dissipation prevention layer 31 can be formed by the following method. SiO2 of about 50 nm is formed on the substrate 1 by steam oxidation at about 900 to 1000C. ₂ A film (not shown) is formed. Thereafter, the Si (about 100 nm) is formed by a CVD (Chemical Vapor Deposition) method. ₃ N ₄ A film (not shown) is formed. Then, a resist mask (not shown) is formed in the first fuse contact region A and the second fuse contact region B. After that, the first fuse contact region A and the second fuse contact region B are made of Si by reactive ion etching (RIE). ₃ N ₄ Patterning is performed by etching so as to leave the film. Then, the patterned Si ₃ N ₄ The resist mask on the film is removed. Then, the patterned Si ₃ N ₄ Using the film as a mask, steam oxidation at about 900 to 1000 ° C. ₃ N ₄ SiO with a thickness of 600 to 800 nm in portions other than the film ₂ Is formed. After that, hot phosphoric acid ₃ N ₄ The film is removed and Si ₃ N ₄ SiO under the film ₂ The film is removed using a hydrogen fluoride (HF) chemical. By the above method, the substrate 1 is made of SiO. ₂ Is formed.
[0028]
Next, as shown in FIG. 3B, a first semiconductor layer 2 is formed on the surface region of the substrate 1 in the first fuse contact region A, and a second semiconductor layer 2 is formed on the surface region of the substrate 1 in the second fuse contact region B. The semiconductor layer 3 is formed. The first semiconductor layer 2 is formed on the substrate 1 with an ion concentration of 10 using an ion plantation technique using a resist mask having an opening in the first fuse contact region A. ^Thirteen -10 ¹⁴ cm ^-2 About P (phosphorus) is implanted and formed. The second semiconductor layer 3 is formed on the substrate 1 by an ion plantation technique using an ion concentration of 10% using a resist mask having an opening in the second fuse contact region B. ^Thirteen -10 ¹⁴ cm ^-2 About B (boron) is implanted and formed.
[0029]
Next, as shown in FIG. 4A, a SiO film having a thickness of about 300 nm is formed on the first heat radiation preventing layer 31, the first heat radiation layer 2, and the second heat radiation layer 3 by the CVD method. ₂ Of the first insulating layer 32 is formed. Thereafter, a heat treatment at about 1050 to 1100 ° C. is performed to form a first semiconductor layer 2 of an n-type semiconductor in the first fuse contact region A and a second semiconductor layer 3 of a p-type semiconductor in the second fuse contact region B.
[0030]
Then, as shown in FIG. 4B, a first contact hole 21b is formed in the first fuse contact region A, and a second contact hole 21c is formed in the second fuse contact region B. The first contact hole 21b and the second contact hole 21c are formed by forming a resist mask having an opening at a predetermined position and then etching the first insulating layer 32 at the opening by RIE. The first contact hole 21b in the first fuse contact region A is formed by etching to a depth where the first semiconductor layer 2 is exposed. Similarly, the second contact hole 21c in the second fuse contact region B is formed by etching to a depth where the second semiconductor layer 3 is exposed. Here, in the first fuse contact region A, the first conductive layer 41a is connected to the first semiconductor layer in a step described later. Therefore, the first contact hole 21b is formed so as to leave a region where the first conductive layer 41a can be connected to the first semiconductor layer.
[0031]
Next, as shown in FIG. 5A, a polysilicon fuse layer 10 is formed so as to bridge the first insulating layer 32, the first semiconductor layer 2, and the second semiconductor layer 3. The fuse layer 10 is formed with a thickness of about 100 to 200 nm by a CVD method. The polysilicon fuse layer 10 is formed so as to cover the exposed first semiconductor layer 2 of the first fuse contact region A and the exposed second semiconductor layer 3 of the second fuse contact region B. Then, the ion concentration of 1 × 10 ^Fifteen ~ 5 × 10 ^Fifteen cm ^-2 About B (boron) is implanted.
[0032]
Then, after a resist mask having a predetermined shape is formed on the fuse layer 10, the fuse layer 10 is etched and processed into a predetermined shape by the RIE method to form a polysilicon fuse 11. As shown in the plan view of FIG. 1A, both ends of the fuse 11 are formed to have a wide width, and the fuse fusing portion F at the center is formed to have a narrow taper shape so as to increase the current density. For example, the width of both ends of the fuse 11 is formed in a range of 1.4 μm to 1.8 μm, and the width of the fuse fusing portion F at the center is formed in a range of 0.4 μm to 0.8 μm.
[0033]
Next, as shown in FIG. ₂ Is formed. The second insulating layer 33 is formed with a thickness of about 300 nm by a CVD method. After forming the second insulating layer 33, a heat treatment at about 900 to 950 ° C. is performed. By this heat treatment, conductivity is imparted to the polysilicon fuse 11, and the fuse 11 becomes a p-type semiconductor. At the same time, B (boron) implanted in the fuse 11 diffuses through the first contact hole 21b and the second contact hole 21c, and the p-type bonding layer 4 is formed in the first semiconductor layer 2 and the second semiconductor layer 3. To form Thus, the fuse 11 is connected to the first semiconductor layer 2 and the second semiconductor layer 3.
[0034]
Next, as shown in FIG. 6, a third contact hole 22a and a fourth contact hole 22b are formed in the first fuse contact region A, and a fifth contact hole 22c is formed in the second fuse contact region B. The third contact hole 22a, the fourth contact hole 22b, and the fifth contact hole 22c are formed by forming a resist mask having an opening at a predetermined position and then etching the second insulating layer 33 at the opening by RIE. You.
[0035]
Next, as shown in FIG. 1B, a first conductive layer 41a is formed in the first fuse contact region A, and a second conductive layer 41b is formed in the second fuse contact region B. The first conductive layer 41a and the second conductive layer 41b are formed by the following method. First, Al (aluminum) is buried in the third contact hole 22a and the fourth contact hole 22b of the first fuse contact region A and the fifth contact hole 22c of the second fuse contact region B by sputtering, and an Al layer (not shown) ) Is formed. After that, the Al layer is etched by the RIE method to form the first conductive layer 41a and the second conductive layer 41b.
[0036]
The operation of the semiconductor device according to the first embodiment will be described.
The fuse 11 of the semiconductor device of the present embodiment is energized by a pair of the first conductive layer 41a and the second conductive layer 41b connected to the fuse 11. Then, the narrow tapered fusing portion F of the fuse 11 generates heat at a high temperature and is blown. The blown fuse 11 is prevented from being scattered by the first insulating layer 32 and the second insulating layer 33. Then, the heat generated by the fuse 11 is transmitted to the first conductive layer 41a and the second conductive layer 41b and is then radiated.
[0037]
As described above, in the present embodiment, heat generated when the fuse 11 is blown is radiated to the substrate 1 from the first semiconductor layer 2 and the second semiconductor layer 3 formed on the substrate 1. Since the first semiconductor layer 2 and the second semiconductor layer 3 have higher thermal conductivity than the first insulating layer 32, heat can be radiated to the substrate 1.
[0038]
Therefore, the heat conducted to the first conductive layer 41a and the second conductive layer 41b and reduced can be reduced, and the melting of the first conductive layer 41a and the second conductive layer 41b can be prevented. For this reason, in the present embodiment, the yield or the reliability can be improved, and miniaturization such as reducing the distance between the first conductive layer 41a and the second conductive layer 41b can be performed. As described above, in the present embodiment, it is possible to achieve both improvement in yield or reliability and miniaturization, which have been contradictory in the related art.
[0039]
Further, as described above, the present embodiment uses SiO 2 ₂ The first heat dissipation prevention layer 31 prevents the heat generated at the fusing portion F of the fuse 11 from being conducted to the substrate 1 side. Since the first heat dissipation prevention layer 31 has a lower thermal conductivity than the substrate 1, the heat dissipation required for fusing can be prevented, and the fusing failure of the fuse 11 can be prevented.
[0040]
In addition, as a method for blowing the fuse of the semiconductor device of the present embodiment, it is desirable to apply a current that causes a reverse bias to the junction between the substrate 1 and the second semiconductor layer 3 through the first conductive layer 41a and the second conductive layer 41b.
For example, in the present embodiment, since the first semiconductor layer 2 is an n-type semiconductor and the second semiconductor layer 3 is a p-type semiconductor, the first conductive layer 41a is set to a positive potential, and the second conductive layer 41b is set to a negative potential. I do. In this case, a reverse bias is applied to the junction between the substrate 1 and the second semiconductor layer 3, and the current applied to the fuse 11 can be prevented from flowing into the semiconductor base. Since the applied current does not flow into the semiconductor substrate, damage to the semiconductor device or the like can be prevented, and the yield or reliability can be improved.
[0041]
In this embodiment, the substrate 1, the first semiconductor layer 2, the second semiconductor layer 3, the fuse 11, the first heat dissipation preventing layer 31, the first insulating layer 32, the second insulating layer 33, the first conductive layer 41a, and the second conductive layer The layer 41b corresponds to the substrate, the first semiconductor layer, the second semiconductor layer, the fuse, the heat dissipation preventing layer, the first insulating layer, the second insulating layer, the first conductive layer, and the second conductive layer of the present invention, respectively.
[0042]
<Embodiment 2>
FIG. 2 is a plan view and a sectional view of a connection portion of the fuse F1 in FIG. 6, which is a semiconductor device according to a second embodiment of the present invention.
[0043]
The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that Si ₃ N ₄ And a heat radiation layer 42 of Al (aluminum). Si ₃ N ₄ The second heat radiation preventing layer 34 is located on the side of the fuse fusing portion F opposite to the substrate 1. The heat radiation layer 42 of Al (aluminum) is formed on each of the first conductive layer 41a and the second conductive layer 41b.
[0044]
The heat radiation layer 42 according to the present embodiment has a thermal conductivity. Therefore, the heat dissipation layer 42 can generate heat after the heat generated at the time of fusing of the fuse 11 conducted to the first conductive layer 41a or the second conductive layer 41b is conducted. The heat radiation layer 42 can radiate heat from the surface when the fuse 11 is blown. Therefore, it is possible to reduce the heat held by the first conductive layer 41a and the second conductive layer 41b, and to prevent the melting of the first conductive layer 41a and the second conductive layer 41b even in the case of miniaturization. Become.
[0045]
As described above, since the heat radiation layer 42 has thermal conductivity, the heat generated when the fuse 11 is blown is heated. Therefore, the heat dissipation layer 42 is preferably formed so as to cover the first conductive layer 41a and the second conductive layer 41b, and the heat dissipation layer 42 is preferably formed thick. Further, in the present embodiment, Al having excellent conductivity is used for the heat radiation layer 42, but it does not matter whether or not the heat dissipation layer 42 has conductivity.
[0046]
In the present embodiment, the heat radiation layer 42 is formed on both the first conductive layer 41a and the second conductive layer 41b, but may be formed on one of them. For example, the heat dissipating layer 42 may be formed only at the portion of the conductive layer of another adjacent fuse, and the heat of the conductive layer on which the heat dissipating layer 42 is formed may be reduced to prevent melting. By forming the heat dissipation layer 42 only on some of the conductive layers, manufacturing efficiency can be improved.
[0047]
Further, in the semiconductor device of the present embodiment, the SiO 2 ₂ Of the first heat dissipation prevention layer 31 and Si ₃ N ₄ And the second heat radiation preventing layer 34. Si forming the second heat dissipation prevention layer (31) ₃ N ₄ Has a thermal conductivity of 10.0 W / m · K, the thermal conductivity of Si forming the substrate 1 is 50.0 W / m · K, and the second heat radiation preventing layer 34 has a thermal conductivity that is lower than that of the substrate 1. Low. For this reason, the second heat radiation preventing layer 34 prevents the heat generated at the fusing portion F of the fuse 11 from being conducted to the outside on the opposite side of the substrate 1. Therefore, heat generation required for fusing the fuse 11 can be prevented, and a defective fuse can be prevented. Since the fuse 11 is provided between both the first heat dissipation prevention layer 31 and the second heat dissipation prevention layer 34, the fusing failure of the fuse 11 can be further prevented.
[0048]
A method for manufacturing a fuse of a semiconductor device according to the second embodiment will be described with reference to FIGS.
As shown in FIG. 1, after forming a first conductive layer 41a and a second conductive layer 41b in the same manner as in the first embodiment, as shown in FIG. ₃ N ₄ Of the second heat dissipation prevention layer 34 and the heat dissipation layer 42 of Al (aluminum).
[0049]
First, Si ₃ N ₄ The second heat radiation preventing layer 34 is formed on the entire surface with a thickness of about 700 nm by the CVD method. And Si ₃ N ₄ The second heat dissipation prevention layer 34 is opened by photolithography or RIE to form a sixth contact hole 23a and a seventh contact hole 23b in the first fuse contact region A and an eighth contact hole 23b in the second fuse contact region B. A contact hole 23c is formed. The sixth contact hole 23a and the seventh contact hole 23b in the first fuse contact region A have a depth at which the first conductive layer 41a is exposed. Further, the eighth contact hole 23c in the second fuse contact region B has a depth at which the second conductive layer 41b is exposed. Then, Al having thermal conductivity is sputtered into the sixth contact hole 23a, the seventh contact hole 23b of the first fuse contact region A and the seventh contact hole 23b of the second fuse contact region B, and an Al layer (shown in FIG. None). Then, the Al layer is formed so as to be connected to each of the first conductive layer 41a and the second conductive layer 41b. Then, the Al layer is patterned by an etching technique such as a photolithography technique or an RIE method to form an Al heat dissipation layer 42 on the first conductive layer 41a and the second conductive layer 41b.
[0050]
The operation of the semiconductor device according to the second embodiment will be described. The semiconductor device of the present embodiment is different from the semiconductor device of the first embodiment in that Si ₃ N ₄ The second embodiment is the same except that the second heat dissipation prevention layer 34 and the heat dissipation layer 42 of Al are provided.
[0051]
As described in the first embodiment, the heat generated when the fuse 11 is blown is conducted and conducted to the first conductive layer 41a or the second conductive layer 41b located at the end of the fuse 11, and further to the first semiconductor layer. 2 and the second semiconductor layer 3 conduct heat to the substrate 1 for heat dissipation.
[0052]
In the second embodiment, heat generated when the fuse 11 is blown is conducted to the first conductive layer 41a or the second conductive layer 41b, and further conducted to the heat radiation layer 43. Therefore, heat conducted to the first conductive layer 41a or the second conductive layer 41b can be stored in the heat radiation layer 42. Then, the heat at the time of blowing the fuse 11 is radiated from the surface of the heat radiation layer 42. Therefore, the heat held by the first conductive layer 41a and the second conductive layer 41b can be reduced, and the first conductive layer 41a and the second conductive layer 41b can be prevented from melting even when the size is reduced. It becomes.
[0053]
In the second embodiment, as in the first embodiment, SiO 2 ₂ The first heat dissipation prevention layer 31 prevents the heat generated at the fusing portion F of the fuse 11 from being conducted to the substrate 1 side. Furthermore, in the second embodiment, Si having a lower thermal conductivity than the substrate 1 is used. ₃ N ₄ To prevent the heat generated at the fusing portion F of the fuse 11 from being conducted to the opposite side of the substrate 1. Therefore, heat generation required for fusing the fuse 11 can be prevented, and a defective fuse can be prevented. Since the fuse 11 is provided between both the first heat dissipation prevention layer 31 and the second heat dissipation prevention layer 34, the fusing failure of the fuse 11 can be further prevented.
[0054]
In this embodiment, the substrate 1, the first semiconductor layer 2, the second semiconductor layer 3, the fuse 11, the first heat dissipation prevention layer 31, the first insulation layer 32, the second insulation layer 33, the second heat dissipation prevention layer 34, the first The conductive layer 41a, the second conductive layer 41b, and the heat dissipation layer 42 are respectively a substrate, a first semiconductor layer, a second semiconductor layer, a fuse, a heat dissipation prevention layer, a first insulation layer, a second insulation layer, and a heat dissipation prevention substrate of the present invention. Layer, a first conductive layer, a second conductive layer, and a heat dissipation layer.
[0055]
The present invention is not limited to the above-described first and second embodiments, but may employ various modifications.
[0056]
For example, the application of the fuse in the semiconductor device of the present embodiment is not limited to the resistance adjustment, and the connection and disconnection of other circuit elements can be controlled to adjust the characteristics of the circuit.
[0057]
In addition, although the conductive polysilicon is used in the fuse 11 of the present embodiment, the fuse 11 may be formed using, for example, Ta (tantalum), Ti (titanium), or TiN (titanium nitride).
[0058]
Further, for example, it is preferable to use a material having a higher thermal conductivity than the first conductive layer 41a and the second conductive layer 41b for the heat radiation layer 42. For example, when the first conductive layer 41a and the second conductive layer 41b are Al, it is preferable to use Cu (copper), Ag (silver), or the like. In this case, heat from the first conductive layer 41a or the second conductive layer 41b can be efficiently transmitted to the heat radiation layer 42, and heat can be efficiently radiated from the surface of the heat radiation layer 42. Further, the volume of the heat radiation layer 42 is higher when the heat radiation layer 42 having a higher thermal conductivity is provided than when the heat radiation layer 42 having the same thermal conductivity as the first conductive layer 41a and the second conductive layer 41b is provided. Can be reduced. An occupied area and a step can be reduced, and high integration and miniaturization are further facilitated.
[0059]
Further, in the first conductive layer 41a, the second conductive layer 41b, and the heat dissipation layer 42, irregularities or the like may be formed in portions where the surfaces are exposed, so that the contact area with the outside can be increased. By increasing the contact area with the outside, heat can be effectively dissipated.
[0060]
In the manufacturing method according to the present embodiment, the second insulating layer 33 is opened by etching, the third contact hole 22a and the fourth contact hole 22b are formed in the first fuse contact region A, and the second fuse contact region is formed. A fifth contact hole 22c is formed in B. The first conductive layer 41a is buried in the third contact hole 22a to be connected to the first semiconductor layer 2, and is buried in the fourth contact hole 22b to be connected to the fuse 11. However, since the semiconductor device of the present embodiment is configured so that the first conductive layer 41a is connected to the first semiconductor layer 2 and the fuse 11, the semiconductor device is not limited to the above-described manufacturing method. For example, instead of forming two contact holes of the third contact hole 22a and the fourth contact hole 22b in the first fuse contact region A, only one contact hole is formed and both the first semiconductor layer 2 and the fuse 11 are formed. May be exposed, and the first conductive layer 41a may be formed in this contact hole.
[0061]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor device capable of preventing a conductive layer at both ends of a fuse from being melted or preventing a fuse from being blown out and improving yield or reliability, and a method of blowing the fuse.
Further, according to the present invention, it is possible to provide a semiconductor device in which conductive layers at both ends of a fuse can be narrowed and miniaturized.
[Brief description of the drawings]
FIGS. 1A and 1B show a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view of a fuse and a pad electrode portion, and FIG. 1B is a schematic sectional view.
FIGS. 2A and 2B show a semiconductor device according to a second embodiment of the present invention, wherein FIG. 2A is a plan view of a fuse and a pad electrode portion, and FIG. 2B is a schematic sectional view.
FIG. 3 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view showing a manufacturing process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration example of a trimming circuit of the semiconductor device according to the related art and the embodiment of the present invention;
8A and 8B show a conventional semiconductor device. FIG. 8A is a plan view of a fuse and a pad electrode portion, and FIG. 8B is a schematic sectional view.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... 1st semiconductor layer, 3 ... 2nd semiconductor layer, 4 ... Junction layer, 10 ... Fuse layer, 11 ... Fuse, 21b ... 1st contact hole, 21c ... 2nd contact hole, 22a ... 3rd Contact hole, 22b: fourth contact hole, 22c: fifth contact hole, 23a: sixth contact hole, 23b: seventh contact hole, 23c: eighth contact hole, 31: first heat dissipation prevention layer, 32: first Insulating layer, 33: second insulating layer, 34: second heat dissipation prevention layer, 41a: first conductive layer, 41b: second conductive layer, 42: heat dissipation layer, A: first fuse contact region, B: second fuse Contact area

Claims (5)

A substrate of a first conductivity type semiconductor;
A first insulating layer formed in a surface region of the substrate;
A first semiconductor layer of a first conductivity type semiconductor located on one side of the first insulating layer and formed in a surface region of the substrate;
A second semiconductor layer of a second conductivity type semiconductor formed on a surface region of the substrate and located on the other side of the first insulating layer opposite to the one side and forming a PN junction with the substrate;
A conductive fuse formed by bridging the first insulating layer and the first semiconductor layer and the second semiconductor layer and having a portion having a high current density and capable of being blown by energization heating;
A first conductive layer connected to one end of the fuse and a first semiconductor layer;
A second conductive layer connected to the other end of the fuse;
A second insulating layer formed on the fuse,
With
A semiconductor device in which the first semiconductor layer and the second semiconductor layer have higher thermal conductivity than the first insulating layer. The semiconductor device according to claim 1, further comprising a heat radiation preventing layer having a lower thermal conductivity than the substrate at a portion of the fuse that can be blown. 2. The semiconductor device according to claim 1, further comprising: a heat dissipation layer having thermal conductivity connected to at least one of said first conductive layer and said second conductive layer. The fuse is formed of conductive polysilicon;
The semiconductor device according to claim 1. A substrate of a first conductivity type semiconductor;
A first insulating layer formed in a surface region of the substrate;
A first semiconductor layer of a first conductivity type semiconductor located on one side of the first insulating layer and formed in a surface region of the substrate;
A second semiconductor layer of a second conductivity type semiconductor formed on a surface region of the substrate and located on the other side of the first insulating layer opposite to the one side and forming a PN junction with the substrate;
A conductive fuse formed by bridging the first insulating layer and the first semiconductor layer and the second semiconductor layer and having a portion having a high current density and capable of being blown by energization heating;
A first conductive layer connected to one end of the fuse and a first semiconductor layer;
A second conductive layer connected to the other end of the fuse;
A second insulating layer formed on the fuse,
With
A fuse blowing method for a semiconductor device, wherein a thermal conductivity of the first semiconductor layer and the second semiconductor layer is higher than that of the first insulating layer,
A fuse blowing method in which a current is applied to the first conductive layer and the second conductive layer so that a reverse bias is applied to the junction between the substrate and the second semiconductor layer, and the fuse is blown by heating the current.

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