JP2004228365A - Soi field-effect transistor, soi semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make avoidable difficulty in introducing channel impurities when forming a fully-depleted device, and to reduce a sidewall component capacitance which occupies a large part of junction capacitance in an SOI (silon on insulator) device. <P>SOLUTION: An SOI field-effect transistor is provided with an insulting film (102) having a projection; and a silicon layer (112) having a source region (103), a drain region (105), and a channel region (107). The source region (103) and the drain region (105) are provided at opposite sides of the projection of the insulating film (102), respectively. The channel region (107) is arranged above the projection of the insulating film (102) and between the source region (103) and the drain region (105). The lower surface of the channel region (107) is positioned at a higher level than the lower surfaces of the source region (103) and the drain region (105), and the upper surface of the channel region (107) is positioned so as to be lower than the upper surfaces of the source region (103) and the drain region (105). <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an SOI (Silicon on Insulator) type semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
In a logic-based semiconductor device in which the technology node is smaller than 100 nm and the miniaturization is being vigorously advanced, a silicon-on-insulator in which a substrate and a device formation region are separated by an insulator in place of a conventionally used bulk type device. (SOI) type devices are becoming mainstream. This is because by completely isolating the device region from the substrate, it is possible to realize high-speed and low-power consumption operation by reducing parasitic capacitance such as junction capacitance, reducing leakage current, low substrate bias effect, and high cut-off characteristics. Also, a large advantage such as a large improvement in latch-up / soft error resistance can be obtained.
[0003]
Such SOI devices include a fully depleted device of FIG. 18A and a partially depleted device of FIG. 18B. A buried oxide film (BOX) 1802 is provided on a silicon substrate 1801, and a silicon layer 1811 is provided thereon. The silicon layer 1811 includes a source region 1803, a source extension region 1804, a drain region 1805, a drain extension region 1806, and a channel region 1807. A gate electrode 1809 is provided over the channel region 1807 with a gate oxide film 1808 interposed therebetween. A sidewall 1810 is provided on a side wall of the gate electrode 1809.
[0004]
The fully depleted device in FIG. 18A operates in a state where the channel region 1807 is completely depleted to the buried oxide film 1802 interface. The partially depleted device in FIG. 18B operates in a state where the channel region 1807 is not completely depleted and a part of the neutral region 1812 remains. Each operation mode has advantages and disadvantages, and it is desirable to appropriately use them depending on the target device or circuit. Since these two operation modes are mainly determined by the thickness of the silicon layer 1811 on the buried insulating film 1802, each device can be used in a wafer, a chip, a circuit, or a large process in accordance with the characteristics of the circuit. It was relatively difficult to separately produce without increasing the number of steps.
[0005]
Further, as shown in FIG. 19, the disadvantage of the fully depleted device is that the silicon layer 1811 on the buried oxide film 1802 is very thin, so that it is difficult to control the threshold voltage by impurities in the channel region 1807 or the like. And an increase in the diffusion layer resistance 1901.
[0006]
As shown in FIG. 20, with respect to the high resistance of the diffusion layer, an elevated source / drain structure by a selective epitaxial growth technique of silicon or the like has been adopted. This is to selectively grow silicon layers 2003 and 2005 on the diffusion layer portions of the source region 1803 and the drain region 1805, increase the thickness 2001 of the diffusion layer, and lower the resistance of the diffusion layer. However, side effects such as an increase in thermal budget and an increase in parasitic capacitance due to an increase in fringe capacitance are also observed. These points are a major factor that makes the fully depleted device not practical despite the ideal cut-off characteristic (small subthreshold coefficient).
[0007]
Further, as shown in FIG. 21, as an advantage of the SOI device, since the bottom surfaces of the diffusion layers 1803 and 1805 are in contact with the buried oxide film 1802, the capacitance 2102 of the junction bottom surface is very small (almost In this case, the junction capacitance 2101 on the side wall occupies most of the entire junction capacitance. Even when an SOI substrate is used, the junction capacitance 2101 is the same as that of a bulk device, and it has been difficult to further reduce the junction capacitance.
[0008]
Patent Documents 1 and 2 below are disclosed.
[0009]
[Patent Document 1]
JP-A-5-121744
[Patent Document 2]
JP-A-11-40817
[0010]
[Problems to be solved by the invention]
As described above, SOI devices have very attractive characteristics of high speed and low power consumption operation, but devices with different operation modes can be manufactured on the same wafer without greatly increasing the number of process steps. It was difficult to fit. Further, in a fully depleted SOI MOS field effect transistor (FET) having an ultrathin SOI film thickness, it is difficult to introduce impurities into the thin film channel region, and it is difficult to obtain a desired threshold voltage. Further, when an elevated source / drain structure (FIG. 20) using a silicon selective epitaxial growth technique is used to lower the resistance of the diffusion layer, there is a problem that the fringe capacitance increases. There is also a problem that the use of the SOI structure cannot reduce the sidewall junction capacitance 2101 (FIG. 21) common to the bulk.
[0011]
An object of the present invention is to control the thickness of a silicon layer without any significant increase in the number of process steps, and to freely arrange the silicon layer in a semiconductor device at a location that makes use of the features of the partially depleted and fully depleted devices. To improve the degree of freedom in design.
It is another object of the present invention to avoid the difficulty of introducing channel impurities in the formation of a fully depleted device, and to further reduce the sidewall component capacitance that occupies most of the junction capacitance in an SOI device. .
Still another object of the present invention is to prevent an increase in fringe capacitance in an elevated source / drain structure, and to make full use of the advantages of an SOI device such as high speed and low power consumption.
[0012]
[Means for Solving the Problems]
According to one embodiment of the present invention, an SOI field-effect transistor including an insulating film having a projection and a silicon layer provided over the insulating film and including a source region, a drain region, and a channel region is provided. The source region and the drain region are provided on both sides of the projection of the insulating film. The channel region is provided on the convex portion of the insulating film and between the source region and the drain region. The lower surface is located above the lower surfaces of the source region and the drain region. Is located below the upper surface of.
[0013]
According to another aspect of the present invention, an ion implantation step of selectively implanting oxygen ions or accelerated oxidizing species into upper and lower portions of the channel region of the silicon layer on the oxide film, and heat treatment or oxidation treatment are performed. Accordingly, a method for manufacturing an SOI semiconductor device, comprising: an oxide film forming step of forming an oxide film above and below a channel region; and a removing step of exposing the channel region by removing the oxide film above the channel region. Is provided.
[0014]
According to the present invention, the thickness of the silicon layer is controlled without any significant increase in the number of process steps, and the silicon layer can be freely disposed in a semiconductor device at a location where the characteristics of the partially depleted and fully depleted devices are utilized. Therefore, the degree of freedom in design can be improved. Further, in forming a fully depleted device, it is possible to avoid difficulty in introducing channel impurities, and further, it is possible to reduce a sidewall component capacitance that occupies most of a junction capacitance in an SOI device. Further, an increase in fringe capacitance in the elevated source / drain structure can be prevented, and the advantages of the SOI device such as high speed and low power consumption can be fully utilized.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a sectional view showing a structure of an SOI field effect transistor (semiconductor device) according to an embodiment of the present invention. A buried silicon oxide film (BOX) 102 having a convex portion is provided on a silicon substrate 101, and a silicon layer 112 is further provided thereon. The silicon layer 112 has a source region 103, a source extension region 104, a drain region 105, a drain extension region 106, and a channel region 107. The source region 103 and the drain region 105 are provided on both sides of the convex portion of the buried oxide film 102. The channel region 107 is provided on the convex portion of the buried oxide film 102 and between the source region 103 and the drain region 105, and the lower surface thereof is located above the lower surfaces of the source region 103 and the drain region 105. The upper surface is located lower than the upper surfaces of the source region 103 and the drain region 105. On the channel region 107, a gate electrode (polysilicon) 109 is provided via a gate silicon oxide film (insulating film). A side wall (silicon oxide) 110 is provided on a side wall of the gate electrode 109. The oxide film 102 may be another film as long as it is an insulating film.
[0016]
In the present embodiment, the thickness of the buried oxide film 102 is increased only in the portion of the channel region 107 of the field effect transistor, and the thickness of the SOI layer 112 is reduced in the portion including the channel region 107. By doing so, a device having a very thin channel (body) portion is manufactured. At this time, the channel region 107 has a shape lower than the surface of the silicon substrate, and the buried oxide film 102 has a shape in which the portion of the channel region 107 is raised.
[0017]
By thinning the SOI layer 112 from both the upper and lower directions of the channel region 107 as described above, it is possible to efficiently form the thin film SOI channel region 107 with good controllability. In addition, by using one-mask exposure, the silicon layer can be selectively thinned only in the channel portion of the field-effect transistor, and furthermore, a completely depleted device and a partially depleted device can be easily formed in a circuit. Can be. Since the thinning of the silicon layer 112 from the upper portion is performed by oxidation and wet etching, a shape that is not steep as compared with the case where the dry etching process of FIG. 2 is used is obtained, and the gate side wall (side wall) later. There is no problem in forming the insulating layer 110, burying the insulating film, and the like, and the uniformity of the thickness of the SOI layer is high. That is, as shown in FIG. 2, when the channel region 107 is thinned by dry etching, a steep step 201 is formed, the uniformity of the film thickness of the channel region 107 is poor, and there is a problem that the channel region 107 is damaged. In the manufacturing method of the present embodiment, such a problem does not occur because the channel region 107 is thinned by oxidation and wet etching. Details of the manufacturing method will be described later.
[0018]
By adopting such a device structure, it is possible to achieve both an ultra-thin silicon channel and a low-resistance diffusion layer (elevated source / drain structure), and to use an elevated source / drain (FIG. 20) using a silicon selective epitaxial growth technique or the like. 1), as shown in FIG. 1, the structure can be such that the distance 111 between the gate 109 and the source / drain 103, 105 is large, so that an increase in fringe capacitance can be prevented. In addition, a sidewall component (corresponding to the capacitor 2101 in FIG. 21) occupying most of the junction capacitance in the SOI device can be reduced to the utmost. Furthermore, by introducing a channel impurity before the SOI layer is thinned, it becomes easy to control the impurity concentration for controlling the threshold voltage, which is difficult in an ultra-thin SOI device.
[0019]
As shown in FIG. 1, only the channel region 107 of the SOI layer 112 has a reduced thickness due to the increase in the thickness of the buried oxide film 102 and the reduction in thickness by surface oxidation and wet etching. In other words, the channel region 107 exists at a position just in the middle of the interface between the wafer surface and the buried oxide film 102 in the depth direction. Since the thinning from the top is performed by oxidation, the gate and the source / drain region are not close to each other via the gate side wall as in the elevated source / drain structure (FIG. 20) formed by silicon selective epitaxial growth.
[0020]
3 to 16 show an example of a process flow for forming an SOI CMOS device. As shown in FIG. 3, an SOI substrate is prepared. In the SOI substrate, a buried silicon oxide film 302 is formed on a silicon substrate 301, and a silicon layer 303 is further formed thereon. The SOI substrate can be formed by implanting oxygen ions into a silicon substrate, bonding a silicon substrate, or the like. The SOI substrate has regions for manufacturing a fully depleted field effect transistor (FIG. 1) T1 and a partially depleted field effect transistor (FIG. 18B) T2. The transistor T1 has a p-channel MOS field-effect transistor P1 and an n-channel MOS field-effect transistor N1. The transistor T2 has a p-channel MOS field-effect transistor P2 and an n-channel MOS field-effect transistor N2. That is, the transistors T1 and T2 each constitute a CMOS.
[0021]
Next, as shown in FIG. 4, a silicon nitride film 401 having a predetermined pattern is formed on the silicon layer 303 by forming a silicon nitride film, photolithography, and etching.
[0022]
Next, using the silicon nitride film 401 as a mask, the silicon layer 303 is dry-etched to leave the silicon layer 303a as shown in FIG.
[0023]
Next, as shown in FIG. 6, a silicon oxide film is deposited by a CVD (Chemical Vapor Deposition) method, flattened by a CMP (Chemical Mechanical Polishing), and an element isolation region 601 made of a silicon oxide is formed.
[0024]
In the above, the process of forming the element isolation region 601 by Shallow Trench Isolation (STI) is described. However, the element isolation region 601 may be formed by Local Oxidation of Silicon (LOCOS), Mesa isolation, or the like.
[0025]
Next, as shown in FIG. 7, if necessary, a sacrificial oxide film 701 of about 5 to 10 nm is formed on the substrate surface. Then, an ion species (B, BF2, In) 703 generally used in a CMOS process is used to form a photoresist 702 having a predetermined pattern as a mask and adjust the threshold voltages of the n-channel MOS field effect transistors N1 and N2. Is ion-implanted. After that, the photoresist 702 is removed.
[0026]
Next, as shown in FIG. 8, a photoresist 802 having a predetermined pattern is formed as a mask, and an ion species commonly used in a CMOS process is used to adjust threshold voltages of p-channel MOS field-effect transistors P1 and P2. (P, As, Sb) 803 is ion-implanted. After that, the photoresist 802 is removed.
[0027]
At the time of the ion implantation shown in FIGS. 7 and 8, regardless of whether the device to be manufactured is a partially depleted type or a fully depleted type (ultra thin film), the initial SOI film thickness is relatively large. The conditions can be selected so that the range becomes about half of the thickness of the SOI layer even when the apparatus is used. If necessary, annealing for activation is performed.
[0028]
Next, as shown in FIG. 9, a photolithography process is performed to pattern only the region where the SOI layer is to be thinned, and a photoresist 901 having a predetermined pattern is formed. Here, the “region where the SOI layer is to be thinned” can be, for example, a region where a fully depleted device T1 in a circuit is to be manufactured, and more specifically, a channel region of this device. At this time, the thickness of the resist 901 needs to be sufficient to serve as a mask for the subsequent high-energy ion implantation.
[0029]
Next, oxygen ions 902 are implanted into a lower portion of the channel region 303a opened in the photolithography process. Oxygen ions 903 are formed below the channel region 303a. At this time, the implantation energy is set so that the range is just near the interface between the SOI layer 303a and the buried oxide film 302, and the dose is set so that a desired SOI film thickness is finally obtained. Is too large, it induces a large number of defects in the SOI layer and seriously affects device characteristics. ¹⁷ cm ^-2 The range is as follows. The implanted oxygen ions 903 are combined with Si in a heat treatment process to be performed thereafter to form SiO 2 ₂ Is an O source for forming
[0030]
Next, as shown in FIG. 10, using the same resist mask 901, ion implantation of accelerated oxidized ion species 1002 is performed above the channel region 303 a. An ion species 1103 is formed above the channel region 303a. Donor / acceptor impurities that affect the threshold voltage and the like are not used as the accelerated oxidizing ion species used here, and IV such as Si and Ge that does not adversely affect other device characteristics such as reliability as much as possible. Group elements, rare gases such as Ar, Kr, and Xe, and halogen elements, and a dose of about 10 ^Fifteen cm ^-2 Ion implantation is performed on the stage at an implantation energy such that the range is about several tens nm from the silicon surface. These accelerated oxidized ion species have the effect of significantly increasing the oxidation rate during oxidation, and are described, for example, in JP-A-2001-244345.
[0031]
Subsequently, after removing the resist mask 901, as shown in FIG. 11, an inert atmosphere is used to react the previously implanted O and Si to grow the buried oxide film only in the channel region only. Heat treatment is performed inside. Conditions at this time include, for example, N ₂ The atmosphere is at a temperature of 1200 ° C. or higher. The optimum condition is selected according to a desired SOI film thickness. The shape at the end of this step is as shown in FIG. 11, and in the cross-sectional view, the buried oxide film 302 has a convex shape in which only the region 1101 into which the ions are implanted is raised (thickened). Protrusions 1102 are also formed on the substrate surface.
[0032]
Subsequently, dry oxidation is performed as shown in FIG. Here, it is desirable to shift the temperature and atmosphere from the entire heat treatment step to the oxidation step as it is, but it is also possible to take out the wafer from the heat treatment furnace once and put it in the oxidation furnace again to perform the treatment. The oxidation is performed in a dry oxidation atmosphere at a temperature of 800 ° C. or less, for example, in order to increase the difference in oxidation rate between the region into which the ions are implanted and the region into which the ions are not implanted. The shape immediately after the oxidation is as shown in FIG. As shown in this figure, the oxide film thickness is increased only in the region 1201 where the ions are implanted. As a result, a source / drain region 303b and a channel region 303c are formed in the silicon layer.
[0033]
Next, when the oxide film formed on the surface is removed with an HF-based etchant, the result is as shown in FIG.
[0034]
Next, as shown in FIG. 14, a gate silicon oxide film 1401 is formed on the surface of the substrate, and a gate electrode (polysilicon) 1402 having a predetermined pattern is formed thereon.
[0035]
Next, as shown in FIG. 15, a side wall (silicon oxide film) 1501 is formed on the side wall of the gate electrode 1402.
[0036]
Next, as shown in FIG. 16, ions are implanted into the source / drain region 1601 from directly above, and ions are implanted into the source / drain extension region 1602 from an oblique direction. P-type impurities are ion-implanted into the regions 1601 and 1602 of the p-channel MOS field-effect transistors P1 and P2. In contrast, n-type impurities are ion-implanted into regions 1601 and 1602 of n-channel MOS field-effect transistors N1 and N2.
[0037]
As described above, the fully depleted field effect transistor T1 and the partially depleted field effect transistor T2 can be formed on the same substrate. The transistor T1 includes a p-channel MOS field-effect transistor P1 and an n-channel MOS field-effect transistor N1. Transistor T2 includes a p-channel MOS field-effect transistor P2 and an n-channel MOS field-effect transistor N2.
[0038]
The transistor T1 has the configuration shown in FIG. 1, in which the channel region 107 is provided on the convex portion of the buried oxide film 102 and between the source region 103 and the drain region 105, and the lower surface thereof is provided with the source region 103 and the drain The region is located above the lower surface of the region 105, and the upper surface is located below the upper surfaces of the source region 103 and the drain region 105.
[0039]
The transistor T2 has a structure illustrated in FIG. 18B, in which a channel region 1807 is provided between the source region 1803 and the drain region 1805, and a lower surface and an upper surface of the channel region 1807 are lower surfaces of the source region 1803 and the drain region 1805. And the same position as the upper surface.
[0040]
By adjusting the ion implantation conditions in FIG. 16, two types of fully depleted field effect transistors T1 and T2 can be formed as shown in FIG. The transistor T1 has the configuration shown in FIG. The transistor T2 has a structure illustrated in FIG. 18A, in which a channel region 1807 is provided between a source region 1803 and a drain region 1805, and the lower surface and the upper surface of the channel region 1807 are lower surfaces of the source region 1803 and the drain region 1805. And the same position as the upper surface. Since the transistors T1 and T2 have different thicknesses of silicon layers (including a source region, a drain region, and a channel region), they can be used as different characteristics.
[0041]
Further, the case where oxygen ions 903 are implanted into the lower portion of the channel region 303a in the step of FIG. 9 and the accelerated oxidizing ion species 1003 are implanted in the upper portion of the channel region 303a in the step of FIG. 10 is not limited thereto. . Oxygen ions or accelerated oxide ion species may be selectively implanted into the upper and lower portions of the channel region. After that, heat treatment or oxidation treatment is performed, whereby an oxide film can be formed over and under the channel region. When the accelerated oxide ion species is implanted below the channel region, oxygen is supplied from the buried oxide film 302 by the heat treatment, and an oxide film is formed below the channel region. The accelerated oxidation ion species is a group IV element, a rare gas or a halogen element as described above.
[0042]
In addition, when ions 902 having a large mass such as oxygen are implanted, a large number of defects may be generated in the silicon layer. In that case, helium (He), which is a lighter element, is implanted instead of the oxygen ion 902, and the oxidation reaction can be performed using the helium as a nucleus.
[0043]
As described above, in the present embodiment, the SOI layer is made thinner in both directions of increasing the thickness of the buried oxide film and the surface oxidation + etching. However, if only one of these is performed, it becomes necessary. It is not preferable because the implantation dose becomes large, and the side effect due to the deterioration of the crystallinity of the silicon channel region and the implanted ion species is unpreferable.
[0044]
By using such a process, the structure as shown in FIG. 1 can be formed. Here, since the channel impurity is introduced before the channel SOI layer is thinned, the difficulty of introducing the impurity into the thin film channel can be avoided. There is a concern that channel impurities may be absorbed into the oxide film during oxidation. However, the amount is not large, and depending on the impurities, the impurity concentration is reduced only on the channel surface, so that the carrier mobility is reduced. Deterioration can also be suppressed.
[0045]
By using the structure and the manufacturing method according to the present embodiment, the SOI film thickness can be controlled in the wafer without a significant increase in the number of process steps, and the partial depletion type and the fully depletion type devices can be used in the circuit. It can be freely placed in a location that makes use of its features, and the degree of freedom in design is improved. Further, it is possible to avoid the difficulty of introducing channel impurities in the formation of a fully depleted device, and to further reduce the side wall component (corresponding to the capacitance 2101 in FIG. 21) which occupies most of the junction capacitance in the SOI device. Can be. In addition, it is possible to prevent an increase in fringe capacitance in the elevated source / drain structure (FIG. 20), and it is possible to make full use of the advantages of the SOI device such as high speed and low power consumption.
[0046]
Further, according to the present embodiment, a fully depleted structure and a partially depleted structure can be separately formed in the same chip (wafer), and furthermore, an increase in parasitic resistance and parasitic capacitance which is a problem in the SOI device is reduced. In addition, it is possible to reduce the difficulty of the manufacturing process in the fully depleted SOI device.
[0047]
It should be noted that each of the above-described embodiments is merely an example of a concrete example in carrying out the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features.
[0048]
Various embodiments can be applied to the embodiment of the present invention, for example, as follows.
[0049]
(Supplementary Note 1) an insulating film having a convex portion;
A silicon layer provided on the insulating film and including a source region, a drain region, and a channel region;
The source region and the drain region are provided on both sides of a convex portion of the insulating film,
The channel region is provided on the protrusion of the insulating film and between the source region and the drain region, and a lower surface thereof is located above a lower surface of the source region and the drain region. Is located below the upper surfaces of the source region and the drain region.
(Supplementary note 2) The SOI field-effect transistor according to supplementary note 1, further comprising a gate electrode provided on the channel region via a gate insulating film.
(Supplementary note 3) The SOI field effect transistor according to supplementary note 1 or 2, wherein the insulating film is an oxide film.
(Supplementary Note 4) an insulating film having a convex portion;
A silicon layer provided on the insulating film to form a first field-effect transistor and a second field-effect transistor each including a source region, a drain region, and a channel region;
The first field effect transistor comprises:
The source region and the drain region are provided on both sides of a protrusion of the insulating film,
The channel region is provided on the convex portion of the insulating film and between the source region and the drain region, and a lower surface thereof is located above a lower surface of the source region and the drain region. Is located below the upper surface of the source region and the drain region,
In the second field-effect transistor, the channel region is provided between the source region and the drain region, and the lower surface and the upper surface of the channel region are at the same position as the lower surface and the upper surface of the source region and the drain region. An SOI semiconductor device.
(Supplementary note 5) The SOI semiconductor device according to supplementary note 4, further comprising a gate electrode provided on each channel region of the first and second field-effect transistors via a gate insulating film.
(Supplementary Note 6) The SOI semiconductor device according to Supplementary Note 4 or 5, wherein the insulating film is an oxide film.
(Supplementary Note 7) An ion implantation step of selectively implanting oxygen ions or accelerated oxide ion species into upper and lower portions of the channel region of the silicon layer on the oxide film;
An oxide film forming step of forming an oxide film on the upper and lower portions of the channel region by performing a heat treatment or an oxidation process;
A removing step of exposing the channel region by removing an oxide film on the channel region;
A method for manufacturing an SOI semiconductor device having:
(Supplementary note 8) The method for manufacturing an SOI semiconductor device according to supplementary note 7, further comprising a step of introducing an impurity for forming an n-type or p-type channel into the channel region before the ion implantation step.
(Supplementary Note 9) In the ion implantation step, oxygen ions are implanted into a lower portion of the channel region, and accelerated oxidizing ion species are implanted into an upper portion of the channel region.
9. The method for manufacturing an SOI semiconductor device according to claim 7, wherein the oxide film forming step performs a heat treatment in an inert gas and a dry oxidation treatment.
(Supplementary note 10) The method for manufacturing an SOI semiconductor device according to Supplementary note 7 or 8, wherein the ion implantation step implants helium ions below the channel region.
(Supplementary Note 11) The method for manufacturing an SOI semiconductor device according to any one of Supplementary Notes 7 to 10, wherein the accelerated oxide ion species is a Group IV element, a rare gas, or a halogen element.
[0050]
【The invention's effect】
As described above, without significantly increasing the number of process steps, the thickness of the silicon layer is controlled, and the silicon layer can be freely arranged in a location utilizing the characteristics of the partially depleted and fully depleted devices in the semiconductor device. Therefore, the degree of freedom in design can be improved. Further, in forming a fully depleted device, it is possible to avoid difficulty in introducing channel impurities, and further, it is possible to reduce a sidewall component capacitance that occupies most of a junction capacitance in an SOI device. In addition, it is possible to prevent an increase in fringe capacitance in the elevated source / drain structure, and to fully utilize the advantages of the SOI device such as high speed and low power consumption.
[Brief description of the drawings]
FIG. 1 is a sectional view showing an example of an SOI semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a method of forming the structure of FIG. 1 by dry etching.
FIG. 3 is a sectional view showing an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 4 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 5 is a sectional view showing an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 6 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 7 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 8 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 9 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 10 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 11 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 12 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 13 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 14 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 15 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 16 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
FIG. 17 is a sectional view illustrating an example of a method for manufacturing an SOI semiconductor device according to the embodiment of the present invention.
18A and 18B are cross-sectional views of a fully depleted device and a partially depleted device.
FIG. 19 is a diagram illustrating a problem in a fully depleted SOI MOSFET.
FIG. 20 is a diagram showing an example of an SOI MOSFET having an elevated source / drain structure using a silicon selective epitaxial growth technique.
FIG. 21 is a diagram illustrating a (parasitic) junction capacitance component in an SOI MOSFET.
[Explanation of symbols]
101 silicon substrate
102 buried oxide film
103 Source area
104 Source extension area
105 Drain region
106 Drain extension area
107 channel area
108 Gate oxide film
109 Gate electrode
110 Sidewall
112 Silicon layer
1801 Silicon substrate
1802 buried oxide film
1803 Source area
1804 Source extension area
1805 Drain region
1806 Drain extension area
1807 channel area
1808 Gate oxide film
1809 Gate electrode
1810 Sidewall
1811 Silicon layer

Claims (5)

An insulating film having a convex portion,
A silicon layer provided on the insulating film and including a source region, a drain region, and a channel region;
The source region and the drain region are provided on both sides of a convex portion of the insulating film,
The channel region is provided on the protrusion of the insulating film and between the source region and the drain region, and a lower surface thereof is located above a lower surface of the source region and the drain region. Is located below the upper surfaces of the source region and the drain region. An insulating film having a convex portion,
A silicon layer provided on the insulating film to form a first field-effect transistor and a second field-effect transistor each including a source region, a drain region, and a channel region;
The first field effect transistor comprises:
The source region and the drain region are provided on both sides of a protrusion of the insulating film,
The channel region is provided on the convex portion of the insulating film and between the source region and the drain region, and a lower surface thereof is located above a lower surface of the source region and the drain region. Is located below the upper surface of the source region and the drain region,
In the second field-effect transistor, the channel region is provided between the source region and the drain region, and the lower surface and the upper surface of the channel region are at the same position as the lower surface and the upper surface of the source region and the drain region. An SOI semiconductor device. An ion implantation step of selectively implanting oxygen ions or accelerated oxide ion species into upper and lower portions of the channel region of the silicon layer on the oxide film,
An oxide film forming step of forming an oxide film on the upper and lower portions of the channel region by performing a heat treatment or an oxidation process;
Removing the oxide film on the channel region to expose the channel region. 4. The method for manufacturing an SOI semiconductor device according to claim 3, further comprising a step of introducing an impurity for forming an n-type or p-type channel into said channel region before said ion implantation step. In the ion implantation step, oxygen ions are implanted in a lower portion of the channel region, and accelerated oxidizing ion species are implanted in an upper portion of the channel region,
5. The method for manufacturing an SOI semiconductor device according to claim 3, wherein said oxide film forming step includes a heat treatment in an inert gas and a dry oxidation treatment.

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