JP2004226291A - Semiconductor test circuit and its test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test circuit for remarkably reducing an amount of a scanning test pattern and shortening a full scanning test time by modifying the constitution of an inside scanning chain at any time without increasing a test terminal and remarkably shortening a once-scanning shift action period in an LSI full scanning design, and to provide its test method. <P>SOLUTION: The semiconductor test circuit for performing the LSI full scanning test by dividing a large number of the scanning chains comprises discrimination circuits 5 and 6 having an outside scanning-in terminal 9, an outside scanning-out terminal 10, a shift operation changeover terminal 11 and a clock terminal 12, and discriminating a specific cycle during shift operation changeover, and selection circuits 7 and 8 for selecting inside scanning-in and inside scanning-out connecting the outside scanning-in terminal 9 and the outside scanning-out terminal 10 on the basis of data for a command of a signal input from the outside scanning-in terminal 9 in the specific cycle. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor test circuit and a test method therefor, and more particularly to a full scan test circuit for an LSI and a test method therefor.
[0002]
[Prior art]
In recent years, with the miniaturization of semiconductor processes, circuits of logic LSIs have become larger, and logic LSIs with millions of gates have been designed. When testing such a logic LSI at the time of shipment, the development period of the test pattern is lengthened, and the amount of test patterns and test time used in actual mass production tests become enormous, thereby increasing the test cost. Therefore, in order to reduce the test cost of the logic LSI, a testability design is generally adopted.
[0003]
A typical method for designing for testability is a full scan design. In the full scan design, the flip-flop inside the circuit is replaced with a scan flip-flop with a scan function, and the scan chain, which is a path that can directly control and observe the internal flip-flop from an external pin, is serialized with each flip-flop with a scan function. And a shift register connected to. Also, the configuration is such that all sequential circuits can be handled as combinational circuits during the test. With such a configuration, the test of the logic LSI becomes very easy.
[0004]
4 shows an example of a full scan test circuit. The full scan circuit changes a normal flip-flop to a scan flip-flop 100 as shown in FIG. The scan flip 100 in FIG. 11 is called a MUX type, and has a structure in which a multiplexer 102 is inserted into a D input portion of a flip-flop 101 and a shift data terminal SIN and a multiplexer switching terminal SMC are added.
[0005]
FIG. 12 is a conceptual diagram of a circuit in which a normal flip-flop in the circuit 103 is replaced with a scan flip-flop and a full scan design is performed. The scan flip-flops 104a, 104b, 104c have the same circuit configuration as that shown in FIG. In the scan connection, the external scan-in terminal 106a is connected to the SIN terminal of the scan flip-flop 104a, and the Q output is connected to the next scan flip-flop 104b. Similarly, it is connected to the scan flip-flop 104c, and finally connected to the external scan-out terminal 107a to form a scan chain. The same connection is made from the external scan-in terminal 106b to the scan-out terminal 107b, and from the external scan-in terminal 106c to the scan-out terminal 107c. In this conceptual diagram, a total of three scan chains are formed. Further, a shift operation switching terminal 108 is added to control the shift operation and the capture operation performed in the scan test, and the shift operation switching terminal 108 is supplied to the SMC terminals of all the scan flip-flops. The clock terminal 109 exists in the circuit before scanning and is used as it is. In the case of FIG. 12, the length of the scan chain is 3, but it is actually the number of all flip-flops in the circuit divided by the number of available scan input / output terminals. For example, if the number of flip-flops is 900, three scan input terminals and three scan output terminals can be used, the length of one chain is 300. With this circuit configuration, a test of the scan flip-flop 104 of the LSI circuit 103 and the test of the combinational circuit 105 are performed.
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-5403 [Patent Document 2]
JP 2000-258500 A
[Problems to be solved by the invention]
In the full scan test, a shift operation is performed to set the state of the scan flip-flop and read out the value after the operation, so that there is a problem that the test pattern length becomes extremely long. Since the length of the test pattern increases in proportion to the increase in the circuit scale, if the circuit size of the logic LSI is large, a large amount of test pattern memory of the logic LSI tester is consumed, and the full scan test time also becomes long. Therefore, it becomes the main cause of increasing the test cost. As a measure for shortening the test pattern, generally, the number of test pattern cycles required for the shift operation is reduced by increasing the number of scan chains. However, since the number of external terminals is usually limited, the number of scan chains is often limited to about 20 to 30. As a method of further reducing the number of scan shift cycles, a scan signal operation cycle is proposed by adding a bypass signal line in the middle of a scan chain and switching modes as proposed in "Semiconductor Integrated Circuit" of Patent Document 1. There are things to shorten. In this method, the scan-in terminal and scan-out terminal are fixed, and a test mode that bypasses the scan flip-flop is added, so that the degree of freedom in generating test patterns is small, and the number of test mode switching terminals increases. There is a problem. Further, in the method proposed in “Semiconductor integrated circuit and recording medium” of Patent Document 2, a plurality of scan chains are connected in parallel, the same scan input signal is supplied to the circuit, and the scan output is compressed by XOR. In this method, the purpose is to reduce the number of shift operations. The problem of this circuit is that the scan chains to be parallelized are fixed, so that the test pattern shortening effect may not be sufficiently obtained. In addition, since the scan output is compressed by the XOR method, if an undefined signal is generated in the circuit, the final output is also undefined and a high failure detection rate may not be obtained. Further, in the present invention, it is considered that a terminal for switching the test mode is additionally required.
[0008]
According to the present invention, in a full scan design of an LSI, the configuration of the internal scan chain is changed as needed without increasing the number of test terminals, and the period of one scan shift operation is significantly shortened. It is an object of the present invention to provide a semiconductor test circuit and a test method thereof capable of greatly reducing the time required for a full scan test.
[0009]
[Means to solve the problem]
The present invention relates to a circuit for performing a full scan test of an LSI by dividing the number of scan chains into a large number without being restricted by an external scan-in terminal and an external scan-out terminal. A determination circuit that has a terminal, an external scan-out terminal, a shift operation switching terminal, and a clock terminal, and that determines a specific cycle when the shift operation is switched; and a signal input from the external scan-in terminal in the specific cycle when the shift operation is switched. And a selection circuit for selecting an internal scan-in and an internal scan-out connected to the external scan-in terminal and the external scan-out terminal based on command data, respectively.
[0010]
Further, the present invention provides a function block unit including a plurality of flip-flops, and a command reception cycle determination for outputting a reception signal event based on a shift operation switching signal input to a shift operation switching terminal and an external clock signal input to a clock terminal. Unit, a command analysis unit that outputs a selection signal based on a test signal, an external clock signal, and an acceptance signal event, and a scan that changes the connection between the functional block unit and an external scan-in terminal or an external scan-out terminal according to the selection signal 1 is a semiconductor test circuit including an input selection unit and a scan output selection unit.
[0011]
Then, when connecting the internal scan-in and the internal scan-out to the external scan-in terminal and the external scan-out terminal, the present invention separately outputs the scan-in signal and the scan-out signal of each scan chain to the external scan-in terminal or This is a semiconductor test circuit connected to an external scan-out terminal.
[0012]
Furthermore, the present invention recognizes a signal input from the scan-in terminal as command data in the specific cycle determined at the time of switching the shift operation, and outputs the signal to the external scan-in terminal and the external scan-out terminal based on the command data. This is a semiconductor test circuit for connecting an unconnected internal scan-in to a necessary circuit in a timely manner.
[0013]
Further, the present invention is a method of performing a full scan test of an LSI by dividing the number of scan chains into a large number without being restricted by an external terminal. The semiconductor test method selects an internal scan-in and an internal scan-out which are respectively connected to the external scan-in terminal and the external scan-out terminal based on command data of a signal input from the external scan-in terminal in a specific cycle.
[0014]
According to the present invention, the first part of the test pattern generation has a circuit configuration for connecting all the scan flip-flops, obtains a certain failure detection rate, and thereafter, a part necessary to improve the failure detection rate Is a semiconductor test method that uses only scan flip-flops and obtains a fault detection rate with a short test pattern.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described.
FIG. 1 shows a configuration of a full scan test circuit according to one embodiment of the present invention. FIG. 1 shows a functional circuit block 2 realizing the function of an original LSI in a LSI circuit 1, a scan input selection circuit 7, a scan output selection circuit 8, a command reception cycle determination unit 6, and a command analysis unit 5. Be composed. In the functional circuit block 2, the flip-flop is replaced with the scan flip-flop 3 after the functional block is designed, and the scan flip-flop is converted into a scan chain 4 configuration in which each scan flip-flop is serially connected. At this time, the number of scan chains is several times larger than in the past, and the length of one chain is shorter than in the past. The scan input selection unit 7 connects the input portions of each scan chain of the functional circuit block 2 by an internal switch according to a selection signal output from the command analysis unit 5. At this time, a part of the scan chain is connected to scan input terminals 9a, 9b, 9c which are external terminals of the LSI circuit. The other input parts of the scan chain are connected to circuits in the scan input selection unit. The scan output selection unit 8 connects the output portions of each scan chain of the functional circuit block 2 by an internal switch according to a selection signal output from the command analysis unit 5. At this time, a part of the scan chain is connected to scan output terminals 10a, 10b and 10c which are external terminals of the LSI circuit. The command analyzer 5 receives a signal input from the scan input terminals 9a, 9b, 9c as a command when a reception signal event from the command reception cycle determiner 6 comes, and the connection contents are determined in advance by the designer. The command is compared with the command, and a selection signal is sent to the scan input selection unit 7 and the scan output selection unit 8. The command reception cycle determination unit 6 determines the timing at which a command comes based on the signal of the shift operation switching terminal 11 and the signal of the external CLK 12, and issues a reception signal event to the command analysis unit. For example, a case where one cycle at the moment when the shift operation switching signal 11 switches from the capture state to the shift state is defined as a command reception cycle will be described with reference to the timing chart of FIG. Assuming that the shift operation switching signal in FIG. 2 is "1", the scan flip-flop is in the shift mode, and "0" is the scan flip-flop in the capture mode, the first cycle (1) is the capture operation. In the second cycle (2), the shift operation switching terminal changes to “1”, the command receiving cycle determining unit 6 determines that a command has been input, and issues a receiving signal event to the command analyzing unit 5 to perform scan input. The terminal data is recognized as a command. The command is processed by the command analyzer 5, and the connection between the scan input selector 7 and the scan output determiner 8 is changed according to the command. In the next cycle (3), the first data set by the scan flip-flop is input from the scan input terminal. Similarly, in the cycle (4), the second data set in the scan flip-flop is input, and the data similarly set in the scan flip-flop is sequentially input until the cycle (n). Until the end, when scan data is input, "0" is input from the shift operation switching terminal in cycle (n + 1), and the capture operation is performed by the scan circuit. After the cycle (n + 2), the command input cycle and the shift data input are similarly repeated. In this example, since there are three scan input terminals, eight kinds of command types can be realized, ie, 2 to the third power. In general, there are ten or more scan input terminals, so commands of 2 10 or more can be used. In this example, the command input cycle is one cycle. However, if the number of cycles is plural, the number of commands can be further increased.
[0016]
An actual command embodiment will be described. As an example, in the case of the command table in FIG. 3, a command is represented by 3 bits, and eight types of commands can be created. For example, three types are defined. The command 000 connects three scan inputs (1), (5), and (8) of the nine internal scan chains to the external scan input terminal, and other internal scan input terminals (2) (4) (6). (7) is input as "0", and (3) and (9) are input as "1". Also, three internal scan outputs (2), (6) and (8) are connected to external scan output terminals. The actual circuit structure is connected as shown in FIG. Although the circuits are directly connected to the scan input selection unit and the scan output selection unit in FIG. 4, they are actually connected by a switch formed of a transistor. Similarly, the command 001 in FIG. 3 connects the three scan inputs (1), (2) and (9) to the external scan input terminal, and the other internal scan input terminals (3) (4) (5) (5). In (6), (7) and (8), a connection is made to a LFSR (Linear Feedback Shift Register), which is a pseudo-random number generation circuit incorporated in the scan input selection unit in advance. The three scan outputs (1), (3) and (9) are connected to an external scan output terminal. By using the LFSR, a random signal value can be input during a full scan test. The circuit of this configuration is connected as shown in FIG.
[0017]
Further, the command 010 in FIG. 3 will be described. This command connects the internal scan-out of scan chain (1) and the internal scan-in of scan chain (2), and connects the internal scan-out of scan chain (2) and the internal scan-in of scan chain (3). The three scan chains have a single scan chain structure. Then, the scan input terminal of the internal scan chain (1) is connected to the external scan input terminal, and the scan-out terminal of the internal scan chain (3) is connected to the external scan-out terminal. Similarly, for the scan chains (4), (5), (6), and (7), (8), and (9), the three scan chains are integrated into one, and the internal scan-in terminal and the scan-out terminal are externally connected. Connect to the scan-in and scan-out terminals. The circuit of this configuration is connected as shown in FIG. By realizing the circuit of this configuration, a circuit having exactly the same function as the conventional method of serially connecting scan flip-flops and connecting them to an external terminal can be allocated by assigning one command. Although only three types are defined in the command example shown in FIG. 3, more combinations are actually defined.
[0018]
Next, an example of a scan test method using the present scan test circuit will be described. First, FIG. 7 shows a relationship between a failure detection rate and a test pattern in a general full scan method. In the full scan test, the failure detection rate sharply rises in the first half of the test pattern and the test is performed efficiently, but in the second half of the test pattern, the failure detection rate curve becomes very gentle, It has been found that the failure detection rate has not been efficiently increased. FIG. 8 shows the relationship between the number of scan flip-flops in the circuit used at this time and the test pattern. In the first half of the rapid rise in the failure detection rate, the number of scan flip-flops used in the circuit is large, but in the second half of the pattern, the number of scan flip-flops used is small.
[0019]
An example of a method of performing a scan test using the scan test circuit of the present invention using the present feature will be described. In this method, as in the past, the first half of the test pattern generates a test pattern using all scan flips, and after the failure detection rate reaches a certain standard, the test pattern is only used for some scan chains. By performing the generation, the total test pattern is shortened.
[0020]
Further, a specific method will be described with reference to the flowchart in FIG. First, in S1, a plurality of scan chains are unified, and a test command using all scan flip-flops as shown in FIG. 6 is set. In S2, a scan test pattern is generated, and a failure detection rate is calculated. In S3, it is determined whether or not the failure detection rate has reached 95%. If the failure detection rate has not been achieved, the process returns to S1 to additionally generate a test pattern. When the failure detection rate becomes 95% or more, the process proceeds to S4. In S4, a test command for extracting a part of the scan chain to the outside as shown in FIGS. 4 and 5 is set. Also in S5, a scan test pattern is generated, and a failure detection rate is calculated. In S6, it is determined whether the failure detection rate is 99% or more. If the failure detection rate is not achieved, the process returns to S4, and a test pattern is additionally generated. The processing is completed when the failure detection rate exceeds 99%.
[0021]
The difference between the length of the test pattern generated by this method and the conventional method will be described with reference to FIG. In this example, it is assumed that the length of one scan chain when all the scan flip-flops are used is 900 steps, and the length of the scan chain when a part of the scan chains is used is 300 steps. In the conventional full scan test method, 900 steps are required in all scan tests, and 3600 steps are performed in four tests. On the other hand, when a test pattern is created in the example of the present invention, one cycle is required as a command reception cycle at the beginning of each test cycle. When a plurality of scan chains are connected, the test pattern cycle is 901 steps, and some scan chains are connected. When using, it is 301 steps. In FIG. 10, even if a test in which a plurality of scan chains are connected is performed twice, and then a test using a part of the scan chains is performed six times, the total number of test steps is 3608. Therefore, in the present method, it is possible to execute more test patterns in a shorter test step than in the related art.
[0022]
【The invention's effect】
According to the present invention, in a full scan design of an LSI, the configuration of the internal scan chain is changed at any time without increasing the number of test terminals, and the period of one scan shift operation is significantly shortened. It is possible to obtain a semiconductor test circuit and a test method thereof capable of greatly reducing the amount and shortening the full scan test time.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a scan test circuit according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of an example of a timing chart when a scan test circuit of the present invention is operated.
FIG. 3 is an explanatory diagram of an example of a test command according to the present invention.
FIG. 4 is a first diagram illustrating an example of a scan circuit structure.
FIG. 5 is a second diagram illustrating an example of a scan circuit structure.
FIG. 6 is a third diagram illustrating an example of a scan circuit structure.
FIG. 7 is a graph showing the relationship between the number of test patterns and the failure detection rate in a general full scan system.
FIG. 8 is a graph showing the relationship between the number of test patterns in a general full scan system and the number of required scan flip-flops in a circuit.
FIG. 9 is a flowchart illustrating an example of a scan test method according to the present invention.
FIG. 10 is a diagram showing the contents of a test pattern.
FIG. 11 illustrates a structure of a scan flip-flop.
FIG. 12 is a schematic circuit diagram of a general full scan design.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 LSI circuit 2 Function block 3 Scan flip-flop 4 Scan chain 5 Command analysis part 6 Command reception cycle judgment part 7 Scan input selection part 8 Scan output selection parts 9a, b, c Scan-in terminals 10a, b, c Scan-out terminals 11 Shift operation switching terminal 12 Clock terminal 100 Scan flip-flop 101 Flip-flop 102 Multiplexer 103 LSI circuit 104 Scan flip-flop 105 Combination circuit 106 Scan input terminal 107 Scan output terminal 108 Shift operation switching terminal 109 Clock terminal

Claims (6)

A circuit for performing a full scan test of an LSI by dividing the number of scan chains into a large number without being restricted by an external scan-in terminal and an external scan-out terminal,
A determination circuit that has an external scan-in terminal, an external scan-out terminal, a shift operation switching terminal, and a clock terminal for use in a scan test, and that determines a specific cycle when the shift operation is switched; and an external scan in a specific cycle when the shift operation is switched A semiconductor test circuit comprising: a selection circuit that selects an internal scan-in and an internal scan-out that are respectively connected to an external scan-in terminal and an external scan-out terminal based on command data of a signal input from an IN terminal. A function block unit including a plurality of flip-flops, a command reception cycle determination unit that outputs a reception signal event based on a shift operation switching signal input to a shift operation switching terminal and an external clock signal input to a clock terminal, a test signal, A command analysis unit that outputs a selection signal based on an external clock signal and a reception signal event; a scan input selection unit and a scan output that change the connection between the function block unit and an external scan-in terminal or an external scan-out terminal according to the selection signal The semiconductor test circuit according to claim 1, further comprising a selection unit. When connecting the internal scan-in and internal scan-out to the external scan-in terminal and external scan-out terminal, respectively connect the scan-in signal and scan-out signal of each scan chain to the external scan-in terminal or external scan-out terminal, respectively. The semiconductor test circuit according to claim 1, wherein In the specific cycle determined at the time of switching the shift operation, a signal input from the scan-in terminal is recognized as command data, and an internal scan-in that is not connected to the external scan-in terminal and the external scan-out terminal is recognized based on the command data. 2. The semiconductor test circuit according to claim 1, wherein the semiconductor test circuit is connected to a necessary circuit as needed. A method of performing a full scan test of an LSI by dividing the number of scan chains into a large number without being restricted by external terminals,
A specific cycle at the time of shift operation switching is determined, and an internal scan-in is connected to the external scan-in terminal and the external scan-out terminal based on command data of a signal input from the external scan-in terminal in the specific cycle at the time of shift operation switching. And selecting an internal scan-out. The first part of the test pattern generation is a circuit configuration that connects all scan flip-flops, obtains a certain failure detection rate, and thereafter, only a part of the scan flip-flops necessary to improve the failure detection rate 6. The semiconductor test method according to claim 5, wherein a fault detection rate is obtained by using a short test pattern.

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