JP2004226185A - Overcurrent detection circuit and its delay circuit - Google Patents

Overcurrent detection circuit and its delay circuit Download PDF

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Publication number
JP2004226185A
JP2004226185A JP2003013085A JP2003013085A JP2004226185A JP 2004226185 A JP2004226185 A JP 2004226185A JP 2003013085 A JP2003013085 A JP 2003013085A JP 2003013085 A JP2003013085 A JP 2003013085A JP 2004226185 A JP2004226185 A JP 2004226185A
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voltage
circuit
current
delay time
predetermined
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JP4221572B2 (en
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Osamu Kawagoe
治 川越
Yasuhiro Tokumaru
泰博 徳丸
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Mitsumi Electric Co Ltd
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Mitsumi Electric Co Ltd
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Priority to JP2003013085A priority Critical patent/JP4221572B2/en
Priority to KR1020030086619A priority patent/KR100975279B1/en
Priority to TW092136338A priority patent/TW200415835A/en
Priority to CNA2004100393401A priority patent/CN1518183A/en
Publication of JP2004226185A publication Critical patent/JP2004226185A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/04—Arrangements for preventing response to transient abnormal conditions, e.g. to lightning or to short duration over voltage or oscillations; Damping the influence of dc component by short circuits in ac networks
    • H02H1/043—Arrangements for preventing response to transient abnormal conditions, e.g. to lightning or to short duration over voltage or oscillations; Damping the influence of dc component by short circuits in ac networks to inrush currents
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an electric discharge control switch may have been broken due to the passage of a large current through the electric discharge control switch when a large current passes due to a short circuit etc. during the delay time of a delay circuit in an overcurrent detecting circuit provided with the delay circuit. <P>SOLUTION: In an overcurrent detecting circuit 20a having a delay circuit 25 for controlling the on-time of an electric discharge control switch 113, by generating continuous and analog changes in the delay time, the delay circuit 25 is capable of speedily turning the electric discharge control switch 113 into an off-state correspondingly to a sudden change in the state of the electric discharge control switch 113. Thereby, it is possible to prevent a large current from passing the electric discharge control switch 113 for a long time and prevent the electric discharge control switch 113 from being broken. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、リチウムイオン電池等、充電可能な二次電池を保護する二次電池保護回路に関し、特に、当該二次電池保護回路に使用される遅延回路に関する。
【０００２】
【従来の技術】
一般に、この種の二次電池保護回路は、正極端子及び負極端子を備えた電池ユニット（電池パック）内に二次電池と共に収容され、使用の際には、電池ユニットの正極端子と負極端子との間には、カメラ等のデバイスが負荷として接続される。このように、電池ユニットに負荷が接続された場合、電池ユニット内の二次電池は、放電状態となり、負荷を駆動、動作させる。他方、電池ユニット内の二次電池を充電する際には、電池ユニットの正極端子と負極端子との間に充電器が接続されて、二次電池は充電状態となる。
【０００３】
ここで、電池ユニット内に収容される二次電池には、ニッケル−カドミウム電池、ニッケル−水銀電池、リチウムイオン電池等、種々の電池が各種のデバイスに応じて接続される。このうち、ニッケル−カドミウム電池及びニッケル水銀電池は、電池容量が０になるまで使った後に充電しないと、即ち、浅い放電・充電を繰り返すと、電池能力が低下すると言う特性を有している。このように、浅い放電・充電を繰り返すことによって電池能力が低下する効果をメモリー効果と呼ぶ。
【０００４】
一方、リチウムイオン電池は、上記したメモリー効果を持たず、二次電池として理想的であるが、放電しすぎて電池電圧が所定電圧よりも低くなってしまうと、電池の構成物質が変質し、過放電状態となって電池寿命が短くなってしまう。また、リチウムイオン電池では、充電器による充電中、満充電状態になっても電池電圧は上昇し続け、過充電状態になることがある。このように、過充電状態になると、リチウムイオン電池では、リチウム金属の析出により電極間ショートが発生するおそれがある。更に、リチウムイオン電池において正極端子と負極端子との間がショート状態になると、大きな放電電流が流れ、過電流状態になることがある。
【０００５】
電池ユニットに二次電池と共に組み込まれる二次電池保護回路、特に、リチウムイオン電池用の二次電池保護回路は、前述した過充電状態、過放電状態、及び、過電流状態を検出して、これらの状態がそれぞれ検出されると、充電電流及び放電電流を遮断することによって、二次電池を保護する機能を備えている。このため、二次電池保護回路は、過充電検出回路、過放電検出回路、及び、過電流検出回路を備えている。
【０００６】
一方、充電中或いは放電中に、短時間の間、電流或いは電圧が何らかの原因により一時的に大きく変動することがある。前述した短時間内の一時的な変動が生じても、実際には、過充電、過放電、或いは、過電流状態にはなっていないから、このような短時間における電流、電圧の変動によって、過充電検出回路、過放電検出回路、及び、過電流検出回路を不動作状態にしておく必要がある。このため、これら過充電検出回路、過放電検出回路、及び、過電流検出回路には、電流、電圧の短時間変動によっては保護動作を行わないようにするために、一定時間だけ、各検出回路を不動作状態、即ち、不感応状態にする不感応時間設定回路がそれぞれ設けられている。具体的には、これら不感応時間設定回路として、遅延回路が設けられており、上記した一定時間は遅延回路の遅延時間として設定されている。
【０００７】
これら二次電池保護回路の過充電検出回路、過放電検出回路、及び、過電流検出回路のうち、過電流検出回路に使用される遅延回路として、特願２００２−３０９４７０明細書に記載された遅延回路がある。提案された遅延回路は、過電流が検出されると、クロック発振器からのクロック信号のカウントを開始し、クロック信号を所定の値までカウントし、所定の値までカウントされても過電流が検出されていると、有効検出信号を出力する構成を有している。この場合、過電流検出回路は、電流ユニットに負荷として接続されるデバイスに流れる負荷電流を検出する抵抗に接続され、当該抵抗の両端電圧を過電流検出回路によって検出することにより、遅延時間を制御している。この構成では、過電流の検出信号に瞬時的な変動があっても、正確に所定の値までカウントすることができる。
【０００８】
図６を参照すると、従来、リチウムイオン電池等の二次電池を含む電池ユニット１１内に設けられる過電流検出回路１０の他の例が示されている。図示された電池ユニット１１は、出力端子として正極端子１０１と負極端子１０２とを備えており、当該正極端子１０１と負極端子１０２間には、放電時にカメラ等の負荷が接続され、充電時に充電器が接続される。
【０００９】
図示された電池ユニット１１は、過電流検出回路１０、リチウムイオン電池等の二次電池１１１、電流検出抵抗１１２、及び、放電制御スイッチ１１３のみによって特徴付けられているが、実際には、過電流検出回路１０のほかに、図示されない過放電検出回路及び過充電検出回路が電池ユニット１１内には設けられている。これら過充電検出回路及び過放電検出回路は説明を簡略化するために、図６では省略されている。
【００１０】
電池ユニット１１の正極端子１０１には、放電制御スイッチ１１３を構成するＰチャンネルＦＥＴのドレインが接続され、そのソースには、二次電池１１１のカソードが接続されている。一方、二次電池１１１のアノードと、負極端子１０２との間には、電流検出抵抗１１２が接続されており、当該電流検出抵抗１１２の両端には、過電流検出回路１０が接続されている。
【００１１】
具体的に説明すると、過電流検出回路１０は過電流検出部２０と、所定の遅延時間を設定された遅延回路２１とによって構成されており、過電流検出部２０は電流検出抵抗１１２の両端に接続され、当該電流検出抵抗１１２に流れる電流によって生じる電圧降下を過電流検出部２０によって検出している。
【００１２】
過電流検出部２０は、閾値電圧を基準電圧として設定された電圧比較器を有し、この電圧比較器において、電流検出抵抗１１２の両端における電圧降下を基準電圧と比較する。この例では、基準電圧よりも電流検出抵抗１１２の両端電圧降下が小さい場合、電圧比較器は論理“０”レベルの出力信号を遅延回路２１に出力し、他方、基準電圧よりも電流検出抵抗１１２の両端電圧降下が大きくなると、過電流であると判定し、論理“１”レベルの出力信号を遅延回路２１に出力する。
【００１３】
ここで、電池ユニット１１の正極端子１０１と負極端子１０２間に、負荷が接続され、二次電池１１１が放電している状態にあるものとする。この状態では、過電流検出部２０は、論理“０”レベルの出力信号を遅延回路２１に出力しており、放電制御スイッチ１１３を構成しているＰチャンネルＦＥＴには、遅延回路２１から低レベル信号が供給されている。この結果、過電流が検出されない状態では、放電制御スイッチ１１３はオン状態にある。
【００１４】
一方、負荷に流れる電流が大きくなり、電流検出抵抗１１２の両端における電圧降下が閾値を超えると、過電流検出部２０は高レベル信号を出力信号として遅延回路２１に出力する。遅延回路２１は、所定の遅延時間の経過した時点においても、過電流検出部２０から高レベル信号が与えられている場合、高レベル信号を放電制御スイッチ１１３に出力することにより、放電制御スイッチ１１３をオフ状態にし、この結果、放電は停止する。
【００１５】
このように、遅延回路２１は、過電流状態が所定の遅延時間継続したことを監視する動作を行っている。この遅延回路２１を設けることにより、所定の遅延時間に満たない時間だけ、一時的に過電流状態が生じても、遅延回路２１は、高レベル信号を放電制御スイッチ１１３に出力しない。言い換えれば、過電流状態が所定の遅延時間継続した場合にのみ、放電制御スイッチ１１３は、オフ状態となる。この構成では、過電流状態が短時間継続しても、放電制御スイッチ１１３はオフ状態とはならないため、一時的に生じる過電流が誤って検出されるのを防止できる。
【００１６】
【特許文献１】
特願２００２−３０９４７０明細書
【００１７】
【発明が解決しようとする課題】
この種、電池ユニットに負荷として接続されるデバイス負荷は、デバイスの動作時と不動作時との間で大きく変動し、この結果、放電状態で負荷に流れる電流も大きく変動する傾向にあり、極端な場合、正極端子と負極端子との間がショートすることもある。
【００１８】
図６に示された電流検出抵抗１１２の抵抗値は、電流検出抵抗１１２による損失が抑えられているため、放電制御スイッチ１１３による損失が問題になるものと予測される。他方、図６に示されている遅延回路における遅延時間は、負荷電流の大小に関係無く一定である。このように、一定の遅延時間を有する遅延回路を使用した場合、一定の遅延時間内には、大きな負荷電流が、瞬間的に、電池ユニットの放電制御スイッチ１１３を構成するＦＥＴに流れる。この結果、当該スイッチ１１３を構成するＦＥＴに悪影響が生じてしまい、場合によってはＦＥＴの破壊を招くこともある。
【００１９】
上記した点を図７を参照して、具体的に説明する。図７には、図６に示された過電流検出回路１０の特性が示されており、図７において、横軸は、電流検出抵抗１１２に流れる電流Ｉをあらわし、縦軸は遅延回路２１における遅延時間Ｔをあらわしている。図からも明らかな通り、電流検出抵抗１１２に流れる電流Ｉが設定電流レベルＩｄを超えると、遅延回路２１は一定の遅延時間Ｔｄだけ、過電流検出部２０の出力を遅延させる特性を有している。尚、電流検出抵抗１１２に流れる電流Ｉは、実際には、過電流検出部２０において、電流検出抵抗１１２の両端電圧に変換され、当該両端電圧が閾値電圧と比較される。
【００２０】
図示された特性を有する過電流検出回路１０を使用した場合、電流検出抵抗１１２に一時的に設定電流レベルＩｄを超える電流が流れ、一定の遅延時間内に、元の正常な電流レベルに戻ると、放電制御スイッチ１１３は、遅延回路２１の出力により一定の遅延時間内においてオン状態に維持されている。このため、放電制御スイッチ１１３には大きな負荷電流が流れ、この結果、放電制御スイッチ１１３を構成するＦＥＴは破壊してしまうことがある。
【００２１】
一方、前述した特願２００２−３０９４７０明細書に記載された遅延回路のように、クロック発振器からのクロックをカウンタによりカウントする形式の遅延回路では、カウンタのカウント値を複数設定しておくことにより、不感応時間をディジタル的に段階的に変化させ得るものと思われる。しかしながら、このように、ディジタル的に不感応時間を変化させる遅延回路では、負荷電流に応じてリアルタイムに遅延時間を変化させることはできない。このため、ショート等のように、急激に負荷電流が変化した場合、前述した遅延回路は、この変化に追随できず、放電制御スイッチを構成する素子の破壊を防止できない。
【００２２】
本発明の目的は、瞬間的に、且つ、急激に電流が変化した場合にも、電池ユニット内の内部素子の破壊を防止できる過電流検出回路を提供することである。
【００２３】
本発明の他の目的は、急激な電流変動が生じても、放電制御スイッチの破壊を防止できる過電流検出回路を備えた電池ユニットを提供することである。
【００２４】
本発明の更に他の目的は、負荷電流に応じて遅延特性を連続的に変化させることができる遅延回路を提供することである。
【００２５】
【課題を解決するための手段】
本発明の第１の態様によれば、一対の入出力端子、二次電池、前記一対の入出力端子の一方の端子と前記二次電池の一方の電極との間に接続された放電制御スイッチ、前記一対の入出力端子の他方の端子と前記二次電池の他方の電極との間に接続された電流検出抵抗を備えた電池ユニットに設けられた過電流検出回路において、前記電流検出抵抗の両端に接続され、当該電流検出抵抗の両端電圧を所定の基準電圧と比較し、比較結果を出力する過電流検出部と、前記電流検出抵抗の両端電圧が前記基準電圧を超えたことをあらわす信号が前記比較結果として与えられると、当該比較結果を所定の遅延時間だけ遅延させ、当該所定の遅延時間以上、前記両端電圧が前記基準電圧を超えている場合、前記放電スイッチをオフにする遅延回路とを有し、前記遅延回路は、前記放電制御スイッチのオン抵抗の両端で生じる電圧降下を監視する監視手段と、前記オン抵抗に流れる電流による前記オン抵抗間の電圧降下が所定の電圧以上になると、前記オン抵抗に流れる電流が大きくなるにしたがって遅延時間が前記所定の遅延時間からアナログ的に減少する特性を有するアナログ遅延部を有することを特徴とする過電流検出回路が得られる。
【００２６】
本発明の第２の態様によれば、前記監視手段は、前記放電制御スイッチの両端に接続され、前記オン抵抗による電圧降下に応じた電流を出力する差動回路によって構成され、他方、前記アナログ遅延部は、前記差動回路からの電流によって、電流制御される電流源と、該電流源に直列に接続されたキャパシタと、当該電流源とキャパシタとの共通接続点における電圧を予め定められた電圧と比較する比較回路とを有することを特徴とする過電流検出回路が得られる。
【００２７】
本発明の第３の態様によれば、前記放電スイッチはＦＥＴによって構成されていることを特徴とする過電流検出回路が得られる。
【００２８】
本発明の第４の態様によれば、一対の入出力端子、二次電池、前記一対の入出力端子の一方の端子と前記二次電池の一方の電極との間に接続された放電制御スイッチ、前記一対の入出力端子の他方の端子と前記二次電池の他方の電極との間に接続された電流検出抵抗と、前記電流検出抵抗の両端に接続され、当該電流検出抵抗の両端電圧を所定の基準電圧と比較し、比較結果を出力する過電流検出部と、前記電流検出抵抗の両端電圧が前記基準電圧を超えたことをあらわす信号が前記比較結果として与えられると、当該比較結果を所定の遅延時間だけ遅延させ、当該所定の遅延時間以上、前記両端電圧が前記基準電圧を超えている場合、前記放電スイッチをオフにする遅延回路とを有し、前記遅延回路は、前記放電制御スイッチのオン抵抗の両端で生じる電圧降下を監視する監視手段と、前記オン抵抗に流れる電流による前記オン抵抗間の電圧降下が所定の電圧以上になると、前記オン抵抗に流れる電流が大きくなるにしたがって遅延時間が前記所定の遅延時間からアナログ的に減少する特性を有するアナログ遅延部を有することを特徴とする電池ユニットが得られる。
【００２９】
本発明の第５の態様によれば、一対の入出力端子、二次電池、前記一対の入出力端子の一方の端子と前記二次電池の一方の電極との間に接続された放電制御スイッチ、前記一対の入出力端子の他方の端子と前記二次電池の他方の電極との間に接続された電流検出抵抗を備えた電池ユニットに設けられた過電流検出回路において、前記電流検出抵抗の両端に接続され、当該電流検出抵抗の両端電圧を所定の基準電圧と比較し、比較結果を出力する過電流検出部と、前記電流検出抵抗の両端電圧が前記基準電圧を超えたことをあらわす信号が前記比較結果として与えられると、当該比較結果を所定の遅延時間だけ遅延させ、当該所定の遅延時間以上、前記両端電圧が前記基準電圧を超えている場合、前記放電スイッチをオフにする遅延回路とを有し、前記遅延回路は、前記電流検出抵抗の両端で生じる電圧降下を監視する監視手段と、前記電流検出抵抗に流れる電流による前記電圧降下が設定された電圧以上になると、前記電流検出抵抗に流れる電流が大きくなるにしたがって遅延時間が前記所定の遅延時間からアナログ的に減少する特性を有するアナログ遅延部を有することを特徴とする過電流検出回路が得られる。
【００３０】
本発明の第６の態様によれば、所定の抵抗素子両端における電圧降下に応じた電流を供給する電流源と、当該電流源に直列に接続されたキャパシタと、当該電流源とキャパシタとの共通接続点における電圧を予め定められた電圧と比較する比較回路とを有し、遅延時間をアナログ的に可変できることを特徴とする遅延回路が得られる。
【００３１】
【発明の実施の形態】
図１を参照すると、本発明の一実施形態に係る電池ユニット１１ａの概略構成が示されている。図１に示された電池ユニット１１ａは、過電流検出回路２０ａとして、放電制御スイッチ１１３のオン抵抗による電圧降下を検出する機能を有する電圧検出機能付遅延回路２５を使用している点で、図６の過電流検出回路２０と相違している。図１に示されているように、電圧検出機能付遅延回路２５は、ＰチャンネルＦＥＴによって構成される放電制御スイッチ１１３の入出力端子（即ち、ＰチャネルＦＥＴのソース、ドレイン）に接続され、当該ＰチャンネルＦＥＴのオン抵抗による電圧降下を検出し、当該電圧降下に応じて遅延時間をアナログ的に、即ち、連続的に変化させる特性を備えている。
【００３２】
図２をも参照すると、図１に示された電圧検出機能付遅延回路２５の特性が示されており、横軸は放電制御スイッチ１１３に流れる電流Ｉ、縦軸は電圧検出機能付遅延回路２５の遅延時間をあらわしている。図２からも明らかな通り、放電制御スイッチ１１３に流れる電流Ｉが設定された電流レベルＩｆを超えると、当該遅延回路２５は過電流検出部２０ａの出力を所定の遅延時間Ｔｄだけ遅延させる状態になる。更に、電流Ｉが大きくなると、電圧検出機能付遅延回路２５の遅延時間は、電流Ｉレベルの増加に応じて、ＴｄからＴａまで、アナログ的に、即ち、連続的に短くなる。このような特性を有する電圧検出機能付遅延回路２５を使用することにより、短時間に瞬間的に大きな電流Ｉが放電制御スイッチ１１３に流れた場合、極めて短い遅延時間後、放電制御スイッチ１１３をオフ状態にすることができ、この結果、放電スイッチ１１３を構成するＦＥＴの破壊を防止できる。
【００３３】
図１に示された放電制御スイッチ１１３を構成するＰチャンネルＦＥＴは、正極端子１０１に接続されたドレイン、二次電池１１１のカソードに接続されたソース、及び、電圧検出機能付遅延回路２５に接続されたゲートを備え、電流検出抵抗１１２は負極端子１０２に接続されている。
【００３４】
一方、放電制御スイッチ１１３をＮチャンネルＦＥＴで構成する場合、負極端子１０２にソースを接続し、ドレインを二次電池１１１のアノードに接続するように構成すると共に、ゲートに対して図１とは逆極性の信号を与えるように構成すれば良い。また、この場合、電流検出抵抗１１２は、正極端子１０１と二次電池１１１のカソードとの間に接続される。この構成自体は知られているので、ここでは、詳述しない。
【００３５】
次に、図３を参照して、図１に示された電圧検出機能付遅延回路２５の具体的構成について説明する。図示された電圧検出機能付遅延回路２５は、ＰチャンネルＦＥＴによって構成された放電制御スイッチ１１３の入出力端子間のオン抵抗による電圧降下を監視する監視回路として、差動回路２５１を有している。即ち、差動回路２５１はＰチャンネルＦＥＴのソース、ドレインとの間に接続され、当該ＦＥＴのオン抵抗を流れる電流によって生じる電圧降下を監視し、監視された電圧を電流に変換して、遅延部に出力している。図３に示された遅延部は、図２に示すようなアナログ的な遅延特性を有しているため、ここでは、アナログ遅延部と呼ぶ。ここで、ＰチャンネルＦＥＴのソース及びドレインの電圧をそれぞれＶｃｃ及びＣＳとする。
【００３６】
図示されたアナログ遅延部は、差動回路２５１から与えられる電流によって電流制御される電流源２５２を備えている。当該電流源２５２には、直列にキャパシタ２５３の一端が接続され、キャパシタ２５３の他端は接地されている。また、電流源２５２とキャパシタ２５３との共通接続点は、比較回路２５４の一方の入力端子に接続されて、当該比較回路２５４の他方の入力端子には、予め定められた電圧を供給する電圧源２５５が接続されている。この構成では、電流源２５２からの電流によってキャパシタ２５３が充電され、このため、比較回路２５４の一方の入力端子の電圧は、電流源２５２の電流に応じて上昇する。
【００３７】
ここで、放電制御スイッチ１１３を流れる電流が急激に増加した場合、差動回路２５１の電流も急激に増加し、結果的に電流源２５２からキャパシタ２５３に供給される電流も急激に増加する。したがって、キャパシタ２５３の電圧は、急速に上昇して電圧源２５５の電圧を短時間で超えてしまい、比較回路２５４からは、短時間の間に出力信号が出力される。
【００３８】
比較回路２５４の出力信号及び過電流検出部の出力信号に応じて、放電制御スイッチ１１３をオフ状態にするように構成しておけば、当該放電制御スイッチ１１３は短時間の間に、オン状態からオフ状態に切り替えられ、短い遅延時間を有する遅延回路を構成できる。
【００３９】
一方、放電制御スイッチ１１３を流れる電流が緩慢に増加した場合、差動回路２５１の電流もゆっくり増加し、電流源２５２からキャパシタ２５３に供給される電流も徐徐に増加する。したがって、キャパシタ２５３の電圧もゆっくり上昇するから、電圧源２５５に設定された電圧を超えるために比較的長い時間がかかる。この結果として、図２に示すような電流Ｉ、遅延時間Ｔ特性が得られる。
【００４０】
図４を参照すると、図３に示された電流源２５２の具体的な構成例が示されている。図４に示されているように、電流源２５２は、差動回路２５１からの出力に応じた電流を供給する電流源回路３１と、ＰＮＰトランジスタＴｒ１、Ｔｒ２、Ｔｒ３によって構成された第１のカレントミラー回路、及び、ＮＰＮトランジスタＴｒ４、Ｔｒ５によって構成された第２のカレントミラー回路とを備えている。トランジスタＴｒ１、Ｔｒ２、及び、Ｔｒ３のエミッタには、それぞれ抵抗が接続され、当該抵抗を介して、Ｖｃｃ、ＣＳ、及び、Ｖｃｃの電圧が与えられている。
【００４１】
差動回路２５１からの出力信号に応じた電流が電流源回路３１から第１のカレントミラー回路に供給されると、トランジスタＴｒ１に流れる電流に比例した電流がトランジスタＴｒ２、Ｔｒ３に流れる。また、トランジスタＴｒ２、Ｔｒ３は第２のカレントミラー回路（Ｔｒ４、Ｔｒ５）に接続されているから、当該トランジスタＴｒ２、Ｔｒ３には互いに比例した電流が流れる。この結果、トランジスタＴｒ３とＴｒ５の共通接続点に接続されたキャパシタ２５３は、差動回路２５１の出力信号に対応した電流で充電される。
【００４２】
図５を参照して、本発明の他の実施形態に係る電池ユニット１１ｂを説明する。図示された電池ユニット１１ｂの過電流検出回路１０ｂは、図１と同様な構成を備えた過電流検出部２０ａと、当該過電流検出部２０ａに接続されると共に、電流検出抵抗１１２の両端に接続された電圧検出機能付遅延回路２５ａとを有している。このように、図示された電圧検出機能付遅延回路２５ａには、電流検出抵抗１１２の両端電圧も与えられる点以外、図１に示された電池ユニット１１ａと同様な構成を備えている。図５に示された電圧検出機能付遅延回路２５ａは、図３に示された回路２５と同様な構成を備え、差動回路２５１の２つの入力端子を電流検出抵抗１１２の両端に接続すれば良い。
【００４３】
上記した実施の形態は、主にリチウムイオン電池を二次電池として使用した場合について説明したが、本発明は何等これに限定されることなく、ニッケル−カドミウム電池、ニッケル−水銀電池等にも適用できる。
【００４４】
【発明の効果】
本発明によれば、ＦＥＴ或いは電流検出抵抗の両端における電圧降下に応じて、遅延時間をアナログ的に可変することにより、極めて短時間内に生じる急激な電流変化によって、ＦＥＴに大電流が流れるのを防止することができ、ディジタル的に遅延時間を変化させる場合に比較して、過電流を高速で検出して、ＦＥＴの破壊を防止できると言う利点がある。
【図面の簡単な説明】
【図１】本発明の一実施形態に係る電池ユニットの構成を説明するためのブロック図である。
【図２】図１に示された電池ユニットに含まれる電圧検出機能付遅延回路の特性を示す図である。
【図３】図１に示された電圧検出機能付遅延回路の一部の構成を具体的に示す回路図である。
【図４】図３に示された回路の一部を詳細に説明する回路図である。
【図５】本発明の他の実施形態に係る電池ユニットの構成を示すブロック図である。
【図６】従来の電池ユニットの構成を説明するブロック図である。
【図７】図６に示された過電流検出回路の特性を説明する図である。
【符号の説明】
１０、１０ａ、１０ｂ 過電流検出回路
１１、１１ａ、１１ｂ 電池ユニット
１１１ 二次電池
１１２ 電流検出抵抗
１１３ 放電制御スイッチ
１０１ 正極端子
１０２ 負極端子
２０ 過電流検出部
２１ 遅延回路
２５、２５ａ 電圧検出機能付遅延回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a secondary battery protection circuit for protecting a rechargeable secondary battery such as a lithium ion battery, and more particularly, to a delay circuit used in the secondary battery protection circuit.
[0002]
[Prior art]
Generally, this type of secondary battery protection circuit is housed together with a secondary battery in a battery unit (battery pack) having a positive terminal and a negative terminal, and when used, the positive terminal and the negative terminal of the battery unit are connected to each other. Between them, a device such as a camera is connected as a load. As described above, when the load is connected to the battery unit, the secondary battery in the battery unit is in a discharged state, and drives and operates the load. On the other hand, when charging the secondary battery in the battery unit, a charger is connected between the positive terminal and the negative terminal of the battery unit, and the secondary battery is charged.
[0003]
Here, various batteries such as a nickel-cadmium battery, a nickel-mercury battery, and a lithium ion battery are connected to the secondary battery housed in the battery unit according to various devices. Among them, the nickel-cadmium battery and the nickel mercury battery have a characteristic that if they are not charged after being used until the battery capacity becomes zero, that is, if the shallow discharge / charge is repeated, the battery capacity is reduced. The effect of reducing the battery capacity by repeating shallow discharge / charge in this manner is called a memory effect.
[0004]
On the other hand, a lithium ion battery does not have the above-mentioned memory effect, and is ideal as a secondary battery.However, if the battery voltage becomes lower than a predetermined voltage due to excessive discharge, the constituent materials of the battery deteriorate, The battery is over-discharged and the life of the battery is shortened. In addition, in a lithium ion battery, the battery voltage continues to increase even when the battery is fully charged during charging by the charger, and may be in an overcharged state. As described above, when the battery is overcharged, in a lithium ion battery, a short circuit between electrodes may occur due to deposition of lithium metal. Furthermore, when a short circuit occurs between the positive electrode terminal and the negative electrode terminal in a lithium ion battery, a large discharge current flows, which may cause an overcurrent state.
[0005]
The secondary battery protection circuit incorporated in the battery unit together with the secondary battery, in particular, the secondary battery protection circuit for a lithium ion battery detects the above-described overcharge state, overdischarge state, and overcurrent state, and When each of the above conditions is detected, the charge current and the discharge current are cut off, thereby protecting the secondary battery. For this reason, the secondary battery protection circuit includes an overcharge detection circuit, an overdischarge detection circuit, and an overcurrent detection circuit.
[0006]
On the other hand, during charging or discharging, the current or voltage may fluctuate temporarily for some reason for a short time. Even if the above-mentioned temporary fluctuation occurs within a short period of time, in fact, overcharging, overdischarging, or overcurrent is not in progress. It is necessary to keep the overcharge detection circuit, overdischarge detection circuit, and overcurrent detection circuit inactive. For this reason, the overcharge detection circuit, the overdischarge detection circuit, and the overcurrent detection circuit are provided with each detection circuit only for a certain period of time in order to prevent the protection operation from being performed due to short-term fluctuations in current and voltage. Are set to an inactive state, that is, an insensitive state. Specifically, a delay circuit is provided as the insensitive time setting circuit, and the above-mentioned fixed time is set as a delay time of the delay circuit.
[0007]
Among the overcharge detection circuit, overdischarge detection circuit, and overcurrent detection circuit of the secondary battery protection circuit, a delay circuit described in Japanese Patent Application No. 2002-309470 is used as a delay circuit used in the overcurrent detection circuit. There is a circuit. The proposed delay circuit starts counting a clock signal from a clock oscillator when an overcurrent is detected, counts the clock signal to a predetermined value, and detects an overcurrent even when the clock signal is counted to a predetermined value. And outputs a valid detection signal. In this case, the overcurrent detection circuit is connected to a resistor that detects a load current flowing to a device connected as a load to the current unit, and controls a delay time by detecting a voltage across the resistor by the overcurrent detection circuit. are doing. With this configuration, even if there is an instantaneous variation in the overcurrent detection signal, it is possible to accurately count to a predetermined value.
[0008]
Referring to FIG. 6, another example of an overcurrent detection circuit 10 conventionally provided in a battery unit 11 including a secondary battery such as a lithium ion battery is shown. The illustrated battery unit 11 includes a positive terminal 101 and a negative terminal 102 as output terminals. A load such as a camera is connected between the positive terminal 101 and the negative terminal 102 during discharging, and a charger is connected during charging. Is connected.
[0009]
The illustrated battery unit 11 is characterized only by an overcurrent detection circuit 10, a secondary battery 111 such as a lithium-ion battery, a current detection resistor 112, and a discharge control switch 113. In addition to the detection circuit 10, an overdischarge detection circuit and an overcharge detection circuit (not shown) are provided in the battery unit 11. These overcharge detection circuit and overdischarge detection circuit are omitted in FIG. 6 to simplify the description.
[0010]
The drain of a P-channel FET constituting the discharge control switch 113 is connected to the positive terminal 101 of the battery unit 11, and the cathode of the secondary battery 111 is connected to its source. On the other hand, a current detection resistor 112 is connected between the anode of the secondary battery 111 and the negative electrode terminal 102, and the overcurrent detection circuit 10 is connected to both ends of the current detection resistor 112.
[0011]
More specifically, the overcurrent detection circuit 10 includes an overcurrent detection unit 20 and a delay circuit 21 in which a predetermined delay time has been set. The overcurrent detection unit 20 detects the voltage drop caused by the current flowing through the connected current detection resistor 112.
[0012]
The overcurrent detection unit 20 includes a voltage comparator having a threshold voltage set as a reference voltage, and compares a voltage drop across the current detection resistor 112 with the reference voltage in the voltage comparator. In this example, when the voltage drop across the current detection resistor 112 is smaller than the reference voltage, the voltage comparator outputs a logic “0” level output signal to the delay circuit 21 while the current detection resistor 112 is smaller than the reference voltage. When the voltage drop between both ends increases, it is determined that an overcurrent has occurred, and an output signal of a logic “1” level is output to the delay circuit 21.
[0013]
Here, it is assumed that a load is connected between the positive terminal 101 and the negative terminal 102 of the battery unit 11 and the secondary battery 111 is in a discharged state. In this state, the overcurrent detection unit 20 outputs an output signal of a logic “0” level to the delay circuit 21, and the P-channel FET constituting the discharge control switch 113 receives the low level signal from the delay circuit 21. A signal is being supplied. As a result, when no overcurrent is detected, the discharge control switch 113 is on.
[0014]
On the other hand, when the current flowing through the load increases and the voltage drop across the current detection resistor 112 exceeds the threshold, the overcurrent detection unit 20 outputs a high-level signal as an output signal to the delay circuit 21. The delay circuit 21 outputs the high-level signal to the discharge control switch 113 even when the predetermined delay time has elapsed, when the high-level signal is given from the overcurrent detection unit 20, and thereby the discharge control switch 113 Is turned off, and as a result, the discharge stops.
[0015]
Thus, the delay circuit 21 performs an operation of monitoring that the overcurrent state has continued for a predetermined delay time. By providing the delay circuit 21, the delay circuit 21 does not output a high-level signal to the discharge control switch 113 even if an overcurrent state occurs temporarily for a time shorter than a predetermined delay time. In other words, the discharge control switch 113 is turned off only when the overcurrent state continues for a predetermined delay time. With this configuration, even if the overcurrent state continues for a short period of time, the discharge control switch 113 does not enter the off state, so that erroneous detection of the temporarily generated overcurrent can be prevented.
[0016]
[Patent Document 1]
Japanese Patent Application No. 2002-309470
[Problems to be solved by the invention]
In this type, the device load connected as a load to the battery unit fluctuates greatly between the operation and non-operation of the device, and as a result, the current flowing to the load in the discharge state also tends to fluctuate greatly, In such a case, a short circuit may occur between the positive terminal and the negative terminal.
[0018]
In the resistance value of the current detection resistor 112 shown in FIG. 6, since the loss due to the current detection resistor 112 is suppressed, the loss due to the discharge control switch 113 is expected to be a problem. On the other hand, the delay time in the delay circuit shown in FIG. 6 is constant regardless of the magnitude of the load current. As described above, when a delay circuit having a fixed delay time is used, a large load current instantaneously flows through the FET constituting the discharge control switch 113 of the battery unit within the fixed delay time. As a result, the FET constituting the switch 113 is adversely affected, and in some cases, the FET may be destroyed.
[0019]
The above points will be specifically described with reference to FIG. 7 shows the characteristics of the overcurrent detection circuit 10 shown in FIG. 6. In FIG. 7, the horizontal axis represents the current I flowing through the current detection resistor 112, and the vertical axis represents the current in the delay circuit 21. The delay time T is shown. As is clear from the figure, when the current I flowing through the current detection resistor 112 exceeds the set current level Id, the delay circuit 21 has a characteristic of delaying the output of the overcurrent detection unit 20 by a fixed delay time Td. I have. The current I flowing through the current detection resistor 112 is actually converted into a voltage across the current detection resistor 112 in the overcurrent detection unit 20, and the voltage across the current detection resistor 112 is compared with a threshold voltage.
[0020]
When the overcurrent detection circuit 10 having the illustrated characteristics is used, a current exceeding the set current level Id temporarily flows through the current detection resistor 112, and returns to the original normal current level within a certain delay time. The discharge control switch 113 is maintained in an on state within a fixed delay time by the output of the delay circuit 21. For this reason, a large load current flows through the discharge control switch 113, and as a result, the FET constituting the discharge control switch 113 may be broken.
[0021]
On the other hand, in a delay circuit in which a clock from a clock oscillator is counted by a counter, such as the delay circuit described in the specification of Japanese Patent Application No. 2002-309470, by setting a plurality of count values of the counter, It seems that the dead time can be changed stepwise digitally. However, such a delay circuit that digitally changes the insensitive time cannot change the delay time in real time according to the load current. Therefore, when the load current changes abruptly, for example, due to a short circuit, the above-described delay circuit cannot follow the change and cannot prevent the elements constituting the discharge control switch from being destroyed.
[0022]
It is an object of the present invention to provide an overcurrent detection circuit that can prevent the destruction of an internal element in a battery unit even when the current changes instantaneously and rapidly.
[0023]
Another object of the present invention is to provide a battery unit provided with an overcurrent detection circuit capable of preventing the discharge control switch from being destroyed even when a sudden current fluctuation occurs.
[0024]
Still another object of the present invention is to provide a delay circuit capable of continuously changing delay characteristics according to a load current.
[0025]
[Means for Solving the Problems]
According to the first aspect of the present invention, a pair of input / output terminals, a secondary battery, and a discharge control switch connected between one terminal of the pair of input / output terminals and one electrode of the secondary battery An overcurrent detection circuit provided in a battery unit having a current detection resistor connected between the other terminal of the pair of input / output terminals and the other electrode of the secondary battery; An overcurrent detection unit connected to both ends and comparing the voltage across the current detection resistor with a predetermined reference voltage and outputting a comparison result; and a signal indicating that the voltage across the current detection resistor exceeds the reference voltage. Is given as the comparison result, the comparison result is delayed by a predetermined delay time, and the delay circuit that turns off the discharge switch when the voltage between both ends exceeds the reference voltage for the predetermined delay time or more. With A monitoring unit that monitors a voltage drop generated between both ends of the on-resistance of the discharge control switch; and when the voltage drop between the on-resistance due to a current flowing through the on-resistance becomes equal to or higher than a predetermined voltage, An overcurrent detection circuit having an analog delay section having a characteristic that the delay time decreases in an analog manner from the predetermined delay time as the current flowing through the resistor increases is obtained.
[0026]
According to a second aspect of the present invention, the monitoring means is configured by a differential circuit connected to both ends of the discharge control switch and outputting a current corresponding to a voltage drop due to the on-resistance, The delay unit has a predetermined current source controlled by a current from the differential circuit, a capacitor connected in series to the current source, and a voltage at a common connection point between the current source and the capacitor. An overcurrent detection circuit having a comparison circuit for comparing with a voltage is obtained.
[0027]
According to a third aspect of the present invention, there is provided an overcurrent detection circuit, wherein the discharge switch is constituted by an FET.
[0028]
According to the fourth aspect of the present invention, a pair of input / output terminals, a secondary battery, a discharge control switch connected between one terminal of the pair of input / output terminals and one electrode of the secondary battery A current detection resistor connected between the other terminal of the pair of input / output terminals and the other electrode of the secondary battery, and connected to both ends of the current detection resistor, and a voltage across the current detection resistor. Compared with a predetermined reference voltage, an overcurrent detection unit that outputs a comparison result, and when a signal indicating that the voltage across the current detection resistor exceeds the reference voltage is given as the comparison result, the comparison result is displayed. A delay circuit that delays by a predetermined delay time, and when the voltage across the terminals exceeds the reference voltage for the predetermined delay time or more, the delay circuit turns off the discharge switch. Switch on resistance Monitoring means for monitoring a voltage drop occurring at the end; and when a voltage drop between the on-resistances due to a current flowing through the on-resistance becomes equal to or higher than a predetermined voltage, the delay time becomes longer as the current flowing through the on-resistance increases. A battery unit having an analog delay section having a characteristic of decreasing analogously from the delay time is obtained.
[0029]
According to the fifth aspect of the present invention, a pair of input / output terminals, a secondary battery, a discharge control switch connected between one terminal of the pair of input / output terminals and one electrode of the secondary battery An overcurrent detection circuit provided in a battery unit having a current detection resistor connected between the other terminal of the pair of input / output terminals and the other electrode of the secondary battery; An overcurrent detection unit connected to both ends and comparing the voltage across the current detection resistor with a predetermined reference voltage and outputting a comparison result; and a signal indicating that the voltage across the current detection resistor exceeds the reference voltage. Is given as the comparison result, the comparison result is delayed by a predetermined delay time, and the delay circuit that turns off the discharge switch when the voltage between both ends exceeds the reference voltage for the predetermined delay time or more. With A monitoring unit that monitors a voltage drop generated at both ends of the current detection resistor; and a current that flows through the current detection resistor when the voltage drop due to the current flowing through the current detection resistor becomes equal to or higher than a set voltage. An overcurrent detection circuit characterized by having an analog delay portion having a characteristic that the delay time decreases in an analog manner from the predetermined delay time as the delay time increases.
[0030]
According to the sixth aspect of the present invention, a current source for supplying a current according to a voltage drop across the predetermined resistance element, a capacitor connected in series to the current source, and a common source for the current source and the capacitor A delay circuit having a comparison circuit for comparing the voltage at the connection point with a predetermined voltage, wherein the delay time can be varied in an analog manner is obtained.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a schematic configuration of a battery unit 11a according to one embodiment of the present invention. The battery unit 11a shown in FIG. 1 uses a delay circuit 25 with a voltage detection function having a function of detecting a voltage drop due to the on-resistance of the discharge control switch 113 as an overcurrent detection circuit 20a. 6 is different from the overcurrent detection circuit 20 of FIG. As shown in FIG. 1, the delay circuit with voltage detection function 25 is connected to the input / output terminals of the discharge control switch 113 composed of a P-channel FET (that is, the source and drain of the P-channel FET). A voltage drop due to the ON resistance of the P-channel FET is detected, and the delay time is changed in an analog manner, that is, continuously, according to the voltage drop.
[0032]
FIG. 2 also shows the characteristics of the delay circuit 25 with a voltage detection function shown in FIG. 1, where the horizontal axis represents the current I flowing through the discharge control switch 113 and the vertical axis represents the delay circuit 25 with a voltage detection function. Represents the delay time. As is clear from FIG. 2, when the current I flowing through the discharge control switch 113 exceeds the set current level If, the delay circuit 25 shifts the output of the overcurrent detection unit 20a to a state delayed by a predetermined delay time Td. Become. Further, when the current I increases, the delay time of the delay circuit with voltage detection function 25 decreases from Td to Ta in an analog manner, that is, continuously, in accordance with the increase in the current I level. By using the delay circuit 25 with a voltage detection function having such characteristics, when a large current I flows to the discharge control switch 113 in a short time, the discharge control switch 113 is turned off after a very short delay time. As a result, the FET constituting the discharge switch 113 can be prevented from being destroyed.
[0033]
The P-channel FET constituting the discharge control switch 113 shown in FIG. 1 is connected to the drain connected to the positive terminal 101, the source connected to the cathode of the secondary battery 111, and the delay circuit with voltage detection function 25. The current detection resistor 112 is connected to the negative terminal 102.
[0034]
On the other hand, when the discharge control switch 113 is formed of an N-channel FET, the source is connected to the negative terminal 102, the drain is connected to the anode of the secondary battery 111, and the gate is opposite to that in FIG. What is necessary is just to comprise so that the signal of a polarity may be given. In this case, the current detection resistor 112 is connected between the positive terminal 101 and the cathode of the secondary battery 111. This configuration itself is known and will not be described in detail here.
[0035]
Next, a specific configuration of the delay circuit with a voltage detection function 25 shown in FIG. 1 will be described with reference to FIG. The illustrated delay circuit 25 with a voltage detection function includes a differential circuit 251 as a monitoring circuit that monitors a voltage drop due to an on-resistance between the input and output terminals of the discharge control switch 113 configured by a P-channel FET. . That is, the differential circuit 251 is connected between the source and the drain of the P-channel FET, monitors a voltage drop caused by a current flowing through the on-resistance of the FET, converts the monitored voltage into a current, and Output to The delay unit shown in FIG. 3 has an analog delay characteristic as shown in FIG. 2, and is therefore called an analog delay unit here. Here, the source and drain voltages of the P-channel FET are Vcc and CS, respectively.
[0036]
The illustrated analog delay unit includes a current source 252 that is current-controlled by a current supplied from the differential circuit 251. One end of a capacitor 253 is connected to the current source 252 in series, and the other end of the capacitor 253 is grounded. A common connection point between the current source 252 and the capacitor 253 is connected to one input terminal of the comparison circuit 254, and a voltage source for supplying a predetermined voltage to the other input terminal of the comparison circuit 254. 255 are connected. In this configuration, the capacitor 253 is charged by the current from the current source 252, and the voltage of one input terminal of the comparison circuit 254 rises according to the current of the current source 252.
[0037]
Here, when the current flowing through the discharge control switch 113 sharply increases, the current of the differential circuit 251 also sharply increases, and as a result, the current supplied from the current source 252 to the capacitor 253 also sharply increases. Therefore, the voltage of capacitor 253 rises rapidly and exceeds the voltage of voltage source 255 in a short time, and an output signal is output from comparison circuit 254 in a short time.
[0038]
If the discharge control switch 113 is configured to be turned off in accordance with the output signal of the comparison circuit 254 and the output signal of the overcurrent detection unit, the discharge control switch 113 can be turned on in a short time. A delay circuit that is switched to the off state and has a short delay time can be configured.
[0039]
On the other hand, when the current flowing through the discharge control switch 113 increases slowly, the current of the differential circuit 251 also increases slowly, and the current supplied from the current source 252 to the capacitor 253 also increases gradually. Therefore, since the voltage of the capacitor 253 also increases slowly, it takes a relatively long time to exceed the voltage set in the voltage source 255. As a result, current I and delay time T characteristics as shown in FIG. 2 are obtained.
[0040]
Referring to FIG. 4, a specific configuration example of the current source 252 shown in FIG. 3 is shown. As shown in FIG. 4, the current source 252 includes a current source circuit 31 that supplies a current according to the output from the differential circuit 251 and a first current source configured by PNP transistors Tr1, Tr2, and Tr3. A mirror circuit, and a second current mirror circuit including NPN transistors Tr4 and Tr5. A resistor is connected to each of the emitters of the transistors Tr1, Tr2, and Tr3, and the voltages Vcc, CS, and Vcc are given through the resistors.
[0041]
When a current corresponding to the output signal from the differential circuit 251 is supplied from the current source circuit 31 to the first current mirror circuit, a current proportional to the current flowing through the transistor Tr1 flows through the transistors Tr2 and Tr3. Since the transistors Tr2 and Tr3 are connected to the second current mirror circuits (Tr4 and Tr5), currents proportional to each other flow through the transistors Tr2 and Tr3. As a result, the capacitor 253 connected to the common connection point of the transistors Tr3 and Tr5 is charged with a current corresponding to the output signal of the differential circuit 251.
[0042]
A battery unit 11b according to another embodiment of the present invention will be described with reference to FIG. The overcurrent detection circuit 10b of the illustrated battery unit 11b is connected to the overcurrent detection unit 20a having the same configuration as that of FIG. 1 and to both ends of the current detection resistor 112 while being connected to the overcurrent detection unit 20a. And a delay circuit 25a with a voltage detection function. Thus, the illustrated delay circuit with voltage detection function 25a has a configuration similar to that of the battery unit 11a illustrated in FIG. 1 except that the voltage across the current detection resistor 112 is also provided. The delay circuit with voltage detection function 25a shown in FIG. 5 has a configuration similar to that of the circuit 25 shown in FIG. 3 and can be obtained by connecting two input terminals of the differential circuit 251 to both ends of the current detection resistor 112. good.
[0043]
Although the above-described embodiment mainly describes a case where a lithium ion battery is used as a secondary battery, the present invention is not limited to this, and is applicable to nickel-cadmium batteries, nickel-mercury batteries, and the like. it can.
[0044]
【The invention's effect】
According to the present invention, the delay time is varied in an analog manner according to the voltage drop across the FET or the current detection resistor, so that a large current flows through the FET due to a sudden current change occurring in a very short time. This is advantageous in that overcurrent can be detected at high speed and the destruction of the FET can be prevented as compared with a case where the delay time is digitally changed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a battery unit according to an embodiment of the present invention.
FIG. 2 is a diagram showing characteristics of a delay circuit with a voltage detection function included in the battery unit shown in FIG. 1;
FIG. 3 is a circuit diagram specifically showing a configuration of a part of the delay circuit with a voltage detection function shown in FIG. 1;
FIG. 4 is a circuit diagram illustrating in detail a part of the circuit shown in FIG. 3;
FIG. 5 is a block diagram showing a configuration of a battery unit according to another embodiment of the present invention.
FIG. 6 is a block diagram illustrating a configuration of a conventional battery unit.
7 is a diagram illustrating characteristics of the overcurrent detection circuit shown in FIG.
[Explanation of symbols]
10, 10a, 10b Overcurrent detection circuit 11, 11a, 11b Battery unit 111 Secondary battery 112 Current detection resistor 113 Discharge control switch 101 Positive terminal 102 Negative terminal 20 Overcurrent detection unit 21 Delay circuit 25, 25a Delay with voltage detection function circuit

Claims (6)

一対の入出力端子、二次電池、前記一対の入出力端子の一方の端子と前記二次電池の一方の電極との間に接続された放電制御スイッチ、前記一対の入出力端子の他方の端子と前記二次電池の他方の電極との間に接続された電流検出抵抗を備えた電池ユニットに設けられた過電流検出回路において、前記電流検出抵抗の両端に接続され、当該電流検出抵抗の両端電圧を所定の基準電圧と比較し、比較結果を出力する過電流検出部と、前記電流検出抵抗の両端電圧が前記基準電圧を超えたことをあらわす信号が前記比較結果として与えられると、当該比較結果を所定の遅延時間だけ遅延させ、当該所定の遅延時間以上、前記両端電圧が前記基準電圧を超えている場合、前記放電スイッチをオフにする遅延回路とを有し、
前記遅延回路は、前記放電制御スイッチのオン抵抗の両端で生じる電圧降下を監視する監視手段と、前記オン抵抗に流れる電流による前記オン抵抗間の電圧降下が所定の電圧以上になると、前記オン抵抗に流れる電流が大きくなるにしたがって遅延時間が前記所定の遅延時間からアナログ的に減少する特性を有するアナログ遅延部を有することを特徴とする過電流検出回路。A pair of input / output terminals, a secondary battery, a discharge control switch connected between one terminal of the pair of input / output terminals and one electrode of the secondary battery, and the other terminal of the pair of input / output terminals An overcurrent detection circuit provided in a battery unit having a current detection resistor connected between the current detection resistor and the other electrode of the secondary battery. An overcurrent detection unit that compares the voltage with a predetermined reference voltage and outputs a comparison result; and when a signal indicating that the voltage across the current detection resistor exceeds the reference voltage is given as the comparison result, the comparison is performed. Delaying the result by a predetermined delay time, the predetermined delay time or more, when the voltage across the terminals exceeds the reference voltage, a delay circuit that turns off the discharge switch,
The delay circuit includes a monitoring unit that monitors a voltage drop generated between both ends of the on-resistance of the discharge control switch. The on-resistance is controlled when a voltage drop between the on-resistance due to a current flowing through the on-resistance becomes equal to or more than a predetermined voltage. An overcurrent detection circuit having an analog delay section having a characteristic that the delay time decreases in an analog manner from the predetermined delay time as the current flowing through the circuit increases. 請求項１において、前記監視手段は、前記放電制御スイッチの両端に接続され、前記オン抵抗による電圧降下に応じた電流を出力する差動回路によって構成され、他方、前記アナログ遅延部は、前記差動回路からの電流によって、電流制御される電流源と、該電流源に直列に接続されたキャパシタと、当該電流源とキャパシタとの共通接続点における電圧を予め定められた電圧と比較する比較回路とを有することを特徴とする過電流検出回路。2. The monitoring device according to claim 1, wherein the monitoring unit is configured by a differential circuit connected to both ends of the discharge control switch and configured to output a current corresponding to a voltage drop due to the on-resistance. A current source controlled by a current from the driving circuit, a capacitor connected in series to the current source, and a comparison circuit for comparing a voltage at a common connection point between the current source and the capacitor with a predetermined voltage. And an overcurrent detection circuit. 請求項１又は２において、前記放電スイッチはＦＥＴによって構成されていることを特徴とする過電流検出回路。3. The overcurrent detection circuit according to claim 1, wherein the discharge switch is constituted by an FET. 一対の入出力端子、二次電池、前記一対の入出力端子の一方の端子と前記二次電池の一方の電極との間に接続された放電制御スイッチ、前記一対の入出力端子の他方の端子と前記二次電池の他方の電極との間に接続された電流検出抵抗と、前記電流検出抵抗の両端に接続され、当該電流検出抵抗の両端電圧を所定の基準電圧と比較し、比較結果を出力する過電流検出部と、前記電流検出抵抗の両端電圧が前記基準電圧を超えたことをあらわす信号が前記比較結果として与えられると、当該比較結果を所定の遅延時間だけ遅延させ、当該所定の遅延時間以上、前記両端電圧が前記基準電圧を超えている場合、前記放電スイッチをオフにする遅延回路とを有し、
前記遅延回路は、前記放電制御スイッチのオン抵抗の両端で生じる電圧降下を監視する監視手段と、前記オン抵抗に流れる電流による前記オン抵抗間の電圧降下が所定の電圧以上になると、前記オン抵抗に流れる電流が大きくなるにしたがって遅延時間が前記所定の遅延時間からアナログ的に減少する特性を有するアナログ遅延部を有することを特徴とする電池ユニット。A pair of input / output terminals, a secondary battery, a discharge control switch connected between one terminal of the pair of input / output terminals and one electrode of the secondary battery, and the other terminal of the pair of input / output terminals And a current detection resistor connected between the other electrode of the secondary battery and the both ends of the current detection resistor, and compares the voltage across the current detection resistor with a predetermined reference voltage. An overcurrent detection unit to be output, when a signal indicating that the voltage across the current detection resistor exceeds the reference voltage is given as the comparison result, the comparison result is delayed by a predetermined delay time, and the predetermined A delay circuit for turning off the discharge switch when the voltage between both ends exceeds the reference voltage,
The delay circuit includes a monitoring unit that monitors a voltage drop generated between both ends of the on-resistance of the discharge control switch. The on-resistance is controlled when a voltage drop between the on-resistance due to a current flowing through the on-resistance becomes equal to or more than a predetermined voltage. A battery unit having an analog delay unit having a characteristic that the delay time decreases in an analog manner from the predetermined delay time as the current flowing through the battery unit increases. 一対の入出力端子、二次電池、前記一対の入出力端子の一方の端子と前記二次電池の一方の電極との間に接続された放電制御スイッチ、前記一対の入出力端子の他方の端子と前記二次電池の他方の電極との間に接続された電流検出抵抗を備えた電池ユニットに設けられた過電流検出回路において、前記電流検出抵抗の両端に接続され、当該電流検出抵抗の両端電圧を所定の基準電圧と比較し、比較結果を出力する過電流検出部と、前記電流検出抵抗の両端電圧が前記基準電圧を超えたことをあらわす信号が前記比較結果として与えられると、当該比較結果を所定の遅延時間だけ遅延させ、当該所定の遅延時間以上、前記両端電圧が前記基準電圧を超えている場合、前記放電スイッチをオフにする遅延回路とを有し、
前記遅延回路は、前記電流検出抵抗の両端で生じる電圧降下を監視する監視手段と、前記電流検出抵抗に流れる電流による前記電圧降下が設定された電圧以上になると、前記電流検出抵抗に流れる電流が大きくなるにしたがって遅延時間が前記所定の遅延時間からアナログ的に減少する特性を有するアナログ遅延部を有することを特徴とする過電流検出回路。A pair of input / output terminals, a secondary battery, a discharge control switch connected between one terminal of the pair of input / output terminals and one electrode of the secondary battery, and the other terminal of the pair of input / output terminals An overcurrent detection circuit provided in a battery unit having a current detection resistor connected between the current detection resistor and the other electrode of the secondary battery. An overcurrent detection unit that compares the voltage with a predetermined reference voltage and outputs a comparison result; and when a signal indicating that the voltage across the current detection resistor exceeds the reference voltage is given as the comparison result, the comparison is performed. Delaying the result by a predetermined delay time, the predetermined delay time or more, when the voltage across the terminals exceeds the reference voltage, a delay circuit that turns off the discharge switch,
The delay circuit includes a monitoring unit that monitors a voltage drop that occurs at both ends of the current detection resistor. An overcurrent detection circuit comprising an analog delay section having a characteristic that the delay time decreases in an analog manner from the predetermined delay time as the delay time increases. 所定の抵抗素子両端における電圧降下に応じた電流を供給する電流源と、当該電流源に直列に接続されたキャパシタと、当該電流源とキャパシタとの共通接続点における電圧を予め定められた電圧と比較する比較回路とを有し、遅延時間をアナログ的に可変できることを特徴とする遅延回路。A current source that supplies a current according to the voltage drop across the predetermined resistance element, a capacitor connected in series to the current source, and a voltage at a common connection point between the current source and the capacitor, and a predetermined voltage. A delay circuit comprising: a comparison circuit for comparing; and a delay time can be varied in an analog manner.
JP2003013085A 2003-01-22 2003-01-22 Overcurrent detection circuit and battery unit Expired - Fee Related JP4221572B2 (en)

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KR20040067807A (en) 2004-07-30
CN1518183A (en) 2004-08-04

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