JP2004223770A - Device with both capacitive load and capacitive load driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device having a capacitive load and a capacitive load driving circuit which has a simple circuit configuration and can efficiently collect and reuse energy stored in the capacitive load. <P>SOLUTION: The device with the capacitive load 311 and the capacitive load driving circuit 301 has a power terminal 309a to which a power supply voltage is supplied, a grounding terminal C(0), capacitors C(1)-C(3), and switching elements S(0)-S(4) for switching connection of the capacitive load. The capacitors are connected sequentially from the capacitor of a lower initial potential to the capacitive load after the grounding terminal is connected to the capacitive load. The capacitive load is connected to the power terminal. Then, the capacitors are connected sequentially from the capacitor of a higher initial potential to the capacitive load. A capacitance component of the capacitors, a capacitance of the capacitive load, a switching time of the switching elements, and a resistance value of a charging discharging route of the capacitors to the capacitive load are set to satisfy a predetermined relational formula. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０１６６】
スイッチＳＷ１のＯＮ後、十分に時間が経過すると、エネルギー蓄積素子Ｃｓ１の電圧Ｖｓと容量性負荷Ｃｄの電圧Ｖｄとの差（エネルギー蓄積素子Ｃｓ１と容量性負荷Ｃｄとの電位差）がなくなり、電流Ｉは０になる。この電圧Ｖｓ・Ｖｄおよび電流Ｉの時間変化を図２４（ａ）（ｂ）に示す。この飽和電圧を、Ｖ１とする。
【０１６７】
【数２】

【０１６８】
次に、スイッチＳＷ１をＯＦＦとし、初期電位Ｖ０＋ΔＶのエネルギー蓄積素子Ｃｓ２に容量性負荷Ｃｄを接続する（図２５参照）。容量性負荷Ｃｄは、容量性負荷Ｃｄとエネルギー蓄積素子Ｃｓ２との電位差によって充電される。このときの容量性負荷Ｃｄの両端電圧は、以下の式で表される。
【０１６９】
【数３】

【０１７０】
スイッチＳＷ２のＯＮ後、十分に時間が経過すると、エネルギー蓄積素子Ｃｓ１と容量性負荷Ｃｄとの電位差がなくなり、電流Ｉは０になる（図２５参照）。この飽和電圧をＶ２とする。
【０１７１】
【数４】

【０１７２】
さらに、スイッチＳＷ２をＯＦＦにし、スイッチＳＷ１をＯＮにする（図２６参照）。容量性負荷Ｃｄとエネルギー蓄積素子Ｃｓ２との電位差によって、容量性負荷Ｃｄが放電される。この時の容量性負荷Ｃｄの両端電圧は、以下の式で表される。
【０１７３】
【数５】

【０１７４】
スイッチＳＷ１のＯＮ後、十分に時間が経過すると、エネルギー蓄積素子Ｃｓ１と容量性負荷Ｃｄとの電位差がなくなり、電流Ｉは０になる。この飽和電圧をＶ３とする。
【０１７５】
【数６】

【０１７６】
いま容量性負荷Ｃｄの静電容量Ｃｄに比べてエネルギー蓄積素子Ｃｓ１の静電容量Ｃｓ１およびエネルギー蓄積素子Ｃｓ２の静電容量Ｃｓ２が十分に大きい場合を考えると、以下の式が成立する。
【０１７７】
【数７】

【０１７８】
従って、エネルギー蓄積素子Ｃｓ１については、初期電位Ｖ０と、容量性負荷Ｃｄを充電した後の電位Ｖ１と、容量性負荷Ｃｄから回生を受けた後の電位Ｖ３とがほぼ等しくなり、エネルギー蓄積素子Ｃｓ１と容量性負荷Ｃｄとの間ではエネルギーロスが見かけ上０になる。
【０１７９】
次に、動作原理説明のための実施形態として、図１２に示す４段の容量性負荷駆動回路３０１を例に挙げて説明する。
【０１８０】
容量性負荷駆動回路３０１は、圧電素子等の容量性負荷３１１を充放電することで容量性負荷３１１を駆動するものであり、容量性負荷３１１とグラウンドとの間に並列に接続されたエネルギー蓄積素子としてのコンデンサＣ（１）、Ｃ（２）、およびＣ（３）を備えている。また、電源電圧ＶＨを供給するための直流電源（電源）である電力源３０９が設けられている。
【０１８１】
図示しないが、これらコンデンサＣ（１）〜Ｃ（３）に初期電位（初期電荷）を付与する初期電位付与手段が設けられている。この初期電位付与手段は、電力源３０９から供給されている電源電圧ＶＨと接地電位（＝０）との間の電位差（電圧）を４等分に分割（分圧）し、分圧によって生成された３つの電位Ｖ１（＝１／４・ＶＨ）、Ｖ２（＝２／４・ＶＨ）、およびＶ３（＝３／４・ＶＨ）をそれぞれコンデンサＣ（１）〜Ｃ（３）に初期電位として付与するものである。この初期電位付与手段は、例えば、グラウンド（接地点）と電力源３０９との間に接続され、接地電位と電源電圧ＶＨとの間の電位差を分圧し、分圧された電圧をコンデンサＣ（１）〜Ｃ（３）が接続されている分圧点に供給する分圧手段である。上記分圧手段としては、例えば、前述した分圧器５と同様、電源電圧Ｖが供給されている電力供給点ＶＨ（電源端子）とグラウンド（接地端子）との間に直列に接続された４つの抵抗を備える抵抗分圧回路を用いることができる。
【０１８２】
さらに、容量性負荷３１１とコンデンサＣ（１）、Ｃ（２）、およびＣ（３）との間にはそれぞれ、スイッチング素子Ｓ（１）、Ｓ（２）、およびＳ（３）が接続され、電力源３０９と容量性負荷３１１との間にはスイッチング素子Ｓ（４）が接続され、接地電位Ｇと容量性負荷３１１との間にはスイッチング素子Ｓ（０）が接続されている。この形態では、スイッチング素子Ｓ（０）〜Ｓ（４）によって切り替え手段が構成されている。一方、容量性負荷３１１の他端はグラウンドに接続されている。また、コンデンサＣ（１）、Ｃ（２）、Ｃ（３）の他端は接地点（基準電位端子、接地端子）Ｃ（０）を介してグラウンドに接続されている。
【０１８３】
以上の構成を備える容量性負荷駆動回路３０１の動作について、以下、図１３〜図１６に基づいて説明する。なお、以下、説明の都合上、電源電圧ＶＨが正電位である場合について説明する。電源電圧ＶＨが負電位である場合の動作も、電位の極性および電荷移動方向が逆になる以外は同様である。
【０１８４】
初期的に、図１３（ａ）に示すように、スイッチング素子Ｓ（０）〜Ｓ（４）のうちスイッチング素子Ｓ（０）のみを接続状態（ＯＮ状態）とし、容量性負荷３１１には電荷が蓄積されていない状態（初期状態）とする（図４５のＳ０）。
【０１８５】
第１のステップとして、図１３（ｂ）に示すように、スイッチング素子Ｓ（０）を切断状態（ＯＦＦ状態）とし、次いで、スイッチング素子Ｓ（１）を接続状態とする。このとき、コンデンサＣ（１）には電位Ｖ１（＝１／４・ＶＨ）のエネルギーが蓄積されており、容量性負荷３１１には電荷が蓄積されていないため、コンデンサＣ（１）と容量性負荷３１１との間には、ＶＨ／４の電位差がある。この電位差ＶＨ／４により、コンデンサＣ（１）の静電容量Ｃ１と容量性負荷３１１の静電容量Ｃｄとの比率に応じた電荷がコンデンサＣ（１）から容量性負荷３１１へ移動する。すなわち、コンデンサＣ（１）から容量性負荷３１１への静電エネルギー（以下、適宜、単に「エネルギー」と呼ぶ）の注入が行われ、容量性負荷３１１が充電される（図４５のＳ１）。コンデンサＣ（１）の電位は容量性負荷３１１に流れ込んだ電荷分低くなり、逆に容量性負荷３１１の電位はコンデンサＣ（１）から流れ込んだ電荷分高くなる。コンデンサＣ（１）の静電容量Ｃ１が容量性負荷３１１の静電容量Ｃｄより十分に大きい（Ｃ１＞Ｃｄ）場合、コンデンサＣ（１）の電位変化は小さい。スイッチング素子Ｓ（１）が接続状態とされている時間が十分に長い場合、エネルギーの移動によりコンデンサＣ（１）と容量性負荷３１１の電位は等しくなる。したがって、充電後のコンデンサＣ（１）および容量性負荷３１１のの電位は、コンデンサＣ（１）の初期電位ＶＨ／４（＝Ｖ１）より若干低い電位となる（図１５参照）。この電位をＶ１’とする。
【０１８６】
第２のステップとして、図１３（ｃ）に示すように、スイッチング素子Ｓ（１）を切断状態とし、次いでスイッチング素子Ｓ（２）を接続状態とする。このときコンデンサＣ（２）には電位Ｖ１’よりも高い電位である電位Ｖ２のエネルギーが蓄積されているため、コンデンサＣ（２）の静電容量Ｃ２と容量性負荷３１１の静電容量Ｃｄとの比率に応じた電荷がコンデンサＣ（２）から容量性負荷３１１へ移動する。すなわち、電位差Ｖ２‐Ｖ１’（＝ＶＨ／４＋α；αはＶＨと比較して小さい値）によって、コンデンサＣ（２）から容量性負荷３１１にエネルギーの注入が行われ、容量性負荷３１１がさらに充電される（図４５のＳ２）。コンデンサＣ（２）の電位は容量性負荷３１１に流れ込んだ電荷分低くなり、逆に容量性負荷３１１の電位はコンデンサＣ（２）から流れ込んだ電荷分高くなる。コンデンサＣ（２）の静電容量Ｃ２が容量性負荷３１１の静電容量Ｃｄより十分に大きい（Ｃ２＞Ｃｄ）場合、コンデンサＣ（２）の電位変化は小さい。スイッチング素子Ｓ（２）が接続されている時間が十分に長い場合、エネルギーの移動によりコンデンサＣ（２）と容量性負荷３１１の電位はほぼ等しくなる。したがって、充電後のコンデンサＣ（２）および容量性負荷３１１の電位は、コンデンサＣ（２）の初期電位２ＶＨ／４（＝Ｖ２）より若干低い電位となる（図１５参照）。この電位をＶ２’とする。
【０１８７】
第３のステップとして、図１３（ｄ）に示すように、スイッチング素子Ｓ（２）を切断状態とし、次いでスイッチング素子Ｓ（３）を接続状態とする。このときコンデンサＣ（３）には電位Ｖ２’よりも高い電位である電位Ｖ３のエネルギーが蓄積されているため、コンデンサＣ（３）の静電容量Ｃ３と容量性負荷３１１の静電容量Ｃｄとの比率に応じた電荷がコンデンサＣ（３）から容量性負荷３１１へ移動する。すなわち、電位差Ｖ３‐Ｖ２’（＝ＶＨ／４＋α）によって、コンデンサＣ（３）から容量性負荷３１１にエネルギーの注入が行われ、容量性負荷３１１がさらに充電される（図４５のＳ３）。コンデンサＣ（３）の電位は容量性負荷３１１に流れ込んだ電荷分低くなり、逆に容量性負荷３１１の電位はコンデンサＣ（３）から流れ込んだ電荷分高くなる。コンデンサＣ（３）の静電容量Ｃ３が容量性負荷３１１の静電容量Ｃｄより十分に大きい（Ｃ３＞Ｃｄ）場合、コンデンサＣ（３）の電位変化は小さい。スイッチング素子Ｓ（３）が接続されている時間が十分に長い場合、エネルギーの移動によりコンデンサＣ（３）と容量性負荷３１１の電位はほぼ等しくなる。したがって、充電後のコンデンサＣ（３）および容量性負荷３１１の電位は、コンデンサＣ（３）の初期電位３ＶＨ／４（＝Ｖ３）より若干低い電位となる（図１５参照）。この電位をＶ３’とする。
【０１８８】
第４のステップとして、図１３（ｄ）に示すように、スイッチング素子Ｓ（３）を切断状態とし、次いでスイッチング素子Ｓ（４）を接続状態とする。このとき、電源電圧（電源電位）ＶＨは電位Ｖ３’よりも高いため、これらの電位差ＶＨ−Ｖ３’（＝ＶＨ／４＋α）によって電力源３０９から容量性負荷３１１にエネルギーの注入が行われ、容量性負荷３１１がさらに充電される（図４５のＳ４）。スイッチング素子Ｓ（４）が接続されている時間が十分に長い場合、充電後の容量性負荷３１１の電位は、電源電圧ＶＨまで吊上げられる。
【０１８９】
第５のステップとして、図１４（ａ）に示すように、スイッチング素子Ｓ（４）を切断状態とし、次いでスイッチング素子Ｓ（３）を接続状態とする（図４５のＳ５）。このとき容量性負荷３１１には、コンデンサＣ（３）の電位Ｖ３’よりも高い電位である電位ＶＨのエネルギーが蓄積されているため、ＶＨ／４＋αである電位差ＶＨ−Ｖ３’によって、コンデンサＣ（３）の静電容量Ｃ３と容量性負荷の静電容量Ｃｄとの比率に応じた電荷がコンデンサＣ（３）に移動し、容量性負荷３１１からコンデンサＣ（３）へ充電される。これにより、コンデンサＣ（３）の電位は容量性負荷３１１から流れ込んだ電荷分高くなり、逆に容量性負荷３１１の電位はコンデンサＣ（３）へ流れ込んだ電荷分低くなる。スイッチング素子Ｓ（３）が接続されている時間が十分に長い場合、エネルギーの移動によりコンデンサＣ（３）と容量性負荷３１１の電位は等しくなる。充電の結果としてコンデンサＣ（３）の電位はほぼ元のＶ３＝３ＶＨ／４に戻り、容量性負荷３１１からコンデンサＣ（３）へエネルギーの回生が行われたことになる（図４５のＳ５）。
【０１９０】
第６のステップとして、図１４（ｂ）に示すように、スイッチング素子Ｓ（３）を切断状態とし、次いでスイッチング素子Ｓ（２）を接続状態とする（図４５のＳ６）。このとき容量性負荷３１１には電位Ｖ２’よりも高い電位である電位Ｖ３のエネルギーが蓄積されているため、ＶＨ／４＋αである電位差Ｖ３−Ｖ２’によって、コンデンサＣ（２）の静電容量Ｃ２と容量性負荷の静電容量Ｃｄとの比率に応じた電荷がコンデンサＣ（２）に移動し、容量性負荷３１１からコンデンサＣ（２）へ充電される。これにより、コンデンサＣ（２）の電位は容量性負荷３１１から流れ込んだ電荷分高くなり、逆に容量性負荷３１１の電位はコンデンサＣ（２）へ流れ込んだ電荷分低くなる。スイッチング素子Ｓ（２）が接続されている時間が十分に長い場合、エネルギーの移動によりコンデンサＣ（２）と容量性負荷３１１の電位は等しくなる。充電の結果としてコンデンサＣ（２）の電位はほぼ元のＶ２＝２ＶＨ／４に戻り、容量性負荷３１１からコンデンサＣ（２）にエネルギーの回生が行われたことになる（図４５のＳ６）。
【０１９１】
第７のステップとして、図１４（ｃ）に示すように、スイッチング素子Ｓ（２）を切断状態とし、次いでスイッチング素子Ｓ（１）を接続状態とする（図４５のＳ７）。このとき容量性負荷３１１には、電位Ｖ１’よりも高い電位である電位Ｖ２のエネルギーが蓄積されているため、ＶＨ／４＋αである電位差Ｖ２−Ｖ１’によって、コンデンサＣ（１）の静電容量Ｃ１と容量性負荷の静電容量Ｃｄとの比率に応じた電荷がコンデンサＣ（１）に移動し、容量性負荷３１１からコンデンサＣ（１）へ充電される。これにより、コンデンサＣ（１）の電位は容量性負荷３１１から流れ込んだ電荷分高くなり、逆に容量性負荷３１１の電位はコンデンサＣ（１）へ流れ込んだ電荷分低くなる。スイッチング素子Ｓ（１）が接続されている時間が十分に長い場合、エネルギーの移動によりコンデンサＣ（１）と容量性負荷３１１の電位は等しくなる。充電の結果としてコンデンサＣ（１）の電位はほぼ元のＶ１＝ＶＨ／４に戻り、容量性負荷３１１からコンデンサＣ（１）にエネルギーの回生が行われたことになる（図４５のＳ７）。
【０１９２】
第８のステップとして、図１４（ｄ）に示すように、スイッチング素子Ｓ（１）を切断状態とし、次いでスイッチング素子Ｓ（０）を接続状態とする。このとき容量性負荷３１１には接地電位’よりも高い電位である電位Ｖ１’のエネルギーが蓄積されているため、電位差ＶＨ／４＋αである電位差Ｖ１’によって容量性負荷３１１の電荷が接地電位に流出（放電）、つまり消費（破棄）される（図４５のＳ８）。その後、Ｓ１に戻る。
【０１９３】
以上、第１〜第８のステップＳ１〜Ｓ８において、エネルギー的に見ると、第１のステップＳ１で容量性負荷３１１に注入されたコンデンサＣ（１）の蓄積エネルギーは、第７のステップＳ７で容量性負荷３１１からコンデンサＣ（１）に戻されるエネルギーによって回生される。第２のステップＳ２で容量性負荷３１１に注入されたエネルギーは、第６のステップＳ６で容量性負荷３１１からコンデンサＣ（１）に戻されるエネルギーによって回生される。第３のステップＳ３で容量性負荷３１１に注入されたエネルギーは、第５のステップＳ５で容量性負荷３１１からコンデンサＣ（１）に戻されるエネルギーによって回生される。つまり、第１〜第８のステップＳ１〜Ｓ８を総合すると、第１〜第８のステップＳ１〜Ｓ８において、容量性負荷３１１へのエネルギー注入は第４のステップＳ４で行われ、エネルギー消費は第８のステップＳ８で行われ、その他のステップにおけるエネルギーの輸送は、相対するステップによりキャンセルされる（図１５参照）ため、エネルギー注入・消費は見かけ上行われないことになる。結果的に、同じ１／４・ＶＨに相当するエネルギーだけが消費されることになる。つまり電圧ＶＨを充電し、そのまま放電するＰｕｓｈ−Ｐｕｌｌなどの方式に比べ２５％のエネルギー消費で充放電ができる。
【０１９４】
さらに具体的な例として、上記４段の容量性負荷駆動回路３０１を用いて波高値１０Ｖｐｐのパルスを作成する際に場合の電圧変化について記述する。１０Ｖを４分割すると１段当りの電位差は２．５Ｖになり、コンデンサＣ（１）〜Ｃ（３）のそれぞれの電位２．５Ｖ、５．０Ｖ、７．５Ｖと、接地電位０Ｖおよび電源電位１０Ｖとの５つの電位に分割される。また、コンデンサＣ（１）〜Ｃ（３）の静電容量は、容量性負荷３１１の静電容量に比べて大きい方が好ましいが、動作を判りやすくするために、容量性負荷３１１の４倍とする。また、系に用いるスイッチング素子Ｓ（０）〜Ｓ（４）には、通常半ＦＥＴ（電界効果トランジスタ）やＧＴＯサイリスタなどの半導体スイッチを用いるが、半導体スイッチの場合、ＯＮ抵抗が無視できないため、容量性負荷３１１への充放電は特定の時定数を持つ指数関数的に行われる。従って、波形形成の場合はスイッチング素子Ｓ（０）〜Ｓ（４）のＯＮ時間と容量性負荷３１１への充放電時定数との関係が重要になるが、簡単化のためにスイッチング素子のＯＮ抵抗は非常に小さく、スイッチング素子Ｓ（０）〜Ｓ（４）のＯＮ抵抗による系の影響は無視できる程度の十分長いスイッチング時間で次段へ切り替えるとの前提で計算を行う。計算結果を表１に示す。表１において、Ｖｄは容量性負荷３１１の電位、Ｖｓ＿０は接地電位、Ｖｓ＿ｎ（ｎは１〜３）は各段のコンデンサＣ（ｎ）の電位、Ｖｓ＿４は電源電位を表す。
【０１９５】
【表１】

【０１９６】
この結果から明らかなように、各コンデンサから容量性負荷へエネルギーが注入されると、それに伴い各コンデンサの電位も減少する。しかし、逆に容量性負荷から各コンデンサへエネルギーが注入されると各コンデンサの電位は元に戻り、結果として電力が回生される。
【０１９７】
以上のように、本実施形態に係る容量性負荷駆動回路３０１は、電力源３０９から電源電位ＶＨが付与された電源端子３０９ａと、接地電位（基準電位）が付与された接地端子Ｃ（０）（基準電位端子）と、接地電位と電源電位ＶＨとの間で、かつ互いに異なる初期電位Ｖ（１）〜Ｖ（３）が付与された３個のコンデンサＣ（１）〜Ｃ（３）と、接地端子Ｃ（０）、コンデンサＣ（１）〜Ｃ（３）、および電源端子３０９ａを選択的に容量性負荷３１１と接続するためのスイッチング素子Ｓ（０）〜Ｓ（４）とを備え、上記スイッチング素子Ｓ（０）〜Ｓ（４）は、接地端子Ｃ（０）を容量性負荷３１１に接続した後に各コンデンサＣ（１）〜Ｃ（３）をその初期電位が接地電位に近い方から順に容量性負荷３１１に接続することで容量性負荷３１１の端子電圧を電源電位ＶＨに近づくように変化させる第１のステップ（Ｓ１〜Ｓ３）と、その後に容量性負荷３１１を電源端子３０９ａと選択的に接続することで容量性負荷３１１の端子電圧の絶対値を増大させる第２のステップ（Ｓ４）と、その後に各コンデンサＣ（１）〜Ｃ（３）をその初期電位が電源電位ＶＨに近い方から順に容量性負荷３１１に接続することで容量性負荷３１１の端子電圧の絶対値を減少させると共に、コンデンサＣ（１）〜Ｃ（３）の蓄積静電エネルギーを第１のステップの前とほぼ等しくなるように回生する第３のステップ（Ｓ５〜Ｓ７）とを実行するようになっている構成である。
【０１９８】
なお、ここでは、接地電位と電源電位ＶＨとの間で、かつ互いに異なる初期電位が付与されたコンデンサの数が３個であり、容量性負荷３１１を充電（または放電）するステップの数（スイッチング素子Ｓ（０）〜Ｓ（４）の電位の種類の数より１つ小さく、コンデンサの数より１つ多い；以下、「段数」と呼ぶ）が４段である場合について説明した。
【０１９９】
しかしながら、段数は２段以上であれば特に限定されるものではない。理想的には、２段の場合には回生効率５０％、３段には回生効率６６．７％、４段の場合には回生効率７５％、５段の場合には回生効率８０％、と段数を増加させるほど回生効率は高くなる。しかしながら、段数を増加させるほど電圧立上げに必要な時間は長くなり、かつ必要な回路数も増加する。従って、段数は、必要な駆動波形や回路のサイズ、コストなどにより決定すればよい。一般には、高速立上げが必要な場合には３〜４段の回路構成が好ましく、電力消費を抑制したい場合には４〜５段の回路構成が好ましい。
【０２００】
また、上記の説明では、電源電圧ＶＨを４段で均等分割した場合を用いて説明したが、必ずしも均等に分割する必要は無い。しかしながら、本実施形態の容量性負荷駆動回路３０１は、コンデンサＣ（Ｉ）（Ｉ＝１，２，３）からＶ（Ｉ−１）（ただしＶ（０）＝０）の電位を持つ容量性負荷３１１へのエネルギー注入（Ｓ１〜Ｓ３）によるコンデンサＣ（Ｉ）のエネルギー減少分を、Ｖ（Ｉ）（ただしＶ（４）＝ＶＨ）の電位を持つ容量性負荷３１１からＣ（Ｉ）へエネルギー注入することにより回生する（Ｓ５〜Ｓ８）原理で電力回生を行うことから、理想的な電力回生を行うためには均等分割が最も好ましい。
【０２０１】
ここで、容量性負荷３１１の時定数とコンデンサＣ（Ｉ）のスイッチング時間について考察する。
【０２０２】
図２７に示す回路において、コンデンサＣｓに初期電位が付与され、容量性負荷Ｃｄが放電されている状態を考えると、スイッチＳＷのＯｎ後、容量性負荷Ｃｄの電圧は、図２８に示すように時間の経過に従って上昇する。十分に時間が経過すると、容量性負荷Ｃｄは、コンデンサＣｓと電位差がなくなり、電流Ｉは０になる。本願明細書では、この飽和電圧を「到達電圧」と呼ぶ。
【０２０３】
図２７に示す回路において、ある時間（スイッチング時間（Ｔｓ））が経過した時点でスイッチを切るとすると、スイッチング時間（Ｔｓ）が時定数（τｏ＝Ｒ・Ｃｄ；Ｒはエネルギー蓄積素子と容量性負荷とを含む充電経路もしくは放電経路の直流抵抗成分、Ｃｄは容量性負荷の静電容量）より短い場合、容量性負荷Ｃｄの電圧は、図２９（ａ）に示すように変化する。したがって、本発明に係る３段の容量性負荷駆動回路においては、容量性負荷Ｃｄの電圧は、図２９（ｂ）に示すように変化する。
【０２０４】
スイッチング時間（Ｔｓ）が時定数（τｏ＝Ｒ・Ｃｄ）と等しい場合、容量性負荷Ｃｄの電圧は、図３０（ａ）に示すように変化する。したがって、本発明に係る３段の容量性負荷駆動回路においては、容量性負荷Ｃｄの電圧は、図３０（ｂ）に示すように変化する。
【０２０５】
スイッチング時間（Ｔｓ）が時定数（τｏ＝Ｒ・Ｃｄ）より長い場合、容量性負荷Ｃｄの電圧は、図３１（ａ）に示すように変化する。したがって、本発明に係る３段の容量性負荷駆動回路においては、容量性負荷Ｃｄの電圧は、図３１（ｂ）に示すように変化する。
【０２０６】
本発明の容量性負荷駆動回路において、エネルギー蓄積素子の静電容量成分をＣｓ、容量性負荷の静電容量をＣｄ、エネルギー蓄積素子と容量性負荷とを含む充電経路もしくは放電経路の直流抵抗成分をＲ、エネルギー蓄積素子のスイッチング時間（切り替え時間；容量性負荷への接続が継続される時間）をＴｓとすると、
τｏ≦Ｔｓ≦２．５・τｏ
（但し、τｏ＝Ｒ・Ｃｄ）
であることが好ましい。Ｔｓ＜τｏであると、得られるパルスの波高値が到達電圧の６３％以下になり、容量性負荷へのエネルギー供給効率が低下する。また、Ｔｓ＞２．５・τｏとすると、スイッチング時間が極端に長くなってしまう。
【０２０７】
〔実施の形態５〕
次に、本発明のさらに他の実施形態について図１６ないし図１９に基づいて以下に説明する。なお、説明の便宜上、前記実施の形態４にて示した各部材と同一の機能を有する部材には、同一の符号を付記し、その説明を省略する。
【０２０８】
本実施形態に係る容量性負荷駆動回路３０２は、実施の形態４の容量性負荷駆動回路３０１における電力源３０９とそれに接続されたスイッチング素子Ｓ（４）との間にエネルギー蓄積素子としてのコンデンサＣ（Ｎ）を追加し、段数（コンデンサ数）を一般化したものである。
【０２０９】
本実施形態に係る容量性負荷駆動回路３０２は、図１６および図１７に示すように、接地電位（基準電位）Ｖ（０）（＝０）を有する接地端子Ｃ（０）と、０でない初期電位Ｖ（１）…Ｖ（Ｎ）（Ｎは２以上の自然数）を持つＮ個のコンデンサＣ（１）…Ｃ（Ｎ）（エネルギー蓄積素子）と、接地端子Ｃ（０）（基準電位端子）と容量性負荷３１１とを接続するスイッチング素子Ｓ（０）（切り替え手段）と、コンデンサＣ（１）…Ｃ（Ｎ）（切り替え手段）と容量性負荷３１１を選択的に接続するＮ個のスイッチング素子Ｓ（１）…Ｓ（Ｎ）とを有し、コンデンサＣ（Ｎ）が電力発生源に（直接、若しくは何らかの回路を介して）接続されているパルス発生回路であって、上記Ｎ個のコンデンサＣ（１）…Ｃ（Ｎ）は、０でない第１の初期電位Ｖ（Ｉ）を持つコンデンサＣ（Ｉ）（第１のエネルギー蓄積素子）と、初期電位Ｖ（Ｉ）と同極性でかつ初期電位Ｖ（Ｉ）より絶対値の大きい第２の初期電位Ｖ（Ｉ＋１）を持つコンデンサＣ（Ｉ＋１）（第２のエネルギー蓄積素子）とを含み、スイッチング素子Ｓ（０）〜Ｓ（Ｎ）（切り替え手段）が、容量性負荷３１１を接地端子またはコンデンサＣ（Ｉ−１）（接地端子または第３のエネルギー蓄積素子）と選択的に接続した後に容量性負荷３１１をコンデンサＣ（Ｉ）と選択的に接続することで容量性負荷３１１の電位（端子電圧）をコンデンサＣ（Ｉ）の初期電位に近づくように変化させる第１の充電ステップと、その後に容量性負荷３１１をコンデンサＣ（Ｉ＋１）と選択的に接続することで容量性負荷３１１の電位（端子電圧）の絶対値を増大させる第２の充電ステップと、その後に容量性負荷３１１をコンデンサＣ（Ｉ）と選択的に接続することで容量性負荷３１１の電位（端子電圧）の絶対値を減少させると共にコンデンサＣ（Ｉ）の蓄積静電エネルギーを第１の充電ステップの前とほぼ等しくなるように回生する放電ステップとを実行するようになっている。なお、図１６においても、初期電荷を与える回路は省略している。
【０２１０】
上記構成の動作を図１７に基づいて説明する。
【０２１１】
パルス発生のエネルギー消費は、コンデンサＣ（Ｎ）からコンデンサＣ（Ｎ−１）への電荷移動分が接地電位に向かって輸送され、接地端子Ｃ（０）で消費される。図１７（ａ）から図１７（ｆ）のサイクルは、実施の形態４におけるステップＳ１〜Ｓ８のサイクルと同様の効果を奏する。すなわち、図１７（ａ）から図１７（ｂ）への移行の際にコンデンサＣ（Ｉ）から流出した電荷と、図１７（ｄ）から図１７（ｅ）への移行の際にコンデンサＣ（Ｉ）へ流入する電荷とをほぼ等しくすることで、図１７（ａ）から図１７（ｆ）のサイクルにおいてコンデンサＣ（Ｉ）は見かけ上エネルギー消費をしなくなる。
【０２１２】
したがって、少なくとも図１７（ａ）から図１７（ｆ）のサイクルを実行するようになっていればよく、Ｎ個のコンデンサＣ（１）…Ｃ（Ｎ）の全てを使用しても一部を使用してもよい。使用するコンデンサは、発生しようとするパルスに応じて適宜設定すればよい。例えば、ベース電位が接地電位で、パルス振幅の大きいパルスを発生したい場合には、全てのコンデンサＣ（１）…Ｃ（Ｎ）を使用すればよい。また、発生しようとするパルスの波高値が電源電圧ＶＨより低い場合や、ベース電位が接地電位でないパルスを発生したい場合には、一部のコンデンサのみを使用すればよい。
【０２１３】
したがって、本実施形態に係る容量性負荷駆動回路３０２は、異なる複数の初期電位Ｖ（１）…Ｖ（Ｎ）（Ｎは２以上の自然数）が付与された複数のコンデンサＣ（１）…Ｃ（Ｎ）と、上記コンデンサＣ（１）…Ｃ（Ｎ）を選択的に容量性負荷３１１と接続するためのスイッチング素子Ｓ（１）…Ｓ（Ｎ）とを備え、上記複数のコンデンサＣ（１）…Ｃ（Ｎ）は、０でない第１の初期電位Ｖ（Ｉ）を持つコンデンサＣ（Ｉ）と、第１の初期電位Ｖ（Ｉ）より絶対値の大きい第２の初期電位Ｖ（Ｉ＋１）を持つコンデンサＣ（Ｉ＋１）と、第１の初期電位Ｖ（Ｉ）と同極性でかつ第１の初期電位Ｖ（Ｉ）より絶対値の小さい電位である第３の初期電位Ｖ（Ｉ−１）を持つコンデンサＣ（Ｉ−１）とを含み、スイッチング素子Ｓ（１）…Ｓ（Ｎ）は、容量性負荷３１１をコンデンサＣ（Ｉ−１）と選択的に接続した後にコンデンサＣ（Ｉ）と選択的に接続することで容量性負荷の端子電圧３１１を第１の初期電位に近づくように変化させる第１の充電ステップと、その後に容量性負荷３１１を第２の初期電位Ｖ（Ｉ＋１）とエネルギー蓄積素子に選択的に接続することで容量性負荷３１１の端子電圧の絶対値を増大させる第２の充電ステップと、その後に容量性負荷３１１をコンデンサＣ（Ｉ）と選択的に接続することで容量性負荷３１１の端子電圧の絶対値を減少させると共に、第１のコンデンサＣ（Ｉ）の蓄積静電エネルギーを第１の充電ステップの前とほぼ等しくなるように回生する放電ステップとを実行するようになっている構成であってもよい。
【０２１４】
また、初期電位Ｖ（１）…Ｖ（Ｎ）は、正であってもよく、負であってもよいが、初期電位Ｖ（１）…Ｖ（Ｎ）が正の場合、例えば図１８に示すパルスを発生できる。また、初期電位Ｖ（１）…Ｖ（Ｎ）が負の場合、例えば図１９に示すパルスを発生できる。
【０２１５】
なお、本実施形態において、電力源３０９に接続されているコンデンサＣ（Ｎ）は無くても動作する（通常は電力源３０９に内蔵される）。
【０２１６】
それゆえ、本実施形態に係る容量性負荷駆動回路３０２は、電力源３０９から電源電位ＶＨが付与された電源端子（ＶＨ）と、異なる複数の初期電位Ｖ（１）…Ｖ（Ｎ）（Ｎは２以上の自然数）が付与されたＮ個のコンデンサＣ（１）…Ｃ（Ｎ）と、上記コンデンサＣ（１）…Ｃ（Ｎ）および電源端子（ＶＨ）を選択的に容量性負荷３１１と接続するためのスイッチング素子Ｓ（１）…Ｓ（Ｎ）とを備え、上記コンデンサＣ（１）…Ｃ（Ｎ）は、電源電位ＶＨと同極性でかつ電源電位ＶＨより絶対値の小さい第１の初期電位Ｖ（Ｉ）を持つコンデンサＣ（Ｉ）と、第１の初期電位Ｖ（Ｉ）と同極性でかつ第１の初期電位Ｖ（Ｉ）より絶対値の小さい電位である第３の初期電位Ｖ（Ｉ−１）を持つコンデンサＣ（Ｉ−１）とを含み、上記スイッチング素子Ｓ（１）…Ｓ（Ｎ）が、容量性負荷３１１をコンデンサＣ（Ｉ−１）と選択的に接続した後にコンデンサＣ（Ｉ）と選択的に接続することで容量性負荷３１１の端子電圧を第１の初期電位Ｖ（Ｉ）に近づくように変化させる第１の充電ステップと、その後に容量性負荷３１１を電源端子（ＶＨ）と選択的に接続することで容量性負荷３１１の端子電圧の絶対値を増大させる第２の充電ステップと、その後に容量性負荷３１１をコンデンサＣ（Ｉ）と選択的に接続することで容量性負荷３１１の端子電圧の絶対値を減少させると共に、コンデンサＣ（Ｉ）の蓄積静電エネルギーを第１の充電ステップの前とほぼ等しくなるように回生する放電ステップとを実行するようになっている構成であってもよい。
【０２１７】
次に、図１２に示す４段の容量性負荷駆動回路３０１において、コンデンサＣ（１）〜Ｃ（３）の静電容量成分、容量性負荷３１１の静電容量、スイッチング素子Ｓ（１）〜Ｓ（３）のスイッチング時間、および充放電経路の抵抗値の設定について考察する。容量性負荷３１１の電圧は、第１〜第３のステップの間に到達電圧（第１〜第３のステップを無限時間継続したときに容量性負荷３１１の電圧が到達する最終の電圧）の９０％に到達することが望ましいと考えられる。そこで、そのための条件を求める。
【０２１８】
まず、スイッチング素子Ｓ（１）のスイッチング時間は第１のステップの時間、スイッチング素子Ｓ（２）のスイッチング時間は第２のステップの時間、スイッチング素子Ｓ（３）のスイッチング時間は第３のステップの時間であり、これらは互いに等しいものとする。
【０２１９】
ここで、容量性負荷３１１の静電容量をＣｄ（単位Ｆ）、容量性負荷３１１に対するコンデンサＣ（１）〜Ｃ（３）の充放電経路の抵抗値の各々をＲ（単位Ω）とすると、コンデンサＣ（１）〜Ｃ（３）の各々の充放電の時定数τ０（単位ｓｅｃ）は、次式
τ０＝Ｒ・Ｃｄ
で表される。コンデンサＣ（１）〜Ｃ（３）の静電容量成分をＣｓ（単位Ｆ）、負荷容量比Ｃｄ／ＣｓをＸ、スイッチング素子Ｓ（１）〜Ｓ（３）のスイッチング時間をＴｓ（単位ｓｅｃ）とすると、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％に到達する条件は、理論計算により求めることができ、図４６の実線に示すようになる。図４６は、時定数τ０とスイッチ時間Ｔｓとの比Ｔｓ／τ０に対して、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％以上となる最大の負荷容量比Ｘ（＝Ｃｄ／Ｃｓ）を表す。
【０２２０】
図４６に示すように、Ｔｓ／τ０＜２．５の場合、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％に到達する条件は、近似曲線
Ｘ＝０．１６４（Ｔｓ／τ０）^{０．２１９８}
にほぼ等しい。一方、Ｔｓ／τ０≧２．５の場合、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％に到達する条件は、直線
Ｘ＝０．２
にほぼ等しい。
【０２２１】
したがって、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％以上となる条件は、近似的に、
Ｔｓ／（Ｒ・Ｃｄ）＜２．５の場合
Ｃｄ／Ｃｓ≦０．１６４｛Ｔｓ／（Ｒ・Ｃｄ）｝^{０．２１９８}
Ｔｓ／（Ｒ・Ｃｄ）≧２．５の場合
Ｃｄ／Ｃｓ≦０．２
で表される。
【０２２２】
それゆえ、上記条件を満たせば、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％以上となり、好ましい。上の式が成立しない場合、コンデンサＣ（１）〜（３）から容量性負荷３１１への電荷の流出によるコンデンサＣ（１）〜（３）の電圧変化が大きくなり、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％に達成しない。この結果、パルス発生時の電力回生率が悪化し、容量性負荷駆動回路の省エネ駆動を害する。また、上の式が成立しない場合、１回のパルス発生によるＣ（１）〜（３）の電圧変化が大きく、次のパルス発生までにその電圧変化を補正する必要が生じる。
【０２２３】
以上の説明では、第１〜第３のステップの間に容量性負荷３１１の電圧が到達電圧の９０％以上となる条件について考察したが、エネルギー回生率を向上させることも重要である。
【０２２４】
図１２に示す４段の容量性負荷駆動回路３０１において、容量性負荷３１１の静電容量をＣｄ（単位Ｆ）、容量性負荷３１１に対するコンデンサＣ（１）〜Ｃ（３）の充放電経路の抵抗値の各々をＲ（単位Ω）とすると、コンデンサＣ（１）〜Ｃ（３）の各々の充放電の時定数τ０（単位ｓｅｃ）は、次式
τ０＝Ｒ・Ｃｄ
で表される。コンデンサＣ（１）〜Ｃ（３）の静電容量成分をＣｓ（単位Ｆ）、負荷容量比Ｃｄ／ＣｓをＸ、スイッチング素子Ｓ（１）〜Ｓ（３）のスイッチング時間をＴｓ（単位ｓｅｃ）とすると、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比Ｔｓ／τ０に対するエネルギー消費率（１からエネルギー回生率を引いた値に等しい）の変化は、理論計算により、図４９に示すように求めることができる。
【０２２５】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを２段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比Ｔｓ／τ０に対するエネルギー消費率の変化は、図４７に示すようになる。
【０２２６】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを３段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比Ｔｓ／τ０に対するエネルギー消費率の変化は、図４８に示すようになる。
【０２２７】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを５段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比Ｔｓ／τ０に対するエネルギー消費率の変化は、図５０に示すようになる。
【０２２８】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを６段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比Ｔｓ／τ０に対するエネルギー消費率の変化は、図５１に示すようになる。なお、図４７〜図５１には示していないが、負荷容量比Ｘが０．００１の場合も、負荷容量比Ｘが０．００３の場合とほぼ同様であった。
【０２２９】
これらの結果から、エネルギー消費率はＴｓ／τ０に大きく依存するものの、負荷容量比Ｘが
Ｘ≦０．０１
を満たす場合に、容量性負荷の静電容量Ｃｄが増大してもエネルギー消費率を十分に低下できることが分かった。上の式が成立する場合、コンデンサの出力電圧を減じること無く有効に容量性負荷３１１に与えることが可能となる。また、Ｘ≦０．０１である場合、コンデンサあるいは容量性負荷の静電容量のバラツキや変動（温度変化など）により駆動電圧が変動することが抑制され、信頼性の高い吐出動作が可能となり、容量性負荷３１１を含む駆動系（容量性負荷駆動回路によって駆動される系）を安定動作させることができる。一方、上の式が成立しない場合、容量性負荷の静電容量Ｃｄの増大時にエネルギー回生率が悪化する。
【０２３０】
次に、容量性負荷に印加されるパルスの波形のスルーレート（１０％−９０％）（パルスが波高値の１０％から９０％まで立ち上がるのに必要な時間に対する、パルスが波高値の１０％から９０％まで立ち上がるときの電圧変化量）が良好となる条件について考察する。
【０２３１】
図１２に示す４段の容量性負荷駆動回路３０１において、容量性負荷３１１の静電容量をＣｄ（単位Ｆ）、容量性負荷３１１に対するコンデンサＣ（１）〜Ｃ（３）の充放電経路の抵抗値の各々をＲ（単位Ω）とすると、コンデンサＣ（１）〜Ｃ（３）の各々の充放電の時定数τ０（単位Ｓｅｃ）は、次式
τ０＝Ｒ・Ｃｄ
で表される。コンデンサＣ（１）〜Ｃ（３）の静電容量成分をＣｓ（単位Ｆ）、スイッチング素子Ｓ（１）〜Ｓ（３）のスイッチング時間をＴｓ（単位ｓｅｃ）、最終到達電圧（コンデンサＣ（１）〜Ｃ（３）による充電を無限時間かけて行った場合に容量性負荷３１１が到達する電圧）をＶ（＝３ＶＨ／４）、容量性負荷３１１に印加されるパルスの波形のスルーレート（１０％−９０％）ＳＲ（単位Ｖ／μｓｅｃ）とし、
ｘ＝Ｔｓ／τ０
とすると、負荷容量比Ｘを０．００１から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比ｘ＝Ｔｓ／τ０に対するスルーレート（１０％−９０％）ＳＲの変化は、理論計算により、図５４に示すように求めることができる。なお、図５４には示していないが、負荷容量比Ｘが０．００３〜０．０３の場合も、負荷容量比Ｘが０．００１の場合とほぼ同様であった。
【０２３２】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを２段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００１から０．１まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比ｘ＝Ｔｓ／τ０に対するスルーレート（１０％−９０％）ＳＲの変化の変化は、図５２に示すようになる。なお、図５２には示していないが、負荷容量比Ｘが０．００３の場合も、負荷容量比Ｘが０．００１の場合とほぼ同様であった。
【０２３３】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを３段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００１から０．１まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比ｘ＝Ｔｓ／τ０に対するスルーレート（１０％−９０％）ＳＲの変化の変化は、図５３に示すようになる。なお、図５３には示していないが、負荷容量比Ｘが０．００３〜０．０１の場合も、負荷容量比Ｘが０．００１の場合とほぼ同様であった。
【０２３４】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを５段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比ｘ＝Ｔｓ／τ０に対するスルーレート（１０％−９０％）ＳＲの変化の変化は、図５５に示すようになる。なお、図５５には示していないが、負荷容量比Ｘが０．００３〜０．０３の場合も、負荷容量比Ｘが０．００１の場合とほぼ同様であった。
【０２３５】
また、図１２に示す４段の容量性負荷駆動回路３０１における段数のみを６段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数τ０とスイッチ時間Ｔｓとの比ｘ＝Ｔｓ／τ０に対するスルーレート（１０％−９０％）ＳＲの変化の変化は、図５６に示すようになる。なお、図５６には示していないが、負荷容量比Ｘが０．００３〜０．１の場合も、負荷容量比Ｘが０．００１の場合とほぼ同様であった。
【０２３６】
以上の結果から、駆動パルスの１周期の間における個々のコンデンサによる充電ステップの実行回数（段数）をＮとすると、スルーレート（１０％−９０％）ＳＲの限界値は、
Ｎ＝２（２段）の場合、ＳＲ＝Ｖ／（Ｒ・Ｃｄ）＊（０．００９ｙ^２−０．１００ｙ＋０．３８６）
Ｎ＝３（３段）の場合、ＳＲ＝Ｖ／（Ｒ・Ｃｄ）＊（０．０７１ｙ^２−０．２２９ｙ＋０．４１４）
Ｎ＝４（４段）の場合、ＳＲ＝Ｖ／（Ｒ・Ｃｄ）＊（０．１３８ｙ^２−０．３３６ｙ＋０．４３４）
Ｎ≧５（５段以上）の場合、ＳＲ＝Ｖ／（Ｒ・Ｃｄ）＊（０．１５３ｙ^２−０．３５６ｙ＋０．４１３）
で表されることが分かった。したがって、スルーレート設計の上で、上の式を基準にスイッチング時間および段数を設定することができる。
【０２３７】
従って、装置に要求されるスルーレートＳＲを満たすために回路パラメータ、スイッチ時間は、
Ｎ＝２（２段）の場合、ＳＲ≦Ｖ／（Ｒ・Ｃｄ）＊（０．００９ｙ^２−０．１００ｙ＋０．３８６）
Ｎ＝３（３段）の場合、ＳＲ≦Ｖ／（Ｒ・Ｃｄ）＊（０．０７１ｙ^２−０．２２９ｙ＋０．４１４）
Ｎ＝４（４段）の場合、ＳＲ≦Ｖ／（Ｒ・Ｃｄ）＊（０．１３８ｙ^２−０．３３６ｙ＋０．４３４）
Ｎ≧５（５段以上）の場合、ＳＲ≦Ｖ／（Ｒ・Ｃｄ）＊（０．１５３ｙ^２−０．３５６ｙ＋０．４１３）
であればよい。
【０２３８】
さらに、インクジェット方式などの５０（Ｖ／μｓｅｃ）以上の高スルーレートが必要な装置においては下記の条件を満たす必要がある。
【０２３９】
Ｎ＝２（２段）の場合、５０（Ｖ／μｓｅｃ）≦Ｖ／（Ｒ・Ｃｄ）＊（０．００９ｙ^２−０．１００ｙ＋０．３８６）
Ｎ＝３（３段）の場合、５０（Ｖ／μｓｅｃ）≦Ｖ／（Ｒ・Ｃｄ）＊（０．０７１ｙ^２−０．２２９ｙ＋０．４１４）
Ｎ＝４（４段）の場合、５０（Ｖ／μｓｅｃ）≦Ｖ／（Ｒ・Ｃｄ）＊（０．１３８ｙ^２−０．３３６ｙ＋０．４３４）
Ｎ≧５（５段以上）の場合、５０（Ｖ／μｓｅｃ）≦Ｖ／（Ｒ・Ｃｄ）＊（０．１５３ｙ^２−０．３５６ｙ＋０．４１３）である。
【０２４０】
また、図５２〜図５６の結果から、回路の段数を増加させると波形のスルーレートは減少することが分かる。
【０２４１】
〔実施の形態６〕
本発明の容量性負荷駆動回路は、複数のエネルギー蓄積素子に蓄積した静電エネルギーを容量性負荷に供給することによって容量性負荷を充電した後、容量性負荷の放電によるエネルギーをエネルギー蓄積素子に回収することによってエネルギー蓄積素子の蓄積静電エネルギーを容量性負荷への供給前とほぼ同し電位まで回生するようになっているが、この回生は限られた時間の間に行われるため、完全に元の電位に戻るわけではない。そのため、初期電位を付与した後、エネルギーを注入することなく繰り返し充放電を行った場合、図４０に示すように、各エネルギー蓄積素子の電圧のドリフト（最高電位と最低電位との中間値に近づく現象）が起こる。すなわち、最高電位と最低電位との中間値より高い初期電位を持つエネルギー蓄積素子は、容量性負荷からのエネルギーの回収が不足し、電位が上昇していく。一方、最高電位と最低電位との中間値より低い初期電位を持つエネルギー蓄積素子は、容量性負荷からのエネルギーの回収が過剰になり、電位が上昇していく。
【０２４２】
なお、図４０は、図１２の容量性負荷駆動回路３０１の段数を６段に変更した構成の、コンデンサＣ（１）〜Ｃ（５）を備える容量性負荷駆動回路において、電源電圧を６等分に分割した初期電位をコンデンサＣ（１）〜Ｃ（５）に付与した後にエネルギーを注入することなく繰り返し容量性負荷３１１の充放電を行ったときのコンデンサＣ（１）〜Ｃ（５）の電圧変化を示す図である。
【０２４３】
そこで、実施の形態５の容量性負荷駆動回路３０２に対して、接地端子Ｃ（０）と、電力源３０９に接続されたコンデンサＣ（Ｎ）とを除くコンデンサＣ（１）〜Ｃ（Ｎ−１）に対応する電力源３３９（１）〜３３９（Ｎ−１）（直流電源）を有し、電力源３３９（１）〜３３９（Ｎ−１）とコンデンサＣ（１）〜Ｃ（Ｎ−１）とを抵抗回路Ｒ（１）〜Ｒ（Ｎ−１）で接続し、電力源３３９（１）〜３３９（Ｎ−１）からエネルギーを注入することによって、上述した電圧のドリフトを防止するようにしている。
【０２４４】
図２１に示すように、実施の形態５の容量性負荷駆動回路３０２に対して、コンデンサＣ（１）〜Ｃ（Ｎ−１）にそれぞれ接続された電力源３３９（１）〜３３９（Ｎ−１）およびそれに付随する抵抗Ｒ（１）〜Ｒ（Ｎ−１）を追加した構成でもよく、図２０に示すように、接地端子Ｃ（０）に代えて、電力源３０９と同極性の第２の電力源（基準電源、基準電位端子、直流電源）３１９およびコンデンサＣ（０）を備える以外は、実施の形態５の容量性負荷駆動回路３０２と同様の構成を備えている容量性負荷駆動回路３０３に対して、それぞれコンデンサＣ（１）〜Ｃ（Ｎ−１）に接続された電力源３３９（１）〜３３９（Ｎ−１）およびそれに付随する抵抗Ｒ（１）〜Ｒ（Ｎ−１）を追加した構成でもよい。図２１に示す構成の場合、例えば図２２に示すパルスを発生できる。
【０２４５】
ここで、電力源３３９（１）〜３３９（Ｎ−１）とコンデンサＣ（１）〜Ｃ（Ｎ−１）との間に設けられる抵抗Ｒ（１）…Ｒ（Ｎ−１）について、抵抗Ｒ（１）…Ｒ（Ｎ−１）とコンデンサＣ（１）〜Ｃ（Ｎ−１）の容量成分と定まる時定数が、容量性負荷３１１に印加される駆動パルスの周期の５０倍以上あることが好ましい。
【０２４６】
すなわち、容量性負荷３１１に印加される駆動パルスの周期（図２２参照）を発生パルス周期Ｔｐ、コンデンサＣ（ｉ）（ｉ＝１、…、Ｉ−１、Ｉ、Ｉ＋１、…、Ｎ−１）の静電容量をＣ（ｉ）、電力源３３９（Ｉ）とコンデンサＣ（Ｉ）との間に設けられる抵抗Ｒ（ｉ）の抵抗値をＲ（ｉ）とすると、コンデンサＣ（ｉ）の時定数τ（ｉ）は、
τ（ｉ）＝Ｃ（ｉ）×Ｒ（ｉ）
となる。ここで、
Ｔｐ＊１０≦τ（ｉ）＝Ｃ（ｉ）×Ｒ（ｉ）
であることが好ましく、
Ｔｐ×５０≦τ（ｉ）＝Ｃ（ｉ）×Ｒ（ｉ）
であることがより好ましい。
【０２４７】
その理由を以下に説明する。
【０２４８】
電力源３３９（１）〜３３９（Ｎ−１）からの電力供給速度が速すぎると、本発明回路による回生が行われる前に電力源３３９（１）〜３３９（Ｎ−１）から電力供給が行われてしまい、系全体の電力回生効率の悪化を招く。
【０２４９】
容量性負荷３１１へのエネルギー注入と回生の時間間隔中の電力源３３９（１）〜３３９（Ｎ−１）からの電力供給を５％以内に抑えるために、電力源３３９（１）〜３３９（Ｎ−１）からの電力供給の時定数は３１１へのエネルギー注入から回生までの時間間隔の２０倍以上あればよい。また、容量性負荷３１１へのエネルギー注入と回生の時間間隔中の電力源３３９（１）〜３３９（Ｎ−１）からの電力供給を１％以内に抑えるために、電力源３３９（１）〜３３９（Ｎ−１）からの電力供給の時定数は容量性負荷３１１へのエネルギー注入から回生までの時間間隔の１００倍以上あればよい。
【０２５０】
一方、エネルギーの注入から回生までの時間間隔の最大は、発生パルス周期Ｔｐの１／２と考えられる。従って、電力源３３９（１）〜３３９（Ｎ−１）からの電力供給の時定数τ（ｉ）は、発生パルス周期Ｔｐの１０倍以上あれば、容量性負荷３１１へのエネルギー注入と回生の時間間隔中の電力源３３９（１）〜３３９（Ｎ−１）からの電力供給を５％以内に抑えることができる。電力源３３９（１）〜３３９（Ｎ−１）からの電力供給の時定数τ（ｉ）は、発生パルス周期Ｔｐの５０倍以上あれば、３１１へのエネルギー注入と回生の時間間隔中の電力源３３９（１）〜３３９（Ｎ−１）からの電力供給を１％以内に抑えることができ、電力回生への影響はほぼ無視できる。
【０２５１】
τ（ｉ）／Ｔｐの上限についての明確な制限は存在しないが、τ（ｉ）／Ｔｐが大きすぎると電力源３３９（１）〜３３９（Ｎ−１）からの供給が行われないことになり、なんらかの理由でエネルギーの供給と回生の間にアンバランスが生じた場合、系の安定化が図れなくなる。つまり電力源３３９（１）〜３３９（Ｎ−１）からの電力供給の時定数τ（ｉ）はエネルギー回生率への影響が少ない範囲でできる限り小さい値が好ましい。
【０２５２】
〔実施の形態７〕
マトリクス型表示装置は、表示素子アレイ（表示素子）３４０、列選択ドライブ回路３４１、行選択ドライブ回路３４２、および行選択ドライブ回路３４２に電力を供給するための電力源３４９を備える。表示素子アレー３４０は、行選択ドライブ回路（駆動回路）３４２と列選択ドライブ回路（駆動回路）３４１とより選択され、特定パルスが印加される。ここで言う表示素子アレイとは、液晶表示素子アレイ、放電ディスプレイ（プラズマディスプレイ）、ＥＬ素子アレイなどを示す。このとき、列選択ドライブ回路３４１に列パルスを供給するための列パルス発生回路として本発明の容量性負荷駆動回路を用いることで列パルスの発生と表示素子アレイからの電力の回収を行う。図３２では、前記実施の形態６の容量性負荷駆動回路３０５を列パルス発生回路（電力回生回路を含む）として用いた場合を示しているが、容量性負荷駆動回路の構成は特に限定されるものではない。
【０２５３】
なお、行選択ドライブ回路３４２側にパルス発生装置が必要な場合、電力源３４９の代わりに本発明の容量性負荷駆動回路を用いてもよい。
【０２５４】
〔実施の形態８〕
インクジェットプリンタにおいては、公知であるセラミック等の圧電材料を利用した剪断モード型の記録ヘッド（例えば特開昭６３−２４７０５１号公報）を使用できる。剪断モード型のインクジェットプリンタに用いられる記録ヘッドの構成及び機能について、以下に説明する。
【０２５５】
図３３は、記録ヘッドにおける一部分を、記録媒体側から見た状態で示した平面図である。一方、図３４は、記録ヘッドの縦断面図である。
【０２５６】
図３３に示すように、記録ヘッド１１００は、圧電材料２００と、天板３００と、複数のインク室４００とを備えている。
【０２５７】
圧電材料２００は櫛歯状に形成されており、各櫛歯の隙間にインク室４００…が嵌め込まれるように形成されている。
【０２５８】
インク室４００は、両側面に形成された駆動電極５００と、吐出ノズル６００とを備えている。このインクジェットプリンタでは、隣接するインク室４００の駆動電極５００同士の間に電界を発生させることにより吐出ノズル６００からインクを吐出する。詳細は後述する。
【０２５９】
天板３００は、複数のインク室４００を圧電材料２００中に嵌合させるためのものであり、導電性樹脂からなる接続電極を備えている。
【０２６０】
また、図３４に示すように、インクは、記録ヘッド１１００内のインクタンク７００内に蓄えられており、複数のインク室４００における吐出ノズル６００に接続された共通インクパス８００を介して、後述する手順により吐出ノズルから吐出される。
【０２６１】
次に、剪断モード型のインクジェットプリンタがインクを吐出する状態について説明する。なお、以下の説明では、隣り合う３つのインク室をそれぞれＡチャンネル・Ｂチャンネル・Ｃチャンネルとして区別する。また、以下の説明では、Ｂチャンネルのインク室からインクを吐出する場合について説明するが、Ａチャンネル・Ｃチャンネルのインク室からのインク吐出についても同様である。
【０２６２】
この記録ヘッド１１００は、Ａチャンネル・Ｂチャンネル・Ｃチャンネルのインク室の駆動電極５００（容量性負荷）を、本発明に係る容量性負荷駆動回路で駆動する構成となっている。
【０２６３】
図３５（ａ）に示すように、インクの吐出を行わない通常状態において、Ａチャンネル・Ｂチャンネル・Ｃチャンネルのインク室のうち、いずれのインク室の駆動電極にも電界が付与されていない。また、圧電材料は、駆動電極の表面と平行な方向即ち駆動電界に直交する方向に分極している。
【０２６４】
その後、図３６に示すように、Ｂチャンネルのインク室の駆動電極５００に対して吐出パルスを与える。一方、Ａチャンネル・Ｂチャンネルのインク室については、吐出パルスは与えない。
【０２６５】
そうすると、Ｂチャンネルのインク室の駆動電極５００から、ＡチャンネルおよびＣチャンネルのインク室の駆動電極５００に向かって電界が発生する。この電界の向きにしたがって、圧電材料は移動しようとする。その結果、図３５（ｂ）に示すように、Ｂチャネルのインク室の側壁が拡張する。
【０２６６】
その後、図３６に示すように、共通パルスを、ＡチャンネルおよびＣチャンネルのインク室の駆動電極５００について与える。そうすると、ＡチャンネルおよびＣチャンネルのインク室の駆動電極５００から、Ｂチャンネルのインク室の駆動電極５００に向かって電界が生じる。その結果、図３５（ｃ）に示すように、Ｂチャンネルのインク室の側壁が収縮し、Ｂチャンネルのインク室内の体積が減少する。これによって、Ｂチャンネルのインク室の吐出ノズルからインクが吐出する。
【０２６７】
なお、いずれのチャンネルからもインクを吐出しない場合は、ＡチャンネルおよびＣチャンネルのインク室の駆動電極５００に共通パルスを与えると同時に、Ｂチャンネルのインク室の駆動電極５００に、共通パルスと同じ電位の非吐出パルスを与える。これにより、Ａ〜Ｃチャンネルのインク室の駆動電極５００は同じ電位となるので、各駆動電極間５００に電界は発生しなくなる。したがって、いずれのチャンネルのインク室も、側壁が拡張したり収縮したりすることがないので、インク吐出は行われない。
【０２６８】
このように、記録ヘッド１１００は、順次に行われる吐出のＡ〜Ｃチャンネルの切替えを繰り返して吐出すること、即ち３相駆動することによりにより印字動作を成し遂げるものである。
【０２６９】
また、吐出パルスを与える時間ＡＬ、共通パルスを与える時間ＡＬ’は、以下の式▲１▼によって決定される。
【０２７０】
ＡＬ（ ｏｒ ＡＬ’）＝インク室長さ／インク中における音速 …▲１▼
したがって、３つのチャンネルのインク室長さがすべて同じであれば、
ＡＬ’＝２ＡＬ
となる。なお、一般的なインクジェットプリンタであれば、ＡＬ＝２μｓ程度である。
【０２７１】
〔実施の形態９〕
次に、インクを記録媒体へ吐出して印刷を行うインクジェットプリンタの回復動作時の吐出動作を改良し、実施の形態８よりも高精度かつ高速度に印刷を行うことが可能なインクジェットプリンタの実施の一形態について説明する。
【０２７２】
図３７に示すように、インクジェットプリンタ１００１は、給紙部（給紙装置）１００２、分離部１００３、搬送部１００４、印刷部（印字部）１００５および排出部１００６から構成される。
【０２７３】
給紙部１００２とは、印刷を行う際にシートＰを供給するものであり、給紙トレイ１００７および図示されないピックアップローラよりなる。印刷を行わない際には、シートＰを保管する機能を果たす。
【０２７４】
分離部１００３は、給紙部１００２より供給されるシートＰを、印刷部１００５へ一枚ずつ供給するためのものであり、給紙ローラ１００８および分離装置１００９よりなる。分離装置１００９では、パッド部分（シートとの接触部分）とシートとの摩擦が、シート間の摩擦より大きくなるように設定されている。また、給紙ローラ１００８では、給紙ローラ１００８とシートとの摩擦が、パッドとシートとの摩擦や、シート間の摩擦よりも大きくなるように設定されている。そのため、２枚のシートが分離部１００３まで送られてきたとしても、給紙ローラ１００８によって、これらのシートを分離し、上側のシートのみを搬送部１００４に送ることができる。
【０２７５】
搬送部１００４は、分離部１００３より一枚ずつ供給されるシートＰを、印刷部１００５へと搬送するためのものであり、ガイド板１０１０およびローラ対１０１１（搬送機構）よりなる。ローラ対１０１１は、シートＰを記録ヘッド１１００とプラテン１０１３の間に送り込む際に、記録ヘッド１１００からのインクがシートＰの適切な位置に吹き付けられるように、シートＰの搬送を調整する部材である。
【０２７６】
印刷部１００５は、搬送部４のローラ対１０１１より供給されるシートＰへ印刷を行うためのものであり、記録ヘッド１１００（印字ヘッド）、記録ヘッド１１００を搭載したキャリッジ１０１４、キャリッジ１０１４を案内するための部材であるガイドシャフト１０１５（図３８参照）、および印刷時にシートＰの台となるプラテン１０１３より構成される。
【０２７７】
排出部１００６は、印刷が行われたシートＰをインクジェットプリンタ１００１の外へ排出するためのものであり、インク乾燥部（図示されない）、排出ローラ１０１６および排出トレイ１０１７よりなる。
【０２７８】
上記の構成において、インクジェットプリンタ１００１は、次のような動作によって印刷を行う。
【０２７９】
まず、図示しないコンピュータ等から、画像情報に基づく印刷要求が、インクジェットプリンタ１００１に対してなされる。印刷要求を受信したインクジェットプリンタ１００１は、給紙トレイ１００７上のシートＰを、ピックアップローラによって給紙部１００２より搬出する。
【０２８０】
次に、搬出されたシートＰは、給紙ローラ１００８によって分離部１００３を通過し、搬送部１００４へと送られる。搬送部１００４では、ローラ対１０１１によって、シートＰを記録ヘッド１０１２とプラテン１０１３の間へと送る。
【０２８１】
そして、印刷部１００５では、記録ヘッド１０１２の吐出ノズルよりプラテン１０１３上のシートＰへ、画像情報に対応してインクが吹き付けられる。この時、シートＰはプラテン１０１３上で一端停止されている。インクを吹き付けつつ、キャリッジ１０１４は、ガイドシャフト１０１５に案内されて、主走査方向Ｄ２に渡って一ライン分走査される。それが終了すると、シートＰは、プラテン１０１３上で副走査方向Ｄ１に一定の幅だけ移動させられる。印刷部１００５において、上記処理が画像情報に対応し継続して実施されることにより、シートＰ全面に印刷がなされる。
【０２８２】
印刷が行われたシートＰは、インク乾燥部を経て、排出ローラ１０１６によって排出トレイ１０１７に排出される。その後、シートＰは印刷物としてユーザに提供される。
【０２８３】
次に、本実施の形態のインクジェットプリンタ１００１の制御系について説明する。
【０２８４】
図３９に示すように、インクジェットプリンタ１００１の制御部１０１８は、インターフェース部１０１９と、メモリ１０２０と、画像処理部１０２１と、駆動系制御部１０２２とを備えている。
【０２８５】
インターフェース部１０１９は、外部機器と画像処理部１０２１および駆動系制御部１０２２との信号のやりとりを行う回路である。
【０２８６】
画像処理部１０２１は、インターフェース部１０１９からの画像情報に基づいて画像処理を行う。また、画像処理部１０２１は、記録ヘッド１１００の駆動を制御するヘッド駆動回路１０２３に接続されている。
【０２８７】
駆動系制御部１０２２は、キャリッジ１０１４の駆動、およびシートＰの搬送を制御する。具体的には、駆動系制御部１０２２は、キャリッジモータの駆動を制御するキャリッジ駆動回路１０２４、および用紙搬送モータの駆動を制御する用紙搬送駆動回路１０２５とに接続されている。
【０２８８】
以上の構成により、インクジェットプリンタは記録ヘッド１１００、キャリッジ１０１４、用紙搬送モータ等を駆動し、印刷作業を行う。
【０２８９】
次に、本実施の形態の特徴点である記録ヘッド１１００のインク吐出動作について説明する。
【０２９０】
記録ヘッド１１００は、図３３に示す圧電材料２００と、天板３００と、複数のインク室４００と、駆動電極５００とを備える、剪断モード型のインクジェットプリンタに用いられるものである。
【０２９１】
印字のための吐出動作においては、複数のインク室４００は、隣り合う３つのインク室をＡチャンネル、Ｂチャンネル、およびＣチャンネルに分け３相駆動を行う。この記録ヘッド１１００は、Ａチャンネル・Ｂチャンネル・Ｃチャンネルのインク室の駆動電極５００（容量性負荷）を、本発明に係る容量性負荷駆動回路で駆動する構成となっている。この駆動は、図３５および図３６を用いて詳細説明した３相駆動であり、ここでは説明を省略する。
【０２９２】
【発明の効果】
本発明の装置は、以上のように、容量性負荷駆動回路は、電源から電源電位が付与された電源端子と、基準電源から供給された電源電位と異なる基準電源電位、または接地電位が基準電位として付与された基準電位端子と、基準電位と電源電位との間の初期電位が付与されたエネルギー蓄積素子と、基準電位端子、エネルギー蓄積素子、および電源端子を選択的に容量性負荷と接続するための切り替え手段とを備え、上記切り替え手段は、基準電位端子を容量性負荷に接続した後にエネルギー蓄積素子を容量性負荷に接続する第１の充電ステップと、その後に容量性負荷を電源端子と選択的に接続する第２の充電ステップと、その後にエネルギー蓄積素子を容量性負荷に接続する放電ステップとを実行するようになっており、エネルギー蓄積素子の静電容量成分をＣｓ、容量性負荷の静電容量をＣｄ、エネルギー蓄積素子の接続が持続される時間をＴｓ、切り替え手段を含む、容量性負荷に対するエネルギー蓄積素子の充放電経路の抵抗値をＲとすると、
Ｔｓ／（Ｒ・Ｃｄ）＜２．５の場合
Ｃｄ／Ｃｓ≦０．１６４｛Ｔｓ／（Ｒ・Ｃｄ）｝^{０．２１９８}
Ｔｓ／（Ｒ・Ｃｄ）≧２．５の場合
Ｃｄ／Ｃｓ≦０．２
が成立する構成である。
【０２９３】
また、本発明の装置は、以上のように、容量性負荷駆動回路は、電源から電源電位が付与された電源端子と、基準電源から供給された電源電位と異なる基準電源電位、または接地電位が基準電位として付与された基準電位端子と、基準電位と電源電位との間で、かつ互いに異なる初期電位が付与された複数のエネルギー蓄積素子と、基準電位端子、複数のエネルギー蓄積素子、および電源端子を選択的に容量性負荷と接続するための切り替え手段とを備え、上記切り替え手段は、基準電位端子を容量性負荷に接続した後に各エネルギー蓄積素子をその初期電位が基準電位に近い方から順に容量性負荷に接続する第１の充電ステップと、その後に容量性負荷を電源端子と選択的に接続する第２の充電ステップと、その後に各エネルギー蓄積素子をその初期電位が電源電位に近い方から順に容量性負荷に接続する放電ステップとを実行するようになっており、エネルギー蓄積素子の静電容量成分をＣｓ、容量性負荷の静電容量をＣｄ、エネルギー蓄積素子の接続が持続される時間をＴｓ、切り替え手段を含む、容量性負荷に対するエネルギー蓄積素子の充放電経路の抵抗値をＲとすると、
Ｔｓ／（Ｒ・Ｃｄ）＜２．５の場合
Ｃｄ／Ｃｓ≦０．１６４｛Ｔｓ／（Ｒ・Ｃｄ）｝^{０．２１９８}
Ｔｓ／（Ｒ・Ｃｄ）≧２．５の場合
Ｃｄ／Ｃｓ≦０．２
が成立する構成である。
【０２９４】
上記各構成によれば、容量性負荷の端子電圧の絶対値を減少させて容量性負荷を放電させたときに、第１のエネルギー蓄積素子の蓄積静電エネルギーを、容量性負荷へのエネルギー供給前とほぼ等しくなるように回生することができる。したがって、第１のエネルギー蓄積素子が見かけ上エネルギーを消費しなくなり、高い効率で電力回生を行うことができる。
【０２９５】
さらに、上記各構成によれば、第１〜第３のステップの間に、容量性負荷の電圧が、最終到達電圧（第１の充電ステップを無限時間継続したときに容量性負荷の電圧が到達する最終の電圧）の９０％に到達する。これにより、エネルギー蓄積素子から容量性負荷への電荷の流出によるエネルギー蓄積素子の電圧変化が小さくなり、パルス発生時の電力回生率が良好となり、消費電力をより一層低減できる。また、１回のパルス発生によるエネルギー蓄積素子の電圧変化が小さくなるので、この電圧変化を補正することなく次のパルス発生を行うことが可能となる。
【図面の簡単な説明】
【図１】本発明の実施の一形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図２】図１の容量性負荷駆動回路の動作を示すタイミングチャートであり、（ａ）は同期信号の波形図、（ｂ）はトランジスタの制御電圧の波形図、（ｃ）はコンデンサへの印加電圧の波形図である。
【図３】図２に示すタイミングチャートの一部を拡大して示すと共にスイッチの動作状態を示すものであり、（ａ）は同期信号の波形図、（ｂ）はスイッチの動作状態を示すタイミングチャート、（ｃ）はトランジスタの制御電圧の波形図、（ｄ）は、コンデンサへの印加電圧の波形図である。
【図４】本発明のさらに他の実施の形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図５】本発明の実施の一形態に係るインクジェットプリンタ（画像形成装置）の要部を示す斜視図である。
【図６】図３のインクジェットプリンタ（画像形成装置）が備えるインクジェットヘッドの構成を示す断面図である。
【図７】従来の容量性負荷駆動回路の一例を示す図であり、（ａ）は容量性負荷駆動回路の構成を示す回路図、（ｂ）（ｃ）は容量性負荷駆動回路が備える２つのトランジスタの動作を制御する制御電圧の波形図、（ｄ）は駆動されるコンデンサの端子電圧の波形図、（ｅ）は容量性負荷駆動回路の抵抗に流れる電流の波形図である。
【図８】従来の容量性負荷駆動回路の一例を示す回路図である。
【図９】（ａ）〜（ｅ）は図９に示す従来の容量性負荷駆動回路の動作を説明するための回路図である。
【図１０】従来の容量性負荷駆動回路の他の一例を示す回路図である。
【図１１】図１０に示す従来の容量性負荷駆動回路の動作を説明するための波形図であり、容量性負荷の端子電圧およびスイッチの状態を示している。
【図１２】本発明のさらに他の実施の形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図１３】（ａ）〜（ｅ）は、図１２に示す容量性負荷駆動回路の動作を説明するための回路図である。
【図１４】（ａ）〜（ｄ）は、図１２に示す容量性負荷駆動回路の動作を説明するための回路図である。
【図１５】図１２に示す容量性負荷駆動回路の動作を説明するための波形図である。
【図１６】本発明のさらに他の実施の形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図１７】（ａ）〜（ｆ）は、図１６に示す容量性負荷駆動回路の動作を説明するための回路図である。
【図１８】図１６に示す容量性負荷駆動回路によって発生されるパルスの一例の波形を示す波形図である。
【図１９】図１６に示す容量性負荷駆動回路によって発生されるパルスの他の一例の波形を示す波形図である。
【図２０】本発明のさらに他の実施の形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図２１】本発明のさらに他の実施の形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図２２】図２１に示す容量性負荷駆動回路によって発生されるパルスの一例の波形を示す波形図である。
【図２３】本発明の原理を説明するための回路図の１つである。
【図２４】本発明の原理を説明するための図の１つであり、（ａ）は電圧変化を示すグラフ、（ｂ）は電流変化を示すグラフである。
【図２５】本発明の原理を説明するための他の回路図である。
【図２６】本発明の原理を説明するための他の回路図である。
【図２７】本発明にかかる容量性負荷駆動回路における１つのコンデンサから容量性負荷へのエネルギー供給を模式的に表した図である。
【図２８】コンデンサからのエネルギー供給による容量性負荷の電圧変化を示すグラフである。
【図２９】（ａ）１つのコンデンサからのエネルギー供給による容量性負荷の電圧変化を示すグラフであり、（ｂ）は本発明にかかる容量性負荷駆動回路における複数のコンデンサからのエネルギー供給による容量性負荷の電圧変化を示すグラフであり、いずれも、コンデンサからのスイッチング時間（Ｔｓ）が時定数（Ｒ・Ｃｄ）より短い場合を示す。
【図３０】（ａ）１つのコンデンサからのエネルギー供給による容量性負荷の電圧変化を示すグラフであり、（ｂ）は本発明にかかる容量性負荷駆動回路における複数のコンデンサからのエネルギー供給による容量性負荷の電圧変化を示すグラフであり、いずれも、スイッチング時間（Ｔｓ）が時定数と等しい場合を示す。
【図３１】（ａ）１つのコンデンサからのエネルギー供給による容量性負荷の電圧変化を示すグラフであり、（ｂ）は本発明にかかる容量性負荷駆動回路における複数のコンデンサからのエネルギー供給による容量性負荷の電圧変化を示すグラフであり、いずれも、、スイッチング時間（Ｔｓ）が時定数より長い場合を示す。
【図３２】本発明の実施の一形態にかかる容量性負荷駆動回路を用いた表示装置を示す図である。
【図３３】記録ヘッドにおける一部分を記録媒体側から見た状態で示した平面図である。
【図３４】記録ヘッドの縦断面図である。
【図３５】（ａ）〜（ｃ）は、図３４の記録ヘッドの動作を説明するための断面図である。
【図３６】図３４の記録ヘッドの動作を説明するためのパルス波形図である。
【図３７】本発明の他の実施の形態にかかる容量性負荷駆動回路を用いたインクジェットプリンタ（画像形成装置）を示す断面図である。
【図３８】本発明の他の実施の形態にかかる容量性負荷駆動回路を用いたインクジェットプリンタ（画像形成装置）を示す斜視図である。
【図３９】図３７のインクジェットプリンタ（画像形成装置）の制御系を示すブロック図である。
【図４０】本発明の実施の一形態にかかる容量性負荷駆動回路において繰り返し容量性負荷の充放電を行ったときのエネルギー蓄積素子の電圧変化を示す図である。
【図４１】本発明のさらに他の実施の形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図４２】図４１の容量性負荷駆動回路の動作を示すタイミングチャートであり、（ａ）は同期信号の波形図、（ｂ）はスイッチの制御電圧の波形図、（ｃ）はコンデンサへの印加電圧の波形図である。
【図４３】図４２に示すタイミングチャートの一部を拡大して示すと共にスイッチの動作状態を示すものであり、（ａ）は同期信号の波形図、（ｂ）はスイッチの動作状態を示すタイミングチャート、（ｃ）はスイッチ（切り替え手段）の制御電圧の波形図、（ｄ）は、コンデンサへの印加電圧の波形図である。
【図４４】本発明のさらに他の実施の形態に係る容量性負荷駆動回路の構成を示す回路図である。
【図４５】本発明の実施の一形態に係る容量性負荷駆動方法を示すフローチャートである。
【図４６】図１２に示す容量性負荷駆動回路において、時定数とスイッチ時間との比に対して、第１〜第３のステップの間に容量性負荷の電圧が到達電圧の９０％以上となる最大の負荷容量比を表すグラフである。
【図４７】図１２に示す４段の容量性負荷駆動回路における段数のみを２段に変更した容量性負荷駆動回路において、負荷容量比を０．００３から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスイッチング素子のエネルギー消費率の変化を表すグラフである。
【図４８】図１２に示す４段の容量性負荷駆動回路における段数のみを３段に変更した容量性負荷駆動回路において、負荷容量比を０．００３から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスイッチング素子のエネルギー消費率の変化を表すグラフである。
【図４９】図１２に示す４段の容量性負荷駆動回路において、負荷容量比を０．００３から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスイッチング素子のエネルギー消費率の変化を表すグラフである。
【図５０】図１２に示す４段の容量性負荷駆動回路における段数のみを５段に変更した容量性負荷駆動回路において、負荷容量比を０．００３から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスイッチング素子のエネルギー消費率の変化を表すグラフである。
【図５１】図１２に示す４段の容量性負荷駆動回路における段数のみを６段に変更した容量性負荷駆動回路において、負荷容量比を０．００３から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスイッチング素子のエネルギー消費率の変化を表すグラフである。
【図５２】図１２に示す４段の容量性負荷駆動回路における段数のみを２段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００１から０．１まで変化させたときの、時定数とスイッチ時間との比に対するスルーレート（１０％−９０％）の変化を表すグラフである。
【図５３】図１２に示す４段の容量性負荷駆動回路における段数のみを３段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００１から０．１まで変化させたときの、時定数とスイッチ時間との比に対するスルーレート（１０％−９０％）の変化を表すグラフである。
【図５４】図１２に示す４段の容量性負荷駆動回路において、負荷容量比を０．００１から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスルーレート（１０％−９０％）の変化を表すグラフである。
【図５５】図１２に示す４段の容量性負荷駆動回路における段数のみを５段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスルーレート（１０％−９０％）の変化を表すグラフである。
【図５６】図１２に示す４段の容量性負荷駆動回路における段数のみを６段に変更した容量性負荷駆動回路において、負荷容量比Ｘを０．００３から０．３まで変化させたときの、時定数とスイッチ時間との比に対するスルーレート（１０％−９０％）の変化を表すグラフである。
【符号の説明】
１ 容量性負荷駆動回路
２ａ〜２ｉ コンデンサ（エネルギー蓄積素子）
３ 蓄電器
４ 抵抗
５ 分圧器（分圧手段）
６ トランジスタ（スイッチング部）
７ スイッチ（切り替え手段）
９ 電源端子
１１ コンデンサ（容量性負荷）
１６Ａ スイッチ（スイッチング部）
２１ 圧電素子（容量性負荷）
２３ インクジェットヘッド
２１０ インクジェットプリンタ（画像形成装置）
３０１，３０２，３０３，３０５ 容量性負荷駆動回路
３０９，３１９，３３９ 電力源（電源、直流電源）
３１１ 容量性負荷
Ｃ（０） 接地端子（基準電位端子）
Ｃ（１）〜Ｃ（３），Ｃ（０）〜Ｃ（Ｎ） コンデンサ（エネルギー蓄積素子）
Ｓ（０）〜Ｓ（４），Ｓ（０）〜Ｓ（Ｎ） スイッチング素子（切り替え手段）
Ｒ（１）〜Ｒ（Ｎ−１） 抵抗回路
ＳＷ１〜ＳＷ９ スイッチ（スイッチング部）[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a device including a capacitive load and a capacitive load driving circuit for charging and discharging the capacitive load. More specifically, the present invention relates to an image forming apparatus using a piezoelectric element or an electrostatic drive electrode, which is a capacitive load, for discharging ink, a discharge electrode of a plasma display, or a drive circuit of a liquid crystal display. Forming device, display device, voltage pulse generator, direct current (DC) -alternating current (AC) converter (converter), etc., which includes a capacitive load and a capacitive load driving circuit for charging and discharging the capacitive load. It concerns the device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, inkjet printers such as an inkjet printer using a piezoelectric element for ink ejection (for example, see Patent Literature 1 and Patent Literature 2), an electrostatic inkjet printer, and a thermal inkjet printer (for example, see Patent Literature 3) are known. Have been.
[0003]
2. Description of the Related Art In an ink jet printer using a piezoelectric element for discharging ink, a piezoelectric element is provided in a pressure generating chamber connected to a nozzle opening of an ink jet head. By applying a voltage to a piezoelectric element, which is a capacitive load, to generate a drive signal, and causing the piezoelectric element to repeat charging and discharging, ink is ejected from a nozzle opening. Here, a capacitive load driving circuit for driving such a capacitive load will be considered.
[0004]
FIG. 7 shows a drive circuit based on a push-pull circuit, which is an example of a conventional capacitive load drive circuit as described above. As shown in the circuit diagram of FIG. 7A, the capacitive load drive circuit is connected to a capacitor CL that is a capacitive load. With respect to the main voltage V applied to the capacitive load driving circuit, the capacitor CL includes a transistor Vupd provided in a charging path for supplying energy to the capacitor CL, and a discharging path for removing energy from the capacitor CL. Is driven by being controlled by the transistor Vdwnd provided in the first stage.
[0005]
FIGS. 7B and 7C show waveforms of control signals for controlling the operations of the transistors Vupd and Vdwnd. When the two transistors Vupd and Vdwnd operate according to the control signals of FIGS. 7B and 7C, the terminal voltage V0 of the capacitor CL changes with time as shown in FIG. Changes with time as shown in FIG.
[0006]
Therefore, in the push-pull method as shown in FIG. 7A, after the transistor Vupd is turned on to flow a charging current to the capacitive load via the charging path, the transistor Vdwnd is turned on to charge the transistor via the discharging path. Were all discharged to the ground.
[0007]
In the conventional capacitive load driving circuit, all the electric charges accumulated in the capacitor CL are discharged to the ground, so that all the electrostatic energy accumulated in the capacitor CL is discarded, and the power consumption is large. there were. For example, if the frequency f of Vupd is 126 kHz, the capacitance CL of the capacitor CL is 0.1 μF, and the main voltage V is 20 V, the average power supply current is
f × CL × V = 0.2520A
And the power consumption is 5.04W.
[0008]
Therefore, there has been proposed a capacitive load drive circuit that collects electric charge discharged from a capacitive load and reuses it for charging the capacitive load, thereby reducing power consumption. For example, Patent Document 4 discloses that during a printing operation, a secondary power supply (a secondary battery or a large-capacity capacitor) is charged by a mutual induction action of a magnetic circuit using a discharge current discharged from a piezoelectric element (piezoelectric vibration element). A print head drive circuit that uses the electric charge stored in the secondary power supply again for charging the piezoelectric element is disclosed.
[0009]
Further, in a driving circuit for driving a discharge cell of a plasma display panel, a technique for recovering power by LC resonance is known (see Patent Document 5). An example of a drive circuit that recovers power from such a discharge cell by LC resonance will be described with reference to FIG. In FIG. 10, Cd is a capacitive component (capacitive load) of the plasma display panel, which is a capacitive load, Css is a capacitor, S1 to S4 are switches, L is an inductor, D1 and D2 are rectifier diodes, and 2V0 is a power supply voltage. Power supply terminals for supplying 2V0 are shown.
[0010]
First, in the initial state, an initial potential V0 is applied to the capacitor Css. It is assumed that the potential of Cd in this initial state is 0. The capacitance Css of the capacitor Css is assumed to be sufficiently larger than the capacitance Cd of the capacitive load Cd.
[0011]
Next, a charging / discharging operation of the capacitive load Cd in the above configuration will be described with reference to FIG. 11 showing a change in the terminal voltage V of the capacitive load Cd and states of the switches S1 to S4. Note that the switches S1 to S4 are in the OFF state except for the period indicated as “On” in FIG.
[0012]
First, at the time of charging, only the switch S1 among the switches S1 to S4 is turned on. Then, a current flows from the capacitor Css to the capacitive load Cd through the inductor L, and the capacitive load Cd is charged ((1) in FIG. 11). The capacitive load Cd is charged by LC resonance until the terminal voltage V becomes equal to or higher than V0 ((2) in FIG. 11). When the current is to be reversed, the current is blocked by the rectifier diode D1, and the terminal voltage V of the capacitive load Cd is clamped ((3) in FIG. 11). Thereafter, the switch S1 is turned off, and then the switch S3 is turned on. Then, the capacitive load Cd is charged until the terminal voltage V becomes 2V0 ((4) in FIG. 11).
[0013]
At the time of discharging, the switch S3 is turned off, and then the switch S2 is turned on. As a result, a current flows from the capacitive load Cd to the capacitor Css through the inductor L, and the capacitive load Cd is discharged, while the capacitor Css is charged ((5) in FIG. 11). The capacitive load Cd is charged by LC resonance until the terminal voltage V becomes equal to or higher than V0 ([6] in FIG. 11). When the current is to be reversed, the current is blocked by the rectifier diode D2, and the terminal voltage V of the capacitive load Cd is clamped ((7) in FIG. 11). Thereafter, the switch S2 is turned off, and then the switch S4 is turned on. Then, the capacitive load Cd is discharged until the terminal voltage V becomes 0 ([8] in FIG. 11). As described above, in the above configuration, power can be recovered from the capacitive load Cd to the capacitor Css using LC resonance.
[0014]
In addition, there is a prior example in which a plurality of inductors L are switched and used in a circuit that performs power recovery by LC resonance as described above (see Patent Document 6).
[0015]
Patent Literatures 7 and 8 disclose a device in which an inductor is inserted for energy recovery.
[0016]
In addition, when discharging from a capacitive load, the charge is stored in the capacitor, and only the charge that cannot be stored is discharged to the ground, and when charging, the charge stored in the capacitor is used again to charge the piezoelectric element, and the charge is completed. There is known a method of supplying only unexposed charges from a power supply. For example, in Patent Document 9, in a drive circuit for a capacitive load such as an EL (electroluminescence) element, a capacitor is provided, and a part of the charged charge is transferred to the capacitor when discharging the capacitive load. A technique is disclosed in which a part of the electric charge charged in the capacitive load is reused by discharging the electric charge of the capacitor, returning the electric charge transferred to the capacitor to the capacitive load, and then starting the charging. Patent Document 9 discloses a method of recovering and reusing electrostatic energy, as shown in FIG. 8, in which one capacitor 263 collects electrostatic energy from a capacitive load (EL element) 261 and reuses it. Is disclosed.
[0017]
Next, a specific operation of the capacitive load driving circuit disclosed in Patent Document 9 will be described with reference to FIG. 8 and 9, in order to facilitate understanding of the operation principle, the drive voltage generation circuit described in Patent Document 9 is connected to a power supply terminal VH of the power supply voltage VH and the drive voltage generation circuit described in Patent Document 9 is used. The ON / OFF control of the generating circuit is schematically shown by a switch 262.
[0018]
First, as shown in FIG. 8A, the capacitive load 261 and the regenerative capacitor 263 are grounded via the ON-state switches 264 and 265 as an initial state. At this time, it is assumed that the switch 262 is turned off, and the supply of the driving voltage from the power supply terminal VH (the driving voltage generating circuit not shown) to the capacitive load 261 is stopped.
[0019]
Next, as shown in FIG. 9B, the switches 264 and 265 are turned off and the switch 262 is turned on. As a result, the power supply voltage VH is output from the power supply terminal VH to the capacitive load 261 via the switch 262 in the ON state, and the capacitive load 261 is charged by the power supply voltage VH from the power supply terminal VH. As a result, the terminal potential of the capacitive load 261 rises until it becomes equal to the power supply voltage VH.
[0020]
Next, as shown in FIG. 9C, the switch 262 is turned off and the switch 265 is turned on. As a result, the supply of the drive voltage from the power supply terminal VH to the capacitive load 261 is stopped, and one end of the capacitive load 261 is connected to the capacitor 263. As a result, a part of the electric charge charged in the capacitive load 261 moves to the capacitor 263, and the capacitive load 261 is discharged, and a part of the electrostatic energy stored in the capacitive load 261 is transferred to the capacitor 263. From the load 261 to the capacitor 263.
[0021]
Next, as shown in FIG. 9D, the switch 265 is turned off and the switch 264 is turned on. As a result, the remaining charge of the capacitive load 261 is discharged to the ground (power supply terminal not shown) via the switch 263. That is, the energy remaining in the capacitive load 261 is consumed through the switch 263. Therefore, by this step, the voltage of the capacitive load 261 becomes the ground potential.
[0022]
Further, in order to reuse the electrostatic energy collected in the capacitor 263 for the capacitive load 261 having the initial charge “0”, the switch 264 is turned off and the switch 265 is turned on as shown in FIG. To As a result, the charge stored in the capacitor 263 moves to the capacitive load 261, and power is regenerated from the capacitor 263 to the capacitive load 261.
[0023]
Thereafter, the operations of FIGS. 9A to 9E are repeated to drive the capacitive load 261. As described above, a part of the electric charge discharged (discharged) from the capacitive load 261 is collected in the capacitor 263 and returned to the capacitive load 261, whereby electric power is regenerated in the capacitive load 261.
[0024]
It is to be noted that there is also known a technique for collecting and reusing electric charges stored in a liquid crystal display panel to reduce power consumption (see Patent Documents 10 to 12).
[0025]
Patent Document 13 discloses a motor control circuit.
[0026]
[Patent Document 1]
JP-A-63-247051 (publication date: October 13, 1988)
[0027]
[Patent Document 2]
Japanese Patent Application Laid-Open No. 2001-10043 (publication date: January 16, 2001)
[0028]
[Patent Document 3]
JP 2000-238245 A (Publication date: September 5, 2000 (2000))
[0029]
[Patent Document 4]
JP-A-11-314364 (publication date: November 16, 1999)
[0030]
[Patent Document 5]
U.S. Pat. No. 4,866,349 (published: September 12, 1989)
[0031]
[Patent Document 6]
JP-A-2-87189 (publication date: March 28, 1990)
(Japanese Patent No. 2771523)
[0032]
[Patent Document 7]
JP-A-11-170529 (publication date: June 29, 1999)
[0033]
[Patent Document 8]
Japanese Patent Application Laid-Open No. 2000-218782 (release date: August 2, 2000)
[0034]
[Patent Document 9]
JP-A-9-322560 (publication date: December 12, 1997 (1997))
(Patent No. 3120210)
[0035]
[Patent Document 10]
Japanese Patent Application Laid-Open No. H11-326863 (publication date: November 26, 1999)
[0036]
[Patent Document 11]
Japanese Patent Application Laid-Open No. H11-352559 (publication date: December 24, 1999)
[0037]
[Patent Document 12]
JP 2001-22329 A (publication date: January 26, 2001)
[0038]
[Patent Document 13]
JP-A-11-206191 (publication date: July 26, 1999)
[0039]
[Problems to be solved by the invention]
However, in the power regeneration circuit using the mutual induction by the magnetic circuit described in Patent Document 4, the electrostatic energy accumulated in the capacitive load is efficiently reduced due to the conversion efficiency of the mutual induction and the efficiency of the charging circuit. It cannot be collected and reused well.
[0040]
In the print head drive circuit of Patent Document 4, an induced electromotive force is generated by mutual induction between inductances from a discharge current of a piezoelectric element, and a secondary battery or a large-capacity capacitor is charged by the generated induced electromotive force. In this configuration, the collection and reuse of the electrostatic energy can be performed repeatedly. However, since the inductance is required, the configuration is complicated, and the loss of the electrostatic energy due to the DC resistance component of the inductance and the inductance between the inductances are required. There is a problem that the loss due to the mutual induction efficiency occurs and the charge collection efficiency is reduced. Furthermore, the loss caused by the charging circuit for charging the secondary battery or the large-capacity capacitor by the induced electromotive force is added, and the recovery efficiency of the entire system does not exceed 50%.
[0041]
The configurations of Patent Documents 5 and 6 have the following problems.
[0042]
First, the configuration of Patent Literature 5 can be applied only to an application in which the capacitance value of a capacitive load to be driven is fixed or has little fluctuation. That is, for example, when driving a large number of piezoelectric elements in an ink-jet head, the capacitance value of the capacitive load greatly changes depending on the number of piezoelectric elements for discharging ink. Also, in a plasma display, when a large number of light emitting elements are driven by one driving circuit, the capacitance value of a capacitive load greatly changes depending on the number of light emitting elements to emit light. In the configuration of Patent Document 5, when the capacitance of the capacitive load changes, the LC resonance frequency changes, and the operating characteristics of the circuit change. In particular, when the capacitance value of the capacitive load increases, the rise of the waveform is delayed, and the terminal voltage of the capacitive load may not rise to a predetermined voltage during the period when the switch S1 is ON. , May cause a decrease in the regeneration rate. For this reason, it is difficult to apply the configuration of Patent Document 5 to driving a capacitive load whose capacitance value greatly changes, for example, a capacitive component of an inkjet head using a piezoelectric element. Although it is conceivable to provide the circuit of Patent Document 5 for each piezoelectric element of the ink jet head, in such a case, a large number of inductors L are provided, and the circuit scale becomes very large.
[0043]
The above problem can be solved by continuously changing the inductance L of the inductor L in accordance with the change in the capacitance of the capacitive load, but it is difficult to change the inductance L of the inductor L continuously. .
[0044]
Further, the configuration of Patent Literature 6 in which a plurality of inductors L are switched and used can solve the above problem to some extent, but the circuit scale is increased by the provision of the plurality of inductors L. Therefore, this configuration can be used only for limited applications.
[0045]
Further, problems common to the configuration using the inductor L (coil) include a problem that the circuit scale becomes large, the arrangement of the circuit is difficult due to leakage of magnetic flux, and the cost increases.
[0046]
Further, Patent Documents 7 and 8 do not describe a technology for collecting and reusing electrostatic energy.
[0047]
The capacitive load drive circuit of Patent Document 9 has a problem that the efficiency of collecting charges into the capacitor is low, and the power regeneration rate (the ratio of the regenerative power to the initial power) of the capacitive load is low.
[0048]
That is, first, in the step of FIG. 9B, the terminal potential V (Cd) of the capacitive load 261 is
V (Cd) = VH
Becomes
[0049]
When a part of the energy of the capacitive load 261 is recovered by the capacitor 263 in the step of FIG. 9C, the terminal potential V (Cd) of the capacitive load 261 and the terminal potential V (Cs) of the capacitor 263 become the capacitance. Assuming that the capacitance of the capacitive load 261 is Cd and the capacitance of the capacitor 263 is Cs,
V (Cd) = V (Cs) = {Cd / (Cd + Cs)} VH
Becomes For example, when the capacitance of the capacitive load 261 is equal to the capacitance of the capacitor 263, the voltage VH / 2 is supplied to the capacitor 263.
[0050]
The voltage V (Cd) supplied to the capacitive load 261 in the step of FIG.
V (Cd) = [Cd · Cs / (Cd + Cs)²  ] VH
Becomes For example, when the capacitance of the capacitive load 261 is equal to the capacitance of the capacitor 263, the voltage VH / 4 can be supplied to the capacitive load 261. When the terminal potential V (Cd) of the capacitive load 261 after the power regeneration is the largest, the maximum power regeneration rate is obtained. Assuming that the regeneration rate of the voltage from the initial voltage VH at this time is Re,
Re = Cd · Cs / (Cd + Cs)²
Becomes When this is expressed by the capacitance ratio X = Cd / Cs between the capacitive load 261 and the capacitor 263,
Re = X / (1 + X)²
Becomes Therefore, the power regeneration rate becomes maximum when X = 1, that is, when the capacitance of the capacitive load 261 is equal to the capacitance of the capacitor 263,
Re = 1 / (1 + 1)²= 1/4
Becomes Therefore, in the configuration of Patent Document 7, the theoretical maximum regeneration rate is 25%. That is, in the configuration of Patent Document 7, in principle, the reuse efficiency is at most 25%. In addition, when charge and discharge are repeatedly performed, the reuse efficiency is much lower than 25% due to residual charges.
[0051]
In the configurations of Patent Documents 8 to 10, the electric charges stored in the liquid crystal display panel cannot be efficiently recovered and reused. Further, Patent Document 13 does not disclose a technique for collecting and reusing electrostatic energy.
[0052]
The present invention has been made in view of the above-mentioned conventional problems, and has as its object to have a simple circuit configuration and to efficiently recover and reuse energy stored in a capacitive load, It is an object of the present invention to provide an apparatus such as an image forming apparatus including a capacitive load driving circuit and a capacitive load with reduced power.
[0053]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the device of the present invention includes a capacitive load, and a capacitive load drive circuit for charging and discharging the capacitive load, wherein the capacitive load drive circuit is connected to a power supply. A power supply terminal provided with a power supply potential, a reference power supply potential different from the power supply potential supplied from the reference power supply, or a reference potential terminal provided with a ground potential as a reference potential, and an initial potential between the reference potential and the power supply potential , And switching means for selectively connecting the reference potential terminal, the energy storage element, and the power supply terminal to the capacitive load, wherein the switching means connects the reference potential terminal to the capacitive load. A first charging step of connecting the energy storage element to the capacitive load after connecting to the power supply terminal; and a second charging step of selectively connecting the capacitive load to the power supply terminal after the connection to the power supply terminal. And a discharging step of connecting the energy storage element to the capacitive load after the step (c). The capacitance component of the energy storage element is Cs, the capacitance of the capacitive load is Cd, and the connection of the energy storage element is performed. Is maintained as Ts, and the resistance value of the charge / discharge path of the energy storage element with respect to the capacitive load, including the switching means, is R,
When Ts / (R · Cd) <2.5
Cd / Cs ≦ 0.164 {Ts / (R · Cd)}^0.2198
When Ts / (R · Cd) ≧ 2.5
Cd / Cs ≦ 0.2
Is established.
[0054]
Further, the device of the present invention, in order to solve the above problems, in a device comprising a capacitive load, a capacitive load drive circuit for charging and discharging the capacitive load, the capacitive load drive circuit, A power supply terminal provided with a power supply potential from a power supply, a reference power supply potential different from the power supply potential supplied from the reference power supply, or a reference potential terminal provided with a ground potential as a reference potential, between the reference potential and the power supply potential. And a plurality of energy storage elements to which different initial potentials are applied, and switching means for selectively connecting a reference potential terminal, a plurality of energy storage elements, and a power supply terminal to a capacitive load. The means includes a first charging step for connecting each energy storage element to the capacitive load in order from the one whose initial potential is closer to the reference potential after connecting the reference potential terminal to the capacitive load. And a second charging step for selectively connecting the capacitive load to the power supply terminal, and a discharging step for subsequently connecting each energy storage element to the capacitive load in order from the one whose initial potential is closer to the power supply potential. The capacitance component of the energy storage element is Cs, the capacitance of the capacitive load is Cd, the time during which the connection of the energy storage element is maintained is Ts, and the capacitance including the switching means. Assuming that the resistance value of the charge / discharge path of the energy storage element with respect to the reactive load
When Ts / (R · Cd) <2.5
Cd / Cs ≦ 0.164 {Ts / (R · Cd)}^0.2198
When Ts / (R · Cd) ≧ 2.5
Cd / Cs ≦ 0.2
Is established.
[0055]
According to the above configurations, when the absolute value of the terminal voltage of the capacitive load is reduced and the capacitive load is discharged, the stored electrostatic energy of the first energy storage element is supplied to the capacitive load by energy supply. It can regenerate so that it is almost equal to before. Therefore, the first energy storage element apparently does not consume energy, and power regeneration can be performed with high efficiency.
[0056]
Further, according to each of the above configurations, during the first to third steps, the voltage of the capacitive load reaches the final attained voltage (the voltage of the capacitive load reaches the voltage when the first charging step is continued for an infinite time). 90% of the final voltage). As a result, the voltage change of the energy storage element due to the outflow of charges from the energy storage element to the capacitive load is reduced, the power regeneration rate at the time of pulse generation is improved, and power consumption can be further reduced. Further, since the voltage change of the energy storage element due to one pulse generation becomes small, the next pulse can be generated without correcting the voltage change.
[0057]
The device (two-stage device) of the present invention including the energy storage element has a capacitance of Cd as the capacitance of the capacitive load, R as a resistance value of a charge / discharge path of the energy storage element with respect to the capacitive load including switching means, Let Ts be the time during which the connection of the storage element is maintained, V be the ultimate voltage, SR be the slew rate (10% -90% rise rate) of the generated voltage waveform,
If y = Ts / (R · Cd),
SR ≦ V / (R · Cd) * (0.009y²-0.100y + 0.386)
It is preferable to satisfy the following.
The device (two-stage device) of the present invention including the energy storage element has a capacitance of Cd as the capacitance of the capacitive load, R as a resistance value of a charge / discharge path of the energy storage element with respect to the capacitive load including switching means, Let Ts be the time that the connection of the storage element is maintained, and V be the final voltage reached,
If y = Ts / (R · Cd),
50 (V / μsec) ≦ V / (R · Cd) * (0.009y²-0.100y + 0.386)
It is preferable to satisfy the following.
[0058]
The device of the present invention having three or more energy storage elements (three or more stages) has a capacitance Cd of the capacitive load, and a resistance value of a charge / discharge path of the energy storage element with respect to the capacitive load including the switching means. R, the time during which the connection of the energy storage element is maintained is Ts, the final attained voltage is V, and the number of executions of the charging step by each energy storage element during one cycle of the driving pulse is N, and the generated voltage waveform is through. Rate (10% -90% rise speed) is SR
If y = Ts / (R · Cd),
When N = 3, SR ≦ V / (R · Cd) * (0.071y²-0.229y + 0.414)
When N = 4, SR ≦ V / (R · Cd) * (0.138y²-0.336y + 0.434)
When N ≧ 5, SR ≦ V / (R · Cd) * (0.153y²-0.356y + 0.413)
It is preferable to satisfy the following.
The device of the present invention having three or more energy storage elements (three or more stages) has a capacitance Cd of the capacitive load, and a resistance value of a charge / discharge path of the energy storage element with respect to the capacitive load including the switching means. R, the time during which the connection of the energy storage element is maintained is Ts, the final attained voltage is V, the number of executions of the charging step by each energy storage element during one cycle of the driving pulse is N,
If y = Ts / (R · Cd),
When N = 3, 50 (V / μsec) ≦ V / (R · Cd) * (0.071y²-0.229y + 0.414)
When N = 4, 50 (V / μsec) ≦ V / (R · Cd) * (0.138y²-0.336y + 0.434)
When N ≧ 5, 50 (V / μsec) ≦ V / (R · Cd) * (0.153y²-0.356y + 0.413)
It is preferable to satisfy the following.
[0059]
According to the above configuration, it is possible to operate the drive waveform generation circuit stably with respect to the parameters of the circuit as the slew rate required for the generated waveform and the connection maintaining time. In particular, when a high-speed slew rate is required as in an ink jet printer, setting the lower limit of the slew rate to 50 (V / μsec) stabilizes the ejection of ink. Therefore, by performing the above, a pulse having a steep waveform can be applied to the capacitive load, and the response of the device is improved.
[0060]
In each of the above inequalities, the value on the right side (for example, V / (R · Cd) * (0.009y²−0.100y + 0.386)) may be made as large as possible without exceeding the limit of the drive circuit, and the upper limit is not particularly limited.
[0061]
The apparatus including the capacitive load driving circuit of each of the above configurations and a capacitive load charged and discharged by the capacitive load driving circuit has a configuration in which the capacitance component of the energy storage element is the capacitance component of the capacitive load. It is preferably 100 times or more.
[0062]
An energy storage element such as a capacitor used in the present invention depends on the waveform of a pulse to be generated. However, in order to obtain a pulse having a steep rising waveform, an energy storage element having a good frequency characteristic (charge / discharge characteristic) (equivalent resistance R is not sufficient) Small ones) are preferred. As a result, it is possible to move to the next stage in a state where the voltage of the capacitive load is saturated to some extent, so that a pulse having a steep rising waveform can be obtained. In order to reduce the equivalent resistance R and improve the charge / discharge characteristics of the energy storage element, for example, the ON resistance of a switching element connected to the energy storage element may be reduced.
[0063]
When the capacitance component of the energy storage element is 100 times or more the capacitance of the capacitive load, the driving system can be operated stably. Further, when the capacitance component of the energy storage element is less than 100 times the capacitance of the capacitive load, the power regeneration rate greatly decreases with respect to the amount of change in the capacitive load.
[0064]
In the specification of the present application, “capacitive load” refers to a load whose main component is capacitance. Examples of the capacitive load include a piezoelectric element (piezoelectric body) provided in an image forming apparatus, an electrostatic driving electrode (electrostatic actuator) provided in an electrostatic inkjet head, a discharge electrode of an image forming apparatus plasma display, and a liquid crystal display. , A piezoelectric actuator (piezoelectric element), a capacitor, an electrostatic motor, an electrostatic image forming apparatus, and the like. Further, when the current consumption is relatively small, application to a DC-AC converter, a voltage waveform generator, or the like can be considered.
[0065]
As the energy storage element, a secondary battery, a capacitor, or the like can be used.
[0066]
Since the capacitor has a smaller internal resistance than a secondary battery or the like, the loss in the capacitor itself is smaller than that of the secondary battery, and the electrostatic energy can be recovered and reused with high efficiency.
[0067]
In addition, the capacitor can be used for a long period of time since the capacitor has a small deterioration and a long life even after repeated charging and discharging many times.
[0068]
Furthermore, capacitors generally have better frequency characteristics than secondary batteries, and therefore can efficiently collect electrostatic energy even with a pulse drive of about 10 μs.
[0069]
As the capacitor, a film capacitor, a tantalum capacitor, an electric double layer capacitor, a functional polymer capacitor, and a ceramic capacitor which are excellent in the above-described characteristics (deterioration characteristics due to charge / discharge, internal impedance, and frequency characteristics) are particularly desirable.
[0070]
On the other hand, a secondary battery takes a long time to accumulate (charge) electrostatic energy, but can accumulate relatively large energy, so that a voltage can be maintained for a long time. Therefore, there is an advantage that the capacitive load driving circuit can be operated for a long time without supplying a voltage from the power supply.
[0071]
Rechargeable batteries include alkaline batteries such as nickel-cadmium batteries, nickel-metal hydride batteries, silver oxide / cadmium batteries, and lithium secondary batteries such as manganese-lithium batteries, carbon-lithium batteries, lithium-polymer batteries, and lithium-ion batteries. A secondary battery can be used. Among secondary batteries, a lithium ion battery is preferable because it does not have a memory effect like a nickel-cadmium battery or a nickel-metal hydride battery and is suitable for repeatedly performing charging and discharging.
[0072]
Further, according to the above configuration, at the time of charging the capacitive load, different voltages are sequentially supplied from the plurality of energy storage elements to the capacitive load, and the drive voltage of the capacitive load is sequentially increased, while the capacitive load is charged. During discharging, different voltages are sequentially supplied from the plurality of energy storage elements to the capacitive load, so that the drive voltage of the capacitive load can be sequentially reduced. Therefore, various drive voltage waveforms can be obtained by adjusting the switching timing of the switching means.
[0073]
It is more preferable that the voltage dividing means divides the voltage supplied from the power supply into n equal parts (n is 2 or more). Thereby, the flow of energy during charging to the capacitive load and the flow of energy to the energy storage element during discharging from the capacitive load can be canceled most efficiently, and the inrush current of the energy storage element and the capacitive load can be reduced. Can be further reduced, and the energy loss can be further reduced.
[0074]
It is preferable that the capacitive load is a piezoelectric element for pressurizing the ink, which is provided in an inkjet head that ejects the ink in a droplet form.
[0075]
According to the above configuration, generally, the power consumption is large, the dielectric constant is high (for example, about expε ≒ 4300), the capacitance is large (for example, 80 pF × 320 ch = 0.0256 μF), and the charge / discharge of the load is high. Since high-efficiency energy recovery and reuse can be achieved for the piezoelectric element of the ink jet head driven at a frequency (10 kpps to 150 kpps), a particularly large power consumption reduction effect is obtained.
[0076]
The device of the present invention is such that the capacitive load is an electrostatic drive electrode or a piezoelectric element provided in an ink jet head that ejects the ink in the form of droplets by pressurizing the ink, and the capacitive load drive circuit includes: In the case of a drive circuit for driving an electrostatic drive electrode or a piezoelectric element of an inkjet head, a voltage pulse is generated and power is regenerated during the pulse generation cycle. ) The feature is that power consumption during driving is small. Therefore, an image forming apparatus with reduced power consumption can be provided.
[0077]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.
[0078]
As shown in FIG. 1, a capacitive load driving circuit 1 of the present embodiment includes a capacitor 3 including nine capacitors (energy storage elements) 2, a voltage divider (voltage dividing unit) 5 including ten resistors 4, It includes a transistor (switching unit) 6, a switch (switching means) 7, a resistor 8, and a power supply terminal 9. The capacitive load driving circuit 1 according to the present embodiment applies a voltage V to a capacitor 11 that is a capacitive load to charge and discharge the capacitor 11.
[0079]
A power supply voltage VH is supplied to the capacitive load drive circuit 1 from a main power supply (not shown) provided outside the capacitive load drive circuit 1 via a power supply terminal 9. The power supply voltage VH is applied from the power supply terminal 9 to the voltage divider 5 via the transistor 6.
[0080]
The transistor 6 has a role of a switch for turning on / off the connection between the power supply terminal 9 and the voltage divider 5 according to the control voltage Q. In this embodiment, the transistor 6 is a PNP transistor, the power supply terminal 9 is connected to the emitter, the voltage divider 5 is connected to the collector, and the control voltage Q is applied to the base. The transistor 6 is always conductive (ON) at the time of driving. Therefore, the transistor 6 may be omitted, and the power supply terminal 9 may be directly connected to the voltage divider 5.
[0081]
The voltage divider 5 divides a power supply voltage VH supplied from an external main power supply with ten resistors 4. The voltage divider 5 has a configuration in which ten resistors 4 are directly connected between a power supply terminal 9 and ground (a potential point serving as a reference of a power supply voltage; typically, a point having a potential of 0). The resistor 4 divides the power supply voltage VH from the external main power supply into voltages V1 to V9 different from each other. That is, when the transistor 6 is on and the positive power supply voltage VH is supplied to the voltage divider 5 (hereinafter, referred to as “power supply”), the nine connection points a connecting the resistors 4 are provided. -The voltages V1, V2, V3, V4, V5, V6, V7, V8, and V9 (provided that 0 <V1 <V2 <V3 <V4 <V5 < V6 <V7 <V8 <V9 <VH). More specifically, for the voltages V1 to V9, R1 is the sum of the resistance values of the resistors 4 existing from the connection point to the power supply terminal 9, and R4 is the sum of the resistance values of the resistors 4 existing from the connection point to the ground. Is R2, it is expressed by VH · R2 / (R1 + R2). In the present embodiment, resistance elements having the same resistance value are used as the individual resistors 4. Therefore, in this embodiment, the voltages V1 to V9 are V1 = VH / 10, V2 = 2VH / 10, V3 = 3VH / 10, V4 = 4VH / 10, V5 = 5VH / 10, and V6 = 6VH / 10, V7. = 7VH / 10, V8 = 8VH / 10, and V9 = 9VH / 10.
[0082]
The storage device 3 includes nine capacitors 2 a to 2 i connected in parallel between the ground and the voltage divider 5. The capacitors 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, and 2i are connected to the connection points a, b, c, d, e, f, g, and h, respectively. Therefore, at the time of power supply, the voltages V1, V2, V3, V4, V5, V6, and V7 divided by the voltage divider 5 are applied to the capacitors 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, and 2i. , V8, and V9 are applied as terminal voltages (voltages of terminals connected to the switch 7).
[0083]
In this way, the voltage divider 5 adjusts the terminal voltages of the capacitors 2a to 2i of the battery 3 to the predetermined voltages V1 to V9, and distributes different terminal voltages V1 to V9 to the capacitors 2a to 2i. As a result, when power is supplied, electric charges corresponding to the voltages V1, V2, V3, V4, V5, V6, V7, V8, and V9 are stored in the capacitors 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, and 2i, respectively. (Electrostatic energy) is accumulated.
[0084]
In the present embodiment, capacitors having the same capacitance (capacitance) C that is sufficiently larger than the capacitance CL of the capacitor 11 are used as the capacitors 2a to 2i. Therefore, the electric charges accumulated in the capacitors 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, and 2i are C, V1, C, V2, C, V3, C, V4, C, V5, and C, respectively. V6, CV7, CV8, CV9.
[0085]
It is preferable that the capacitance C of the capacitors 2a to 2i be at least 10 times the capacitance CL of the capacitor 11. Thereby, the collection efficiency of the electrostatic energy can be improved.
[0086]
The battery 3 and the voltage divider 5 are connected to a capacitor 11 via a switch 7 and a resistor 8. The switch 7 has eleven contacts T0 to T10, and selectively connects one of the contacts T0 to T10 to an output terminal (an end connected to the resistor 8). Of the eleven contacts T0 to T10, the contact T0 is grounded, and the contacts T1, T2, T3, T4, T5, T6, T7, T8, T9 are capacitors 2a, 2b, 2c, 2d, 2e, 2f. 2g, 2h, and 2i, respectively, and T10 is connected to the power supply terminal 9. Therefore, when the capacitor 11 is driven, the contacts T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 respectively have voltages 0, V1, V2, V3, V4, V5, V6, V7, V8, V9, and VH are applied.
[0087]
The switch 7 is connected to the contact T0 in an initial state (a state before the start of the driving operation). When the driving operation is started, the contacts are sequentially switched from the contact T0 to the contact T10, and then are sequentially switched from the contact T10 to the contact T0. Is repeated. The switch 7 receives a synchronization signal SYNC for pulse driving the capacitor 11 from a synchronization signal source (not shown), and performs a switching operation of the contacts T0 to T10 according to the synchronization signal SYNC. The details of the synchronization signal SYNC and the switching timing of the contacts T0 to T10 will be described later.
[0088]
The resistor 8 is for limiting the current flowing to the capacitor (capacitive load) 11. When a semiconductor switch is used as the switch 7, the resistor 8 is equivalently inserted as an ON resistance of the semiconductor switch.
[0089]
Next, the operation of the capacitive load driving circuit 1 will be described with reference to FIGS. Here, description is made on the assumption that VH is a positive voltage.
[0090]
FIG. 2 is a timing chart showing the operation of the capacitive load driving circuit 1. FIG. 2A is a waveform diagram showing a waveform of the synchronization signal SYNC input to the switch 7. FIG. 2B is a waveform diagram showing a waveform of a control voltage Q of the transistor 6 for controlling the operation of the transistor 6. FIG. 2C is a waveform diagram illustrating a waveform of the voltage V applied to the capacitor 11.
[0091]
FIG. 3 is an enlarged view of a part of the timing chart shown in FIG. FIG. 3A is an enlarged waveform diagram showing a part of the waveform of the synchronization signal SYNC shown in FIG. FIG. 3B is a timing chart showing the operating state of the switch 7 in FIG. 1, that is, which of the contacts T0 to T10 is connected. FIG. 3C is an enlarged waveform diagram showing a part of the waveform of the control voltage Q shown in FIG. 2B. FIG. 3D is an enlarged waveform diagram showing a part of the waveform of the voltage V shown in FIG. 2C.
[0092]
First, as a preparatory operation before starting the driving operation of the capacitor 11, the control voltage Q becomes high level as shown in FIG. 2B, and the transistor 6 is turned on (ON). Thereby, predetermined voltages V1 to V9 different from each other obtained by dividing the external power supply voltage VH by the voltage divider 5 are applied to the capacitors 2a to 2i of the battery 3 as terminal voltages, and the capacitors 2a to 2i Is charged. In the present embodiment, the transistor 6 is always in a conductive state until the driving operation of the capacitor 11 ends. At this time, the switch 7 is connected to the contact T0, and the capacitor 11 is grounded.
[0093]
After preparation for adjusting the terminal voltages of the capacitors 2a to 2i to the predetermined voltages V1 to V9, as shown in FIG. 2A, the synchronization signal SYNC becomes active and the driving operation is started. At this time, the time t0 from the time when the transistor 6 becomes conductive (the time when the preparation operation starts) to the time when the synchronization signal SYNC becomes active (the time when the driving operation starts) is charged so that the capacitors 2a to 2i can be sufficiently charged. It is preferable to set the time constant to at least 2.5 times.
[0094]
Then, by sequentially switching the switch 7 from the contact T0 to the contact T10 according to the synchronization signal SYNC, a plurality of different voltages V1 to V9 and VH are applied to the capacitor 11 as the voltage V. Thereby, as shown in FIGS. 2C and 3C, a substantially trapezoidal stepped pulse voltage is applied to the capacitor 11 as the voltage V.
[0095]
Next, the driving operation of the capacitor 11 will be described in detail. Here, the synchronization signal SYNC is a pulse signal having a constant period T and a pulse width t, as shown in FIG. For example, the period T is set to 8 μs, and the pulse width t is set to 0.32 μs.
[0096]
When the capacitor 11 is driven, first, the switch 7 is switched from the contact point T0 to the contact point T1 in synchronization with the rise of the synchronization signal SYNC. When switch 7 is switched to contact point T1, capacitor 2a of capacitor 3 and capacitor 11 are connected. At this time, since the terminal voltage of the capacitor 2a is V1 and the terminal voltage of the capacitor 11 is the ground potential, electrostatic energy (charge) is supplied from the capacitor 2a to the capacitor 11, and the capacitor 11 is charged.
[0097]
At this time, since the electric charge stored in the capacitor 2a is C · V1, if the capacitance of the capacitor 11 is assumed to be CL and the electric charge is supplied from only the capacitor 2a to the capacitor 11, the voltage applied to the capacitor 11 V is
V = CV1 / (C + CL)
It is. Since the capacitance C of the capacitor 2a is sufficiently larger than the capacitance CL of the capacitor 11, the voltage V can be considered to be substantially equal to the predetermined voltage V1 generated by the voltage divider 5. Therefore, the voltage V1 is applied from the capacitor 2a to the capacitor 11 by switching the switch 7 from the contact T0 to the contact T1.
[0098]
Thereafter, the connection of the switch 7 includes the contacts T1 to T2, the contacts T2 to T3, the contacts T3 to T4, the contacts T4 to T5, the contacts T5 to T6, the contacts T6 to T7, and the contacts T7 to T8. The contact is switched from the contact T8 to the contact T9. By switching these switches 7, the capacitor 11 is connected to the capacitors 2b to 2i in ascending order of terminal voltage. Accordingly, in the same manner as switching from the contact point T0 to the contact point T1, electrostatic energy is sequentially supplied to the capacitor 11 from the capacitors 2b to 2i, and the voltages V2 to V9 are applied to the capacitor 11 in ascending order. As a result, the voltage V of the capacitor 11 increases to the voltage V9.
[0099]
Next, when the connection of the switch 7 is switched from the contact T9 to the contact T10, the capacitor 11 is connected to the power supply terminal 9, and the voltage V applied to the capacitor 11 becomes equal to the external power supply voltage VH.
[0100]
As described above, the voltage V of the capacitor 11 rises from 0 to the power supply voltage VH substantially stepwise as shown in FIG. 3D.
[0101]
Next, after the contact of the switch 7 is held at the contact T10 and the voltage V of the capacitor 11 is maintained at the power supply voltage VH, the contact of the switch 7 is switched from the contact T10 to the contact T9. As a result, the capacitor 2i of the battery 3 and the capacitor 11 are connected.
[0102]
At this time, the electric charge accumulated in the capacitor 2i is C · V9. Therefore, if electric charge is supplied to the capacitor 2i only from the capacitor 11, the voltage V applied to the capacitor 11 is
V = (CLVH + CV9) / (C + CL)
It is. Since the capacitance C of the capacitor 2i is sufficiently larger than the capacitance CL of the capacitor 11, the voltage V becomes substantially equal to the voltage V9. Therefore, by switching the switch 7 from the contact point T10 to the contact point T9, the capacitor 11 is connected to the capacitor 2i, and the voltage V of the capacitor 11 is adjusted to a predetermined voltage adjusted by the voltage divider 5 as shown in FIG. The voltage decreases to V9.
[0103]
At this time, since energy is injected from the capacitor 2i to the capacitor 11 in the step of connecting the capacitor 11 to the capacitor 2h after connecting the capacitor 11 to the capacitor 2h, a circuit other than the capacitor 11 is connected between the rise and fall of the voltage pulse. Assuming that energy is not supplied to the capacitor 3, the terminal voltage of the capacitor 2i immediately after connecting the capacitor 11 to the capacitor 2i after connecting the capacitor 11 to the power supply terminal 9 is not strictly V9 but slightly lower than V9. Value.
[0104]
However, when the capacitor 11 charged to the power supply voltage VH is connected to the capacitor 2i having a terminal voltage slightly smaller than V9, the terminal voltage of the capacitor 11 is the power supply voltage VH and is larger than the terminal voltage of the capacitor 2i. Therefore, electrostatic energy (charge) is recovered from the capacitor 11 to the capacitor 2i, and the capacitor 11 is discharged. At this time, the voltage of the capacitor 2i returns (regenerates) to a value substantially equal to V9 (a value that can be regarded as V9) by recovering energy from the capacitor 11.
[0105]
After that, the switches 7 are connected to the contacts T9 to T8, the contacts T8 to T7, the contacts T7 to T6, the contacts T6 to T5, the contacts T5 to T4, the contacts T4 to T3, and the contacts T3 to T2. The contact is switched from the contact T2 to the contact T1. By switching these switches 7, the capacitor 11 is connected to the capacitors 2a to 2h in order of terminal voltage. Accordingly, in the same manner as switching from the contact point T10 to the contact point T9, energy is sequentially recovered from the capacitor 11 to the capacitors 2a to 2h, and the voltages V1 to V8 are applied to the capacitor 11 in the descending order.
[0106]
Finally, when the connection of the switch 7 is switched from the contact T1 to the contact T0, the capacitor 11 is grounded, and the voltage V applied to the capacitor 11 becomes 0, which is the same as the ground. Here, the reason why the voltage V is set to 0 is to set the electric charge accumulated in the capacitor 11 to 0 and to perform a stable repetitive operation.
[0107]
As described above, the voltage V of the capacitor 11 gradually decreases from the power supply voltage VH to 0 as shown in FIG. 3D.
[0108]
At the end of the step-down of the switch 7 (switching from the contact point T1 to the contact point T0), all the charges stored in the capacitor 11 are dropped to the ground without returning to the capacitors 2a to 2i. Some of the electrical energy will be discarded. In the present embodiment, the voltage V applied to the capacitor 11 is the maximum VH, and the voltage V of the capacitor 11 at the end of the step-down of the switch 7 is equal to V1, that is, VH / 10. Therefore, the charge stored in the capacitor 11 is CL · VH, and the charge discharged from the capacitor 11 at the end of the step-down of the switch 7 is CL · VH / 10. Therefore, energy is not supplied to the battery 3 from circuits other than the capacitor 11 during the period from the rise to the fall of the voltage pulse, and the charge discharged from the capacitor 11 is not used except at the end of the step-down of the switch 7. Is collected by the capacitors 2a to 2i, the charge collected from the capacitor 11 to the capacitors 2a to 2i is 9CL · VH / 10. Therefore, the collection efficiency of the electrostatic energy is 9/10 = 90%.
[0109]
In this manner, the switch 7 is sequentially switched from the contact T0 to the contact T10 to step up the applied voltage V of the capacitor 11, and then the switch 7 is sequentially switched from the contact T10 to the contact T0 to reverse the applied voltage V of the capacitor 11. Is stepped down, the electrostatic energy can be supplied from the capacitors 2a to 2i of the capacitor 3 to the capacitor 11, and the electrostatic energy stored in the capacitor 11 can be substantially recovered by the capacitors 2a to 2i of the capacitor 3. .
[0110]
As described above, the capacitive load driving circuit 1 according to the present embodiment distributes the voltage of the main power supply into n divisions, stores the divided voltage in the capacitor 3, and switches the connection between the capacitor 3 and the capacitor 11. , The electrostatic energy is supplied from the capacitor 11 to the capacitor 11 and the electrostatic energy discharged from the capacitor 11 is collected in the battery 3, so that highly efficient energy collection and reuse can be achieved.
[0111]
[Embodiment 1A]
The following will describe another embodiment of the present invention with reference to FIGS. For the sake of convenience, members having the same functions as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0112]
The capacitive load drive circuit of the present embodiment has the same configuration as the capacitive load drive circuit 1 of the first embodiment, except for the following differences.
[0113]
The first difference is that in the capacitive load drive circuit 1 of the first embodiment, the nine connection points (voltage division points) a to i of the voltage divider 5 and the lines connected to the contacts T1 to T9 are directly connected. In contrast, as shown in FIG. 41, the capacitive load drive circuit 1A of this embodiment has nine connection points (voltage division points) a to i of the voltage divider 5 and contact points T1 to T1. The point is that switches SW1 to SW9 are respectively provided between the lines connected to T9. The switches SW1 to SW9 are provided as switching units for controlling the supply of voltage from the voltage divider 5 to the capacitors 2a to 2i of the electric storage device 3, and are connected only for a predetermined period before charging of the capacitor 11. Is controlled.
[0114]
The second difference is that the capacitive load driving circuit 1 of the first embodiment includes a transistor 6 and operates according to the timing charts shown in FIGS. 2 and 3, whereas the capacitive load driving circuit 1A 6 in that a switch 16A whose operation is controlled by the control voltage Q shown in the timing charts of FIGS. 42 and 43 is provided.
[0115]
That is, the switch 16A is different from the transistor 6 of the first embodiment in a period before the charging of the capacitor 11 is started (in this case, the capacitor 11 is connected to the contact T0 of the switch 7 as shown in FIG. 42). (Grounded), and is controlled to be in a conductive state (ON) for a predetermined time t0. The operation of the switches SW1 to SW9 is also controlled by a control voltage similar to the control voltage Q of the switch 16A.
[0116]
In the first embodiment, since the power storage device 3 and the voltage divider 5 are always connected and the power supply voltage is always supplied to the voltage divider 5 at the time of driving, the voltage pulse rises and falls. During this time, energy is supplied to the battery 3 from another circuit. When such energy supply is performed, there is a possibility that the efficiency of energy recovery from the capacitor 11 to the power storage device 3 is deteriorated.
[0117]
On the other hand, in the present embodiment, due to the first and second differences, no energy is supplied to the battery 3 from another circuit during the period from the rise to the fall of the voltage pulse. I have. Thus, it is possible to prevent the energy recovery efficiency from the capacitor 11 to the storage battery 3 from being deteriorated due to the supply of energy from another circuit.
[0118]
Next, a driving operation of the capacitor 11 by the capacitive load driving circuit 1A will be described with reference to FIGS. Here, the synchronization signal SYNC is a pulse signal having a constant period T and a pulse width t, as shown in FIG. For example, the period T is set to 8 μs, and the pulse width t is set to 0.32 μs. Note that VH is described as a positive voltage.
[0119]
FIG. 42 is a timing chart showing the operation of the capacitive load drive circuit 1A. FIG. 42A is a waveform diagram showing a waveform of the synchronization signal SYNC input to the switch 7. FIG. 42B is a waveform diagram showing a waveform of a control voltage Q for controlling the operation of the switch 16A. FIG. 42C is a waveform diagram showing a waveform of the voltage V applied to the capacitor 11.
[0120]
FIG. 43 is an enlarged view of a part of the timing chart shown in FIG. 42 and shows the operation state of the switch 7. FIG. 43A is an enlarged waveform diagram showing a part of the waveform of the synchronization signal SYNC shown in FIG. FIG. 43B is a timing chart showing the operating state of the switch 7 in FIG. 1, that is, which of the contacts T0 to T10 is connected. FIG. 43 (c) is an enlarged waveform diagram showing a part of the waveform of the control voltage Q shown in FIG. 42 (b). FIG. 43D is an enlarged waveform diagram showing a part of the waveform of the voltage V shown in FIG. 42C.
[0121]
When the capacitor 11 is driven, first, as in the first embodiment, the switch 7 is connected to the contacts T0 to T1, the contacts T1 to T2, the contacts T2 to T3, the contacts T3 to T4, and the contacts T4 to T4. T5, contact T5 to contact T6, contact T6 to contact T7, contact T7 to contact T8, contact T8 to contact T9, and electrostatic energy is supplied from the capacitors 2a to 2i to the capacitor 11. Next, the connection of the switch 7 is switched from the contact T9 to the contact T10, and the voltage V applied to the capacitor 11 becomes equal to the power supply voltage VH. As described above, the voltage V of the capacitor 11 rises from 0 to the power supply voltage VH substantially stepwise as shown in FIG. 3D.
[0122]
Next, the contact of the switch 7 is switched from the contact T10 to the contact T9. As a result, the capacitor 2i of the battery 3 and the capacitor 11 are connected.
[0123]
At this time, the electric charge accumulated in the capacitor 2i is C · V9, and electric charge is supplied to the capacitor 2i from almost only the capacitor 11, so that the voltage V applied to the capacitor 11 is
V = (CLVH + CV9) / (C + CL)
It is. Since the capacitance C of the capacitor 2i is sufficiently larger than the capacitance CL of the capacitor 11, the voltage V is substantially equal to the voltage V9.
[0124]
At this time, in the step of connecting the capacitor 11 to the capacitor 2h and then connecting to the capacitor 2i, energy is injected from the capacitor 2i to the capacitor 11 and the circuit other than the capacitor 11 is supplied between the rise and fall of the voltage pulse. Since the energy is not supplied from the power supply 3 to the capacitor 3, the terminal voltage of the capacitor 2i immediately before the capacitor 11 is connected to the capacitor 2i after the capacitor 11 is connected to the power supply terminal 9 is not strictly V9 but a value slightly smaller than V9. become.
[0125]
However, when the capacitor 11 charged to the power supply voltage VH is connected to the capacitor 2i having a terminal voltage slightly smaller than V9, the terminal voltage of the capacitor 11 is the power supply voltage VH and is larger than the terminal voltage of the capacitor 2i. Therefore, electrostatic energy (charge) is recovered from the capacitor 11 to the capacitor 2i, and the capacitor 11 is discharged. At this time, the voltage of the capacitor 2i returns (regenerates) to a value substantially equal to V9 (a value that can be regarded as V9) by recovering energy from the capacitor 11.
[0126]
After that, the switches 7 are connected to the contacts T9 to T8, the contacts T8 to T7, the contacts T7 to T6, the contacts T6 to T5, the contacts T5 to T4, the contacts T4 to T3, and the contacts T3 to T2. The contact is switched from the contact T2 to the contact T1, and energy is recovered from the capacitor 11 to the capacitors 2a to 2h. Finally, when the connection of the switch 7 is switched from the contact T1 to the contact T0, the capacitor 11 is grounded, and the voltage V applied to the capacitor 11 becomes 0, which is the same as the ground.
[0127]
As described above, the voltage V of the capacitor 11 gradually decreases from the power supply voltage VH to 0 as shown in FIG. 3D.
[0128]
At the end of the step-down of the switch 7 (switching from the contact point T1 to the contact point T0), all the charges stored in the capacitor 11 are dropped to the ground without returning to the capacitors 2a to 2i. Some of the electrical energy will be discarded. In the present embodiment, the voltage V applied to the capacitor 11 is the maximum VH, and the voltage V of the capacitor 11 at the end of the step-down of the switch 7 is equal to V1, that is, VH / 10. In the present embodiment, energy is not supplied to the battery 3 from a circuit other than the capacitor 11 during the period from the rise to the fall of the voltage pulse. The collected electric charges are substantially recovered by the capacitors 2a to 2i. Therefore, the charge stored in the capacitor 11 is CL · VH, and the charge discharged from the capacitor 11 at the end of the step-down of the switch 7 is CL · VH / 10. Therefore, the charge collected from the capacitor 11 to the capacitors 2a to 2i is 9CL · VH / 10. Therefore, the collection efficiency of the electrostatic energy is 9/10 = 90%.
[0129]
In this manner, the switch 7 is sequentially switched from the contact T0 to the contact T10 to step up the applied voltage V of the capacitor 11, and then the switch 7 is sequentially switched from the contact T10 to the contact T0 to reverse the applied voltage V of the capacitor 11. Is stepped down, the electrostatic energy can be supplied from the capacitors 2a to 2i of the capacitor 3 to the capacitor 11, and the electrostatic energy stored in the capacitor 11 can be substantially recovered by the capacitors 2a to 2i of the capacitor 3. .
[0130]
As described above, the capacitive load driving circuit 1 </ b> A of the present embodiment distributes the voltage of the main power supply into n divisions, stores the divided voltage in the capacitor 3, and switches the connection between the capacitor 3 and the capacitor 11, thereby switching the capacitor 3. , The electrostatic energy is supplied from the capacitor 11 to the capacitor 11 and the electrostatic energy discharged from the capacitor 11 is collected in the battery 3, so that highly efficient energy collection and reuse can be achieved.
[0131]
In addition, since the capacitors 2a to 2i of the capacitor 3 are switched in the order of the terminal voltage, the rush current of the capacitors 2a to 2i and the capacitor 11 can be suppressed small, and the energy loss can be reduced. Further, the capacitor 11 can be pulse-driven. In addition, power consumption can be further reduced by increasing the number of switching stages n of the switch 7.
[0132]
Furthermore, since the capacitive load driving circuits 1 and 1A of the first and 1A have a configuration in which the voltage divider 5 is connected by the resistor 4 connected in series, the terminal voltages of the capacitors 2a to 2i are equal to the predetermined voltages V1 to V9. And stable repetitive operation is possible.
[0133]
In Embodiments 1 and 1A, intervals of voltage values (0, V1 to V9, VH) that output voltage V can take, that is, V1-0, V2-V1, V3-V2, V4-V3, V5-V4 , V6-V5, V7-V6, V8-V7, V9-V8, and VH-V9 have the same value VH / 10. However, the intervals need not necessarily be equal. However, there is an advantage that making the intervals equal increases the energy recovery efficiency. By making the intervals equal, the inrush current of the capacitors 2a to 2i and the capacitor 11 can be further reduced.
[0134]
Further, in Embodiments 1 and 1A, the number of capacitors of the battery 3 is set to ten, but the number is not particularly limited as long as the number is two or more. When the number of capacitors of the battery 3 is n (n is an integer of 2 or more), the collection efficiency of electrostatic energy is n / (n + 1).
[0135]
In the capacitive load driving circuits 1 and 1A of the first and 1A, the switch 7 is used from T0 to T10 when a series of pulses are generated. However, if the required pulse peak value is lower than VH, Even if the rise of the voltage V of the capacitor 11 is stopped at an arbitrary voltage m · VH / 10 (m is an integer of 2 or more and 9 or less) without using some of the contacts 7, a sufficient driving operation can be performed. . For example, when the required pulse crest value is 9 VH / 10, the type that uses the contacts T0 to T9 of the switch 7 may be used. Similarly, even if the rise of the voltage V of the capacitor 11 is stopped at an arbitrary voltage m · VH / 10 (m is an integer of 2 or more and 9 or less), a sufficient driving operation can be performed. When the increase in the voltage V of the capacitor 11 is stopped at an arbitrary voltage m · VH / 10 (m is an integer of 2 or more and 9 or less), the collection efficiency of the electrostatic energy is (m−1) / m.
[0136]
In a system in which some of the contacts of the switch 7 are not used, the capacitor (any one of 2a to i) in which the imbalance between the supply of energy to the capacitor 11 and the recovery of energy from the capacitor 11 partially occurs in the battery 3 Therefore, it is necessary to correct imbalance caused by energy supply from the voltage divider 5 or the like.
[0137]
In Embodiment 1A, when a voltage pulse is applied to capacitor 11 as a capacitive load, energy is sequentially supplied from capacitor 3 to capacitor 11 when the voltage waveform rises, and the capacitor is This is a method for reducing power consumption as a system by collecting energy from the power storage 11 into the capacitor 3. When energy is supplied to the capacitor 3 from another circuit during the period from the rise to the fall of the voltage pulse, the capacitor is The efficiency of recovering energy from the battery 11 to the battery 3 is reduced.
[0138]
Therefore, the correction of the imbalance between the energy supply and the energy recovery generated in the capacitor 3 is performed during a period in which no waveform is generated to the capacitor 11 or is performed slowly compared with the time of the waveform applied to the capacitor 11. Need to be done.
[0139]
Further, in the capacitive load drive circuits 1 and 1A of the first and first embodiments, the rotary switch 7 is used. However, eleven one-contact switches provided in parallel may be used as the switching means.
[0140]
[Embodiment 2]
Next, still another embodiment of the present invention will be described below with reference to FIG. For the sake of convenience, members having the same functions as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0141]
As shown in FIG. 4, the capacitive load drive circuit of the present embodiment is the same capacitive load drive circuit 1 as in the first embodiment, or the same capacitive load drive circuit 1A as in the embodiment 1A shown in FIG. It is.
[0142]
In the present embodiment, only the configuration of the capacitive load to be driven by the capacitive load drive circuit 1 or 1A is different from the first and 1A. In other words, this embodiment differs from the first and 1A only in the method of using the capacitive load drive circuit 1 or 1A.
[0143]
In Embodiment 1 or 1A, the capacitive load to be driven is the capacitor 11, whereas in the present embodiment, the capacitive load to be driven is, as shown in FIG. 4 and FIG. 23, a plurality of piezoelectric elements 21 provided. In addition to the piezoelectric element 21, the inkjet head 23 is provided with an analog switch 22 for turning on / off the connection between the capacitive load drive circuit 1 or 1 </ b> A and the piezoelectric element 21.
[0144]
According to the above-described usage method, by charging and discharging the piezoelectric element 21 having a high dielectric constant and a large capacitance, the piezoelectric element 21 is driven at a high repetition frequency and has a high efficiency in driving the inkjet head 23 having a large power consumption. Energy recovery and reuse becomes possible.
[0145]
The power consumption when the inkjet head 23 is driven will be estimated in the capacitive load driving circuit 1A of the present embodiment and the conventional capacitive load driving circuit that does not collect electrostatic energy.
[0146]
First, the inkjet head 23 has heads of four colors of YMCK, 64 piezoelectric elements 21 and ink ejection nozzles are provided for each color head, and heads of up to three colors of the heads of each color are simultaneously turned on. Suppose Then, the number of piezoelectric elements 21 connected to the capacitive load drive circuit is 64 × 3 at the maximum. Therefore, when the capacitance of each piezoelectric element 21 is 80 pF, the total capacitance of the piezoelectric elements 21 connected to the capacitive load driving circuit is at most
80 × 64 × 3 = 0.0153 μF
Becomes
[0147]
Then, in a conventional capacitive load driving circuit, when a rectangular wave having a peak value of 20 V and a pulse width of 8 μs is applied to the piezoelectric element 21 as a driving voltage, a current I flowing from the capacitive load driving circuit to the piezoelectric element 21 is:
I = 0.0153μF × 20V ÷ 8μs = 0.0384A
Becomes Therefore, in the conventional capacitive load driving circuit, the power consumption E per pulse is
E = 0.0384A × 20V = 0.768W
Becomes
[0148]
On the other hand, using the capacitive load driving circuit 1A of the present embodiment, V1 = 2 (V), V2 = 4 (V), V3 = 6 (V), V4 = 8 (V), and V5 = 10 (V). ), V6 = 12 (V), V7 = 14 (V), V8 = 16 (V), V9 = 18 (V), VH = 20 (V), and a conventional capacitive load driving circuit is used for the inkjet head 23. When the same operation is performed as in the case of using, the power consumption per pulse is 0.077 W.
[0149]
Therefore, in the capacitive load drive circuit 1A of the present embodiment, the power consumption may be 1/10 of the conventional capacitive load drive circuit. This 1/10 is due to the fact that the energy is finally discharged to the ground without returning to the capacitor of the battery 3, and the rest is not consumed because it is returned to the capacitor.
[0150]
In the case of this embodiment, in order to perform sufficient power recovery, the capacitance of each of the capacitors 2 constituting the battery 3 is determined by the load capacitance when the piezoelectric elements 21 of the inkjet head 23 are driven by the maximum number (in the above example, 80 × 64 × 3 = 0.0153 μF).
[0151]
In the device of the present embodiment, power is recovered using a capacitor. Therefore, unlike a circuit that recovers power using LC resonance, even if a large number of capacitive loads (piezoelectric elements 21) are driven at the same time. (1) Operation characteristics (regenerative efficiency and the like) equivalent to the case of driving one capacitive load can be obtained.
[0152]
[Embodiment 3]
One embodiment of an ink jet printer (image forming apparatus) to which the present invention is applied will be described with reference to FIGS. 4, 5, and 6. FIG.
[0153]
FIG. 5 is a perspective view showing a main part of an ink jet printer (image forming apparatus).
[0154]
As shown in FIG. 5, in the ink jet printer (image forming apparatus) 210 of the present embodiment, the carriage 211 is connected to the pulse motor 213 via the timing belt 212, and is guided by the guide member 214 so that the recording paper 215 in the paper width direction is It is configured to reciprocate.
[0155]
The ink-jet head 23 receives ink from an ink cartridge 217 mounted on the upper part of the carriage 211 and discharges ink droplets on the recording paper 215 in accordance with the movement of the carriage 211 to form dots. Print images and text on
[0156]
FIG. 6 is a cross-sectional view illustrating the configuration of the inkjet head 23.
[0157]
As shown in FIG. 6, in the ink jet head 23, the nozzle openings 221 are formed in the nozzle plate 220, and the flow path forming plate 222 communicates with the through holes that define the pressure generation chambers 223, and communicates with the pressure generation chambers 223 on both sides. A through-hole or groove that partitions the two ink supply ports 224 and a through-hole that partitions two common ink chambers 225 that respectively communicate with the ink supply ports 224 are formed. The vibration plate 226 is made of an elastically deformable thin plate, abuts against the tip of the piezoelectric element 21 such as a piezo element, and is integrally fixed in a liquid-tight manner with the nozzle plate 220 with the flow path forming plate 222 interposed therebetween. 228. The piezoelectric element 21 is fixed to a fixed substrate 232.
[0158]
With such a configuration, when the piezoelectric element 21 contracts and the pressure generating chamber 223 expands, ink in the common ink chamber 225 flows into the pressure generating chamber 223 via the ink supply port 224. When the piezoelectric element 21 expands and the pressure generating chamber 223 contracts after a lapse of a predetermined time, the ink in the pressure generating chamber 223 is compressed and ink droplets are ejected from the nozzle openings 221.
[0159]
As shown in FIG. 4, the capacitive load driving circuit 1 is connected to the piezoelectric element 21 of the ink jet head 23 via an analog switch 22. The capacitive load drive circuit 1 is configured to generate a trapezoidal wave having a voltage value necessary for discharging an ink droplet from the nozzle opening 221. The analog switch 22 selectively applies the output voltage V of the capacitive load driving circuit 1 to the piezoelectric element 21 corresponding to the print data.
[0160]
As described above, by using the capacitive load driving circuit 1 according to the present invention to drive the piezoelectric elements of the ink jet printer (image forming apparatus) 210, the power consumption of the ink jet printer (image forming apparatus) 210 can be reduced. Can be.
[0161]
As described above, in the ink jet printer (image forming apparatus) 210 using a piezoelectric element as an ink discharging unit that discharges the ink in the form of droplets by pressurizing the ink, the capacitive load driving circuit according to the present invention includes the piezoelectric element ( The example used for driving the capacitive load has been described. However, the capacitive load drive circuit according to the present invention employs an electrostatic method using an electrostatic drive electrode as an ink discharge means (electrostatic between electrodes by applying a voltage between two electrodes (electrostatic drive electrodes)). It can also be used for driving an electrostatic drive electrode in an ink jet printer of the type that discharges ink by using a suction force. In this case, the same effect of suppressing power consumption can be obtained.
[0162]
Further, the ink jet printer or the image forming apparatus according to the present invention is not necessarily an apparatus dedicated to printing, but may be a multifunction peripheral having functions such as a copying machine and a facsimile machine.
[0163]
[Embodiment 4]
Here, the principle of the present invention will be described.
[0164]
In the circuit of FIG. 23, as shown in FIG. 23A, the initial potential of the energy storage element Cs1 is set to V0, and the initial potential of the capacitive load Cd is set to 0. When the switch SW1 is turned on at t = 0, a current I flows from the energy storage element Cs1 to the capacitive load Cd due to a potential difference between the energy storage element Cs1 and the capacitive load Cd, as shown in FIG. The capacitive load Cd is charged. The voltage across the capacitive load Cd at this time is expressed by the following equation.
[0165]
(Equation 1)

[0166]
When a sufficient time has elapsed after the switch SW1 is turned on, the difference between the voltage Vs of the energy storage element Cs1 and the voltage Vd of the capacitive load Cd (the potential difference between the energy storage element Cs1 and the capacitive load Cd) disappears, and the current I Becomes 0. 24 (a) and 24 (b) show changes over time of the voltage Vs · Vd and the current I. This saturation voltage is defined as V1.
[0167]
(Equation 2)

[0168]
Next, the switch SW1 is turned off, and the capacitive load Cd is connected to the energy storage element Cs2 having the initial potential V0 + ΔV (see FIG. 25). The capacitive load Cd is charged by a potential difference between the capacitive load Cd and the energy storage element Cs2. The voltage across the capacitive load Cd at this time is expressed by the following equation.
[0169]
(Equation 3)

[0170]
When a sufficient time elapses after the switch SW2 is turned on, the potential difference between the energy storage element Cs1 and the capacitive load Cd disappears, and the current I becomes 0 (see FIG. 25). This saturation voltage is defined as V2.
[0171]
(Equation 4)

[0172]
Further, the switch SW2 is turned off and the switch SW1 is turned on (see FIG. 26). Due to the potential difference between the capacitive load Cd and the energy storage element Cs2, the capacitive load Cd is discharged. The voltage across the capacitive load Cd at this time is expressed by the following equation.
[0173]
(Equation 5)

[0174]
When a sufficient time has elapsed after the switch SW1 is turned on, the potential difference between the energy storage element Cs1 and the capacitive load Cd disappears, and the current I becomes zero. This saturation voltage is defined as V3.
[0175]
(Equation 6)

[0176]
Considering now the case where the capacitance Cs1 of the energy storage element Cs1 and the capacitance Cs2 of the energy storage element Cs2 are sufficiently larger than the capacitance Cd of the capacitive load Cd, the following equation is established.
[0177]
(Equation 7)

[0178]
Therefore, for the energy storage element Cs1, the initial potential V0, the potential V1 after charging the capacitive load Cd, and the potential V3 after regenerating from the capacitive load Cd become substantially equal, and the energy storage element Cs1 The energy loss is apparently zero between the capacitor and the capacitive load Cd.
[0179]
Next, a four-stage capacitive load drive circuit 301 shown in FIG. 12 will be described as an embodiment for explaining the operation principle.
[0180]
The capacitive load driving circuit 301 drives the capacitive load 311 by charging / discharging the capacitive load 311 such as a piezoelectric element, and stores the energy stored in parallel between the capacitive load 311 and the ground. It has capacitors C (1), C (2), and C (3) as elements. Further, a power source 309, which is a DC power supply (power supply) for supplying the power supply voltage VH, is provided.
[0181]
Although not shown, an initial potential applying means for applying an initial potential (initial charge) to these capacitors C (1) to C (3) is provided. This initial potential applying means divides (divides) the potential difference (voltage) between the power supply voltage VH supplied from the power source 309 and the ground potential (= 0) into four equal parts, and generates the divided voltage. The three potentials V1 (= 1 / 4.VH), V2 (= 2 / 4.VH), and V3 (= 3 / 4.VH) are used as initial potentials in the capacitors C (1) to C (3), respectively. Is to be granted. The initial potential applying means is connected, for example, between a ground (ground point) and a power source 309, divides a potential difference between a ground potential and a power supply voltage VH, and divides the divided voltage into a capacitor C (1). ) To C (3) are voltage dividing means for supplying to the connected voltage dividing points. As the voltage dividing means, for example, like the above-described voltage divider 5, four voltage sources connected in series between a power supply point VH (power supply terminal) to which the power supply voltage V is supplied and a ground (ground terminal) are provided. A resistor voltage dividing circuit having a resistor can be used.
[0182]
Further, switching elements S (1), S (2), and S (3) are connected between the capacitive load 311 and the capacitors C (1), C (2), and C (3), respectively. The switching element S (4) is connected between the power source 309 and the capacitive load 311. The switching element S (0) is connected between the ground potential G and the capacitive load 311. In this embodiment, switching means is constituted by the switching elements S (0) to S (4). On the other hand, the other end of the capacitive load 311 is connected to the ground. The other ends of the capacitors C (1), C (2), and C (3) are connected to ground via a ground point (reference potential terminal, ground terminal) C (0).
[0183]
The operation of the capacitive load driving circuit 301 having the above configuration will be described below with reference to FIGS. Hereinafter, for convenience of explanation, a case where the power supply voltage VH is a positive potential will be described. The operation when the power supply voltage VH is a negative potential is the same except that the polarity of the potential and the direction of charge transfer are reversed.
[0184]
Initially, as shown in FIG. 13A, only the switching element S (0) among the switching elements S (0) to S (4) is set to the connected state (ON state), and the capacitive load 311 is charged. Are stored (initial state) (S0 in FIG. 45).
[0185]
As a first step, as shown in FIG. 13B, the switching element S (0) is turned off (OFF state), and then the switching element S (1) is turned on. At this time, the energy of the potential V1 (= 1 / 4.VH) is stored in the capacitor C (1), and no electric charge is stored in the capacitive load 311. There is a potential difference of VH / 4 with the load 311. Due to this potential difference VH / 4, charges corresponding to the ratio between the capacitance C1 of the capacitor C (1) and the capacitance Cd of the capacitive load 311 move from the capacitor C (1) to the capacitive load 311. That is, electrostatic energy (hereinafter, simply referred to as “energy”) is injected from the capacitor C (1) to the capacitive load 311 to charge the capacitive load 311 (S1 in FIG. 45). The potential of the capacitor C (1) decreases by the amount of charge flowing into the capacitive load 311. Conversely, the potential of the capacitive load 311 increases by the amount of charge flowing from the capacitor C (1). When the capacitance C1 of the capacitor C (1) is sufficiently larger than the capacitance Cd of the capacitive load 311 (C1> Cd), the change in the potential of the capacitor C (1) is small. When the switching element S (1) is in the connection state for a sufficiently long time, the potential of the capacitor C (1) and the potential of the capacitive load 311 become equal due to the transfer of energy. Therefore, the potentials of the capacitor C (1) and the capacitive load 311 after charging are slightly lower than the initial potential VH / 4 (= V1) of the capacitor C (1) (see FIG. 15). This potential is defined as V1 '.
[0186]
As a second step, as shown in FIG. 13C, the switching element S (1) is turned off, and then the switching element S (2) is turned on. At this time, since the energy of the potential V2, which is higher than the potential V1 ', is stored in the capacitor C (2), the capacitance C2 of the capacitor C (2) and the capacitance Cd of the capacitive load 311 are equal to each other. Transfer from the capacitor C (2) to the capacitive load 311. That is, energy is injected from the capacitor C (2) to the capacitive load 311 by the potential difference V2-V1 ′ (= VH / 4 + α; α is smaller than VH), and the capacitive load 311 is further charged. (S2 in FIG. 45). The potential of the capacitor C (2) decreases by the amount of charge flowing into the capacitive load 311. Conversely, the potential of the capacitive load 311 increases by the amount of charge flowing from the capacitor C (2). When the capacitance C2 of the capacitor C (2) is sufficiently larger than the capacitance Cd of the capacitive load 311 (C2> Cd), the change in the potential of the capacitor C (2) is small. When the time during which the switching element S (2) is connected is sufficiently long, the potential of the capacitor C (2) and the potential of the capacitive load 311 become substantially equal due to the transfer of energy. Therefore, the potentials of the capacitor C (2) and the capacitive load 311 after charging are slightly lower than the initial potential 2VH / 4 (= V2) of the capacitor C (2) (see FIG. 15). This potential is set to V2 '.
[0187]
As a third step, as shown in FIG. 13D, the switching element S (2) is turned off, and then the switching element S (3) is turned on. At this time, since the energy of the potential V3 which is higher than the potential V2 'is accumulated in the capacitor C (3), the capacitance C3 of the capacitor C (3) and the capacitance Cd of the capacitive load 311 are equal to each other. Transfer from the capacitor C (3) to the capacitive load 311. That is, energy is injected from the capacitor C (3) to the capacitive load 311 by the potential difference V3-V2 '(= VH / 4 + α), and the capacitive load 311 is further charged (S3 in FIG. 45). The potential of the capacitor C (3) decreases by the amount of charge flowing into the capacitive load 311. Conversely, the potential of the capacitive load 311 increases by the amount of charge flowing from the capacitor C (3). When the capacitance C3 of the capacitor C (3) is sufficiently larger than the capacitance Cd of the capacitive load 311 (C3> Cd), the potential change of the capacitor C (3) is small. If the time during which the switching element S (3) is connected is sufficiently long, the potential of the capacitor C (3) and the potential of the capacitive load 311 become substantially equal due to the transfer of energy. Therefore, the potentials of the capacitor C (3) and the capacitive load 311 after charging are slightly lower than the initial potential 3VH / 4 (= V3) of the capacitor C (3) (see FIG. 15). This potential is set to V3 '.
[0188]
As a fourth step, as shown in FIG. 13D, the switching element S (3) is turned off, and then the switching element S (4) is turned on. At this time, since the power supply voltage (power supply potential) VH is higher than the potential V3 ', energy is injected from the power source 309 to the capacitive load 311 by the potential difference VH-V3' (= VH / 4 + α), and the capacitance is increased. The sexual load 311 is further charged (S4 in FIG. 45). When the time during which the switching element S (4) is connected is sufficiently long, the potential of the capacitive load 311 after charging is raised to the power supply voltage VH.
[0189]
As a fifth step, as shown in FIG. 14A, the switching element S (4) is turned off, and then the switching element S (3) is turned on (S5 in FIG. 45). At this time, since the energy of the potential VH that is higher than the potential V3 ′ of the capacitor C (3) is stored in the capacitive load 311, the potential difference VH−V3 ′ of VH / 4 + α causes the capacitor C ( The charge corresponding to the ratio between the capacitance C3 of 3) and the capacitance Cd of the capacitive load moves to the capacitor C (3), and is charged from the capacitive load 311 to the capacitor C (3). As a result, the potential of the capacitor C (3) increases by the amount of charge flowing from the capacitive load 311. Conversely, the potential of the capacitive load 311 decreases by the amount of charge flowing into the capacitor C (3). When the switching element S (3) is connected for a sufficiently long time, the potential of the capacitor C (3) becomes equal to the potential of the capacitive load 311 due to the transfer of energy. As a result of the charging, the potential of the capacitor C (3) returns to almost the original V3 = 3VH / 4, and energy regeneration from the capacitive load 311 to the capacitor C (3) is performed (S5 in FIG. 45). .
[0190]
As a sixth step, as shown in FIG. 14B, the switching element S (3) is turned off, and then the switching element S (2) is turned on (S6 in FIG. 45). At this time, since the energy of the potential V3, which is higher than the potential V2 ', is stored in the capacitive load 311, the potential difference V3-V2' of VH / 4 + α causes the capacitance C2 of the capacitor C (2) to change. The charge corresponding to the ratio between the capacitance and the capacitance Cd of the capacitive load moves to the capacitor C (2), and is charged from the capacitive load 311 to the capacitor C (2). As a result, the potential of the capacitor C (2) increases by the amount of charge flowing from the capacitive load 311. Conversely, the potential of the capacitive load 311 decreases by the amount of charge flowing into the capacitor C (2). When the time during which the switching element S (2) is connected is sufficiently long, the potential of the capacitor C (2) and the potential of the capacitive load 311 become equal due to the transfer of energy. As a result of charging, the potential of the capacitor C (2) returns to almost the original V2 = 2VH / 4, and energy is regenerated from the capacitive load 311 to the capacitor C (2) (S6 in FIG. 45). .
[0191]
As a seventh step, as shown in FIG. 14C, the switching element S (2) is turned off, and then the switching element S (1) is turned on (S7 in FIG. 45). At this time, since the energy of the potential V2 which is higher than the potential V1 'is accumulated in the capacitive load 311, the capacitance of the capacitor C (1) is increased by the potential difference V2-V1' which is VH / 4 + α. The charge corresponding to the ratio between C1 and the capacitance Cd of the capacitive load moves to the capacitor C (1), and is charged from the capacitive load 311 to the capacitor C (1). As a result, the potential of the capacitor C (1) becomes higher by the amount of charge flowing from the capacitive load 311. Conversely, the potential of the capacitive load 311 becomes lower by the amount of charge flowing into the capacitor C (1). If the time during which the switching element S (1) is connected is sufficiently long, the potential of the capacitor C (1) and the potential of the capacitive load 311 become equal due to the transfer of energy. As a result of the charging, the potential of the capacitor C (1) returns to almost the original V1 = VH / 4, and the energy is regenerated from the capacitive load 311 to the capacitor C (1) (S7 in FIG. 45). .
[0192]
As an eighth step, as shown in FIG. 14D, the switching element S (1) is turned off, and then the switching element S (0) is turned on. At this time, since the energy of the potential V1 'which is higher than the ground potential' is accumulated in the capacitive load 311, the charge of the capacitive load 311 flows out to the ground potential due to the potential difference V1 'which is the potential difference VH / 4 + α. (Discharge), that is, consumed (discarded) (S8 in FIG. 45). Then, the process returns to S1.
[0193]
As described above, in terms of energies in the first to eighth steps S1 to S8, the stored energy of the capacitor C (1) injected into the capacitive load 311 in the first step S1 is determined in the seventh step S7. It is regenerated by energy returned from the capacitive load 311 to the capacitor C (1). The energy injected into the capacitive load 311 in the second step S2 is regenerated by the energy returned from the capacitive load 311 to the capacitor C (1) in the sixth step S6. The energy injected into the capacitive load 311 in the third step S3 is regenerated by the energy returned from the capacitive load 311 to the capacitor C (1) in the fifth step S5. That is, when the first to eighth steps S1 to S8 are combined, in the first to eighth steps S1 to S8, the energy injection to the capacitive load 311 is performed in the fourth step S4, and the energy consumption is In step S8 of FIG. 8, the energy transfer in the other steps is canceled by the opposing step (see FIG. 15), so that the energy injection / consumption is not apparently performed. As a result, only the energy corresponding to the same １ ／ · VH is consumed. That is, charging and discharging can be performed with 25% energy consumption as compared with a method such as Push-Pull in which the voltage VH is charged and discharged as it is.
[0194]
As a more specific example, a voltage change when a pulse having a peak value of 10 Vpp is created using the four-stage capacitive load driving circuit 301 will be described. When 10 V is divided into four, the potential difference per stage becomes 2.5 V, and the respective potentials of the capacitors C (1) to C (3) are 2.5 V, 5.0 V, 7.5 V, the ground potential 0 V and the power supply potential. It is divided into five potentials of 10V. It is preferable that the capacitance of the capacitors C (1) to C (3) is larger than the capacitance of the capacitive load 311. However, in order to make the operation easier to understand, the capacitance is four times that of the capacitive load 311. And A semiconductor switch such as a half FET (field effect transistor) or a GTO thyristor is usually used for the switching elements S (0) to S (4) used in the system. However, in the case of a semiconductor switch, the ON resistance cannot be ignored. The charging and discharging of the capacitive load 311 is performed exponentially with a specific time constant. Therefore, in the case of waveform formation, the relationship between the ON time of the switching elements S (0) to S (4) and the time constant of charging / discharging the capacitive load 311 is important. The resistance is very small, and the calculation is performed on the assumption that the switching to the next stage is performed in a sufficiently long switching time in which the influence of the system due to the ON resistance of the switching elements S (0) to S (4) can be ignored. Table 1 shows the calculation results. In Table 1, Vd represents the potential of the capacitive load 311, Vs_0 represents the ground potential, Vs_n (n is 1 to 3) represents the potential of the capacitor C (n) in each stage, and Vs_4 represents the power supply potential.
[0195]
[Table 1]

[0196]
As is apparent from this result, when energy is injected from each capacitor to the capacitive load, the potential of each capacitor also decreases accordingly. However, conversely, when energy is injected from the capacitive load to each capacitor, the potential of each capacitor returns to its original state, and as a result, power is regenerated.
[0197]
As described above, the capacitive load drive circuit 301 according to the present embodiment includes the power supply terminal 309a to which the power supply potential VH is applied from the power source 309 and the ground terminal C (0) to which the ground potential (reference potential) is applied. (Reference potential terminal) and three capacitors C (1) to C (3) provided with initial potentials V (1) to V (3) different from each other between the ground potential and the power supply potential VH. , Grounding terminal C (0), capacitors C (1) to C (3), and switching elements S (0) to S (4) for selectively connecting power supply terminal 309a to capacitive load 311. The switching elements S (0) to S (4) connect the capacitors C (1) to C (3) after the ground terminal C (0) is connected to the capacitive load 311 so that their initial potentials are close to the ground potential. By connecting to the capacitive load 311 in order from the A first step (S1 to S3) of changing the terminal voltage of the capacitive load 311 so as to approach the power supply potential VH, and then selectively connecting the capacitive load 311 to the power supply terminal 309a to thereby change the terminal voltage of the capacitive load 311 The second step (S4) is to increase the absolute value of, and thereafter, the capacitors C (1) to C (3) are connected to the capacitive load 311 in order from the one whose initial potential is closer to the power supply potential VH. A third step of reducing the absolute value of the terminal voltage of the capacitive load 311 and regenerating the stored electrostatic energy of the capacitors C (1) to C (3) so as to be substantially equal to that before the first step ( S5 to S7).
[0198]
Here, the number of capacitors to which the initial potential is different between the ground potential and the power supply potential VH and which is different from each other is three, and the number of steps for charging (or discharging) the capacitive load 311 (switching) There has been described the case where the number of potential types of the elements S (0) to S (4) is one and the number of capacitors is one more than the number of capacitors;
[0199]
However, the number of stages is not particularly limited as long as it is two or more. Ideally, the regeneration efficiency is 50% for two stages, 66.7% for three stages, 75% for four stages, and 80% for five stages. The regeneration efficiency increases as the number of stages increases. However, as the number of stages increases, the time required for voltage rise increases, and the number of required circuits also increases. Therefore, the number of stages may be determined based on the required drive waveform, circuit size, cost, and the like. Generally, a three- to four-stage circuit configuration is preferable when high-speed startup is required, and a four- to five-stage circuit configuration is preferable when power consumption is to be suppressed.
[0200]
In the above description, the case where the power supply voltage VH is equally divided into four stages has been described, but it is not always necessary to divide the power supply voltage VH equally. However, the capacitive load driving circuit 301 according to the present embodiment includes a capacitive load driving circuit 301 having a potential ranging from the capacitor C (I) (I = 1, 2, 3) to V (I-1) (where V (0) = 0). The energy decrease of the capacitor C (I) due to the energy injection (S1 to S3) into the load 311 is transferred from the capacitive load 311 having the potential of V (I) (where V (4) = VH) to C (I). Since power regeneration is performed based on the principle of regeneration by energy injection (S5 to S8), equal division is most preferable for performing ideal power regeneration.
[0201]
Here, the time constant of the capacitive load 311 and the switching time of the capacitor C (I) will be considered.
[0202]
In the circuit shown in FIG. 27, considering the state where the initial potential is applied to the capacitor Cs and the capacitive load Cd is discharged, after the switch SW is turned on, the voltage of the capacitive load Cd becomes as shown in FIG. It rises over time. After a sufficient time has passed, the potential difference between the capacitive load Cd and the capacitor Cs disappears, and the current I becomes zero. In the present specification, this saturation voltage is referred to as “attained voltage”.
[0203]
In the circuit shown in FIG. 27, assuming that the switch is turned off after a certain time (switching time (Ts)) has elapsed, the switching time (Ts) has a time constant (τo = R · Cd; R is the energy storage element and the capacitance When the DC resistance component of the charging path or the discharging path including the load and Cd is shorter than the capacitance of the capacitive load (Cd), the voltage of the capacitive load Cd changes as shown in FIG. Therefore, in the three-stage capacitive load driving circuit according to the present invention, the voltage of the capacitive load Cd changes as shown in FIG.
[0204]
When the switching time (Ts) is equal to the time constant (τo = R · Cd), the voltage of the capacitive load Cd changes as shown in FIG. Therefore, in the three-stage capacitive load driving circuit according to the present invention, the voltage of the capacitive load Cd changes as shown in FIG.
[0205]
When the switching time (Ts) is longer than the time constant (τo = R · Cd), the voltage of the capacitive load Cd changes as shown in FIG. Therefore, in the three-stage capacitive load driving circuit according to the present invention, the voltage of the capacitive load Cd changes as shown in FIG.
[0206]
In the capacitive load drive circuit according to the present invention, the capacitance component of the energy storage element is Cs, the capacitance of the capacitive load is Cd, and the DC resistance component of the charging path or the discharging path including the energy storage element and the capacitive load. Is R, and the switching time of the energy storage element (switching time; time during which connection to the capacitive load is continued) is Ts.
τo ≦ Ts ≦ 2.5 · τo
(However, τo = R · Cd)
It is preferable that When Ts <τo, the peak value of the obtained pulse becomes 63% or less of the attained voltage, and the efficiency of supplying energy to the capacitive load decreases. If Ts> 2.5 · τo, the switching time becomes extremely long.
[0207]
[Embodiment 5]
Next, still another embodiment of the present invention will be described below with reference to FIGS. For the sake of convenience, members having the same functions as those described in the fourth embodiment will be denoted by the same reference numerals, and description thereof will be omitted.
[0208]
The capacitive load driving circuit 302 according to the present embodiment includes a capacitor C as an energy storage element between the power source 309 and the switching element S (4) connected thereto in the capacitive load driving circuit 301 according to the fourth embodiment. (N) is added to generalize the number of stages (the number of capacitors).
[0209]
As shown in FIGS. 16 and 17, the capacitive load drive circuit 302 according to the present embodiment includes a ground terminal C (0) having a ground potential (reference potential) V (0) (= 0) and an initial non-zero terminal. N capacitors C (1)... C (N) (energy storage elements) having potentials V (1)... V (N) (N is a natural number of 2 or more) and a ground terminal C (0) (reference potential terminal) ) And the capacitive load 311, a switching element S (0) (switching means), and N capacitors C (1)... C (N) (switching means) for selectively connecting the capacitive load 311. A switching element S (1)... S (N), and a capacitor C (N) connected to a power generation source (directly or through any circuit); .. C (N) are non-zero first initial values. A capacitor C (I) (first energy storage element) having a potential V (I) and a second initial potential V having the same polarity as the initial potential V (I) and an absolute value larger than the initial potential V (I). (I + 1) (second energy storage element), and the switching elements S (0) to S (N) (switching means) connect the capacitive load 311 to the ground terminal or the capacitor C ( I-1) The potential (terminal voltage) of the capacitive load 311 by selectively connecting the capacitive load 311 to the capacitor C (I) after selectively connecting to the (ground terminal or the third energy storage element). Is changed so as to approach the initial potential of the capacitor C (I), and thereafter, by selectively connecting the capacitive load 311 to the capacitor C (I + 1), the potential of the capacitive load 311 (terminal Pressure), the absolute value of the potential (terminal voltage) of the capacitive load 311 is reduced by selectively connecting the capacitive load 311 to the capacitor C (I) thereafter. And a discharging step of regenerating the stored electrostatic energy of the capacitor C (I) so as to be substantially equal to that before the first charging step. In FIG. 16, a circuit for giving an initial charge is omitted.
[0210]
The operation of the above configuration will be described with reference to FIG.
[0211]
Regarding the energy consumption of the pulse generation, the charge transfer from the capacitor C (N) to the capacitor C (N-1) is transported toward the ground potential and is consumed at the ground terminal C (0). The cycles of FIGS. 17A to 17F have the same effects as the cycles of steps S1 to S8 in the fourth embodiment. That is, the electric charge flowing out of the capacitor C (I) at the time of transition from FIG. 17 (a) to FIG. 17 (b) and the electric charge of the capacitor C (at the time of transition from FIG. 17 (d) to FIG. By making the charge flowing into I) approximately equal, the capacitor C (I) apparently consumes no energy in the cycles of FIGS. 17A to 17F.
[0212]
Therefore, it is sufficient that at least the cycles of FIGS. 17A to 17F are executed, and even if all of the N capacitors C (1). May be used. The capacitor to be used may be appropriately set according to the pulse to be generated. For example, when the base potential is the ground potential and a pulse having a large pulse amplitude is to be generated, all the capacitors C (1) to C (N) may be used. When the peak value of the pulse to be generated is lower than the power supply voltage VH or when it is desired to generate a pulse whose base potential is not the ground potential, only a part of the capacitors may be used.
[0213]
Therefore, the capacitive load driving circuit 302 according to the present embodiment includes a plurality of capacitors C (1)... C to which a plurality of different initial potentials V (1)... V (N) (N is a natural number of 2 or more). (N) and switching elements S (1)... S (N) for selectively connecting the capacitors C (1)... C (N) to the capacitive load 311; 1) C (N) is a capacitor C (I) having a non-zero first initial potential V (I), and a second initial potential V (I) having an absolute value larger than the first initial potential V (I). I (1 + 1) and a third initial potential V (I) having the same polarity as the first initial potential V (I) and having a smaller absolute value than the first initial potential V (I). -1) and a switching element S (1)... S (N) By selectively connecting the capacitive load 311 to the capacitor C (I-1) and then selectively connecting it to the capacitor C (I), the terminal voltage 311 of the capacitive load approaches the first initial potential. A first charging step of changing, and thereafter, the capacitive load 311 is selectively connected to the second initial potential V (I + 1) and the energy storage element to increase the absolute value of the terminal voltage of the capacitive load 311. In the second charging step, the absolute value of the terminal voltage of the capacitive load 311 is reduced by selectively connecting the capacitive load 311 to the capacitor C (I), and the first capacitor C (I). And a discharging step for regenerating the accumulated electrostatic energy of the first charging step so as to be substantially equal to that before the first charging step.
[0214]
Also, the initial potentials V (1)... V (N) may be positive or negative, but when the initial potentials V (1). The indicated pulse can be generated. When the initial potentials V (1)... V (N) are negative, for example, a pulse shown in FIG. 19 can be generated.
[0215]
Note that, in the present embodiment, the operation is performed even without the capacitor C (N) connected to the power source 309 (usually built in the power source 309).
[0216]
Therefore, the capacitive load drive circuit 302 according to the present embodiment is different from the power supply terminal (VH) to which the power supply potential VH is applied from the power source 309 with a plurality of different initial potentials V (1)... V (N) (N C (1)... C (N) to which a natural load of 2 or more is added, and the capacitors C (1)... C (N) and the power supply terminal (VH) are selectively loaded into the capacitive load 311. .. S (N) for connection to the first and second capacitors C (1)... C (N). A capacitor C (I) having an initial potential V (I) of 1 and a third potential having the same polarity as the first initial potential V (I) and an absolute value smaller than the first initial potential V (I). And a capacitor C (I-1) having an initial potential V (I-1) of .. S (N) selectively connect the capacitive load 311 to the capacitor C (I-1) and then selectively connect to the capacitor C (I), so that the capacitive load 311 A first charging step of changing the terminal voltage to approach the first initial potential V (I), and thereafter, by selectively connecting the capacitive load 311 to the power supply terminal (VH), A second charging step of increasing the absolute value of the terminal voltage, and thereafter selectively connecting the capacitive load 311 to the capacitor C (I) to reduce the absolute value of the terminal voltage of the capacitive load 311; And a discharging step of regenerating the stored electrostatic energy of the capacitor C (I) so as to be substantially equal to that before the first charging step.
[0217]
Next, in the four-stage capacitive load drive circuit 301 shown in FIG. 12, the capacitance components of the capacitors C (1) to C (3), the capacitance of the capacitive load 311 and the switching elements S (1) to S (1). The switching time of S (3) and the setting of the resistance value of the charge / discharge path will be considered. The voltage of the capacitive load 311 is 90 of the voltage reached during the first to third steps (the final voltage reached by the voltage of the capacitive load 311 when the first to third steps are continued for an infinite time). % May be desirable. Therefore, conditions for that are determined.
[0218]
First, the switching time of the switching element S (1) is the time of the first step, the switching time of the switching element S (2) is the time of the second step, and the switching time of the switching element S (3) is the third step. And these are assumed to be equal to each other.
[0219]
Here, assuming that the capacitance of the capacitive load 311 is Cd (unit F) and the resistance value of the charge and discharge path of the capacitors C (1) to C (3) with respect to the capacitive load 311 is R (unit Ω). , The charging / discharging time constant τ0 (unit sec) of each of the capacitors C (1) to C (3) is expressed by the following equation.
τ0 = R · Cd
Is represented by The capacitance component of the capacitors C (1) to C (3) is Cs (unit F), the load capacitance ratio Cd / Cs is X, and the switching time of the switching elements S (1) to S (3) is Ts (unit sec). ), The condition under which the voltage of the capacitive load 311 reaches 90% of the attained voltage during the first to third steps can be obtained by theoretical calculation, as shown by the solid line in FIG. FIG. 46 shows the maximum load capacitance at which the voltage of the capacitive load 311 becomes 90% or more of the attained voltage during the first to third steps with respect to the ratio Ts / τ0 between the time constant τ0 and the switch time Ts. Represents the ratio X (= Cd / Cs).
[0220]
As shown in FIG. 46, when Ts / τ0 <2.5, the condition under which the voltage of the capacitive load 311 reaches 90% of the attained voltage during the first to third steps is determined by an approximate curve.
X = 0.164 (Ts / τ0)^0.2198
Is approximately equal to On the other hand, when Ts / τ0 ≧ 2.5, the condition under which the voltage of the capacitive load 311 reaches 90% of the attained voltage during the first to third steps is a straight line.
X = 0.2
Is approximately equal to
[0221]
Therefore, the condition that the voltage of the capacitive load 311 becomes 90% or more of the attained voltage during the first to third steps is approximately as follows:
When Ts / (R · Cd) <2.5
Cd / Cs ≦ 0.164 {Ts / (R · Cd)}^0.2198
When Ts / (R · Cd) ≧ 2.5
Cd / Cs ≦ 0.2
Is represented by
[0222]
Therefore, if the above condition is satisfied, the voltage of the capacitive load 311 becomes 90% or more of the attained voltage during the first to third steps, which is preferable. If the above equations do not hold, the voltage change of the capacitors C (1) to (3) due to the outflow of charges from the capacitors C (1) to (3) to the capacitive load 311 becomes large, and the first to the third During the step, the voltage of the capacitive load 311 does not reach 90% of the reached voltage. As a result, the power regeneration rate at the time of pulse generation deteriorates, which impairs energy-saving driving of the capacitive load drive circuit. If the above equation does not hold, the voltage change of C (1) to C (3) due to one pulse generation is large, and it is necessary to correct the voltage change before the next pulse generation.
[0223]
In the above description, the conditions under which the voltage of the capacitive load 311 becomes 90% or more of the attained voltage during the first to third steps have been considered, but it is also important to improve the energy regeneration rate.
[0224]
In the four-stage capacitive load driving circuit 301 shown in FIG. 12, the capacitance of the capacitive load 311 is represented by Cd (unit F), and the charge and discharge paths of the capacitors C (1) to C (3) with respect to the capacitive load 311. Assuming that each of the resistance values is R (Ω), the time constant τ0 (unit sec) of charging and discharging of each of the capacitors C (1) to C (3) is expressed by the following equation.
τ0 = R · Cd
Is represented by The capacitance component of the capacitors C (1) to C (3) is Cs (unit F), the load capacitance ratio Cd / Cs is X, and the switching time of the switching elements S (1) to S (3) is Ts (unit sec). ), The energy consumption rate (the value obtained by subtracting the energy regeneration rate from 1) with respect to the ratio Ts / τ0 between the time constant τ0 and the switch time Ts when the load capacity ratio X is changed from 0.003 to 0.3. ) Can be obtained by theoretical calculation as shown in FIG.
[0225]
Further, in the capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to two, when the load capacitance ratio X is changed from 0.003 to 0.3, The change of the energy consumption rate with respect to the ratio Ts / τ0 between the time constant τ0 and the switch time Ts is as shown in FIG.
[0226]
In a capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to three, when the load capacitance ratio X is changed from 0.003 to 0.3, The change of the energy consumption rate with respect to the ratio Ts / τ0 between the time constant τ0 and the switch time Ts is as shown in FIG.
[0227]
Further, in the capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to five, when the load capacitance ratio X is changed from 0.003 to 0.3, The change of the energy consumption rate with respect to the ratio Ts / τ0 between the time constant τ0 and the switch time Ts is as shown in FIG.
[0228]
Further, in the capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to six, when the load capacitance ratio X is changed from 0.003 to 0.3, The change of the energy consumption rate with respect to the ratio Ts / τ0 between the time constant τ0 and the switch time Ts is as shown in FIG. Although not shown in FIGS. 47 to 51, the case where the load capacity ratio X was 0.001 was almost the same as the case where the load capacity ratio X was 0.003.
[0229]
From these results, although the energy consumption rate greatly depends on Ts / τ0, the load capacity ratio X is
X ≦ 0.01
It has been found that when the above condition is satisfied, the energy consumption rate can be sufficiently reduced even if the capacitance Cd of the capacitive load increases. When the above expression holds, it is possible to effectively apply the capacitive load 311 without reducing the output voltage of the capacitor. Further, when X ≦ 0.01, the fluctuation of the driving voltage due to the variation or fluctuation (such as temperature change) of the capacitance of the capacitor or the capacitive load is suppressed, and a highly reliable ejection operation becomes possible. A drive system including the capacitive load 311 (a system driven by a capacitive load drive circuit) can be stably operated. On the other hand, when the above equation does not hold, the energy regeneration rate deteriorates when the capacitance Cd of the capacitive load increases.
[0230]
Next, the slew rate (10% -90%) of the waveform of the pulse applied to the capacitive load (10% of the time required for the pulse to rise from 10% to 90% of the peak value, where the pulse is 10% of the peak value) Conditions under which the voltage change when the voltage rises from 90% to 90%) are considered.
[0231]
In the four-stage capacitive load driving circuit 301 shown in FIG. 12, the capacitance of the capacitive load 311 is represented by Cd (unit F), and the charge and discharge paths of the capacitors C (1) to C (3) with respect to the capacitive load 311. Assuming that each of the resistance values is R (unit Ω), the time constant τ0 (unit Sec) of charging and discharging of each of the capacitors C (1) to C (3) is expressed by the following equation.
τ0 = R · Cd
Is represented by The capacitance component of the capacitors C (1) to C (3) is Cs (unit F), the switching time of the switching elements S (1) to S (3) is Ts (unit sec), and the ultimate voltage (capacitor C ( 1) to C (3), when charging is performed over an infinite time, the voltage reached by the capacitive load 311) is V (= 3VH / 4), and the slew rate of the pulse waveform applied to the capacitive load 311 (10% -90%) SR (unit: V / μsec)
x = Ts / τ0
Then, when the load capacitance ratio X is changed from 0.001 to 0.3, the change in the slew rate (10% -90%) SR with respect to the ratio x = Ts / τ0 between the time constant τ0 and the switch time Ts Can be obtained by theoretical calculation as shown in FIG. Although not shown in FIG. 54, the case where the load capacity ratio X was 0.003 to 0.03 was almost the same as the case where the load capacity ratio X was 0.001.
[0232]
Further, in the capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to two, when the load capacitance ratio X is changed from 0.001 to 0.1, The change of the change of the slew rate (10% -90%) SR with respect to the ratio x = Ts / τ0 between the time constant τ0 and the switch time Ts is as shown in FIG. Although not shown in FIG. 52, the case where the load capacity ratio X was 0.003 was almost the same as the case where the load capacity ratio X was 0.001.
[0233]
Further, in the capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to three, when the load capacitance ratio X is changed from 0.001 to 0.1, The change of the change of the slew rate (10% -90%) SR with respect to the ratio x = Ts / τ0 between the time constant τ0 and the switch time Ts is as shown in FIG. Although not shown in FIG. 53, the case where the load capacity ratio X was 0.003 to 0.01 was almost the same as the case where the load capacity ratio X was 0.001.
[0234]
Further, in the capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to five, when the load capacitance ratio X is changed from 0.003 to 0.3, The change of the change of the slew rate (10% -90%) SR with respect to the ratio x = Ts / τ0 between the time constant τ0 and the switch time Ts is as shown in FIG. Although not shown in FIG. 55, the case where the load capacity ratio X was 0.003 to 0.03 was almost the same as the case where the load capacity ratio X was 0.001.
[0235]
Further, in the capacitive load driving circuit in which only the number of stages in the four-stage capacitive load driving circuit 301 shown in FIG. 12 is changed to six, when the load capacitance ratio X is changed from 0.003 to 0.3, FIG. 56 shows the change in the change of the slew rate (10% -90%) SR with respect to the ratio x = Ts / τ0 between the time constant τ0 and the switch time Ts. Although not shown in FIG. 56, the case where the load capacity ratio X was 0.003 to 0.1 was almost the same as the case where the load capacity ratio X was 0.001.
[0236]
From the above results, assuming that the number of executions (the number of stages) of the charging step by each capacitor during one cycle of the driving pulse is N, the limit value of the slew rate (10% -90%) SR is
When N = 2 (two stages), SR = V / (R · Cd) * (0.009y²-0.100y + 0.386)
When N = 3 (three stages), SR = V / (R · Cd) * (0.071y²-0.229y + 0.414)
When N = 4 (four stages), SR = V / (R · Cd) * (0.138y²-0.336y + 0.434)
When N ≧ 5 (5 steps or more), SR = V / (R · Cd) * (0.153y²-0.356y + 0.413)
It was found to be represented by Therefore, in the slew rate design, the switching time and the number of stages can be set based on the above equation.
[0237]
Therefore, the circuit parameters and the switch time for satisfying the slew rate SR required for the device are as follows:
When N = 2 (two stages), SR ≦ V / (R · Cd) * (0.009y²-0.100y + 0.386)
When N = 3 (three stages), SR ≦ V / (R · Cd) * (0.071y²-0.229y + 0.414)
When N = 4 (four stages), SR ≦ V / (R · Cd) * (0.138y²-0.336y + 0.434)
When N ≧ 5 (5 steps or more), SR ≦ V / (R · Cd) * (0.153y²-0.356y + 0.413)
Should be fine.
[0238]
Further, in an apparatus such as an ink jet system requiring a high slew rate of 50 (V / μsec) or more, the following conditions must be satisfied.
[0239]
When N = 2 (two stages), 50 (V / μsec) ≦ V / (R · Cd) * (0.009y²-0.100y + 0.386)
When N = 3 (three stages), 50 (V / μsec) ≦ V / (R · Cd) * (0.071y²-0.229y + 0.414)
When N = 4 (four stages), 50 (V / μsec) ≦ V / (R · Cd) * (0.138y²-0.336y + 0.434)
When N ≧ 5 (5 steps or more), 50 (V / μsec) ≦ V / (R · Cd) * (0.153y²-0.356y + 0.413).
[0240]
Further, it can be seen from the results of FIGS. 52 to 56 that the slew rate of the waveform decreases as the number of stages of the circuit increases.
[0241]
[Embodiment 6]
The capacitive load driving circuit of the present invention charges the capacitive load by supplying the electrostatic energy stored in the plurality of energy storage elements to the capacitive load, and then supplies the energy by discharging the capacitive load to the energy storage element. By recovering, the stored electrostatic energy of the energy storage element is regenerated to almost the same potential as before supply to the capacitive load, but since this regeneration is performed for a limited time, complete Does not return to the original potential. Therefore, when charge and discharge are repeatedly performed without injecting energy after the application of the initial potential, as shown in FIG. Phenomenon) occurs. That is, an energy storage element having an initial potential higher than the intermediate value between the highest potential and the lowest potential has insufficient recovery of energy from the capacitive load, and the potential increases. On the other hand, in an energy storage element having an initial potential lower than the intermediate value between the highest potential and the lowest potential, energy is excessively recovered from the capacitive load, and the potential increases.
[0242]
FIG. 40 shows a capacitive load driving circuit including capacitors C (1) to C (5) having a configuration in which the number of stages of the capacitive load driving circuit 301 in FIG. Capacitors C (1) to C (5) when charging and discharging the capacitive load 311 repeatedly without injecting energy after applying the divided initial potentials to the capacitors C (1) to C (5) FIG. 5 is a diagram showing a voltage change of the first embodiment.
[0243]
Therefore, for the capacitive load drive circuit 302 of the fifth embodiment, the capacitors C (1) to C (N−) excluding the ground terminal C (0) and the capacitor C (N) connected to the power source 309. 1) has power sources 339 (1) to 339 (N-1) (DC power supply), and includes power sources 339 (1) to 339 (N-1) and capacitors C (1) to C (N- 1) are connected by resistance circuits R (1) to R (N-1), and energy is injected from power sources 339 (1) to 339 (N-1) to prevent the above-described voltage drift. Like that.
[0244]
As shown in FIG. 21, with respect to the capacitive load driving circuit 302 of the fifth embodiment, power sources 339 (1) to 339 (N−) connected to capacitors C (1) to C (N−1), respectively. 1) and a configuration in which resistors R (1) to R (N-1) associated with the power source 309 may be added. As shown in FIG. Capacitive load drive having the same configuration as that of the capacitive load drive circuit 302 of the fifth embodiment except that the second power source (reference power supply, reference potential terminal, DC power supply) 319 and the capacitor C (0) are provided. For circuit 303, power sources 339 (1) -339 (N-1) connected to capacitors C (1) -C (N-1) and associated resistors R (1) -R (N- A configuration in which 1) is added may be used. In the case of the configuration shown in FIG. 21, for example, the pulse shown in FIG. 22 can be generated.
[0245]
Here, for the resistors R (1)... R (N-1) provided between the power sources 339 (1) to 339 (N-1) and the capacitors C (1) to C (N-1), R (1)... A time constant determined by R (N-1) and the capacitance components of the capacitors C (1) to C (N-1) is at least 50 times the cycle of the drive pulse applied to the capacitive load 311. Is preferred.
[0246]
That is, the period of the drive pulse applied to the capacitive load 311 (see FIG. 22) is determined by the generated pulse period Tp and the capacitors C (i) (i = 1,..., I-1, I, I + 1,. ) Is C (i), and the resistance value of a resistor R (i) provided between the power source 339 (I) and the capacitor C (I) is R (i). The time constant τ (i) of
τ (i) = C (i) × R (i)
Becomes here,
Tp * 10 ≦ τ (i) = C (i) × R (i)
Is preferably
Tp × 50 ≦ τ (i) = C (i) × R (i)
Is more preferable.
[0247]
The reason will be described below.
[0248]
If the power supply speed from the power sources 339 (1) to 339 (N-1) is too fast, power is supplied from the power sources 339 (1) to 339 (N-1) before the circuit of the present invention performs regeneration. This is done, and the power regeneration efficiency of the entire system is deteriorated.
[0249]
In order to suppress the power supply from the power sources 339 (1) to 339 (N-1) during the time interval between the energy injection into the capacitive load 311 and the regeneration, the power sources 339 (1) to 339 ( The time constant of power supply from N-1) may be at least 20 times the time interval from energy injection to 311 to regeneration. Also, in order to suppress the power supply from the power sources 339 (1) to 339 (N-1) during the time interval between the energy injection into the capacitive load 311 and the regeneration, the power sources 339 (1) to The time constant of power supply from 339 (N-1) may be at least 100 times the time interval from energy injection to regeneration to capacitive load 311.
[0250]
On the other hand, the maximum time interval from energy injection to regeneration is considered to be 考 え of the generated pulse period Tp. Therefore, if the time constant τ (i) of the power supply from the power sources 339 (1) to 339 (N−1) is 10 times or more the generation pulse period Tp, the energy is injected into the capacitive load 311 and the regeneration is performed. Power supply from the power sources 339 (1) to 339 (N-1) during the time interval can be suppressed within 5%. If the time constant τ (i) of the power supply from the power sources 339 (1) to 339 (N−1) is 50 times or more the generated pulse period Tp, the power during the time interval between the energy injection into the 311 and the regeneration The power supply from the sources 339 (1) to 339 (N-1) can be suppressed to within 1%, and the effect on power regeneration can be almost ignored.
[0251]
There is no clear limit on the upper limit of τ (i) / Tp, but if τ (i) / Tp is too large, power is not supplied from power sources 339 (1) to 339 (N−1). In other words, if an imbalance occurs between energy supply and regeneration for some reason, the system cannot be stabilized. That is, the time constant τ (i) of the power supply from the power sources 339 (1) to 339 (N−1) is preferably as small as possible within a range where the influence on the energy regeneration rate is small.
[0252]
[Embodiment 7]
The matrix display device includes a display element array (display element) 340, a column selection drive circuit 341, a row selection drive circuit 342, and a power source 349 for supplying power to the row selection drive circuit 342. The display element array 340 is selected from a row selection drive circuit (drive circuit) 342 and a column selection drive circuit (drive circuit) 341 and a specific pulse is applied. The display element array here refers to a liquid crystal display element array, a discharge display (plasma display), an EL element array, or the like. At this time, by using the capacitive load drive circuit of the present invention as a column pulse generation circuit for supplying a column pulse to the column selection drive circuit 341, generation of a column pulse and recovery of power from the display element array are performed. FIG. 32 shows a case where the capacitive load driving circuit 305 of the sixth embodiment is used as a column pulse generating circuit (including a power regeneration circuit), but the configuration of the capacitive load driving circuit is particularly limited. Not something.
[0253]
When a pulse generator is required on the row selection drive circuit 342 side, the capacitive load drive circuit of the present invention may be used instead of the power source 349.
[0254]
Embodiment 8
In the ink jet printer, a shear mode recording head using a known piezoelectric material such as ceramic (for example, JP-A-63-247051) can be used. The configuration and function of the recording head used in the shear mode ink jet printer will be described below.
[0255]
FIG. 33 is a plan view showing a part of the recording head as viewed from the recording medium side. FIG. 34 is a longitudinal sectional view of the recording head.
[0256]
As shown in FIG. 33, the recording head 1100 includes a piezoelectric material 200, a top plate 300, and a plurality of ink chambers 400.
[0257]
The piezoelectric material 200 is formed in a comb shape, and is formed such that the ink chambers 400 are fitted in gaps between the comb teeth.
[0258]
The ink chamber 400 includes a drive electrode 500 formed on both side surfaces and a discharge nozzle 600. In this inkjet printer, ink is ejected from the ejection nozzle 600 by generating an electric field between the drive electrodes 500 of the adjacent ink chambers 400. Details will be described later.
[0259]
The top plate 300 is for fitting the plurality of ink chambers 400 into the piezoelectric material 200, and includes a connection electrode made of a conductive resin.
[0260]
In addition, as shown in FIG. 34, ink is stored in an ink tank 700 in the print head 1100, and a procedure described later is performed via a common ink path 800 connected to the ejection nozzles 600 in the plurality of ink chambers 400. Is discharged from the discharge nozzle.
[0261]
Next, a state in which the ink jet printer of the shear mode discharges ink will be described. In the following description, three adjacent ink chambers are distinguished as A channel, B channel, and C channel, respectively. In the following description, a case will be described in which ink is ejected from the B-channel ink chamber. However, the same applies to ink ejection from the A-channel and C-channel ink chambers.
[0262]
The recording head 1100 is configured to drive the driving electrodes 500 (capacitive load) of the ink chambers of the A channel, the B channel, and the C channel by the capacitive load driving circuit according to the present invention.
[0263]
As shown in FIG. 35A, in the normal state where the ink is not ejected, no electric field is applied to the drive electrodes of any of the ink chambers of the A channel, the B channel, and the C channel. The piezoelectric material is polarized in a direction parallel to the surface of the drive electrode, that is, in a direction perpendicular to the drive electric field.
[0264]
Thereafter, as shown in FIG. 36, an ejection pulse is given to the drive electrode 500 of the ink chamber of the B channel. On the other hand, no ejection pulse is given to the ink chambers of the A channel and the B channel.
[0265]
Then, an electric field is generated from the driving electrodes 500 of the ink chambers of the B channel toward the driving electrodes 500 of the ink chambers of the A channel and the C channel. The piezoelectric material tends to move according to the direction of the electric field. As a result, as shown in FIG. 35B, the side wall of the ink chamber of the B channel expands.
[0266]
Thereafter, as shown in FIG. 36, a common pulse is applied to the drive electrodes 500 of the ink chambers of the A channel and the C channel. Then, an electric field is generated from the driving electrodes 500 of the ink chambers of the A channel and the C channel toward the driving electrodes 500 of the ink chamber of the B channel. As a result, as shown in FIG. 35C, the side wall of the ink chamber of the B channel contracts, and the volume in the ink chamber of the B channel decreases. As a result, ink is ejected from the ejection nozzles of the B-channel ink chamber.
[0267]
When ink is not ejected from any of the channels, a common pulse is applied to the drive electrodes 500 of the ink chambers of the A and C channels, and the same potential as the common pulse is applied to the drive electrodes 500 of the ink chamber of the B channel. Is given. As a result, the driving electrodes 500 of the ink chambers of the A to C channels have the same potential, so that no electric field is generated between the driving electrodes 500. Therefore, since the side walls of the ink chambers of any of the channels do not expand or contract, ink is not ejected.
[0268]
As described above, the recording head 1100 achieves a printing operation by repeatedly performing the switching of the discharging channels A to C, that is, by performing three-phase driving.
[0269]
The time AL for applying the ejection pulse and the time AL 'for applying the common pulse are determined by the following equation (1).
[0270]
AL (or AL ') = length of ink chamber / speed of sound in ink ... [1]
Therefore, if all three channels have the same ink chamber length,
AL '= 2AL
Becomes In the case of a general inkjet printer, AL is about 2 μs.
[0271]
[Embodiment 9]
Next, an ink jet printer that can perform printing with higher accuracy and higher speed than the eighth embodiment by improving the ejection operation during the recovery operation of the ink jet printer that performs printing by discharging ink to the recording medium is described. An embodiment will be described.
[0272]
As shown in FIG. 37, the inkjet printer 1001 includes a paper feeding unit (paper feeding device) 1002, a separating unit 1003, a transporting unit 1004, a printing unit (printing unit) 1005, and a discharging unit 1006.
[0273]
The paper feed unit 1002 supplies the sheet P when printing is performed, and includes a paper feed tray 1007 and a pickup roller (not shown). When printing is not performed, the sheet P is stored.
[0274]
The separation unit 1003 is for supplying sheets P supplied from the paper supply unit 1002 to the printing unit 1005 one by one, and includes a paper supply roller 1008 and a separation device 1009. In the separation device 1009, the friction between the pad portion (the contact portion with the sheet) and the sheet is set to be larger than the friction between the sheets. Further, the paper feed roller 1008 is set so that the friction between the paper feed roller 1008 and the sheet is larger than the friction between the pad and the sheet and the friction between the sheets. Therefore, even if two sheets are sent to the separation unit 1003, these sheets can be separated by the paper feed roller 1008 and only the upper sheet can be sent to the conveyance unit 1004.
[0275]
The transport unit 1004 transports the sheets P supplied one by one from the separation unit 1003 to the printing unit 1005, and includes a guide plate 1010 and a roller pair 1011 (transport mechanism). The roller pair 1011 is a member that adjusts the conveyance of the sheet P so that when the sheet P is sent between the recording head 1100 and the platen 1013, ink from the recording head 1100 is sprayed to an appropriate position on the sheet P. .
[0276]
The printing unit 1005 is for printing on the sheet P supplied from the roller pair 1011 of the transport unit 4 and guides the print head 1100 (print head), the carriage 1014 on which the print head 1100 is mounted, and the carriage 1014. A guide shaft 1015 (see FIG. 38), which is a member for performing printing, and a platen 1013 serving as a base for the sheet P during printing.
[0277]
The discharge unit 1006 is for discharging the printed sheet P to the outside of the inkjet printer 1001, and includes an ink drying unit (not shown), a discharge roller 1016, and a discharge tray 1017.
[0278]
In the above configuration, the inkjet printer 1001 performs printing by the following operation.
[0279]
First, a print request based on image information is made to the inkjet printer 1001 from a computer or the like (not shown). Upon receiving the print request, the inkjet printer 1001 carries out the sheet P on the paper feed tray 1007 from the paper feed unit 1002 by a pickup roller.
[0280]
Next, the conveyed sheet P passes through the separation unit 1003 by the paper feed roller 1008, and is sent to the conveyance unit 1004. In the conveyance unit 1004, the sheet P is sent between the recording head 1012 and the platen 1013 by the roller pair 1011.
[0281]
In the printing unit 1005, ink is sprayed from a discharge nozzle of the recording head 1012 onto the sheet P on the platen 1013 in accordance with image information. At this time, the sheet P is temporarily stopped on the platen 1013. While spraying ink, the carriage 1014 is guided by the guide shaft 1015, and is scanned by one line in the main scanning direction D2. When this is completed, the sheet P is moved on the platen 1013 by a fixed width in the sub-scanning direction D1. In the printing unit 1005, printing is performed on the entire surface of the sheet P by continuously performing the above-described processing according to the image information.
[0282]
The printed sheet P is discharged to a discharge tray 1017 by a discharge roller 1016 via an ink drying unit. Thereafter, the sheet P is provided to the user as a printed matter.
[0283]
Next, a control system of the inkjet printer 1001 of the present embodiment will be described.
[0284]
As shown in FIG. 39, the control unit 1018 of the inkjet printer 1001 includes an interface unit 1019, a memory 1020, an image processing unit 1021, and a drive system control unit 1022.
[0285]
The interface unit 1019 is a circuit that exchanges signals with an external device and the image processing unit 1021 and the drive system control unit 1022.
[0286]
The image processing unit 1021 performs image processing based on image information from the interface unit 1019. Further, the image processing unit 1021 is connected to a head driving circuit 1023 that controls driving of the recording head 1100.
[0287]
The drive system control unit 1022 controls driving of the carriage 1014 and conveyance of the sheet P. Specifically, the drive system control unit 1022 is connected to a carriage drive circuit 1024 that controls the drive of the carriage motor, and a paper transport drive circuit 1025 that controls the drive of the paper transport motor.
[0288]
With the above configuration, the inkjet printer drives the recording head 1100, the carriage 1014, the paper transport motor, and the like to perform a printing operation.
[0289]
Next, an ink discharging operation of the recording head 1100, which is a feature of the present embodiment, will be described.
[0290]
The recording head 1100 is used for a shear mode ink jet printer including the piezoelectric material 200, the top plate 300, the plurality of ink chambers 400, and the drive electrodes 500 shown in FIG.
[0291]
In the ejection operation for printing, the plurality of ink chambers 400 divide three adjacent ink chambers into an A channel, a B channel, and a C channel, and perform three-phase driving. The recording head 1100 is configured to drive the driving electrodes 500 (capacitive load) of the ink chambers of the A channel, the B channel, and the C channel by the capacitive load driving circuit according to the present invention. This drive is a three-phase drive described in detail with reference to FIGS. 35 and 36, and a description thereof will be omitted.
[0292]
【The invention's effect】
As described above, in the device of the present invention, the capacitive load drive circuit includes a power supply terminal to which a power supply potential is applied from a power supply, and a reference power supply potential different from the power supply potential supplied from the reference power supply, or a ground potential. And an energy storage element to which an initial potential between the reference potential and the power supply potential is applied, and the reference potential terminal, the energy storage element, and the power supply terminal are selectively connected to a capacitive load. A first charging step of connecting the energy storage element to the capacitive load after connecting the reference potential terminal to the capacitive load, and thereafter connecting the capacitive load to the power supply terminal. A second charging step for selectively connecting, and a discharging step for connecting the energy storage element to the capacitive load thereafter, are performed. The capacitance component of the capacitor is Cs, the capacitance of the capacitive load is Cd, the time during which the connection of the energy storage element is maintained is Ts, and the resistance of the charge / discharge path of the energy storage element to the capacitive load, including the switching means. If the value is R,
When Ts / (R · Cd) <2.5
Cd / Cs ≦ 0.164 {Ts / (R · Cd)}^0.2198
When Ts / (R · Cd) ≧ 2.5
Cd / Cs ≦ 0.2
Is satisfied.
[0293]
Further, in the device of the present invention, as described above, the capacitive load drive circuit includes a power supply terminal to which a power supply potential is applied from a power supply and a reference power supply potential different from the power supply potential supplied from the reference power supply, or a ground potential. A reference potential terminal provided as a reference potential; a plurality of energy storage elements provided with initial potentials different from each other between the reference potential and the power supply potential; a reference potential terminal, a plurality of energy storage elements, and a power supply terminal And a switching unit for selectively connecting the capacitor to a capacitive load, wherein the switching unit connects each reference potential terminal to the capacitive load, and sequentially switches each energy storage element from the one whose initial potential is closer to the reference potential. A first charging step for connecting to the capacitive load, a second charging step for selectively connecting the capacitive load to the power supply terminal, and thereafter each energy storage element And a discharging step of connecting to the capacitive load in order from the one whose initial potential is closer to the power supply potential. The capacitance component of the energy storage element is Cs, the capacitance of the capacitive load is Cd, Assuming that the time during which the connection of the energy storage element is maintained is Ts, and the resistance value of the charge / discharge path of the energy storage element to the capacitive load including the switching means is R,
When Ts / (R · Cd) <2.5
Cd / Cs ≦ 0.164 {Ts / (R · Cd)}^0.2198
When Ts / (R · Cd) ≧ 2.5
Cd / Cs ≦ 0.2
Is satisfied.
[0294]
According to the above configurations, when the absolute value of the terminal voltage of the capacitive load is reduced and the capacitive load is discharged, the stored electrostatic energy of the first energy storage element is supplied to the capacitive load by energy supply. It can regenerate so that it is almost equal to before. Therefore, the first energy storage element apparently does not consume energy, and power regeneration can be performed with high efficiency.
[0295]
Further, according to each of the above configurations, during the first to third steps, the voltage of the capacitive load reaches the final attained voltage (the voltage of the capacitive load reaches the voltage when the first charging step is continued for an infinite time). 90% of the final voltage). As a result, the voltage change of the energy storage element due to the outflow of charges from the energy storage element to the capacitive load is reduced, the power regeneration rate at the time of pulse generation is improved, and power consumption can be further reduced. Further, since the voltage change of the energy storage element due to one pulse generation becomes small, the next pulse can be generated without correcting the voltage change.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a capacitive load drive circuit according to an embodiment of the present invention.
FIGS. 2A and 2B are timing charts showing the operation of the capacitive load driving circuit of FIG. 1, wherein FIG. 2A is a waveform diagram of a synchronization signal, FIG. 2B is a waveform diagram of a control voltage of a transistor, and FIG. It is a waveform diagram of an applied voltage.
3 is an enlarged view of a part of the timing chart shown in FIG. 2 and shows an operation state of a switch. FIG. 3 (a) is a waveform diagram of a synchronization signal, and FIG. 3 (b) is a timing chart showing an operation state of the switch. The chart, (c) is a waveform diagram of the control voltage of the transistor, and (d) is a waveform diagram of the voltage applied to the capacitor.
FIG. 4 is a circuit diagram showing a configuration of a capacitive load drive circuit according to still another embodiment of the present invention.
FIG. 5 is a perspective view showing a main part of an ink jet printer (image forming apparatus) according to one embodiment of the present invention.
FIG. 6 is a cross-sectional view illustrating a configuration of an inkjet head provided in the inkjet printer (image forming apparatus) of FIG.
7A and 7B are diagrams illustrating an example of a conventional capacitive load drive circuit, where FIG. 7A is a circuit diagram illustrating a configuration of the capacitive load drive circuit, and FIGS. FIG. 4D is a waveform diagram of a control voltage for controlling the operation of one transistor, FIG. 4D is a waveform diagram of a terminal voltage of a capacitor to be driven, and FIG.
FIG. 8 is a circuit diagram showing an example of a conventional capacitive load driving circuit.
9A to 9E are circuit diagrams for explaining the operation of the conventional capacitive load drive circuit shown in FIG.
FIG. 10 is a circuit diagram showing another example of a conventional capacitive load driving circuit.
11 is a waveform diagram for explaining the operation of the conventional capacitive load driving circuit shown in FIG. 10, and shows the terminal voltage of the capacitive load and the state of the switch.
FIG. 12 is a circuit diagram showing a configuration of a capacitive load drive circuit according to still another embodiment of the present invention.
FIGS. 13A to 13E are circuit diagrams for explaining the operation of the capacitive load drive circuit shown in FIG.
FIGS. 14A to 14D are circuit diagrams illustrating the operation of the capacitive load drive circuit shown in FIG.
FIG. 15 is a waveform chart for explaining the operation of the capacitive load drive circuit shown in FIG.
FIG. 16 is a circuit diagram showing a configuration of a capacitive load drive circuit according to still another embodiment of the present invention.
17 (a) to (f) are circuit diagrams for explaining the operation of the capacitive load drive circuit shown in FIG.
18 is a waveform chart showing an example of a waveform of a pulse generated by the capacitive load driving circuit shown in FIG.
19 is a waveform chart showing another example of a waveform of a pulse generated by the capacitive load driving circuit shown in FIG.
FIG. 20 is a circuit diagram showing a configuration of a capacitive load drive circuit according to still another embodiment of the present invention.
FIG. 21 is a circuit diagram showing a configuration of a capacitive load drive circuit according to still another embodiment of the present invention.
FIG. 22 is a waveform chart showing an example of a pulse generated by the capacitive load drive circuit shown in FIG. 21.
FIG. 23 is one of circuit diagrams for explaining the principle of the present invention.
24A and 24B are diagrams for explaining the principle of the present invention, in which FIG. 24A is a graph showing a voltage change, and FIG. 24B is a graph showing a current change.
FIG. 25 is another circuit diagram for explaining the principle of the present invention.
FIG. 26 is another circuit diagram for explaining the principle of the present invention.
FIG. 27 is a diagram schematically showing energy supply from one capacitor to a capacitive load in the capacitive load drive circuit according to the present invention.
FIG. 28 is a graph showing a voltage change of a capacitive load due to energy supply from a capacitor.
FIG. 29A is a graph showing a voltage change of a capacitive load due to energy supply from one capacitor, and FIG. 29B is a graph showing capacitance due to energy supply from a plurality of capacitors in the capacitive load drive circuit according to the present invention. 7 is a graph showing a change in voltage of a reactive load, and shows a case where a switching time (Ts) from a capacitor is shorter than a time constant (R · Cd).
30A is a graph showing a voltage change of a capacitive load due to the supply of energy from one capacitor, and FIG. 30B is a diagram showing the capacitance due to the supply of energy from a plurality of capacitors in the capacitive load drive circuit according to the present invention. 5 is a graph showing a voltage change of a reactive load, and shows a case where a switching time (Ts) is equal to a time constant.
FIG. 31 (a) is a graph showing a voltage change of a capacitive load due to energy supply from one capacitor, and FIG. 31 (b) is a capacitance due to energy supply from a plurality of capacitors in the capacitive load drive circuit according to the present invention. 7 is a graph showing a voltage change of a reactive load, and each shows a case where a switching time (Ts) is longer than a time constant.
FIG. 32 is a diagram showing a display device using a capacitive load drive circuit according to one embodiment of the present invention.
FIG. 33 is a plan view showing a part of the recording head as viewed from the recording medium side.
FIG. 34 is a longitudinal sectional view of a recording head.
FIGS. 35A to 35C are cross-sectional views illustrating the operation of the recording head of FIG.
36 is a pulse waveform chart for explaining the operation of the recording head in FIG.
FIG. 37 is a sectional view showing an ink jet printer (image forming apparatus) using a capacitive load drive circuit according to another embodiment of the present invention.
FIG. 38 is a perspective view showing an inkjet printer (image forming apparatus) using a capacitive load drive circuit according to another embodiment of the present invention.
39 is a block diagram illustrating a control system of the inkjet printer (image forming apparatus) in FIG. 37.
FIG. 40 is a diagram illustrating a voltage change of the energy storage element when the capacitive load is repeatedly charged and discharged in the capacitive load drive circuit according to one embodiment of the present invention.
FIG. 41 is a circuit diagram showing a configuration of a capacitive load drive circuit according to still another embodiment of the present invention.
42 is a timing chart showing the operation of the capacitive load driving circuit of FIG. 41, (a) is a waveform diagram of a synchronization signal, (b) is a waveform diagram of a control voltage of a switch, and (c) is a waveform diagram of a capacitor. It is a waveform diagram of an applied voltage.
43 shows a part of the timing chart shown in FIG. 42 in an enlarged manner and shows the operation state of the switch. FIG. 43 (a) is a waveform diagram of a synchronization signal, and FIG. 43 (b) is a timing chart showing the operation state of the switch. The chart, (c) is a waveform diagram of a control voltage of a switch (switching means), and (d) is a waveform diagram of a voltage applied to a capacitor.
FIG. 44 is a circuit diagram showing a configuration of a capacitive load drive circuit according to still another embodiment of the present invention.
FIG. 45 is a flowchart showing a capacitive load driving method according to an embodiment of the present invention.
FIG. 46 shows that in the capacitive load driving circuit shown in FIG. 12, the voltage of the capacitive load is 90% or more of the attained voltage during the first to third steps with respect to the ratio between the time constant and the switch time. 4 is a graph showing a maximum load capacity ratio.
FIG. 47 shows a case where the load capacitance ratio is changed from 0.003 to 0.3 in the capacitive load drive circuit in which only the number of stages is changed to two in the four-stage capacitive load drive circuit shown in FIG. 6 is a graph illustrating a change in an energy consumption rate of a switching element with respect to a ratio between a time constant and a switch time.
FIG. 48 illustrates a case where the load capacitance ratio is changed from 0.003 to 0.3 in the capacitive load drive circuit in which only the number of stages is changed to three in the four-stage capacitive load drive circuit illustrated in FIG. 6 is a graph illustrating a change in an energy consumption rate of a switching element with respect to a ratio between a time constant and a switch time.
FIG. 49 shows the energy consumption of the switching element with respect to the ratio between the time constant and the switch time when the load capacitance ratio is changed from 0.003 to 0.3 in the four-stage capacitive load drive circuit shown in FIG. It is a graph showing the change of a rate.
50 is a diagram illustrating a case where the load capacitance ratio is changed from 0.003 to 0.3 in the capacitive load drive circuit in which only the number of stages is changed to five in the four-stage capacitive load drive circuit illustrated in FIG. 6 is a graph illustrating a change in an energy consumption rate of a switching element with respect to a ratio between a time constant and a switch time.
FIG. 51 shows a capacitive load drive circuit in which only the number of stages in the four-stage capacitive load drive circuit shown in FIG. 12 is changed to six, when the load capacitance ratio is changed from 0.003 to 0.3. 6 is a graph illustrating a change in an energy consumption rate of a switching element with respect to a ratio between a time constant and a switch time.
FIG. 52 shows a case where the load capacitance ratio X is changed from 0.001 to 0.1 in the capacitive load drive circuit in which only the number of stages is changed to two in the four-stage capacitive load drive circuit shown in FIG. 7 is a graph showing a change in a slew rate (10% -90%) with respect to a ratio between a time constant and a switch time.
FIG. 53 shows a case where the load capacitance ratio X is changed from 0.001 to 0.1 in the capacitive load drive circuit of FIG. 12 in which only the number of stages is changed to three. 7 is a graph showing a change in a slew rate (10% -90%) with respect to a ratio between a time constant and a switch time.
FIG. 54 shows a slew rate (10%) with respect to the ratio between the time constant and the switch time when the load capacitance ratio is changed from 0.001 to 0.3 in the four-stage capacitive load drive circuit shown in FIG. It is a graph showing the change of (-90%).
FIG. 55 shows a case where the load capacitance ratio X is changed from 0.003 to 0.3 in the capacitive load drive circuit in which only the number of stages is changed to five in the four-stage capacitive load drive circuit shown in FIG. 7 is a graph showing a change in a slew rate (10% -90%) with respect to a ratio between a time constant and a switch time.
FIG. 56 shows a case where the load capacitance ratio X is changed from 0.003 to 0.3 in the capacitive load drive circuit in which only the number of stages is changed to six in the four-stage capacitive load drive circuit shown in FIG. 7 is a graph showing a change in a slew rate (10% -90%) with respect to a ratio between a time constant and a switch time.
[Explanation of symbols]
1 Capacitive load drive circuit
2a to 2i capacitors (energy storage elements)
3 Battery
4 Resistance
5 voltage divider (voltage division means)
6. Transistor (switching part)
7. Switch (switching means)
9 Power supply terminal
11 Capacitor (capacitive load)
16A switch (switching part)
21 Piezoelectric element (capacitive load)
23 Inkjet head
210 Inkjet Printer (Image Forming Apparatus)
301, 302, 303, 305 Capacitive load drive circuit
309, 319, 339 Power source (power supply, DC power supply)
311 Capacitive load
C (0) Ground terminal (reference potential terminal)
C (1) to C (3), C (0) to C (N) Capacitor (energy storage element)
S (0) to S (4), S (0) to S (N) Switching element (switching means)
R (1) to R (N-1) resistance circuit
SW1 to SW9 switch (switching part)

Claims (8)

In a device including a capacitive load and a capacitive load drive circuit for charging and discharging the capacitive load,
The capacitive load driving circuit is
A power supply terminal provided with a power supply potential from a power supply;
A reference power supply potential different from the power supply potential supplied from the reference power supply, or a reference potential terminal to which a ground potential is applied as a reference potential;
An energy storage element to which an initial potential between the reference potential and the power supply potential has been applied;
A switching unit for selectively connecting the reference potential terminal, the energy storage element, and the power supply terminal to the capacitive load,
The switching means includes a first charging step of connecting the energy storage element to the capacitive load after connecting the reference potential terminal to the capacitive load, and a second charging step of selectively connecting the capacitive load to the power supply terminal after that. A charging step and a discharging step for connecting the energy storage element to the capacitive load thereafter.
The capacitance component of the energy storage element is Cs, the capacitance of the capacitive load is Cd, the time during which the connection of the energy storage element is maintained is Ts, and the charging / discharging path of the energy storage element to the capacitive load, including switching means. Let R be the resistance of
When Ts / (R · Cd) <2.5, Cd / Cs ≦ 0.164 {Ts / (R · Cd)} ^0.2198
When Ts / (R · Cd) ≧ 2.5, Cd / Cs ≦ 0.2
A device characterized by the following. In a device including a capacitive load and a capacitive load drive circuit for charging and discharging the capacitive load,
The capacitive load driving circuit is
A power supply terminal provided with a power supply potential from a power supply;
A reference power supply potential different from the power supply potential supplied from the reference power supply, or a reference potential terminal to which a ground potential is applied as a reference potential;
A plurality of energy storage elements to which a different initial potential is applied between a reference potential and a power supply potential,
A reference potential terminal, a plurality of energy storage elements, and switching means for selectively connecting the power supply terminal to the capacitive load,
The switching means comprises: a first charging step of connecting each energy storage element to the capacitive load in order from the one whose initial potential is closer to the reference potential after connecting the reference potential terminal to the capacitive load; And a discharging step of connecting each energy storage element to a capacitive load in order from the one whose initial potential is closer to the power supply potential. Yes,
The capacitance component of the energy storage element is Cs, the capacitance of the capacitive load is Cd, the time during which the connection of the energy storage element is maintained is Ts, and the charging / discharging path of the energy storage element to the capacitive load, including switching means. Let R be the resistance of
When Ts / (R · Cd) <2.5, Cd / Cs ≦ 0.164 {Ts / (R · Cd)} ^0.2198
When Ts / (R · Cd) ≧ 2.5, Cd / Cs ≦ 0.2
A device characterized by the following. The capacitance of the capacitive load is Cd, the resistance value of the charge / discharge path of the energy storage element to the capacitive load including the switching means is R, the time for which the connection of the energy storage element is maintained is Ts, and the ultimate voltage is V. , The slew rate (10% -90% rise rate) of the generated voltage waveform is defined as SR,
If y = Ts / (R · Cd),
SR ≦ V / (R · Cd) * (0.009y ² −0.100y + 0.386)
The device according to claim 1, wherein the following condition is satisfied. The capacitance of the capacitive load is Cd, the resistance value of the charge / discharge path of the energy storage element to the capacitive load including the switching means is R, the time for which the connection of the energy storage element is maintained is Ts, and the ultimate voltage is V. age,
If y = Ts / (R · Cd),
50 (V / μsec) ≦ V / (R · Cd) * (0.009y ² −0.100y + 0.386)
4. The device according to claim 3, wherein The capacitance of the capacitive load is Cd, the resistance value of the charge / discharge path of the energy storage element to the capacitive load including the switching means is R, the time for which the connection of the energy storage element is maintained is Ts, and the ultimate voltage is V. , The number of executions of the charging step by each energy storage element during one cycle of the driving pulse is N, and the slew rate (10% -90% rise rate) of the generated voltage waveform is SR.
If y = Ts / (R · Cd),
When N = 3, SR ≦ V / (R · Cd) * (0.071y ² −0.229y + 0.414)
When N = 4, SR ≦ V / (R · Cd) * (0.138y ² −0.336y + 0.434)
When N ≧ 5, SR ≦ V / (R · Cd) * (0.153y ² −0.356y + 0.413)
The device according to claim 2, wherein the following condition is satisfied. The capacitance of the capacitive load is Cd, the resistance value of the charge / discharge path of the energy storage element to the capacitive load including the switching means is R, the time for which the connection of the energy storage element is maintained is Ts, and the ultimate voltage is V. The number of executions of the charging step by each energy storage element during one cycle of the driving pulse is N,
If y = Ts / (R · Cd),
When N = 3, 50 (V / μsec) ≦ V / (R · Cd) * (0.071y ² −0.229y + 0.414)
When N = 4, 50 (V / μsec) ≦ V / (R · Cd) * (0.138y ² −0.336y + 0.434)
When N ≧ 5, 50 (V / μsec) ≦ V / (R · Cd) * (0.153y ² −0.356y + 0.413)
The device according to claim 5, wherein the following is satisfied. When the capacitance component of the energy storage element is Cs and the capacitance of the capacitive load is Cd,
Cd / Cs ≦ 0.01
The device according to any one of claims 1 to 6, wherein The capacitive load is an electrostatic drive electrode or a piezoelectric element provided in an inkjet head that ejects the ink in the form of droplets by pressurizing the ink,
8. The apparatus according to claim 1, wherein said capacitive load drive circuit is a drive circuit for driving an electrostatic drive electrode or a piezoelectric element of an ink jet head.

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