JP2004222196A - Device and method for signal processing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speedily and easily perform rate detection when pieces of variable rate convolutional code etc. are received. <P>SOLUTION: The device comprises: a decoding means 51 for decoding received data; an error calculation processing means 53 for performing a calculation process of error detection from a head bit position to a termination bit position in every predetermined unit by using an error detection code added to the data sequentially decoded and inputted by the decoding means; and a storing means 56 for temporarily storing the data inputted to the error calculation processing means. When the data of the termination bit position is inputted to the error calculation processing means, the data is temporarily stored into the storing means after being moved thereto, and the data temporarily stored is moved to the error calculation processing means after inputting the data of termination bit position of each data rate and performing the calculation process for error detection by the error calculation processing means. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal processing apparatus and method for performing maximum likelihood decoding on data encoded by a convolutional code or the like, and particularly to a signal processing apparatus and method for detecting a data rate of transmitted data.
[0002]
[Prior art]
Conventionally, transmission is performed at a predetermined data rate among a plurality of data rates prepared, and the reception side detects the data rate. FIG. 5 shows a configuration example of a communication system including the conventional receiving device 3 and transmitting and receiving data at an arbitrary data rate among a plurality of predetermined data rates.
[0003]
The transmitting device 1 transmits the convolutionally encoded data to the receiving device 3 via the communication path 2 at an arbitrary data rate among a plurality of predetermined data rates.
[0004]
FIG. 6 shows an example of a transport format of data transmitted and received here. According to this format, a CRC (Cyclic Redundancy Check) code is added to the data stream, but since the length of the data stream is variable according to the data rate, the end bit (the last bit of the CRC) n _end Depends on the data rate. In the following description, the last bit of the CRC is replaced with the termination bit n. _end Called.
[0005]
For example, as shown in FIG. 6, when there are four data rates R1, R2, R3, R4 (data rate R1 <data rate R2 <data rate R3 <data rate R4) for each predetermined unit, Termination bit n for each of R1 to R4 _end Is the E1 bit (FIG. 9A), the E2 bit (FIG. 9B), the E3 bit (FIG. 9C), or the This is the E4th bit (FIG. 9D).
[0006]
In the transport format for the data rates R1 to R3, the end bit n of the data rates R1 to R3 _end From the E1 bit, E2 bit, or E3 bit to the end bit n of the data rate R4 _end Until the bit corresponding to the E4th bit, there is an empty section where there is no data.
[0007]
The receiving device 3 performs a Viterbi decoding process on the data (FIG. 6) transmitted from the transmitting device 1 via the communication channel 2. The receiving device 3 also detects the data rate of the received data, and outputs the decoded data at the detected data rate to a data processing device (not shown) connected to the receiving device.
[0008]
Next, the configurations of the transmitting device 1 and the receiving device 3 shown in FIG. 5 will be described.
[0009]
The transmission device 1 has a CRC (Cyclic Redundancy Check) encoder 11, a convolutional encoding unit 12, and a modulation unit 13. The CRC encoder 11 adds the CRC parity bits of the data to be transmitted to the data stream and supplies the data stream to the convolutional encoder 12.
[0010]
The convolutional encoder 12 performs convolutional encoding on the data from the CRC encoder 11 and supplies the data to the modulator 13. The modulator 13 modulates the data from the convolutional encoder 12 and transmits the data to the receiver 3 via the communication channel 2.
[0011]
The receiving device 3 includes a demodulation unit 31, a Viterbi decoding unit 32, a CRC decoder 33, and a data rate detection unit. The demodulation unit 31 demodulates the received data and supplies the demodulated data to the Viterbi decoding unit 32.
[0012]
The Viterbi decoding unit 32 is controlled by the data rate detection unit 34, performs a Viterbi decoding process on the data from the demodulation unit 31, and supplies the data (decoded data) obtained as a result to the CRC decoder 33.
[0013]
The Viterbi decoding unit 32 supplies the calculated maximum path metric value, minimum path metric value, and zero-state path metric value to the data rate detection unit 34.
[0014]
The Viterbi decoding unit 32 outputs the decoded data obtained as a result of the Viterbi decoding process to a device (not shown) at the data rate detected by the data rate detection unit 34.
[0015]
The CRC decoder 33 is controlled by the data rate detection unit 34, performs a CRC determination on the data from the Viterbi decoding unit 32, and supplies the determination result to the data rate detection unit 34.
[0016]
The data rate detection unit 34 controls the Viterbi decoding unit 32 and the CRC decoder 33 to perform Viterbi decoding and CRC determination, and also outputs the maximum path metric value, the minimum path metric value, and the zero state from the Viterbi decoding unit 32. Based on the path metric value and the CRC determination result from the CRC decoder 33, the data rate of the received data is detected.
[0017]
FIG. 7 illustrates a configuration example of the Viterbi decoding unit 32. The ACS unit 35 is a circuit that executes a so-called ACS (Add Compare Select) process of adding, comparing, and selecting, and calculates a branch metric value and a state metric value, and performs a predetermined calculation based on them. , Calculate the path metric value. The ACS unit 35 also supplies the calculated path metric values (the maximum path metric value, the minimum path metric value, and the zero-state path metric value) to the data rate detection unit 34, and, based on the data, detects the maximum likelihood. A high path is selected, and the selection information of the path is supplied to the path memory 36.
[0018]
The path memory 36 stores information (path memory data) on a surviving path based on the selection information from the ACS unit 35 for a predetermined number of bits (L bits) of the received data, and among the likelihood, Is supplied to the CRC decoder 33 as decoded data. The path memory 36 also outputs decoded data at the data rate detected by the data rate detection unit 34.
[0019]
FIG. 8 shows a configuration example of the CRC decoder 33. The CRC calculation unit 37 performs calculation processing for a CRC (Cyclic Redundancy Check) using the decoded data and the path memory data from the Viterbi decoding unit 32 (path memory 36), and supplies the result to the CRC determination unit 38. I do.
[0020]
The CRC determination unit 38 compares the CRC calculated by the CRC calculation unit 37 with the CRC code (see FIG. 6) included in the decoded data from the Viterbi decoding unit 32, and determines whether or not both match. The determination result is supplied to the data rate detection unit 34.
[0021]
Next, the operation of the receiving device 3 when detecting the data rate of the received data will be described with reference to the flowchart of FIG. Here, it is assumed that there are four data rates Ri (i = 1, 2, 3, 4) as data to be received, as shown in FIG.
[0022]
In step S1, the data rate detector 34 initializes the value of a built-in counter i to a value 1, a value of a register Smin to a predetermined value Db, and a value of the register tr to a value 0.
[0023]
In step S2, the data rate detection unit 34 controls the Viterbi decoding unit 32 to calculate the end bit n of the data rate Ri identified by the value of the counter i from the first bit S of the received data. _end , A maximum path metric value, a minimum path metric value, and a zero state path metric value.
[0024]
Thereby, the Viterbi decoding unit 32 (ACS unit 35) calculates the maximum path metric value, the minimum path metric value, and the zero-state path metric value. The Viterbi decoding unit 32 (ACS unit 35) holds the calculated data and supplies the data to the data rate detection unit 34.
[0025]
The receiving device 3 (data rate detection unit 34) recognizes possible data rates Ri in advance, and can identify the data rates Ri based on the value of the counter i.
[0026]
In this example, the value of the counter i is value 1, value 2, value 3, or value 4 (maximum value) (i = 1, 2, 3, 4), and each of the data rates R1, R2, R3, R4 Is identified. That is, in this case, from the first bit S, the E1st (FIG. 6A), the E2th (FIG. 6B), the E3th (FIG. 6C), or the E4th (FIG. D) The maximum path metric value, the minimum path metric value, and the zero-state path metric value are calculated for each of the bits up to the bits of (D)).
[0027]
Next, in step S3, the data rate detection unit 34 calculates the equation (1) based on the maximum path metric value, the minimum path metric value, and the zero state path metric value supplied from the Viterbi decoding unit 32 in step S2. ) To calculate the S value.
S value = 10 Log ((a ₀ -A _min ) / (A _max -A _min )) ・ ・ ・ ・ (1)
In the formula, a _max Is the maximum path metric value, a _min Is the minimum path metric value, and a ₀ Indicates a zero state path metric value. The maximum value of the S value is 0, and the minimum value is minus infinity.
[0028]
In step S4, the data rate detection unit 34 determines whether the S value calculated in step S3 is equal to or less than the threshold D1.
[0029]
If the data rate Ri identified by the value of the counter i is the true data rate of the received data, the zero-state path metric value calculated by the Viterbi decoding unit 32 at this time is a sufficiently small value. The S value shown in (1) is a small value. On the other hand, when the data rate Ri is not the true data rate of the received data, the zero state path metric value calculated at this time does not become a sufficiently small value, and thus the S value does not become a small value. That is, by determining whether or not the calculated S value is equal to or less than the threshold value D1, it is determined whether or not the data rate Ri can be regarded as the true data rate of the received data (the true data rate). Or not).
[0030]
The threshold value D1 is set to a relatively large value so that the S value of the true data rate of the received data is not determined to be NO here (so that it is not determined that the S value is not less than the threshold value D1). Has become.
[0031]
When it is determined in step S4 that the S value is equal to or less than the threshold value D1, that is, the data rate Ri identified by the value of the counter i at this time is determined to be the true data rate of the received data. If possible (when there is a possibility that the data rate is true), the process proceeds to step S5.
[0032]
In step S5, the data rate detection unit 34 controls the Viterbi decoding unit 32 so that the end bit n _end The data stream up to this point is Viterbi decoded, and the CRC decoder 33 is controlled to make a CRC determination based on the decoded data and the path memory data at this time.
[0033]
Thereby, the Viterbi decoding unit 32 refers to the maximum path metric value, the minimum path metric value, the zero-state path metric value, or the like calculated in step S2, and calculates the end bit n of the data rate Ri from the start bit S. _end Viterbi decoding is performed on the data stream up to and the resulting decoded data is supplied to the CRC decoder 33. Further, the Viterbi decoding unit 32 supplies the path memory data stored in the path memory 36 to the CRC decoder 33.
[0034]
For example, when the counter i = 1, as shown in FIG. 10A, the bit L (the (E1-L) th bit) before the E1th bit from the first bit S of the received data. (The data indicated by the solid-line bidirectional arrows in the figure) and the path memory data (in the figure, the data from the (E1-L + 1) th bit to the E1th bit). The data indicated by the dotted double-headed arrow) is supplied to the CRC decoder 33 (CRC calculation unit 37).
[0035]
When the counter i = 2, as shown in FIG. 10B, the decoded data from the first bit S to the (E2-L) -th bit of the received data and the (E2-L + 1) -th bit When the path memory data for the data up to the E2th bit is the counter i = 3, as shown in FIG. 10C, from the first bit S of the received data to the (E3-L) th bit. And the path memory data for the data from the (E3−L + 1) th bit to the E3th bit, and when the counter i = 4, as shown in FIG. The decoded data from the first bit S to the (E4-L) th bit of the data and the path memory data for the data from the (E4-L + 1) th bit to the E4th bit are: It is supplied to the respectively CRC decoder 33 (CRC calculation section 37).
[0036]
The CRC decoder 33 (CRC calculation unit 37) calculates a CRC based on the supplied decoded data and path memory data.
[0037]
The CRC decoder 33 (CRC determination unit 38) compares the calculated CRC with the data of the location where the CRC originally added to the data stream is located, and determines whether or not both match.
[0038]
If the data rate Ri identified by the value of the counter i is the true data rate of the received data, the CRC calculated at this time is compared with the CRC added to the data stream, and both are the same data. In this case, it is determined that they match. On the other hand, if the data rate Ri is not the true data rate of the received data, the CRC calculated at this time is not compared with the CRC added to the data stream (where the CRC is located at the data rate Ri). And the calculated CRC is not the same data as the original CRC added to the data stream, and it is naturally determined that they do not match.
[0039]
The CRC decoder 33 (CRC determination unit 38) notifies the data rate detection unit 34 of the CRC determination result.
[0040]
Returning to FIG. 5, in step S6, the data rate detection unit 34 determines whether an error exists in the received data based on the CRC determination result from the CRC decoder 33. That is, whether or not an error exists in the received data is determined by the CRC determination when the data rate Ri indicated by the value of the counter i at this time is the data rate of the received data. When the CRC determination result indicates that they do not match (when the data rate Ri is not the true data rate), it is determined that an error exists, while when the CRC determination result indicates that they match (true If the data rate is possible), it is determined that no error exists.
[0041]
If it is determined in step S6 that there is no error, the process proceeds to step S7, where the data rate detection unit 34 determines whether the S value calculated in step S3 is smaller than the value of the register Smin. If it is determined, the process proceeds to step S8. Since the value Db initially set in the register Smin is a sufficiently large value, usually, the first calculated S value is smaller than the value Db, and the process proceeds to step S8.
[0042]
In step S8, the data rate detection unit 34 replaces the value of the register Smin with the currently calculated S value. That is, in step S7, it is determined whether the S value calculated this time is the smallest of the S values calculated so far.
[0043]
At this time, the data rate detector 34 also replaces the value of the register tr with the value of the counter i at this time.
[0044]
When it is determined in step S4 that the S value is not less than the threshold value D1, when it is determined in step S6 that an error exists, in step S7, it is determined that the S value is not smaller than the value of the register Smin. When the value of the register Smin and the value of the register tr are replaced in step S8, the process proceeds to step S9.
[0045]
In step S9, the data rate detection unit 34 determines whether or not the value of the counter i is the maximum value (value 4). If it is determined that the value is not the maximum value, the process proceeds to step S10 and the value of the counter i is determined. Is incremented by 1 and the process returns to step S2 to execute the subsequent processing.
[0046]
If it is determined in step S9 that the value of the counter i is the maximum value, the process proceeds to step S11, where the data rate detection unit 34 determines the data rate Ri identified by the value of the register tr as the true value of the received data. Detect as data rate. Then, the data rate detection section 34 controls the Viterbi decoding section 32 (path memory 36) to output the decoded data at the detected data rate Ri. Thereafter, the process ends.
[0047]
By the way, as described above, the threshold value D1 is set to a relatively large value so that the S value at the true data rate is not determined to be larger than the value (step S4). All the S values (step S3) may be determined to be equal to or less than the threshold value D1. That is, CRC determination is performed for all data rates Ri (step S5).
[0048]
Next, an example of a CRC calculation process in the CRC decoder 33 will be described with reference to the flowchart in FIG. Here, the number of bits output from the Viterbi decoding unit 32 is x, the end bit position number assigned to each end bit position is y, the last end bit position number is n, and the number of bits in the path memory is L. . First, the end bit position number y is set to 0 (step S21), and then 1 is added to the end bit position number y (step S22). Also, the number of bits x is set to 0 (step S23), and 1 is added to the number of bits x (step S24).
[0049]
Then, the x-th data of the Viterbi decoding result is input to the CRC calculation unit 37 (step S25). Then, it is determined whether or not the bit number x output by the Viterbi decoding unit 32 is a value obtained by subtracting the bit number L of the path memory from the bit number of the end bit position number y set at this time (step S26). ). The process returns to step S24 until the value reaches the corresponding value, and the output of the Viterbi decoding unit 32 is input.
[0050]
In the determination at step S26, the path memory data of the end bit position number y is set to the number determined to be a value obtained by subtracting the bit number L of the path memory from the bit number of the end bit position number y set at this time. Then, the CRC calculation is completed (step S27). After the completion of the CRC calculation, it is determined whether or not the end bit position number y set at this time is equal to the final end bit position number n (step S28). If the end bit position number y is equal, the CRC calculation processing is terminated. If not equal, the flow returns to step S22 to advance the end bit position number y.
[0051]
The conventional CRC calculation process shown in the flowchart of FIG. 11 is a process of repeating the process of inputting data up to each end bit position and performing an operation each time the end bit position is reached. That is, for example, four types of data rates are set as shown in FIG. _end When there is a position, the data from the first bit shown in FIG. 10A to the end bit position E1 of the end bit position number 1 is input to the CRC calculation unit 37, and the CRC calculation is performed. When the CRC calculation for the end bit position number 1 is completed, the data from the first bit shown in FIG. 10B to the end bit position E2 of the end bit position number 2 is input to the CRC calculation unit 37, Perform CRC operation. Further, when the CRC calculation of the end bit position number 2 is completed, the data from the first bit shown in FIG. 10C to the end bit position E3 of the end bit position number 3 is input to the CRC calculation unit 37, Perform the operation. Further, when the CRC calculation of the end bit position number 3 is completed, the data from the first bit shown in FIG. 10D to the end bit position E4 of the end bit position number 4 is input to the CRC calculation unit 37, Perform the operation.
[0052]
In order to perform the repetitive CRC calculation as shown in the flowchart of FIG. 9, the Viterbi decoding unit 36 needs a memory for temporarily storing output data.
[0053]
By repeating such CRC calculation for each terminal bit position, in step S11 of the flowchart shown in FIG. 9, a correct data rate is detected by the CRC determination processing, and correct decoded data is output.
[0054]
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2002-76923) describes the data rate detection processing described so far.
[0055]
[Patent Document 1]
JP-A-2002-76923
[0056]
[Problems to be solved by the invention]
In the above-described data rate detection processing, for example, when the four types of data rates shown in FIG. 6 exist, it is necessary to repeatedly input data to the CRC calculation unit four times, which takes a long time. there were. Further, since the data temporarily stored in the Viterbi decoding unit needs to be repeatedly sent to the CRC calculation unit, the number of accesses to the memory increases, and there is a problem that the power consumption of the circuit increases. Further, when the area of the memory is shared with another application, there is a problem that the number of accesses to the memory increases, and the probability that other accesses are hindered increases.
[0057]
The present invention has been made in view of such a point, and an object of the present invention is to make it possible to detect the rate of received data by simple processing.
[0058]
[Means for Solving the Problems]
The signal processing device of the present invention detects a data rate of data transmitted at a predetermined data rate selected from a plurality of data rates prepared in advance by error determination based on an error detection code, and detects the data rate. A signal processing device that performs maximum likelihood decoding of received data in a signal processing device that performs maximum likelihood decoding of data at a data rate that has been input, and data decoded by the decoding unit are sequentially input, and an error added to the data is input. Error calculation processing means for performing error detection calculation processing from the first bit to the end bit position of each data rate for each predetermined unit using a detection code, and storage means for temporarily storing data input to the error calculation processing means When the data at the respective end bit positions of the plurality of data rates prepared are input to the error calculation processing means, the data is transferred to the storage means and temporarily stored. Control means for transferring the temporarily stored data to the error calculation processing means after inputting the data at the end bit position of each data rate by the calculation processing means and performing error detection calculation processing; Determining means for determining a data rate of received data based on a calculation result at each end bit position.
[0059]
Further, the signal processing method of the present invention is a signal processing method of performing maximum likelihood decoding on data transmitted by performing error detection coding and error correction coding on data at an arbitrary data rate among a plurality of predetermined data rates. Calculating the average of the received data, normalizing the received data using the calculated average, and selecting a plurality of data in a predetermined order from the output of the normalization step, Assuming that the rate is the selected data rate, performing a maximum likelihood decoding process, a calculating step of subtracting a minimum metric value among predetermined metric values obtained in the maximum likelihood decoding process step, Determining the correct data rate based on the metric value and the error detection result in state 0 at each rate obtained as a result of the calculation in It is characterized in that an output step of outputting the decoded data at the rate determined by the step.
[0060]
By doing so, every time the error calculation processing means performs calculation at each end bit position, the data temporarily saved in the temporary storage means is returned after the error calculation, and the Viterbi decoding processing is performed. By performing the error calculation process only once continuously for one unit of data, the error calculation is performed at the end bit positions at all rates.
[0061]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
[0062]
In this example, similarly to the system described as the conventional example, convolutionally encoded data is applied to a communication system in which data is transmitted and received at an arbitrary data rate among a plurality of predetermined data rates. That is, in the case of this example, as shown in FIG. _end Are the E1st bit (FIG. 6A), the E2th bit (FIG. 6B), the E3th bit (FIG. 6C), counting from the first bit S, Alternatively, a data format in which four types of data rates R1, R2, R3, and R4 (data rate R1 <data rate R2 <data rate R3 <data rate R4), which is the E4th bit (FIG. 6D) There is.
[0063]
FIG. 1 shows an example of the configuration of the receiving apparatus of the present embodiment. This receiving device is a device that receives data that has been convolutionally coded at an arbitrary data rate among a plurality of predetermined data rates on the transmitting side. This transmission data is convolutionally encoded with a CRC parity bit added.
[0064]
The configuration of the receiving apparatus shown in FIG. 1 will be described. The Viterbi decoding unit 51 that receives received data and performs Viterbi decoding performs Viterbi decoding processing of convolutionally encoded and transmitted data. As the configuration of the Viterbi decoding unit 51, for example, the configuration shown in FIG. 7 is applied as a conventional example, and decoded data is output from the path memory 52 included in the Viterbi decoding unit 51.
[0065]
The decoded data output from the path memory 52 is supplied to a CRC calculator 53, where a CRC (Cyclic Redundancy Check) calculation based on the decoded data is performed. Further, a CRC determination unit 54 that determines the position of the correct CRC code by comparing the CRC code added to the decoded data output from the path memory 52 with the CRC code calculated by the CRC calculation unit 53 is provided. The decoded data at the correct data rate determined by the CRC determination unit 54 is output to a subsequent circuit. The CRC calculation unit 53 and the CRC determination unit 54 are circuits corresponding to the CRC decoder described in the conventional example.
[0066]
The output of the demodulated data from the path memory 52 and the calculation processing in the CRC calculation unit 53 are executed under the control of the control unit 55. The control unit 55 may be configured as a control unit that controls only the path memory 52 and the CRC calculation unit 53, or may be configured to perform control of a reception system around these circuits. A general-purpose memory 56 is connected to the control unit 55, and data that needs to be temporarily stored can be stored in the general-purpose memory 56 during control by the control unit 55.
[0067]
FIG. 2 is a flowchart illustrating an example of the CRC calculation process in the CRC calculation unit 53 and its peripheral circuits, which is executed under the control of the control unit 55 in the receiving apparatus of the present example thus configured. The following description is based on the flowchart of FIG. 2. Here, the number of bits output from the path memory 52 of the Viterbi decoding unit 51 is x, the end bit position number assigned to each position of the end bit is y, and the final bit position number is y. Let the end bit position number be n and the number of bits in the path memory be L. First, the number of bits x is set to 0, the end bit position number y is set to 0 (step S31), and 1 is added to the end bit position number y (step S32). Further, 1 is added to the bit number x (step S33).
[0068]
Then, the x-th data of the Viterbi decoding result is input to the CRC calculation unit 53 (step S34). Then, it is determined whether or not the bit number x output from the path memory 52 of the Viterbi decoding unit 51 is a value obtained by subtracting the bit number L of the path memory from the bit number of the end bit position number y set at this time. (Step S35). The process returns to step S33 until the corresponding value is reached, and the output of the path memory 52 is input.
[0069]
In the judgment of step S35, the end bit position number y is set to the final end bit position number in the number determined to be a value obtained by subtracting the bit number L of the path memory from the bit number of the end bit position number y set at this time. It is determined whether or not the number n has been reached (step S36). If the final end bit position number n is not reached, the data input so far to the CRC calculation unit 53 is temporarily saved in the general-purpose memory 56 connected to the control unit 55 (step S37). However, the data is also left as it is in the CRC calculation unit 53.
[0070]
Immediately after the saving, the CRC calculation process at the end bit position of the data rate at that time is completed using the data remaining in the CRC calculation unit 53, and the result is sent to the CRC determination unit 54. (Step S38).
[0071]
Then, when the calculation process by the CRC calculation unit 53 in step S38 is completed, the process of returning the data saved in the general-purpose memory 56 in the immediately preceding step S37 to the CRC calculation unit 53 is performed under the control of the control unit 55 (step S37). S39). After the process of returning the save data in step S39 is performed, the process returns to step S32, and after adding one end bit position number y, the process of inputting the subsequent decoded data from the path memory is continued. Do.
[0072]
When the end bit position number y becomes the final end bit position number n in step S36 as described above, the CRC calculation unit 53 executes the CRC calculation process using the data input so far. The calculation is completed, the result is sent to the CRC determination unit 54, and the CRC calculation process is ended (step S40).
[0073]
By completing the processing up to this point, the CRC calculation results at all end bit positions are supplied to the CRC determination unit 54, and the received and decoded data can be compared with the CRC code. A correct end bit position (that is, a correct data rate) can be determined, and data of a correct rate can be output.
[0074]
Here, the CRC calculation process shown in the flowchart of FIG. 2 will be described in time series with reference to FIG. FIG. 3A shows the number of bits input from the path memory 52 to the CRC calculation unit 53, and FIG. 3B shows the position where the CRC calculation is performed based on the data input to the CRC calculation unit 53. It is shown.
[0075]
As shown in FIG. 3A, the decoded data is input to the CRC calculation unit 53 one bit at a time in order from 0 bit, and the number k of bits obtained by subtracting the number of bits of the path memory from the number of bits of the first end bit position is obtained. At this time, the data from 0 bits to k bits input to the CRC calculation unit 53 is saved in the general-purpose memory 56, and the data remaining in the CRC calculation unit 53 is used, as shown in FIG. As shown in (5), the CRC calculation process is completed, and the calculation result is supplied to the CRC determination unit 54. This CRC calculation process is quickly executed before the next decoded data is supplied from the path memory 52 to the CRC calculation unit 53.
[0076]
When the calculation by the CRC calculation unit 53 is completed, the data saved in the general-purpose memory 56 is restored to the CRC calculation unit 53 as shown in FIG. The input processing of the subsequent data from the path memory 52 one bit at a time is continued. In this way, when the bit number of the next end bit position is subtracted by the bit number of the path memory from the bit number of the next end bit position, the data from 0 bit to 1 bit input to the CRC calculation unit 53 is transferred to the general-purpose memory 56. Then, using the data remaining in the CRC calculation unit 53, the CRC calculation process is completed as shown in FIG. 3B, and the calculation result is supplied to the CRC determination unit 54. This CRC calculation process is also quickly executed before the next decoded data is supplied from the path memory 52 to the CRC calculation unit 53.
[0077]
When the calculation by the CRC calculation unit 53 is completed, the data saved in the general-purpose memory 56 is restored to the CRC calculation unit 53, and then the 1-bit data of the subsequent data from the path memory 52 is processed. Input processing is continued.
[0078]
Thereafter, this process is repeated, and when the number of bits obtained by subtracting the number of bits of the path memory from the number of bits m of the last end bit position becomes the number of bits, the data input to the CRC calculation unit 53 is used, and FIG. As shown in b), the CRC calculation process is completed, and the calculation result is supplied to the CRC determination unit 54.
[0079]
In this way, the CRC determination section 54 is supplied with the results of the CRC calculation at all end bit positions, and can determine the correct end bit position according to the data rate at that time. In the data output process from the path memory 52 to the CRC calculation unit 53, it is only necessary to output the decoded data once in a predetermined order for each unit of data, as shown in FIG. 10 as a conventional example. Thus, it is not necessary to repeatedly send data to the CRC calculation unit 53 by the number of data rates. Therefore, the number of accesses to the path memory 52 and the CRC calculation unit 53 can be reduced accordingly, and the power consumption for detecting the data rate can be reduced. Also, by reducing the number of accesses to the path memory 52 and the CRC calculation unit 53 under the control of the control unit 55, it is possible to reduce the probability that the access control by the control unit 55 will interfere with other access controls, and to achieve good data reception. Processing will be possible.
[0080]
By performing the processing of this example, it is necessary to save and restore data to and from the memory before and after the CRC calculation in the CRC calculation unit. Can be collectively saved and restored, and the number of times of access itself under the control of the control unit is significantly reduced as compared with the conventional process shown in FIG.
[0081]
If a general-purpose memory originally provided in the control unit 55 is used as a memory for saving data as in this example, a dedicated memory for saving is not required, and the configuration can be simplified accordingly. Needless to say, a configuration in which a dedicated memory for saving data may be provided.
[0082]
The series of processes described so far can be realized by hardware, but can also be realized by software. When a series of processes is realized by software, a program constituting the software is installed in a data processing device such as a computer device, and the program is executed by the computer device or the like, thereby achieving the processing shown in FIG. 1 described above. The receiving device is functionally realized.
[0083]
FIG. 4 is a block diagram illustrating a configuration example of the computer 101 functioning as the above-described receiving device. An input / output interface 116 is connected to a CPU (Central Processing Unit) 111 via a bus 115. The CPU 111 receives a command from a user via an input / output unit 118 such as a keyboard and a mouse via the input / output interface 116. When input, the information is stored in a recording medium such as a ROM (Read Only Memory) 112, a hard disk 114, or a magnetic disk 131, an optical disk 132, a magneto-optical disk 133, or a semiconductor memory 134 mounted on the drive 120. The program is loaded into a RAM (Random Access Memory) 113 and executed. Thus, the various processes described above (for example, the process shown by the flowchart in FIG. 2) are performed. Further, the CPU 111 outputs the processing result to a display unit 117 such as an LCD (Liquid Crystal Display) via the input / output interface 116 as necessary. The program is stored in the hard disk 114 or the ROM 112 in advance and provided to the user integrally with the computer 101, or provided as package media such as the magnetic disk 131, the optical disk 132, the magneto-optical disk 133, and the semiconductor memory 134. Or can be provided to the hard disk 114 via a communication unit 119 from a satellite, a network, or the like.
[0084]
In this specification, the steps of describing a program provided by a recording medium may be performed in chronological order according to the described order, or may be performed in parallel or not necessarily in chronological order. This also includes processes executed individually.
[0085]
【The invention's effect】
According to the present invention, every time the error calculation processing means performs a calculation at each terminal bit position, the data temporarily saved in the temporary storage means is returned after the error calculation, and the Viterbi decoding processing and the error The error calculation is performed at the end bit positions at all rates only by performing the calculation process once for one unit of data continuously. Therefore, the processing speed of data rate detection can be remarkably improved as compared with the case where data is input to the repetitive error calculation processing means as in the related art. Further, since the number of accesses to the storage unit can be reduced, the power consumption required for the access can be reduced. Furthermore, when the storage area of the storage unit is shared with another application, the number of accesses is reduced, so that the probability that other accesses will be hindered can be reduced, and good data reception processing can be performed. .
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating an example of a CRC calculation process according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram showing an example of a CRC calculation processing state according to an embodiment of the present invention.
FIG. 4 is a block diagram illustrating an example of a computer device.
FIG. 5 is a block diagram showing a conventional configuration example.
FIG. 6 is an explanatory diagram showing an example of types of data rates.
FIG. 7 is a block diagram illustrating a configuration example of a conventional Viterbi decoding unit.
FIG. 8 is a block diagram illustrating a configuration example of a conventional CRC decoder.
FIG. 9 is a flowchart showing an example of a conventional data rate detection process.
FIG. 10 is an explanatory diagram showing an example of a conventional CRC calculation processing state.
FIG. 11 is a flowchart showing an example of a conventional CRC calculation process.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Transmission apparatus, 2 ... Communication channel, 3, 4 ... Receiving apparatus, 11 ... CRC encoder, 12 ... Convolution coding part, 13 ... Modulation part, 31 ... Demodulation part, 32 ... Viterbi decoding part, 33 ... CRC decoder , 34: data rate detecting unit, 51: Viterbi decoding unit, 52: path memory, 53: CRC calculating unit, 54: CRC determining unit, 55: control unit, 56: general-purpose memory, 111: central control unit, 112: ROM 113, RAM, 114, hard disk drive, 115, bus line, 116, input / output interface, 117, display unit, 118, input unit, 119, communication unit, 120, drive, 131, magnetic disk, 132, optical disk, 133 ... Magneto-optical disk, 134 ... Semiconductor memory

Claims (5)

The data rate of data transmitted at a predetermined data rate selected from a plurality of data rates prepared in advance is detected by an error determination based on an error detection code, and the data is detected at the detected data rate. In a signal processing device that decodes
Decoding means for executing a decoding process of the received data;
The data decoded by the decoding means are sequentially input, and the error detection code added to the data is used to perform error detection calculation processing from the first bit to the end bit position of each data rate for each predetermined unit. Error calculation processing means to perform;
Storage means for temporarily storing data input to the error calculation processing means,
When the data at the respective end bit positions of the plurality of data rates prepared are input to the error calculation processing means, the data is transferred to the storage means and temporarily stored, and the calculation processing means terminates each data rate. Control means for transferring the temporarily stored data to the error calculation processing means, after the data at the bit position is input and the error detection calculation processing is performed,
A signal processing device comprising: a determination unit configured to determine a data rate of received data based on a calculation result at each end bit position by the error calculation processing unit. The signal processing device according to claim 1,
The signal processing device uses a general-purpose storage unit built in or connected to the control unit. The signal processing device according to claim 1,
The signal processing device performs the determination by the determination unit when the error calculation processing at the end bit positions of all the prepared data rates is completed. The data rate of data transmitted at a predetermined data rate selected from a plurality of data rates prepared in advance is detected by an error determination based on an error detection code, and the data is detected at the detected data rate. In a signal processing method for decoding
A decryption step of performing a decryption process on the received data;
The data decoded in the decoding step are sequentially input, and the error detection code added to the data is used to perform error detection calculation processing from the first bit to the end bit position of each data rate for each predetermined unit. Error calculation processing steps to be performed;
In the error calculation processing step, when data at each end bit position of a plurality of data rates prepared is input, the data is temporarily stored, and at the calculation processing step, the data at the end bit position at each data rate is input. A control step of restoring the temporarily stored data after performing the error detection calculation process,
A determination step of determining a data rate of received data based on a calculation result at each end bit position in the error calculation processing step. The signal processing method according to claim 4,
A signal processing method in which the determination in the determination step is performed at the stage when the error calculation processing at the end bit positions of all prepared data rates is completed.

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