JP2004222115A - Clock data recovery circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock data recovery circuit which is easy to analyze a logical system, and regenerates a clock signal which is small in jitters and is stable. <P>SOLUTION: This clock data recovery circuit is provided with a phase comparator which outputs a control signal being a detection result of the phase difference between input data and a clock signal, a charge pump circuit which outputs an error signal corresponding to the phase difference on the basis of the control signal, a loop filter for outputting a controlling voltage level corresponding to the error signal, and a voltage controlled oscillator which changes the oscillation frequency of the clock signal according to the controlling voltage level. Here, the phase comparator comprises: an edge detection circuit for detecting timing where data changes; and a phase frequency comparison circuit which outputs a control signal based on the output of the edge detection circuit and the clock signal. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock data recovery circuit (hereinafter, referred to as a CDR circuit) for recovering a clock signal synchronized with input data from input data.
[0002]
[Prior art]
FIG. 6 is a schematic configuration diagram of an example of the CDR circuit. As shown in FIG. 1, the CDR circuit 10 includes a phase comparator 12, a charge pump circuit 14, a loop filter 16, and a voltage controlled oscillator 18.
[0003]
In the CDR circuit 10, the phase comparator 12 detects a phase difference between the data Data and the clock signal Clock, and outputs control signals up and down as a result of the detection. Subsequently, an error signal corresponding to the phase difference is generated by the charge pump circuit 14 based on the control signals up and down, and a control voltage level Vcont corresponding to the error signal is generated by the loop filter 16 to control the voltage. The oscillator 18 changes the oscillation frequency of the clock signal Clock according to the control voltage level Vcont.
[0004]
For example, when the phase of the clock signal Clock is later than that of the data Data, the control voltage level Vcont is increased in order to advance the phase of the clock signal Clock. Conversely, when the phase of the clock signal Clock is earlier, the control voltage level Vcont is low. Be killed. Thereafter, similarly, the phase difference between the data Data and the clock signal Clock whose oscillation frequency has been changed is repeatedly detected, and the frequency and phase between the data Data and the clock signal Clock are synchronized.
[0005]
By the way, as a CDR circuit, two types of a binary CDR circuit using an Alexander type phase comparator and a linear CDR circuit using a Hogge type phase comparator are widely used. Hereinafter, these two types of CDR circuits will be described.
[0006]
First, FIG. 7 is a schematic configuration diagram of an Alexander type phase comparator. As shown in the figure, the Alexander type phase comparator 12a includes four flip-flops 52, 54, 56, 58, two EOR gates 60, 62, an inverter 64, and two AND gates 66, 68. It has.
[0007]
Here, the signal P (the output of the EOR gate 62) indicates the detection result of the presence / absence of the transition of the data Data. When the signal P is at the high level, there is a transition of the data Data. State. The signal Q (output of the EOR gate 60) indicates the phase relationship between the clock signal Clock and the data Data. When the signal Q is at a high level, the phase of the clock signal Clock is ahead of the phase of the data Data. This is a state where the phase of the clock signal Clock lags behind the phase of the data Data.
[0008]
In the Alexander type phase comparator 12a, when the phase of the clock signal Clock is ahead of the phase of the data Data, as shown in FIG. 8, in synchronization with the rise of the clock signal Clock after the transition of the data Data, During one clock, a high level is output to the control signal down. Further, when the data Data continuously transitions every clock, the control signal down also continuously goes high according to the transition state of the data Data. As a result, the control voltage level Vcont is gradually reduced according to the high level time of the control signal down, and the phase of the clock signal Clock is controlled to be delayed. In the timing chart shown in FIG. 8, the same symbols as those of the internal nodes A, B, C, P, and Q shown in FIG. 7 are assigned. The same applies to the timing charts of FIGS. 9 and 10 described later.
[0009]
On the other hand, when the phase of the clock signal Clock lags behind the phase of the data Data, as shown in FIG. 9, the control signal up goes high in synchronization with the rising edge of the clock signal Clock after the data Data changes. The level is output. Further, when the data Data continuously transitions every clock, the control signal up also continuously goes high according to the transition state of the data Data. As a result, the control voltage level Vcont gradually increases in accordance with the high-level time of the control signal up, and is controlled so that the phase of the clock signal Clock is advanced.
[0010]
When the phase of the clock signal Clock matches the phase of the data Data, as shown in FIG. 10, the transition timing of the data Data matches the falling timing of the clock signal Clock. Therefore, the data Data taken into the flip-flop 56 is undefined and its data output Q is undefined, and both the control signal P and the control signals up and down are undefined, so that the control voltage level Vcont fluctuates in a minute voltage range. Will be.
[0011]
FIG. 11 is a schematic diagram of a Hogge type phase comparator.
As shown in the figure, the Hogge type phase comparator 12b includes two flip-flops 70 and 72, two EOR gates 74 and 76, and a delay circuit 78.
[0012]
In the Hogge type phase comparator 12b, when the data Data changes, the control signal up becomes high level from the change of the data Data to the rise of the next clock signal Clock, and after the clock signal Clock rises, Until the fall, the control signal down is at the high level.
[0013]
When the phase of the clock signal Clock is ahead of the phase of the data Data, as shown in FIG. 12, the high-level pulse width of the control signal down is longer than that of the control signal up. As a result, the control voltage level Vcont increases slightly according to the high level of the control signal up, and largely decreases according to the high level time of the control signal down, so that the phase of the clock signal Clock is controlled to be delayed. Is done. The same reference numerals as those of the internal nodes A and B shown in FIG. 11 are given to the timing chart shown in FIG. The same applies to the timing charts of FIGS. 13 and 14 described later.
[0014]
On the other hand, when the phase of the clock signal Clock lags behind the phase of the data Data, as shown in FIG. 13, the control signal up has a higher-level pulse width than the control signal down. As a result, the control voltage level Vcont increases greatly according to the high level of the control signal up, and decreases slightly according to the high level time of the control signal down, so that the phase of the clock signal Clock is controlled to be advanced. Is done.
[0015]
When the phase of the clock signal Clock matches the phase of the data Data, as shown in FIG. 14, the control signal up and the control signal down having substantially the same high-level pulse width are output alternately. As a result, the control voltage level Vcont repeatedly increases according to the high level of the control signal up and decreases according to the high level time of the control signal down, so that the phase of the clock signal Clock and the phase of the data Data are repeated. Are the same, the phase of the clock signal Clock fluctuates.
[0016]
Further, since the binary CDR circuit using the Alexander type phase comparator 12a is a non-linear system, it is difficult to perform a system analysis based on linear PLL logic when designing. Here, the linear PLL logic is a logic for performing a system analysis of the PLL assuming a linear transfer function for each element block. Therefore, it is necessary to perform the operation of determining the system parameters such as the loop bandwidth and the loop filter constant on a simulation basis, which requires a large number of design steps.
[0017]
On the other hand, since the linear CDR circuit using the Hogge type phase comparator 12b is a linear system, system analysis based on linear PLL logic is possible. However, similarly to the binary CDR circuit using the Alexander type phase comparator 12a and the linear CDR circuit using the Hogge type phase comparator 12b, as shown in FIG. Since the use voltage level Vcont fluctuates, there is a problem that it causes the generation of jitter of the clock signal Clock.
[0018]
Here, the nonlinear system, the linear system, and the linear PLL logic will be described. When a system exists, its temporal and spatial evolution (change) can usually be expressed by differential equations. For example, for a differential equation describing a change over time, when an initial condition (a value at t = 0) is given and one solution is obtained, a case where the principle of superposition is established between solutions of different initial conditions is obtained. Call it a linear system.
[0019]
For example, in a linear system, as an initial condition, a solution 1 when t = 0 and an initial value A (1), a solution 2 when A (2), and A (3) = A (1) + A (2). When the solution 3 is obtained in this case, the solution 3 = the solution 1 + the solution 2, and such a relationship is called a superposition principle. When the relationship between the input and output for a certain system is proportional, the system is called a linear system.
[0020]
On the other hand, a nonlinear system is a system in which the principle of superposition of solutions does not hold, or a system in which the relationship between input and output is not proportional. When analyzing a non-linear system, it is necessary to solve a non-linear equation, but a numerical analysis by a computer is required except for special cases. Therefore, as described above, in the case of a nonlinear system, system analysis is very difficult.
[0021]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a clock / data recovery circuit which solves the problems based on the prior art, can easily analyze a logical system, and can reproduce a stable clock signal with little jitter. Is to do.
[0022]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a phase comparator which outputs a control signal which is a detection result of a phase difference between input data and a clock signal, and the phase difference based on the control signal. A charge pump circuit that outputs an error signal corresponding to the error signal, a loop filter that outputs a control voltage level corresponding to the error signal, and a voltage control oscillator that changes an oscillation frequency of the clock signal according to the control voltage level With
A clock / data recovery circuit for recovering the clock signal synchronized with the data from the data,
The phase comparator includes an edge detection circuit that detects a timing at which the data changes, and a phase frequency comparison circuit that outputs the control signal based on an output of the edge detection circuit and the clock signal. And a clock / data recovery circuit that performs the operation.
[0023]
Here, a data transition detection circuit for detecting a state without data transition is further provided, and the charge pump circuit operates during a state without data transition based on an output of the data transition detection circuit. Preferably, it is stopped.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a clock data recovery circuit of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0025]
The configuration of the CDR circuit of the present invention is basically the same as the configuration of the conventional CDR circuit 10 shown in FIG. That is, the CDR circuit of the present invention includes the phase comparator 12, the charge pump circuit 14, the loop filter 16, and the voltage controlled oscillator 18. A feature of the CDR circuit of the present invention resides in that a phase comparator having a configuration different from that of a conventional CDR circuit is provided. Hereinafter, the phase comparator used in the CDR circuit of the present invention will be described.
[0026]
FIG. 1 is a schematic configuration diagram of one embodiment of a phase comparator used in a CDR circuit of the present invention. The phase comparator 12c shown in the figure includes an edge detection circuit 20 for detecting the timing at which the data Data changes, and a signal between the data Data and the clock signal Clock based on the output of the edge detection circuit 20 and the clock signal Clock. A phase frequency comparison circuit 22 that outputs control signals up and down as detection results of the phase difference.
[0027]
The edge detection circuit 20 includes a delay circuit 24 and an EOR gate 26. Data Data is directly input to one input of the EOR gate 26, and Data Data is input to the other input via the delay circuit 24. The edge detection circuit 20 outputs a high-level pulse for a predetermined time corresponding to the delay time of the delay circuit 24 after the data Data changes from the high level to the low level and from the low level to the high level.
[0028]
The phase frequency comparison circuit 22 includes two flip-flops 28 and 30 and an AND gate 32. The data inputs D of the flip-flops 28 and 30 are both connected to a power supply, and the clock input receives the output of the EOR gate 26 and the clock signal Clock, respectively. The data output Q of the flip-flops 28 and 30 outputs a signal up and a signal down, respectively. These signals up and down are input to the AND gate 32, and the output of the AND gate 32 is commonly input to the reset inputs rest of the flip-flops 28 and 30.
[0029]
In the phase frequency comparison circuit 22, the data output Q of the flip-flop 28, that is, the signal up goes high at the rising edge of the output A of the edge detection circuit 20, and the data output Q of the flip-flop 30, ie, the signal down, at the rising edge of the clock signal Clock. Becomes high level. When the outputs Q of the flip-flops 28 and 30 both go high, the output of the AND gate 32 goes high, the flip-flops 28 and 30 are reset, and their outputs Q both go low.
[0030]
Next, the operation of the CDR circuit using the phase comparator 12c shown in FIG. 1 will be described with reference to the timing chart of FIG. Here, FIG. 2A shows a case where the phase of the clock signal Clock leads the phase of the data Data, and FIG. 2B shows a case where the phase of the clock signal Clock lags behind the phase of the data Data. 2C shows the operation of the CDR circuit when the phase of the clock signal Clock and the phase of the data Data match.
[0031]
First, when the phase of the clock signal Clock is ahead of the phase of the data Data, as shown in the timing chart of FIG. 2A, first, the output Q of the flip-flop 30 at the rising of the clock signal Clock, that is, the control signal Down becomes high level, and thereafter, a change in data Data is detected by the edge detection circuit 20. When the output A rises, the output Q of the flip-flop 28, that is, the control signal up becomes high level.
[0032]
As a result, the output of the AND gate 32 becomes high level, and the outputs Q of the flip-flops 28 and 30, ie, the control signals up and down, are both reset to low level. Accordingly, the output of the loop filter 16, that is, the control voltage level Vcont gradually decreases in accordance with the time when the control signal down becomes the high level, and the output of the voltage control oscillator 18, that is, the phase of the clock signal Clock is changed. It is controlled to be slow.
[0033]
On the other hand, when the phase of the clock signal Clock lags behind the phase of the data Data, a change in the data Data is detected by the edge detection circuit 20 as shown in the timing chart of FIG. Rises, the output Q of the flip-flop 28, that is, the control signal up goes high, and then the output Q of the flip-flop 30, that is, the control signal down, goes high at the rise of the clock signal Clock.
[0034]
As a result, the output of the AND gate 32 becomes high level, and the outputs Q of the flip-flops 28 and 30, ie, the control signals up and down, are both reset to low level. Therefore, the output of the loop filter 16, that is, the control voltage level Vcont gradually increases in accordance with the time when the control signal up becomes the high level, and the output of the voltage control oscillator 18, that is, the phase of the clock signal Clock is changed. It is controlled to be faster.
[0035]
When the phase of the clock signal Clock matches the phase of the data Data, a change in the data Data is detected by the edge detection circuit 20 and the output A thereof rises as shown in the timing chart of FIG. At the same time as the output Q of the flip-flop 28, that is, the control signal up goes high, the output Q of the flip-flop 30, that is, the control signal down, goes high at the rise of the clock signal Clock.
[0036]
As a result, the output of the AND gate 32 becomes high level, and the outputs Q of the flip-flops 28 and 30, ie, the control signals up and down, are both reset to low level. Therefore, the output of the loop filter 16, that is, the control voltage level Vcont does not change, and the output of the voltage controlled oscillator 18, that is, the phase of the clock signal Clock is controlled so as to maintain the current state.
[0037]
Since the phase comparator 12 shown in FIG. 1 is a linear system, there is an advantage that system analysis is easy and the number of design steps can be reduced. In the CDR circuit using the phase comparator 12c shown in FIG. 1, when the phase difference between the data Data and the clock signal Clock disappears, the control voltage level Vcont of the voltage-controlled oscillator 18 does not fluctuate. Therefore, a stable system in which no jitter occurs in the clock signal Clock can be realized.
[0038]
Further, as shown in FIG. 3, in the CDR circuit using the phase comparator 12c shown in FIG. 1, a data transition detection circuit 34 for detecting a state where there is no transition of data Data can be used in combination. As a result, even when the non-transition state of the data Data continues, the operation of the charge pump circuit 14 is stopped, whereby the fluctuation of the control voltage level Vcont of the voltage controlled oscillator 18 can be suppressed, and higher performance can be achieved. It is possible to plan.
[0039]
Hereinafter, the data transition detection circuit 34 will be described.
FIGS. 4A and 4B are a schematic configuration diagram and an operation timing chart of an embodiment of a data transition detection circuit used in the CDR circuit shown in FIG. 3, respectively, and FIGS. 5A and 5B. 4 is a schematic configuration diagram of one embodiment of a charge pump circuit used in the CDR circuit shown in FIG. 3 and a charge pump circuit used in a conventional CDR circuit, respectively.
[0040]
The data transition detection circuit 34a illustrated in FIG. 4A includes two flip-flops 36 and 38 and an ENOR gate 40. Data Data is input to the data input D of the flip-flop 36, and its data output Q is input to the data input D of the flip-flop 38. The clock signal Clock is commonly input to the clock inputs of the flip-flops 36 and 38. The data output Q of the flip-flops 36 and 38 is input to the ENOR gate 40, and the signal NT is output from the ENOR gate 40.
[0041]
In the data transition detection circuit 34a, as shown in the timing chart of FIG. 4B, during one clock from the rise of the clock signal Clock after the transition of the data Data to the rise of the next clock signal Clock, A low level is output to NT. Further, when the data Data continuously transitions every clock, the signal NT also continuously goes low according to the transition state of the data Data. In the timing chart shown in FIG. 4B, the same reference numerals as those of the internal nodes A and C shown in FIG.
[0042]
The charge pump circuit 14a shown in FIG. 5A includes a P-type MOS transistor (hereinafter, referred to as PMOS) 42, an N-type MOS transistor (hereinafter, referred to as NMOS) 44, a NAND gate 46, and an AND gate 48. , An inverter 50. The control signal up is input to one input of the NAND gate 46, and the control signal down is input to one input of the AND gate 48. The signal NT is commonly input to the other inputs of the NAND gate 46 and the AND gate 48 via the inverter 50, and the outputs of the NAND gate 46 and the AND gate 48 are input to the gates of the PMOS 42 and the NMOS 44, respectively. The PMOS 42 and the NMOS 44 are connected in series between the power supply and the ground, and a control voltage level Vcont is output from a connection point between the two.
[0043]
In the charge pump circuit 14a shown in FIG. 5A, the inverted signal of the control signal up is output from the NAND gate 46 and the control signal down is output from the AND gate 48 while the signal NT is at the low level. That is, it operates in the same manner as the charge pump circuit 14b used in the conventional CDR circuit shown in FIG. 4B, and during the period when the control signal up is at the high level, the PMOS 42 is turned on and the control voltage level Vcont is charged up. While the control signal down is at the high level, the NMOS 44 is turned on and the control voltage level Vcont is discharged.
[0044]
On the other hand, when the signal NT goes high, the output of the NAND gate 46 goes high, the output of the AND gate 48 goes low, and both the PMOS 42 and the NMOS 44 are turned off and their operation is stopped. As a result, it is possible to suppress a change in the control voltage level Vcont during a period when the data Data is not transitioning, and it is possible to suppress the occurrence of the jitter of the clock signal Clock.
[0045]
The specific circuit configurations of the phase comparator 12, the charge pump circuit 14, and the data transition detection circuit 34 have been described. However, the present invention is not limited to the specific example illustrated, and performs the same functions. Another circuit configuration may be used. Further, the charge pump circuit 14, the loop filter 16, and the voltage controlled oscillator 18 may have any of conventionally known configurations, and the CDR circuit of the present invention includes other components other than these. You may.
[0046]
The present invention is basically as described above.
As described above, the clock data recovery circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.
[0047]
【The invention's effect】
As described in detail above, the clock data recovery circuit of the present invention includes an edge detection circuit for detecting a timing at which data changes, a phase frequency for outputting a control signal based on an output of the edge detection circuit and a clock signal. And a phase comparator including a comparison circuit.
Thus, according to the clock / data recovery circuit of the present invention, since the phase comparator of the linear system is used, there is an advantage that the system analysis is easy and the number of design steps can be reduced. Further, when the phase difference between the data and the clock signal disappears, the control voltage level of the voltage controlled oscillator does not fluctuate. Therefore, it is possible to realize a stable system in which no jitter occurs in the clock signal in the recovery state. .
[Brief description of the drawings]
FIG. 1 is a schematic diagram of an embodiment of a phase comparator used in a clock data recovery circuit of the present invention.
FIGS. 2A, 2B, and 2C are timing charts of one embodiment showing an operation of a clock data recovery circuit using the phase comparator shown in FIG. 1;
FIG. 3 is a schematic configuration diagram of another embodiment of the clock / data recovery circuit of the present invention.
4A is a schematic configuration diagram of an embodiment of a data transition detection circuit used in the clock / data recovery circuit shown in FIG. 3, and FIG. 4B is a timing chart of the embodiment showing the operation thereof; It is.
5 (a) is a schematic configuration diagram of an embodiment of a charge pump used in the clock data recovery circuit shown in FIG. 3, and FIG. 5 (b) is a charge pump used in a conventional clock data recovery circuit. FIG. 3 is a schematic diagram illustrating an example of a configuration of a pump.
FIG. 6 is a schematic configuration diagram of an example of a clock data recovery circuit.
FIG. 7 is a schematic configuration diagram of an Alexander type phase comparator.
8 is an example timing chart illustrating an operation of the clock data recovery circuit using the phase comparator illustrated in FIG. 7;
9 is a timing chart showing another example of the operation of the clock data recovery circuit using the phase comparator shown in FIG. 7;
10 is a timing chart showing another example of the operation of the clock data recovery circuit using the phase comparator shown in FIG.
FIG. 11 is a schematic diagram of a configuration of a Hogge type phase comparator.
12 is an example timing chart illustrating an operation of the clock data recovery circuit using the phase comparator illustrated in FIG. 11;
FIG. 13 is a timing chart of another example showing the operation of the clock data recovery circuit using the phase comparator shown in FIG.
FIG. 14 is a timing chart of another example showing the operation of the clock data recovery circuit using the phase comparator shown in FIG.
FIG. 15 is a timing chart showing an example of an operation in a recovery state of the clock data recovery circuit using the phase comparator shown in FIGS. 7 and 11;
[Explanation of symbols]
10 Clock data recovery circuit
12 Phase comparator
14. Charge pump circuit
16 Loop filter
18 Voltage controlled oscillator
20 Edge detection circuit
22 Phase frequency comparison circuit
24 Delay circuit
26,60,62,74,76 EOR gate
28, 30, 36, 38, 52, 54, 56, 58, 70, 72 flip-flops
32, 48, 66, 68 AND gate
34 Data transition detection circuit
40 ENOR gate
42 P-type MOS transistor
44 N-type MOS transistor
46 NAND gate
50,64 inverter
78 delay circuit

Claims (2)

A phase comparator that outputs a control signal that is a detection result of a phase difference between input data and a clock signal, and a charge pump circuit that outputs an error signal corresponding to the phase difference based on the control signal. A loop filter that outputs a control voltage level according to the error signal, and a voltage control oscillator that changes an oscillation frequency of the clock signal according to the control voltage level,
A clock / data recovery circuit for recovering the clock signal synchronized with the data from the data,
The phase comparator includes an edge detection circuit that detects a timing at which the data changes, and a phase frequency comparison circuit that outputs the control signal based on an output of the edge detection circuit and the clock signal. Clock data recovery circuit. The charge pump circuit further includes a data transition detection circuit that detects a state without data transition, and the charge pump circuit stops operation during a state without data transition based on an output of the data transition detection circuit. The clock data recovery circuit according to claim 1.

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