JP2004221996A - Integrated circuit device provided with reconfigurable circuit, and processing device with circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a plurality of circuits which do not operate simultaneously by a processing device provided with a reconfigurable circuit. <P>SOLUTION: This processing device 10 resets the circuit configuration of the reconfigurable circuit 12 as necessary. A storage unit 24 stores a plurality of patterns of setting data 32 for configuring the circuit 12 as an initial circuit, and a setting unit 14 sets a circuit configuration of the circuit 12 on the basis of the selected setting data 32. Circuits which do not operate simultaneously are reduced in circuit scale and power consumption by preventing reconfiguration on the circuit 12. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit technology, and particularly to an integrated circuit device and a processing device provided with a reconfigurable circuit.
[0002]
[Prior art]
An FPGA (Field Programmable Gate Array) is capable of writing circuit data after LSI manufacture and designing a circuit configuration relatively freely, and is used for designing dedicated hardware. The FPGA includes a look-up table (LUT) for storing a truth table of a logic circuit, a basic cell including an output flip-flop, and a programmable wiring resource connecting the basic cells. In the FPGA, a target logical operation can be realized by writing data to be stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area becomes very large and the cost increases, as compared with the design using an ASIC (Application Specific IC). Therefore, a method of reusing the circuit configuration by dynamically reconfiguring the FPGA has been proposed (for example, see Patent Document 1).
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H10-256383 (Full text, Fig. 1-4)
[0004]
[Problems to be solved by the invention]
In satellite broadcasting, the image quality may be adjusted by switching the broadcast mode depending on the season or the like. In the receiver, a plurality of circuits are previously built in hardware for each broadcast mode, and the circuits are switched by a selector according to the broadcast mode to receive. Therefore, the circuits for the other broadcast modes of the receiver are idle during that time. When a plurality of dedicated circuits are switched and used, as in mode switching, and the switching interval is relatively long, an LSI can be instantly reconfigured at the time of switching instead of creating a plurality of dedicated circuits. The structure can be simplified to increase versatility, and at the same time, the mounting cost can be reduced. In order to meet such needs, dynamically reconfigurable LSIs have attracted interest in the manufacturing industry. In particular, an LSI mounted on a mobile terminal such as a mobile phone or a PDA (Personal Data Assistant) needs to be miniaturized. If the LSI can be dynamically reconfigured and the function can be appropriately switched according to the application, the LSI is required. Mounting area can be reduced.
[0005]
FPGAs have a high degree of freedom in circuit configuration design and are versatile, but need to include a large number of switches and a control circuit for controlling ON / OFF of the switches in order to enable connection between all basic cells. Inevitably, the mounting area of the control circuit is inevitably increased. In addition, a complicated wiring pattern is used for connection between the basic cells, so that the wiring tends to be long. In addition, since a large number of switches are connected to one wiring, a delay increases. For this reason, LSIs using FPGAs are often used only for trial production and experiments, and are not suitable for mass production in view of mounting efficiency, performance, cost, and the like.
[0006]
Further, in the FPGA, since it is necessary to send setting data to a large number of LUT-type basic cells, it takes a considerable time to configure the circuit. Therefore, the FPGA is not suitable for applications that require instantaneous switching of the circuit configuration. Therefore, even if an attempt is made to configure a receiving circuit for satellite broadcasting using an FPGA, the circuit configuration cannot be switched instantaneously, so that the circuit reconfiguration function of the FPGA cannot be used. Must be built on hardware. As described above, when one of a plurality of circuits is selected and used, having all the circuits on hardware even in a situation where the selected circuit is not frequently changed is a circuit scale. This leads to an increase and unnecessary circuits operate, so that power consumption also increases.
[0007]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an integrated circuit device and a processing device including a reconfigurable circuit that contributes to a reduction in circuit scale.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, an embodiment of the present invention provides a reconfigurable circuit having a logic circuit whose function can be changed, and a plurality of patterns of setting data for configuring the reconfigurable circuit as an intended circuit. A storage unit for storing, a control unit for receiving a selection signal for specifying a circuit to be selected, and selecting setting data from a plurality of patterns stored in the storage unit, and a control unit based on the selected setting data. A setting unit for setting a circuit configuration of the configurable circuit. According to the processing device of this aspect, a circuit having a necessary function is dynamically reconfigured into a reconfigurable circuit according to a situation, so that the circuit scale can be reduced. Further, since it is not necessary to configure an unnecessary circuit, power consumption can be reduced. The setting data selected by the control unit is not limited to one pattern, and may be a plurality of patterns if necessary.
[0009]
The selection signal received by the control unit may be instructed by the user. Further, the control unit may receive the status information of the broadcast data signal as the selection signal. The broadcast data signal switches the broadcast mode according to the season or the like. At that time, the broadcast data signal includes state information indicating the state of the mode. Conventionally, one of a plurality of circuits built on an LSI has been selected based on this state information. However, in the processing apparatus of this embodiment, a new circuit is selected based on the state information. The circuit will be reconfigured. By appropriately changing the circuits configured on the reconfigurable circuit based on the selection signal, the circuit scale is reduced and the power consumption is further reduced compared to the case where a plurality of circuits are built in advance. Becomes possible.
[0010]
The reconfigurable circuit has a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection portion capable of setting a connection relationship between an output of the preceding logic circuit and an input of the following logic circuit. In addition, the setting unit may set functions and connection relationships of a plurality of logic circuits. The structure of the multi-stage arrangement of the logic circuits has an arrangement in which the rows of the logic circuits arranged in the horizontal direction are combined in a plurality of stages in the vertical direction. May be provided with a connection for connection between the output of the logic circuit row of (1) and the input of the logic circuit row of the next stage.
[0011]
Each logic circuit may be a circuit capable of performing relatively high-performance operations, for example, an arithmetic logic circuit (ALU (Arithmetic Logic Unit)) capable of selectively executing a plurality of types of multi-bit operations. Good. The logic circuit has a selector for selecting a plurality of arithmetic functions, and the selector selects an arithmetic function according to setting data loaded from the outside. By making the operation function of the logic circuit selectable by the selector, the function of the logic circuit can be switched instantaneously, and the function of the reconfigurable circuit can be instantaneously set.
[0012]
Another embodiment of the present invention provides a reconfigurable circuit having a logic circuit whose function can be changed, and a setting data selected from a plurality of patterns of setting data for configuring the reconfigurable circuit as an intended circuit. And a setting unit for setting a circuit configuration of the reconfigurable circuit based on the integrated circuit device.
[0013]
In addition, any combination of the above-described components, and the expression of the present invention expressed as a method, an apparatus, a system, or a computer program are also effective as embodiments of the present invention.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a configuration diagram of a processing apparatus 10 according to the embodiment. The processing device 10 includes an integrated circuit device 16 and an external control device 26. The integrated circuit device 16 has a function of enabling a circuit configuration to be reconfigured. The external control device 26 creates setting data for setting the circuit configuration of the integrated circuit device 16 and supplies the setting data to the integrated circuit device 16. The integrated circuit device 16 is configured as one chip, and includes the reconfigurable circuit 12 and the setting unit 14. The external control device 26 includes a control unit 18, a compiling unit 20, a setting data generating unit 22, and a storage unit 24.
[0015]
The reconfigurable circuit 12 includes a logic circuit whose function can be changed. Specifically, the reconfigurable circuit 12 has a configuration in which a plurality of logic circuits capable of selectively executing a plurality of arithmetic functions are arranged in a plurality of stages, and outputs a preceding logic circuit row and an input of a subsequent logic circuit row. And a connection unit that can set the connection relationship of The function of each logic circuit and the connection relationship between the logic circuits are set based on the setting data 32 supplied by the setting unit 14. The setting data 32 is generated in the following procedure.
[0016]
Various programs 28 to be implemented by the integrated circuit device 16 are stored in the storage unit 24. The program 28 describes a signal processing circuit or a signal processing algorithm which does not operate simultaneously with each other in a high-level language such as C language. The compiling unit 20 compiles the program 28 stored in the storage unit 24, converts the program 28 into a data flow graph 30, and stores the data flow graph 30 in the storage unit 24. The data flow graph 30 expresses the flow of operation of input variables and constants in a graph structure.
[0017]
The setting data generating unit 22 generates setting data 32 from the data flow graph 30 and stores the setting data 32 in the storage unit 24. The setting data 32 is data for mapping the data flow graph 30 to the reconfigurable circuit 12, and determines the functions of the logic circuits in the reconfigurable circuit 12 and the connection relation between the logic circuits. By executing this procedure for each program 28, the storage unit 24 stores a plurality of patterns of setting data 32 for configuring the reconfigurable circuit 12 as a desired circuit.
[0018]
FIG. 2 is a configuration diagram of the reconfigurable circuit 12. The reconfigurable circuit 12 has a plurality of columns of logic circuits 40 arranged in a plurality of stages, and a connection section 42 provided at each stage outputs an output of a preceding logic circuit column and an input of a subsequent logic circuit column. Has a structure that can be arbitrarily connected by setting. Here, an ALU is shown as an example of the logic circuit 40. Each ALU can selectively execute a plurality of types of multi-bit operations such as a logical sum, a logical product, and a bit shift by setting. Each ALU has a selector for selecting a plurality of arithmetic functions.
[0019]
As illustrated, the reconfigurable circuit 12 is configured as an ALU array in which Y ALUs are arranged in the horizontal direction and X ALUs are arranged in the vertical direction. , ALU1Y of the first stage are input with input variables and constants, and set predetermined operations are performed. The output of the operation result is input to the second-stage ALU 21, ALU22,..., ALU2Y according to the connection set in the first-stage connection unit 42. In the first-stage connection unit 42, a connection is configured so that an arbitrary connection relationship can be realized between the output of the first-stage ALU column and the input of the second-stage ALU column. Is effective. Hereinafter, the configuration is the same up to the connection section 42 of the (X-1) th stage, and the ALU column of the Xth stage, which is the final stage, outputs the final result of the operation.
[0020]
FIG. 3 is a diagram showing an example of the data flow graph 30. The setting data generator 22 generates setting data 32 for mapping the data flow graph 30 to the reconfigurable circuit 12. In the data flow graph 30, the flow of the operation of the input variables and constants is represented in a stepwise graph structure. In the figure, operators are indicated by circles. In order to realize the operation flow by the data flow graph 30 on the circuit, the setting data 32 specifies a logic circuit to which the operation function is assigned, determines a connection relationship between the logic circuits, and further defines input variables and input constants. Data. Therefore, the setting data 32 is configured to include selection information supplied to a selector for selecting a function of each logic circuit 40, connection information for setting the connection of the connection unit 42, necessary variable data and constant data, and the like.
[0021]
Returning to FIG. 1, the control unit 18 receives a selection signal for specifying a circuit to be selected, and selects one pattern of the setting data 32 stored in the storage unit 24 based on the selection signal. If necessary, the selected setting data 32 may be two or more patterns. The selection signal may be specified by the user, or may be status information included in a broadcast data signal or the like. Although the state information will be described later, it is information necessary for decoding by the receiver, and corresponds to, for example, setting information such as a mode and a modulation method of a broadcast data signal. The control unit 18 supplies the selected setting data 32 to the setting unit 14.
[0022]
The setting unit 14 sets the selected setting data 32 in the reconfigurable circuit 12, and reconfigures the circuit of the reconfigurable circuit 12. Thereby, the reconfigurable circuit 12 can execute a new desired operation. By configuring the reconfigurable circuit 12 and the setting unit 14 on the same chip, the circuit content of the reconfigurable circuit 12 can be changed at high speed. The setting unit 14 has a cache memory or another type of memory, and may store a plurality of setting data 32 in advance. In this case, the control unit 18 supplies a selection signal to the setting unit 14, and the setting unit 14 can instantly set the desired setting data 32 in the reconfigurable circuit 12 based on the selection signal. In the present embodiment, the control unit 18 is provided in the external control device 26, but the control unit 18 may be provided in the integrated circuit device 16.
[0023]
As described above, according to the processing device 10 of the present embodiment, it is not necessary to have a plurality of circuits that do not operate simultaneously on hardware, and necessary circuits are instantaneously constituted by the reconfigurable circuit 12. be able to. For example, even when the mode is switched at the time of receiving a broadcast, the storage unit 24 previously holds the circuit setting data 32 for each mode, thereby reconfiguring the circuit on the reconfigurable circuit 12 according to the mode. You can respond by doing. Thus, the circuit scale of the processing device 10 can be reduced, and the power consumption can be reduced.
[0024]
FIG. 4 is an explanatory diagram for explaining the operation of the processing apparatus 10 of the present invention. In this example, three types of data for configuring the circuit A, the circuit B, and the circuit C are prepared as the setting data 32, and the setting unit 14 loads the setting data 32 of the circuit A into the reconfigurable circuit 12. 2 shows a state in which the reconfigurable circuit 12 has the function of the circuit A. Naturally, when the setting unit 14 loads another setting data 32, for example, the setting data 32 of the circuit B into the reconfigurable circuit 12, the reconfigurable circuit 12 has the function of the circuit B. .
[0025]
FIG. 5 is an explanatory diagram for explaining the operation of the processing apparatus 10 of the present invention. In this example, as the setting data 32, data for configuring an FIR filter circuit using three types of filter coefficients D, E, and F is prepared, and the setting unit 14 uses the filter coefficient E. By loading the FIR filter circuit setting data 32 to the reconfigurable circuit 12, the reconfigurable circuit 12 has a function of the FIR filter circuit using the filter coefficient E. Naturally, when the setting unit 14 loads another setting data 32, for example, setting data 32 of the FIR filter circuit using the filter coefficient F into the reconfigurable circuit 12, the reconfigurable circuit 12 It has the function of an FIR filter circuit using F.
[0026]
The processing apparatus 10 of the present embodiment can be used for various purposes. In particular, when a plurality of circuit functions that are not used at the same time are required, and a circuit to be used is changed depending on the situation, but the circuit is frequently used for designing a circuit device that does not frequently change, The processing device 10 is very suitable. Hereinafter, such an example will be described.
[0027]
<Example 1>
In the case of Japanese terrestrial digital broadcasting In Japanese terrestrial digital broadcasting, there are mainly the following seven types of parameters that are not changed so much once determined by the transmitting carrier. Information for specifying these parameters is called "state information". The state information is included in the broadcast data signal.
[0028]
“Transmission mode”: There are three types of modes with different OFDM carrier intervals. The carrier interval is about 4 kHz in mode 1, about 2 kHz in mode 2, and about 1 kHz in mode 3. Mode 1 having the widest carrier interval is most resistant to transmission path noise, but the number of data that can be transmitted at one time is the smallest.
[0029]
"Guard interval": Output data after a IFFT (Inverse Fast Fourier Transform), in which data of a designated time length is added directly before an effective symbol from the temporally rear side. Eliminate obstacles caused by multipath time differences such as ghost disturbance. Four types of guard intervals are provided for each of the three types of modes. The larger the guard interval ratio, the stronger the multipath, but the longer the signal processing time.
[0030]
"Modulation scheme": There are four types of modulation schemes: DQPSK, QPSK, 16QAM, and 64QAM. For noise, DQPSK is the strongest and 64QAM is the weakest in this order. On the other hand, the amount of information sent at one time is the smallest in DQPSK and the largest in 64QAM in this order.
[0031]
“Inner code (convolutional code) coding rate”: Indicates the ratio of the number of bits before coding to the number of bits after convolutional coding. There are five coding rates, 1/2, 2/3, 3/4, 5/6, and 7/8, for the four modulation schemes, respectively. With respect to noise, the order of the arrangement is the strongest when the coding rate is 1/2, and the weakest when the coding rate is 7/8. On the other hand, the amount of information sent at a time is the smallest in this order when the coding rate is 1/2, and is the largest when the coding rate is 7/8.
[0032]
"Hierarchy transmission designation": Simultaneous transmission of OFDM segment groups subjected to different transmission path coding. Up to three levels can be specified.
[0033]
"Segment length": Specifies the number of segments of each layer to be used among the 13 segments.
[0034]
"Time interleave length": time-dispersed symbol data after modulation to improve anti-fading performance. The time interleave length is specified independently for each layer.
[0035]
These parameters are changed, for example, in response to changes in the transmission state due to changes in the ionosphere depending on the season. In addition, since these are digital / analog mixed broadcasts, analog broadcasts are not affected. It is conceivable that the transmission power is reduced but the transmission power is increased when only digital broadcasting is performed in the future.
[0036]
In the processing device 10 including the reconfigurable circuit 12, the storage unit 24 stores in advance circuit setting data 32 required according to the change of these parameters. When the processing device 10 is compatible with terrestrial digital broadcasting, the circuits corresponding to the respective parameters are not all mapped to the reconfigurable circuit 12 at the same time, but the corresponding circuits are reconfigured only when the parameters are changed. It is set in the configurable circuit 12. Referring to FIG. 1, specifically, control unit 18 detects state information included in the broadcast data signal, and supplies corresponding setting data 32 to setting unit 14. The setting unit 14 reconfigures the reconfigurable circuit 12 based on the setting data 32. The data portion of the broadcast data signal is sent to the reconfigurable circuit 12, and the reconfigurable circuit 12 executes a desired process. According to the processing device 10, only the necessary circuits are mapped at each time, so that the circuit scale can be small and the power consumption is small.
[0037]
<Example 2>
In the case of Japanese BS digital broadcasting In Japanese BS digital broadcasting, there are mainly the following six types of parameters that are not changed so much once determined by the transmitting carrier. Information for specifying these parameters is called "state information". The state information is included in the broadcast data signal.
[0038]
"Transmission mode (modulation method)": There are seven types of modes, modes 1 to 7, BPSK (1/2), QPSK (1/2), QPSK (2/3), QPSK (3/4), QPSK. (5/6), QPSK (7/8), and TC8PSK (2/3). However, the value in parentheses indicates the coding rate.
[0039]
"Inner coding rate": As shown in "transmission mode (modulation method)", there are five types of coding rates of 1/2, 2/3, 3/4, 5/6, and 7/8. .
[0040]
"Hierarchy transmission designation": Out of a total of 48 slots, up to four types, such as TC8PSK, QPSK, and BPSK, can be arranged in a frame in the order of the number of phases and in the order of coding rate up to slot numbers 1 to 48 and transmitted. .
[0041]
“Relative TS / slot information”: TS transmitted in each slot in order from slot 1 is represented using a relative TS number. A maximum of 8 TSs can be transmitted in one modulated wave.
[0042]
"Relative TS / TS number correspondence table": A correspondence table for converting a relative TS number used in the item of relative TS / slot information into TS_ID of the MPEG2 system.
[0043]
"Transmission / reception control information": a signal for controlling the activation of a receiver in an emergency alert broadcast and a control signal for switching an uplink station.
[0044]
In the processing device 10 including the reconfigurable circuit 12, the storage unit 24 stores in advance circuit setting data 32 required according to the change of these parameters. When the processing device 10 supports BS digital broadcasting, instead of mapping all circuits corresponding to the respective parameters to the reconfigurable circuit 12 at the same time, the corresponding circuit is reconfigured only when the parameter is changed. Is set in the cable circuit 12. Referring to FIG. 1, specifically, control unit 18 detects state information included in the broadcast data signal, and supplies corresponding setting data 32 to setting unit 14. The setting unit 14 reconfigures the reconfigurable circuit 12 based on the setting data 32. The data portion of the broadcast data signal is sent to the reconfigurable circuit 12, and the reconfigurable circuit 12 executes a desired process. According to the processing device 10, only the necessary circuits are mapped at each time, so that the circuit scale can be small and the power consumption is small.
[0045]
For example, the receiver activation control circuit in the emergency alert broadcast only needs to operate only during the emergency alert broadcast, and does not need to operate normally. Therefore, the processing device 10 usually does not have the receiver activation control circuit, and only needs to map the receiver activation control circuit to the reconfigurable circuit 12 at the time of emergency alert broadcasting. When the emergency alert broadcast ends, the signal processing circuit for normal video reception may be re-mapped to the reconfigurable circuit 12. As described above, the processing device 10 does not need to have a receiver activation control circuit and a signal processing circuit which do not operate simultaneously.
[0046]
As described above, the reconfigurable circuit 12 included in the processing device 10 uses an ALU having a high-performance arithmetic function as a basic cell, and the reconfigurable circuit 12 and the setting unit 14 are configured on one chip. Therefore, the configuration can be realized at high speed, for example, with one clock. Therefore, even at the time of receiving the broadcast data, the circuit can be instantly reconfigured by loading the setting data 32, and the viewer can watch a continuous video.
[0047]
The present invention has been described based on the embodiments. It should be understood by those skilled in the art that the embodiments are exemplifications, and that various modifications can be made to the combination of each component and each processing process, and that such modifications are also within the scope of the present invention. .
[0048]
For example, the arrangement of ALUs in the reconfigurable circuit 12 is not limited to a multi-stage arrangement in which connections are allowed only in the vertical direction, and may be a mesh-like arrangement in which connections in the horizontal direction are also allowed. Further, in the above description, a connection for skipping a stage and connecting a logic circuit is not provided, but a connection for skipping such a stage may be provided.
[0049]
Also, an example in which the processing device 10 is applied to a satellite broadcast receiving decoder has been described. However, the application is not limited to this. It is understood by traders.
[0050]
【The invention's effect】
According to the present invention, it is possible to provide an integrated circuit device and a processing device including a reconfigurable circuit that contributes to a reduction in circuit size.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a processing apparatus according to an embodiment.
FIG. 2 is a configuration diagram of a reconfigurable circuit.
FIG. 3 is a diagram showing an example of a data flow graph.
FIG. 4 is an explanatory diagram for explaining an operation of the processing device.
FIG. 5 is an explanatory diagram for explaining an operation of the processing device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Processing device, 12 ... Reconfigurable circuit, 14 ... Setting part, 16 ... Integrated circuit device, 18 ... Control part, 20 ... Compile part, 22 ... Setting Data generation unit, 24 storage unit, 26 external control device, 28 program, 30 data flow graph, 32 setting data, 40 logic circuit, 42.・ Connection part.

Claims (5)

A reconfigurable circuit having a logic circuit whose function can be changed,
A storage unit that stores a plurality of patterns of setting data for configuring the reconfigurable circuit as an intended circuit;
A control unit that receives a selection signal for specifying a circuit to be selected, and selects setting data from a plurality of patterns stored in the storage unit;
A setting unit that sets a circuit configuration of the reconfigurable circuit based on the selected setting data;
A processing device comprising: The processing device according to claim 1, wherein the control unit receives status information of a broadcast data signal as the selection signal. The reconfigurable circuit has a multi-stage array of logic circuits, each of which can selectively execute a plurality of arithmetic functions, and a connection unit that can set a connection relationship between an output of a preceding logic circuit and an input of a following logic circuit. Including
The processing device according to claim 1, wherein the setting unit sets functions of the plurality of logic circuits and the connection relationship. 4. The processing device according to claim 1, wherein the logic circuit is an arithmetic logic circuit that can selectively execute a plurality of types of multi-bit operations. A reconfigurable circuit having a logic circuit whose function can be changed,
A setting unit for setting a circuit configuration of the reconfigurable circuit based on setting data selected from a plurality of patterns of setting data for configuring the reconfigurable circuit as an intended circuit;
An integrated circuit device comprising:

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