JP2004221195A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-speed SiGe bipolar transistor in which an operation is hardly varied. <P>SOLUTION: The SiGe bipolar transistor has a semiconductor substrate, a first conductivity type collector layer on the substrate, a second conductivity type base layer brought into contact with the collector layer and formed by an epitaxial growth so that germanium is contained in at least a part, and a first conductivity type emitter layer brought into contact with the base layer and formed by the epitaxial growth. The emitter layer contains germanium and carbon. Carbon contained in the emitter layer prevents the diffusion of a dopant, and germanium has action in which the change of a lattice constant by carbon doping is compensated and the emitter layer is lattice-matched with a semiconductor substrate material. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bipolar transistor and a method of manufacturing the same, and more particularly, to a SiGe bipolar transistor having a base layer formed of a mixed crystal of silicon and germanium and a method of manufacturing the same.
[0002]
[Prior art]
Among the bipolar transistors, a SiGe bipolar transistor using a mixed crystal of silicon (Si) and germanium (Ge) having a narrower band gap than the silicon material forming the emitter and collector is known as a semiconductor material forming the base. . By utilizing such a band gap difference, the SiGe bipolar transistor can efficiently inject carriers into the base while suppressing reverse injection of minority carriers from the base to the emitter.
[0003]
FIG. 1A shows a doping profile of a bipolar transistor using a SiGe base, and FIG. 1B shows a device structure of a main part of such a SiGe bipolar transistor. As shown in the profile of FIG. 1A, this bipolar transistor adopts a SiGe composition gradient structure in which the Ge concentration of the p + type base layer has a gradient composition for speeding up. This is because, by setting the Ge concentration to a gradient composition, the band gap in the base can be tilted and the base traveling time of the carrier can be reduced.
[0004]
The mixed crystal of SiGe is in a strong strain state near the interface with silicon, and misfit transition is likely to occur. In order to suppress misfit transition at the emitter-base junction surface, germanium is introduced not only into the base layer but also into a part of the emitter layer near the junction surface with the base layer, so that the concentration of germanium increases from the emitter region to the base region. A technique is known in which a configuration is configured to gradually increase over a region (for example, see Patent Document 1).
[0005]
The bipolar transistor shown in FIG. 1B has an n + -type buried layer 111 formed on a semiconductor substrate 110 and an n-type collector layer 112 located in a region defined by the LOCOS oxide film 121 on the buried layer 111. A p + -type SiGe base layer 113 in contact with the n-type collector layer; a heat diffusion emitter region 120 forming a base-emitter junction with the SiGe base layer 113; and a heat diffusion emitter region 120 between the sidewalls 116. And an n + type polycrystalline silicon layer 119 connected to the semiconductor device.
[0006]
The n + -type polycrystalline silicon layer 119 is a diffusion source of the thermal diffusion emitter region 120 and is connected to an upper metal emitter electrode (not shown) to function as an emitter connection layer. SiGe base layer 113 is connected to an upper metal base electrode (not shown) via p + -type polycrystalline silicon layer 117. The n-type collector layer 112 is connected to an upper metal collector electrode (not shown) via the n + -type buried layer 111 and an n + -type lead layer (not shown). Phosphorus (P) is generally used as the p-type dopant of the emitter layer.
[0007]
[Patent Document 1]
JP-A-5-144834
[Problems to be solved by the invention]
In the above-described SiGe bipolar transistor, the heat diffusion emitter region 120 is formed by forming the n + -type polycrystalline silicon layer 119 and then performing a heat treatment to diffuse the dopant. Since the dopant diffusion by the heat treatment is used for the emitter-base junction, the doping profile varies in the wafer surface as shown by A and B in FIG. Since the emitter-base junction interface is substantially determined by the cross point between the n-type dopant profile and the p-type dopant profile, if the profile varies, the thickness of the base layer varies, leading to variations in current gain and delay time. Further, the emitter-base junction is formed in the germanium (Ge) composition gradient layer due to the thermal diffusion, and the on-voltage varies due to the variation of the interface, causing a problem that the characteristics are not stable.
[0009]
In order to avoid this problem, it is conceivable to form an emitter layer by epitaxial growth of silicon (Si) and then dope an n-type dopant to form an emitter-base junction interface. However, a heat treatment is eventually required in the subsequent process, and the heat treatment in a later step causes the dopant to diffuse, causing the same problem.
[0010]
Accordingly, it is an object of the present invention to provide a semiconductor device that constitutes a SiGe bipolar transistor with small characteristic variations.
[0011]
Further, a method of manufacturing a semiconductor device and a growth apparatus capable of easily realizing such a SiGe bipolar transistor are provided.
[0012]
[Means for Solving the Problems]
As a first aspect of the present invention, a semiconductor device includes a semiconductor substrate, a first conductivity type collector layer on the semiconductor substrate, and a semiconductor layer formed by epitaxial growth in contact with the collector layer and containing at least a portion of germanium. The semiconductor device includes a two-conductivity-type base layer and a first-conductivity-type emitter layer in contact with the base layer and formed by epitaxial growth. The emitter layer contains germanium and carbon.
[0013]
Carbon (C) contained in the emitter layer has an effect of suppressing diffusion of a predetermined conductivity type (for example, n-type) dopant doped into the emitter layer. Carbon (C) also acts to reduce the lattice constant of the epitaxially grown emitter layer.
[0014]
Germanium (Ge) contained in the emitter layer has a function of compensating for the shrinkage of the crystal lattice (change in lattice constant) due to carbon (C) doping and causing lattice matching with the semiconductor substrate.
[0015]
With such a configuration, dopant diffusion in the epitaxially grown emitter layer is suppressed, and the emitter-base junction interface is stably determined by epitaxial growth. As a result, variations in device characteristics are suppressed, and operation reliability is improved.
[0016]
Further, diffusion of the dopant due to heat treatment in the subsequent process is also suppressed by the carbon-doped emitter layer, and a doping profile almost as designed is realized.
[0017]
The doping concentration of carbon contained in the emitter layer is 1 × 10 ²⁰ cm ⁻³ or less. On the other hand, the doping concentration of germanium contained in the emitter layer is a concentration that compensates for a change in lattice constant due to carbon doping and lattice matches with the semiconductor substrate. For example, germanium (Ge) and carbon (C) have a box-type doping profile with a constant concentration in the depth direction. Thereby, unnecessary diffusion of the dopant can be suppressed over the entire thickness direction of the emitter layer.
[0018]
According to a second aspect of the present invention, there is provided a method of manufacturing the above-described semiconductor device. This manufacturing method includes the following steps.
(A) A first conductivity type collector layer is formed on a semiconductor substrate.
(B) A second conductivity type base layer in contact with the collector layer is formed by epitaxial growth while introducing germanium.
(C) A first conductivity type emitter layer in contact with the base layer is formed by epitaxial growth, and a predetermined concentration of germanium and carbon is introduced into the emitter layer.
[0019]
By forming the emitter layer of the first conductivity type by epitaxial growth and introducing germanium and carbon into the doped portion of the first conductivity type, the emitter-base junction interface can be formed with good control. Further, by introducing germanium into the emitter layer, the emitter layer can be lattice-matched to the semiconductor substrate material.
[0020]
According to a third aspect of the present invention, there is provided an apparatus for manufacturing a semiconductor device capable of continuously forming layers of different conductivity types without mixing a dopant. This manufacturing apparatus includes a first growth chamber for growing a layer of a first conductivity type, a second growth chamber for growing a layer of a second conductivity type, and an atmosphere shut-off transfer connecting the first growth chamber and the second growth chamber. And a transfer arm for transferring the wafer between the first growth chamber and the second growth chamber without exposing the wafer to the atmosphere via an air-shielded transfer chamber.
[0021]
With such a semiconductor device, it becomes possible to prevent the intermixing of dopants and to continuously epitaxially grow layers of different conductivity types while keeping the pn junction interface clean.
[0022]
Preferably, at least one of the first growth chamber and the second growth chamber includes a first source gas for suppressing diffusion of a dopant and a growth layer for compensating for a change in lattice constant due to the introduction of the first source gas. A gas introduction port for introducing a second source gas for lattice-matching with the substrate material of the wafer.
[0023]
Thereby, even when layers of different conductivity types are formed of a hetero material, the diffusion of the dopant can be suppressed and the layer can be grown with good lattice matching, and the junction surface between the two layers can be easily controlled.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 2 is a doping profile of a SiGe bipolar transistor according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing a device structure of a main part of the SiGe bipolar transistor.
[0025]
The SiGe bipolar transistor according to the present embodiment is located in a p-type silicon substrate 10, an n + -type buried layer 11 formed on the silicon substrate, and a region defined on the n + -type buried layer 11 by a LOCOS oxide film 21. An n-type collector layer 12, ap + -type SiGe base layer 13 in contact with the n-type collector layer 12 and formed by epitaxial growth, and a Ge / C-doped n-type emitter layer 15 in contact with the SiGe base layer 13 and formed by epitaxial growth. , The n-type emitter layer 15 contains germanium (Ge) and carbon (C) doped with a box-type doping profile as shown in FIG.
[0026]
The p + type SiGe base layer 13 has a thickness of 100 nm and contains boron (B) having a doping concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ as a p-type dopant. On the other hand, the Ge / C-doped n-type emitter layer 15 has a thickness of 5 nm, and contains phosphorus (P) having a doping concentration of 1 × 10 ¹⁹ cm ⁻³ as an n-type dopant.
[0027]
A high-concentration n + -type polycrystalline silicon layer 19 extending on sidewall 16 is located in contact with Ge / C-doped n-type emitter layer 15. The n + -type polycrystalline silicon layer 19 is connected to an upper metal emitter electrode (not shown) and functions as an emitter connection layer.
[0028]
The p + type SiGe base layer 13 is connected to an upper metal base electrode (not shown) via a p + type polycrystalline silicon layer 17 extending between the LOCOS oxide film 21 and the insulating film 23. By applying a voltage to the p + -type SiGe base layer 13, the energy barrier between the emitter and the base is controlled, and a large amount of carriers flow from the emitter layer 15 into the SiGe base layer 13.
[0029]
The n-type collector layer 112 is connected to an upper metal collector electrode (not shown) through an n + buried layer 111 and an n + lead layer (not shown).
[0030]
As described above, by making the n-type emitter layer 15 contain carbon (C), it is possible to prevent the n-type dopant such as phosphorus (P) from diffusing into the SiGe base 13. Such a Ge / C-doped n-type emitter layer 15 is selected to have a completely depleted concentration and thickness depending on the concentration of the SiGe base layer 13. For example, in the embodiment, the doping concentration of carbon (C) is substantially constant in the depth direction, and the concentration is 1 × 10 ²⁰ cm ⁻³ or less. If the order of magnitude is higher, the effect is sufficiently obtained.
[0031]
By including germanium (Ge) in the n-type emitter layer 15, reduction of the lattice constant due to carbon doping is compensated, and the emitter layer is lattice-matched with silicon. In the embodiment, the doping concentration of germanium contained in the n-type emitter layer 15 is substantially constant in the depth direction, compensates for a change in lattice constant due to carbon doping, and is a concentration that lattice-matches with the semiconductor substrate. Specifically, the concentration is about 5 to 10 times the carbon (C) concentration.
[0032]
The concentration of the p + -type SiGe base layer 13 continuously increases in the depth direction, and the germanium concentration near the junction surface with the Ge / C-doped n-type emitter layer 15 is included in the Ge / C-doped n-type emitter layer 15. Higher than the germanium concentration.
[0033]
4 and 5 are views showing a manufacturing process of a main part of the SiGe bipolar transistor shown in FIG.
[0034]
First, as shown in FIG. 4A, an n + -type buried layer 11 and an n-type collector layer 12 are formed on a p-type silicon substrate 10 by a usual method, and LOCOS oxidation for element isolation is performed by a LOCOS method. A film 21 is formed. The n + buried layer 11 is formed by ion implantation of an n-type dopant such as antimony (Sb), and the n-type collector layer 12 is formed by performing Si epitaxial growth on the substrate 10 and adding an n-type dopant such as phosphorus (P). It is formed by ion implantation.
[0035]
Next, as shown in FIG. 4B, a silicon oxide film 22 is formed on the entire surface by the CVD method, and ap + -type polycrystalline silicon layer 17 is formed on the silicon oxide film 22 by the CVD method. A silicon oxide film 23 is formed on the silicon layer 17 by a CVD method.
[0036]
Next, as shown in FIG. 4C, an opening 31 for growing a base layer is formed by photolithography and dry etching to expose the n-type collector layer 12.
[0037]
Next, as shown in FIG. 5D, a p + type SiGe base layer 13 is formed in the opening 31 to a thickness of 100 nm by selective epitaxial growth. As the raw material gas, a disilane _(Si 2 _{H 6)} and germane _{(Ge n H 2n + 2)} , by introducing a diborane _(B 2 _{H 6)} as a p-type dopant gas, pressure ¹⁰ -2 ^~10 -1 Pa, 600 Grow at ° C. About 50 nm of the p + -type SiGe base layer 13 having a thickness of 100 nm is grown as a p-type doping layer to have a doping concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ .
[0038]
The p + -type SiGe base layer 13 is formed by using a semiconductor manufacturing apparatus (ultra-high vacuum CVD layer apparatus) 50 having two growth chambers shown in FIG. 6 and placing a wafer in the first growth chamber 51 for p-type. Let it grow. Details of the semiconductor manufacturing apparatus 50 will be described later.
[0039]
Subsequently, the wafer on which the SiGe base layer 13 has been formed is transferred to the second growth chamber 52 for n-type via the air-shielded transfer chamber 53 maintained at a high vacuum, and Ge / C-doped n is transferred to the second transfer chamber. The emitter layer 15 is formed to a thickness of 5 nm by selective epitaxial growth. Growth of Ge / C doped n-type emitter layer 15, as a source gas, disilane _{(Si 2 H} 6), germane _{(Ge n H 2n + 2)} , with monomethyl silane _{(SiH 3 (CH 3))} , n -type dopant gas by introducing phosphine (PH ₃₎ as is grown at a pressure ^{10 -2 ~10 -1 Pa, 600 ℃} . In this embodiment, the doping concentration of the n-type dopant is 1 × 10 ¹⁹ cm ⁻³ , and the carbon (C) concentration is 1 × 10 ²⁰ cm ⁻³ . The concentration of germanium (Ge) is selected so that the n-type emitter layer 15 lattice-matches with silicon (Si), and is, for example, 5 to 10 times the concentration of carbon (C).
[0040]
The thickness (5 nm) and the dopant concentration (1 × 10 ¹⁹ cm ⁻³ ) of the Ge / C-doped n-type emitter layer 15 described above are such that the n-type emitter layer 15 is completely formed in consideration of the concentration of the SiGe base layer 13. It is set to deplete. During epitaxial growth in the first growth chamber 51 and the second growth chamber 52, p-type polycrystalline poly-SiGe mixed crystal and n-type polycrystalline silicon are also formed on the side walls of the opening (emitter window) 31, but n By completely depleting the mold emitter layer 15, a leakage current between the emitter and the base is prevented.
[0041]
In the embodiment, the p + -type SiGe base layer 13 and the n-type emitter layer 15 are formed in the opening 31 by selective epitaxial growth. After these layers are grown on the entire surface of the wafer, the opening 31 is formed by photolithography and etching. Alternatively, a method of leaving the inside may be adopted.
[0042]
Next, as shown in FIG. 5E, an insulating film such as a silicon nitride film or a silicon oxide film is formed on the entire surface by the CVD method, and the Ge / C-doped n-type emitter layer 15 is exposed by anisotropic etching. Etch back to leave the sidewall 16 on the side wall.
[0043]
Next, as shown in FIG. 5F, a high-concentration n + -type polycrystalline silicon layer is formed, and heat treatment by annealing is performed to form a contact with the Ge / C-doped n-type emitter layer 15. The portion other than the opening 31 and its periphery is selectively removed by photolithography and dry etching to form an n + -type polycrystalline silicon layer 19 as an emitter connection layer.
[0044]
FIG. 6 is a schematic plan view of a semiconductor manufacturing apparatus 50 used in the above-described manufacturing method. The semiconductor manufacturing apparatus 50 includes a first growth chamber 51 for growing a layer of one conductivity type (for example, p-type), a second growth chamber 52 for growing a layer of the other conductivity type (for example, n-type), and a first growth chamber. An air-shielded transfer chamber 53 connecting the growth chamber 51 and the second growth chamber 52, and a transfer arm 54 for transferring the wafer between the first growth chamber and the second growth chamber via the air-shielded transfer chamber without exposing the wafer to the atmosphere. And
[0045]
The first and second growth chambers 51 and 52 are connected to an atmosphere shut-off transfer chamber 53 via airtight ports 55 and 56, respectively, and the air shut-off transfer chamber 53 is a load lock chamber 58 for making the processing chamber an ultra-high vacuum. Connected to.
[0046]
The first and second growth chambers 51 and 52 include a susceptor 57 for holding a wafer to be processed, gas introduction systems 61 and 63 for introducing a source gas, and exhaust systems 62 and 64, respectively. The gas introduction systems 61 and 63 include a control system (not shown) for controlling the concentration and composition of the gas sent to the growth chambers 51 and 53, and introduction ports 51a and 53a for introducing the gas into the growth chambers 51 and 53. Prepare. The exhaust systems 62 and 64 include a gas processing system (not shown) for processing gas to be exhausted.
[0047]
The first and second growth chambers 51 and 52 include, for example, a chemical vapor deposition apparatus, a molecular beam epitaxy apparatus, a reactive sputtering apparatus, and the like.
[0048]
In one embodiment, the semiconductor manufacturing apparatus 50 forms the p + -type base layer 13 (FIG. 3) of the SiGe bipolar transistor in the first growth chamber 51 and continuously forms the n-type emitter layer 15 in the second growth chamber 52. Used when doing. However, the present invention is not limited to this example, and the present invention can be used for any step of continuously growing layers of different conductivity types. Since the wafer is transported between the first growth chamber 51 and the second growth chamber 52 without being exposed to the atmosphere, intermixing of dopants is prevented, and continuous epitaxial growth is performed with the pn junction surface kept clean. Will be possible.
[0049]
In the embodiment, the first source gas containing carbon (C) for suppressing the diffusion of the n-type dopant from the introduction port 62a of the second growth chamber 52, and the change in the lattice constant due to the introduction of the first source gas. Is introduced, and a second source gas containing germanium (Ge) is introduced to lattice-match the growth layer with the substrate material of the wafer. Thereby, even if there is a dopant that diffuses in the heat treatment in the subsequent process, the diffusion is suppressed by the carbon (C) -doped emitter layer 15, so that the characteristic variation due to the heat treatment is also controlled. By introducing germanium (Ge), the emitter layer 15 is lattice-matched to silicon, and the device does not deteriorate.
[0050]
In the embodiment described above, the emitter layer is disposed above the collector layer formed on the semiconductor substrate with the base layer interposed therebetween. However, the present invention is not limited to this example. May be arranged as a collector-up structure. In this case, the emitter layer and the base layer are sequentially formed by epitaxial growth in the second growth chamber 52 and the first growth chamber 51, and germanium (Ge) and carbon (C) are simultaneously introduced during the growth of the emitter layer. The introduction of carbon prevents diffusion of the dopant, and germanium compensates for changes in the lattice constant. In addition, it is possible to prevent the dopant (for example, boron (B)) of the base layer from diffusing into the emitter layer by the heat treatment after the growth of the base layer, and to form a uniform emitter-base junction surface.
[0051]
In the above-described embodiment, both carbon (C) and germanium (Ge) are doped so as to have a box-type doping profile. However, the present invention is not limited to this, and carbon (C) is introduced into the emitter layer. It is sufficient to dope germanium as much as necessary for lattice matching with the substrate material, compensating for the change in the lattice constant due to, and any of the doping amounts may change in the depth direction. Also in this case, the doping profile does not need to change continuously, and for example, a doping profile that changes stepwise may be used.
[0052]
Further, the n-type dopant is not limited to phosphorus (P), and arsenic (AS), antimony (Sb), or the like may be used.
[0053]
Finally, with regard to the above description, the following supplementary notes are disclosed.
(Supplementary Note 1) A semiconductor substrate, a collector layer of a first conductivity type on the semiconductor substrate, a base layer of a second conductivity type in contact with the collector layer and formed by epitaxial growth so as to at least partially contain germanium, and a base. A semiconductor device, comprising: a first conductivity type emitter layer formed by epitaxial growth in contact with a layer, wherein the emitter layer contains germanium and carbon.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein a doping concentration of carbon contained in the emitter layer is 1 × 10 ²⁰ cm ⁻³ or less.
(Supplementary note 3) The semiconductor device according to supplementary note 1 or 2, wherein carbon contained in the emitter layer has a box-type doping profile that is distributed at a substantially constant concentration in a depth direction.
(Supplementary Note 4) The doping concentration of germanium contained in the emitter layer is a concentration that compensates for a change in lattice constant due to carbon doping and lattice matches with the semiconductor substrate. Semiconductor device.
(Supplementary note 5) The semiconductor device according to any one of Supplementary notes 1 to 4, wherein germanium contained in the emitter layer has a box-type doping profile distributed at a substantially constant concentration in a depth direction.
(Supplementary Note 6) The semiconductor device according to any one of Supplementary notes 1 to 5, wherein the emitter layer has a concentration and a film thickness that are completely depleted in relation to a base concentration.
(Supplementary Note 7) The concentration of germanium contained in the base layer changes in the depth direction, and the concentration of germanium near the junction surface with the emitter layer is higher than the concentration of germanium contained in the emitter layer. 7. The semiconductor device according to any one of supplementary notes 1 to 6, wherein
(Supplementary Note 8) The semiconductor device according to supplementary note 1, wherein the emitter layer is located above the collector layer with a base layer interposed therebetween.
(Supplementary Note 9) The semiconductor device according to supplementary note 1, wherein the collector layer has a collector-up structure located above the emitter layer via the base layer.
(Supplementary Note 10) A step of forming a first conductivity type collector layer on the semiconductor substrate;
Forming a second conductivity type base layer in contact with the collector layer by epitaxial growth while introducing germanium;
Forming a first conductivity type emitter layer in contact with the base layer by epitaxial growth, and introducing a predetermined concentration of germanium and carbon.
(Supplementary note 11) The method of manufacturing a semiconductor device according to supplementary note 10, wherein carbon is introduced into the emitter layer at a concentration of 1 × 10 ²⁰ cm ⁻³ or less.
(Supplementary Note 12) The semiconductor device according to Supplementary note 10 or 11, wherein germanium is introduced into the emitter layer at a concentration that compensates for a change in lattice constant due to carbon doping and is lattice-matched to the semiconductor substrate. Production method.
(Supplementary note 13) The method according to Supplementary notes 10 to 11, further comprising a step of selecting a concentration and a film thickness of the emitter layer such that the emitter layer is completely depleted in consideration of a concentration of the base layer. A method for manufacturing a semiconductor device according to any one of the above.
(Supplementary Note 14) A first growth chamber for growing a layer of the first conductivity type, a second growth chamber for growing a layer of the second conductivity type, and an atmosphere-blocking transfer chamber connecting the first growth chamber and the second growth chamber. And a transfer arm for transferring a wafer between the first growth chamber and the second growth chamber without exposing the wafer to the atmosphere via an air cutoff transfer chamber.
(Supplementary Note 15) At least one of the first growth chamber and the second growth chamber compensates for a change in lattice constant due to the introduction of the first source gas for suppressing the diffusion of the dopant and the first source gas. 15. The semiconductor manufacturing apparatus according to claim 14, further comprising a gas introduction port for introducing a second source gas for lattice-matching the growth layer with the substrate material of the wafer.
[0054]
【The invention's effect】
As described above, according to the present invention, it is possible to easily realize a SiGe bipolar transistor with small characteristic variations.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a problem of characteristic variation of a conventional SiGe bipolar transistor.
FIG. 2 shows a doping profile in a depth direction of a SiGe bipolar transistor according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a device structure of a main part of a SiGe bipolar transistor according to one embodiment of the present invention.
FIG. 4 is a manufacturing process diagram (part 1) of a main portion of the SiGe bipolar transistor shown in FIG. 3;
5 is a view (part 2) of a process of manufacturing the main part of the SiGe bipolar transistor shown in FIG. 3, showing a step subsequent to FIG. 4 (c);
6 is a schematic plan view of a semiconductor manufacturing apparatus used for manufacturing the SiGe bipolar transistor shown in FIG.
[Explanation of symbols]
Reference Signs List 10 p-type silicon substrate 11 n + -type buried layer 12 n-type collector layer 13 SiGe base layer 15 Ge / C-doped n-type emitter layer 16 Side wall 17 p + -type polycrystalline silicon layer (base connection layer)
19 n + type polycrystalline silicon layer (emitter connection layer)
21 LOCOS oxide film (element isolation region)
23 Insulating film 51 First growth chamber 52 Second growth chamber 53 Airtight transfer chamber 54 Transfer arms 55, 56 Airtight port 58 Load lock chamber 61, 63 Gas introduction system 61a, 63a Gas introduction port 62, 64 Exhaust system

Claims (5)

A semiconductor substrate;
A first conductivity type collector layer on the semiconductor substrate;
A second conductivity type base layer formed by epitaxial growth so as to be in contact with the collector layer and at least partially to contain germanium;
A semiconductor device, comprising: a first conductivity type emitter layer formed by epitaxial growth in contact with the base layer; wherein the emitter layer contains germanium and carbon. The semiconductor device according to claim 1, wherein a doping concentration of carbon contained in the emitter layer is 1 × 10 ²⁰ cm ⁻³ or less. 3. The semiconductor device according to claim 1, wherein the doping concentration of germanium contained in the emitter layer is a concentration that compensates for a change in lattice constant due to carbon doping and lattice matches with the semiconductor substrate. Forming a collector layer of the first conductivity type on the semiconductor substrate; and forming a base layer of the second conductivity type in contact with the collector layer by epitaxial growth while introducing germanium;
Forming a first conductivity type emitter layer in contact with the base layer by epitaxial growth, and introducing a predetermined concentration of germanium and carbon. A first growth chamber for growing a first conductivity type layer;
A second growth chamber for growing a layer of the second conductivity type;
An atmosphere cut-off transfer chamber connecting the first growth chamber and the second growth chamber;
A semiconductor manufacturing apparatus comprising: a transfer arm that transfers a wafer between the first growth chamber and the second growth chamber without exposing the wafer to the atmosphere via the air cutoff transfer chamber.

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