JP2004219647A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display capable of enhancing display quality and reducing power consumption. <P>SOLUTION: The liquid crystal display is provided with a pixel array part 1 where signal lines and scanning lines are arrayed, a signal line driving circuit 2 driving the signal lines, and a scanning line driving circuit 3 driving the scanning lines, and the signal line driving circuit 2 has a bus interface part (Bus 1/F) 11, a VRAM 12, a D/A conversion circuit 13, a ΔΣ modulator 14 quantizing analog pixel data, a digital filter 15, a multiplexer 16 switching and controlling which signal line demodulated data are to be supplied to, and a timing controlling circuit 17 controlling the timing of the multiplexer 16 and the scanning driving circuit 3. Since binarized data quantized by the ΔΣ modulator 14 are supplied to the pixel array part 1 and the binarized data are demodulated and converted into an analog pixel voltage in the interior of a pixel part 6, all the exchanges of signals from the signal line driving circuit 2 to the pixel part 6 can be digitized and influence of noise is lessened. Thus, pixel quality can be enhanced. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device that performs signal line driving using ΔΣ conversion.
[0002]
[Prior art]
Display devices such as a personal computer, a word processor, and a PDA (Personal Digital Assistance) are often driven by a battery and used in a mobile environment, and therefore are required to have low power consumption.
[0003]
Examples of the thin display device include a liquid crystal display (LCD), a plasma display, and a flat CRT. Among them, a liquid crystal display device is most suitable from the viewpoint of low power consumption, and has been put to practical use in many portable devices (portable terminals) (see Patent Document 1).
[0004]
FIG. 4 is a block diagram showing a schematic configuration of a conventional display device. The image data calculated by the CPU system 5 is stored in the VRAM 12, and the D / A conversion circuit 13 sequentially converts the image data in the VRAM 12 into a liquid crystal drive signal (analog signal). This converted signal is amplified by the analog amplifier circuit 31 and then written to each signal line. At the same time as writing to the signal lines, the scanning line driving circuit 3 sequentially drives the scanning lines, whereby a writing voltage to the signal lines is supplied to the pixel portion 6 and pixel display is performed.
[0005]
The analog amplifier circuits 31 are provided one by one for a plurality of signal lines, and the multiplexer 16 switches and controls to which signal line the output of the analog amplifier circuit 31 is supplied.
[0006]
[Patent Document 1]
JP 2002-140051 A
[Problems to be solved by the invention]
The analog amplifier circuit 31 needs to write a predetermined potential to a pixel on the scanning line specified by the scanning line driving circuit 3 within a predetermined time. Therefore, the analog amplifier circuit 31 is required to have two current supply capabilities and signal control capabilities. These two abilities are in an opposite relationship to each other. If the current flows too much, overshoot occurs and the current controllability decreases. Conversely, if the signal controllability increases, the current is reduced. Sufficient current cannot flow.
[0008]
As a method of solving such a problem, an amplifier circuit that constantly increases a current supply capability by constantly flowing a predetermined current is conceivable. However, it is difficult to employ the amplifier in a portable terminal in terms of power consumption.
[0009]
The present invention has been made in view of such a point, and an object of the present invention is to provide a liquid crystal display device capable of improving display quality and reducing power consumption.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention includes a signal line and a scanning line arranged in a row, and a pixel portion formed near each intersection of the signal line and the scanning line, and the pixel portion includes: In a liquid crystal display device having a liquid crystal capacitance for accumulating charges corresponding to a voltage of a corresponding signal line, a ΔΣ modulator for quantizing an analog pixel signal or a digital pixel signal to generate binarized data, and the binarized data And a filter circuit for supplying an analog signal obtained by demodulating the signal to the liquid crystal capacitor.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the liquid crystal display device according to the present invention will be specifically described with reference to the drawings.
[0012]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the liquid crystal display device according to the present invention. The liquid crystal display device of FIG. 1 includes a pixel array unit 1 in which signal lines and scanning lines are arranged in a row, a signal line driving circuit 2 that drives signal lines, and a scanning line driving circuit 3 that drives scanning lines. I have. The CPU system 5 is connected to the signal line driving circuit 2 via a signal bus 4 such as an FPC (Flexible Print Circuit).
[0013]
At least a part of the signal line driving circuit 2 and the scanning line driving circuit 3 are formed on the same insulating substrate as the pixel array unit 1, but the CPU system 5 is mounted on a separate substrate from the insulating substrate. Each circuit formed on the insulating substrate is formed using crystalline silicon or polycrystalline silicon (hereinafter referred to as polysilicon) formed by a method such as a low-temperature process of 500 ° C. or lower (eg, excimer laser annealing). Is done.
[0014]
The pixel section 6 is formed near each intersection of the signal line and the scanning line in the pixel array section 1. The pixel unit 6 has a pixel TFT, a liquid crystal capacitor, and an auxiliary capacitor not shown in FIG. A scanning line is connected to a gate terminal of the pixel TFT, and a liquid crystal capacitance and an auxiliary capacitance are connected to a source terminal via an inductor. The inductor is formed using a signal line and a wiring pattern of the pixel TFT, as described later.
[0015]
The signal line drive circuit 2 includes a bus interface unit (Bus I / F) 11 for receiving 6-bit RGB digital pixel data from the CPU system 5, a VRAM 12 for storing digital pixel data, and converting digital pixel data into analog pixel data. A D / A conversion circuit 13 for conversion, a ΔΣ modulator 14 for quantizing analog pixel data, a digital filter 15 for removing unnecessary frequency components from an output of the ΔΣ modulator 14 and generating binary data, The multiplexer 16 includes a multiplexer 16 for switching and controlling which signal line the demodulated data is supplied to, and a timing control circuit 17 for controlling the timing of the multiplexer 16 and the scanning line driving circuit 3.
[0016]
The signal line driving circuit 2 of FIG. 1 is characterized in that a ΔΣ modulator 14 and a digital filter 15 are newly added to the signal line driving circuit 2 of FIG.
[0017]
FIG. 2 is a block diagram showing the internal configuration of the ΔΣ modulator 14. In FIG. 2, the digital filter 15 of FIG. 1 is omitted for convenience. The ΔΣ modulator 14 in FIG. 2 is a first-order modulator, and includes adders 21 and 22, a one-clock delay unit 23, and a quantizer 24. In general, if the number of binarization levels is n, the input signal of the ΔΣ modulator 14 is u, the output signal is y, the rounding error when quantized is q, and the clock delay is Z-1, the equation (1) The relationship holds.
[0018]
y = n + (1−Z ⁻¹ ) n × q (1)
The quantizer 24 outputs either high or low binary data according to the signal level of the analog pixel data output from the D / A conversion circuit 13. The binarized data is added by the adder 22 to the inverted signal of the signal before entering the quantizer 24. As a result, the adder 22 outputs a signal obtained by inverting the remaining signal components of the binary data. The adder 21 calculates the difference between this signal and the analog pixel data when the next clock is input. This difference is then quantized by the quantizer 24.
[0019]
The ΔΣ modulator 14 of FIG. 2 performs digital signal processing synchronized with a clock. The reproducibility of the output waveform of the ΔΣ modulator 14 depends on the clock frequency. The output error amount of the ΔΣ modulator 14 is represented by the following equation (2) from the above equation (1).
[0020]
Signal error = (1−Z ⁻¹ ) n × q (2)
When quantization is performed using a plurality of quantizers 24 having different binarization levels, binarization at a fine signal level can be realized, and output errors can be reduced.
[0021]
FIG. 2 shows an example in which the quantizer 24 performs only one 1-bit quantization operation, but it is also possible to perform multi-bit quantization by connecting the quantizers 24 of FIG. 2 in series. is there.
[0022]
The output of the quantizer 24 is input to the digital filter 15 where unnecessary frequency components are removed to generate final binary data.
[0023]
If the D / A conversion circuit 13, the ΔΣ modulator 14, and the digital filter 15 are provided for each pixel, the circuit scale of the signal line driving circuit 2 increases, and power consumption also increases. For this reason, in the present embodiment, a D / A conversion circuit 13, a Δ１４ modulator 14, and a digital filter 15 are provided for each of a plurality of pixels, and a multiplexer 16 switches which signal line binary data is supplied to. I have.
[0024]
The binarized data output from the multiplexer 16 is supplied to the selected pixel unit 6. In the pixel section 6, a liquid crystal capacitor C1 and a capacitor or an inductor formed by a thin film process are formed. These functions as a low-pass filter, and converts the binary data into an analog signal. Note that the resistance component, the capacitance component, and the inductance component of the signal line connected to the pixel unit 6 are also used as a material for forming the low-pass filter.
[0025]
The low-pass filter is formed by an inductor and a capacitor or a resistor and a capacitor. Although these circuit elements can be formed by integrated circuit technology, forming an inductor on a substrate requires sub-micron fine wiring, and is difficult to manufacture. For this reason, it is desirable to form an inductor using a signal line or a signal line in the pixel portion 6. Specifically, a signal line or the like is spirally formed to have a desired inductance component. In addition, a magnetic film is formed on the upper surface of the signal line or the like by patterning.
[0026]
Since the capacitance value of the liquid crystal capacitance C1 of the pixel unit 6 varies depending on the signal line voltage applied to one end thereof, it is necessary to apply an initialization voltage before operating as a signal conversion filter to maintain the capacitance value constant. Is desirable. The initialization voltage is desirably at a voltage level at which the liquid crystal capacitance C1 increases.
[0027]
On the other hand, a signal conversion filter may be formed using an auxiliary capacitor C2 connected in parallel with the liquid crystal capacitor C1. The auxiliary capacitance C2 is provided for the purpose of maintaining the voltage applied to the liquid crystal in order to suppress a change in display quality. When the auxiliary capacitance C2 is used as a signal conversion filter, a change in the capacitance value of the liquid crystal capacitance C1 causes a change in filter characteristics. Therefore, it is effective to apply an initialization signal to the liquid crystal so as to reduce the liquid crystal capacitance C1. It is.
[0028]
In addition, signal lines and wiring of a wiring portion are used as the resistance element of the signal conversion filter. By forming these by meandering as necessary, the resistance value can be adjusted. In the process of polycrystalline silicon, a silicon film having different doping conditions can be obtained at the time of forming a thin film transistor. Therefore, a wiring can be appropriately selected from these films. Since an undoped silicon film can be selected from the metal wiring, various circuit constants can be set.
[0029]
Further, a pixel TFT in the pixel section 6 can be used as a resistance element of the signal conversion filter. The on-resistance characteristics of the pixel TFT can be appropriately set by adjusting the signal voltage input to the gate terminal. The on-resistance of the pixel TFT also includes the channel length, the channel width, the material of the gate oxide film, the thickness of the gate oxide film, the resistance of an LDD (Lightly Doped Drain) region, the gate bias voltage, and the mobility of polycrystalline silicon. It can be changed by adjusting etc.
[0030]
FIG. 3 is a block diagram illustrating a schematic configuration of the pixel unit 6. In FIG. 3, the digital filter 15 and the multiplexer 16 of FIG. 1 are omitted for convenience.
[0031]
As shown in FIG. 3, the pixel unit 6 includes a gate driver 21, two transistors Q1 and Q2 connected in series between a power supply terminal and a ground terminal, and a series connection between the power supply terminal and the ground terminal. The two transistors Q3 and Q4, the pixel TFT 22, and the low-pass filter unit 23.
[0032]
The gate driver 21 supplies the binary data and its inverted signal to the gate terminals of the transistors Q1, Q2, Q3, Q4, respectively. The low-pass filter unit 23 demodulates the binary data and converts it into an analog signal.
[0033]
As described above, the low-pass filter unit 23 is formed using a signal line and a wiring in the pixel unit 6. In the example of FIG. 3, the low-pass filter unit 23 is formed by the inductor L1, the capacitor C3, and the inductor L2 connected in series. One end of the inductor L1 is connected to a connection path between the transistors Q1 and Q2, and one end of the inductor L2 is connected to a connection path between the transistors Q3 and Q4.
[0034]
As described above, the liquid crystal display device of the present embodiment supplies the binarized data quantized by the ΔΣ modulator 14 to the pixel array unit 1, demodulates the binarized data inside the pixel unit 6, Since the conversion into the voltage is performed, the exchange of the signal from the signal line driving circuit 2 to the pixel unit 6 can be all-digitalized, and the image quality can be improved because it is less affected by noise.
[0035]
In addition, since signal transmission is performed in all digital, class D operation is performed, so that power efficiency is extremely improved and power consumption can be reduced.
[0036]
As an example, a sampling frequency when performing VGA display and XGA display in the liquid crystal display device of the present embodiment will be described. In the case of performing gradation display of 6 bits for each of RGB, a resolution of about 10 bits is required at regular intervals in consideration of display gamma.
[0037]
Assuming that the display refresh interval is 60 Hz, it is necessary to perform 2 ¹⁰ = 1024-bit display data calculations within this refresh interval.
[0038]
Therefore, the lowest sampling frequency is 60 Hz × 2 ¹⁰ = 61.4 kHz.
[0039]
When displaying one screen is performed by one Δ１４ modulator 14, the following sampling frequency is required to perform VGA display and XGA display.
[0040]
VGA: 61.4 kHz × 640 × 480 × 3 = 57 × 10 ⁹ Hz (57 GHz)
XGA: 61.4 kHz × 1024 × 768 × 3 = 150 × 10 ⁹ Hz (150 GHz)
Since such a high frequency is not practical, it is necessary to provide the ΔΣ modulator 14 for each of a plurality of signal lines. If the Δ の modulator 14 is provided for each signal line, the sampling frequency is as follows.
[0041]
VGA: 61.4 kHz x 480 = 30 MHz
XGA: 61.4 kHz x 768 = 48 MHz
A frequency of this level can be realized using a polysilicon process.
[0042]
In the above description, an example in which the first-order ΔΣ modulator 14 is used has been described. For example, the use of the fifth-order ΔΣ modulator 14 has an effect of improving the dynamic range by two digits or more, and the sampling frequency is It can be reduced to about 500 kHz.
[0043]
In the above-described embodiment, the digital pixel data supplied from the CPU system is once converted to analog pixel data and then input to the ΔΣ modulator. May be generated. In this case, the D / A conversion circuit becomes unnecessary, and the circuit scale can be reduced, and the deterioration of image quality due to the D / A conversion processing can be prevented.
[0044]
The following method is considered as a method of directly generating a modulation signal from digital pixel data. For example, when a 6-bit digital pixel signal is input, the binary data is converted to bit data (bit information converted into a simple sequence of 1) using a binary to bit data converter. In this case, 2 ¹⁰ stage data structure (arrangement of the "H""L") has a periodicity of the data, and "H" as the period of "L" is the pulse width such that equal Make the signal output.
[0045]
Shaping as a pulse having such a periodicity and outputting it is performed with a high reproducibility by fixing to a frequency in which the band of the filter circuit configured in the pixel matches, that is, a frequency at which the conversion efficiency is constant. This is because an image signal can be obtained. The period may be designed based on the pass characteristics of the low-pass filter.
[0046]
In an XGA display panel, an output driver is arranged for each wiring, and the data rate for outputting with 10-bit resolution is 48 MHz. The output frequency when 10 bits are output is about 48 kHz, and assuming a pulse of 10 cycles, a desired characteristic can be obtained by repeating a pulse of about 2 μsec by a filter passing 1 MHz.
[0047]
FIG. 5 shows an example of the above-mentioned pulse. In this example, the output cycle is set to 10 when outputting one pixel. When the black level of the image display is low, the continuity of the periodic pulse is small (FIG. 5 (a)), and when it reaches the halftone, it becomes a rectangular wave with a duty ratio of 50% (FIG. 5 (b)). ). When the black level becomes higher, the duty of black increases, and the output becomes complete "H" at the end (FIG. 5 (c)).
[0048]
In forming the above-described waveform, a drive waveform can be generated from binary pixel data as follows. First, the binary data is converted into bit data (a series of simple bits). For example, 0011 is “0000000000001111”, and 1000 is “000000011111111”. The conversion to the bit data can be performed by taking a logical sum using a logic circuit.
[0049]
Then, based on the bit data obtained from the logical sum, the drive bit data is arranged at a data position corresponding to the output cycle. The drive signal is sampled once by a shift register which is sequentially read out by a clock signal, and is sequentially read out to be supplied with a signal. The original signal is obtained by converting bit data obtained by logical OR into a predetermined value. This is realized by wiring distributed to the shift register. In the allocated signal, the width of the rectangular pulse having periodicity varies depending on the bit data amount.
[0050]
【The invention's effect】
As described above in detail, according to the present invention, since the binarized data generated by the ΔΣ modulator is transmitted to the filter circuit, all-digital signal transmission can be realized and the effect of noise is reduced. Display quality can be improved, and power-efficient class D operation is performed, so that power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a liquid crystal display device according to the present invention.
FIG. 2 is a block diagram showing an internal configuration of a ΔΣ modulator 14;
FIG. 3 is a block diagram showing a schematic configuration of a pixel unit 6;
FIG. 4 is a block diagram illustrating a schematic configuration of a conventional display device.
FIG. 5 is a diagram illustrating an example of an output pulse of a ΔΣ modulator.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Pixel array part 2 Signal line drive circuit 3 Scan line drive circuit 4 Signal bus 5 CPU system 6 Pixel part 11 Bus interface part 12 VRAM
13 D / A conversion circuit 14 ΔΣ modulator 15 Digital filter 16 Multiplexer 17 Timing control circuit 21, 22 Adder 23 1-clock delay unit 24 Quantizer

Claims (9)

Signal lines and scanning lines arranged in a row, and a pixel portion formed near each intersection of the signal lines and scanning lines,
In the liquid crystal display device, the pixel portion includes a liquid crystal capacitor that accumulates a charge corresponding to a voltage of a corresponding signal line.
A ΔΣ modulator that quantizes an analog pixel signal or a digital pixel signal to generate binary data;
A liquid crystal display device, comprising: a filter circuit that supplies an analog signal obtained by demodulating the binary data to the liquid crystal capacitor. The filter circuit is formed using at least one of the liquid crystal capacitor, a capacitor or an inductor formed by a thin film process in the pixel portion, and a wiring resistance or a wiring capacitance of the signal line. The liquid crystal display device according to claim 1. The liquid crystal display device according to claim 1, further comprising a precharge unit that supplies an initial charge to the liquid crystal capacitance. The pixel unit has an auxiliary capacitance connected in parallel to the liquid crystal capacitance,
4. The liquid crystal display device according to claim 1, wherein the filter circuit is formed using the liquid crystal capacitance and the auxiliary capacitance. 5. A scanning line driving circuit for driving the scanning line;
The pixel unit includes a thin film transistor that is controlled to be turned on and off by the scanning line driving circuit,
The liquid crystal display device according to any one of claims 1 to 4, wherein a band-pass characteristic of the filter circuit is optimized by controlling an on-resistance characteristic of the thin film transistor. The on-resistance characteristic of the thin film transistor is controlled by changing at least one of a channel width, a channel length, a gate oxide film, a resistance of an LDD (Lightly Doped Drain) region, and a gate bias voltage of the thin film transistor. The liquid crystal display device according to claim 5, wherein The ΔΣ modulator is provided for each of a plurality of signal lines,
7. The liquid crystal display device according to claim 1, further comprising a signal line selection circuit for selecting a signal line for supplying the binarized data generated by the ΔΣ modulator. 8. The liquid crystal according to claim 7, wherein the Δ 周期 modulator outputs a cycle of the quantized signal output as a basic cycle of n times (n is a natural number greater than 1) a frequency of the binarized data. 9. Display device. 9. The liquid crystal display device according to claim 8, wherein the ΔΣ modulator generates the quantized signal by taking a logical sum of the binarized data using a logic circuit. 10.

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