JP2004212291A - Adjusting device and testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an adjusting device for appropriately adjusting the amount of delay in a variable delay circuit, and to provide a testing device. <P>SOLUTION: The adjusting device for adjusting the amount of delay to be set to the variable delay circuit comprises a setting information memory for storing setting information for adjusting the amount of delay corresponding to each of a plurality of amounts of delay to be set to the variable delay circuit; an expected-value memory for storing the expected value of the amount of delay; an address output section for outputting the address of a setting information memory in which the setting information should be stored to the setting information memory corresponding to the amount of target delay to be adjusted; and an amount-of-delay measurement section for setting one setting value that is the candidate of the setting information to the variable delay circuit to measure the amount of delay in the variable delay circuit. Additionally, the adjusting device is equipped with a write section for writing one setting value to the setting information memory; and an address update section that updates the address to be outputted to the setting information memory when the measured amount of delay meets the expected value, sets other setting values to the variable delay circuit when the measured amount of delay does not meet the expected value, and allows the amount-of-delay measurement section to measure the amount of delay in the variable delay circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an adjustment device and a test device. In particular, the present invention relates to an adjustment device and a test device for adjusting a delay amount of a variable delay circuit.
[0002]
[Prior art]
The semiconductor test apparatus inputs a plurality of input signals delayed by different delay amounts to a semiconductor device to be tested, and tests whether an appropriate output is obtained according to the input signals. Accordingly, the semiconductor test apparatus can test whether or not the semiconductor device to be tested operates properly even when the delay amount and the input signal are delayed within a predetermined standard range. .
Conventionally, a semiconductor test apparatus can appropriately delay an input signal by previously selecting a shifter capable of delaying an appropriate delay amount from a plurality of shifters shifted by a plurality of different shift amounts. (See Patent Document 1).
[0003]
[Patent Document 1]
JP-A-2000-332584
[0004]
[Problems to be solved by the invention]
However, it is difficult to accurately set the delay amount of the delay circuit used for delaying the input signal in advance due to factors such as variations in delay elements. Therefore, it is necessary to adjust the delay amount of the delay circuit before starting the test.
Therefore, an object of the present invention is to provide an adjustment device and a test device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.
[0005]
[Means for Solving the Problems]
That is, according to the first embodiment of the present invention, there is provided an adjustment device for adjusting a delay amount to be set in a variable delay circuit, the delay device being associated with each of a plurality of delay amounts to be set in the variable delay circuit. A setting information memory for storing setting information for adjusting the amount, an expected value memory for storing an expected value of the delay amount in association with each of the plurality of delay amounts, and an address of a setting information memory for storing the setting information Is selected according to a target delay amount that is an adjustment target delay amount, and an address output unit that outputs the setting information to a setting information memory, and one setting value that is a setting information candidate is set in a variable delay circuit. A delay amount measuring unit for measuring a delay amount of the circuit, a writing unit for writing one set value to an address of the setting information memory, and an address to be output to the setting information memory when the measured delay amount satisfies an expected value. The other subject Update to the address corresponding to the delay amount, and if the measured delay amount does not meet the expected value, set another setting value to the variable delay circuit, and measure the delay amount of the variable delay circuit to the delay amount measurement unit. The present invention provides an adjustment device including an address updating unit for performing the adjustment.
[0006]
A delay amount storage unit for storing a change amount of the delay amount of the variable delay circuit with respect to a temperature, and an expected value based on a difference between a temperature when the variable delay circuit is used and a temperature when the delay amount is adjusted. An expected value adjustment unit for performing minute adjustment may be further provided.
The delay amount measuring unit sequentially sets each of the plurality of set values including one measured value in the variable delay circuit, measures the delay amount of the variable delay circuit, and the adjustment device adjusts each of the plurality of set values. A delay error calculator that calculates a delay error that is an error from an expected value, a delay error corresponding to one set value, and a set value obtained by measuring a delay amount before the one set value in a plurality of set values And a comparing unit for comparing the delay error corresponding to the one set value with the minimum value of the delay error corresponding to the one set value. It may be written to the address.
The delay amount measuring section further outputs each of the plurality of setting values to the setting information memory sequentially, and the writing section outputs the setting information when the delay error corresponding to the one setting value is smaller than the minimum value. A set signal may be written to an address of the setting information memory by inputting a write signal instructing writing of data to the memory.
[0007]
According to a second aspect of the present invention, there is provided a test apparatus for testing an electronic device, wherein each of the plurality of test signals used for testing the electronic device is variable to delay a designated delay amount corresponding to the test signal. A delay circuit, a setting information memory that stores setting information for adjusting the delay amount in association with each of the plurality of delay amounts to be set in the variable delay circuit, and a corresponding setting information memory in correspondence with each of the plurality of delay amounts. An address output for selecting an expected value memory for storing an expected value of the delay amount and an address of the setting information memory in which the setting information is to be stored according to a target delay amount which is a delay amount to be adjusted, and outputting the selected information to the setting information memory And a delay value measuring unit that sets one set value that is a candidate for setting information to the variable delay circuit and measures the delay amount of the variable delay circuit, and writes one set value to an address of the setting information memory. When the writing unit and the measured delay amount satisfy the expected value, the address output to the setting information memory is updated to an address corresponding to another target delay amount, and the measured delay amount does not satisfy the expected value. In the case, an address update unit that sets another set value to the variable delay circuit and causes the delay amount measurement unit to measure the delay amount of the variable delay circuit is provided, and a plurality of test signals delayed by the variable delay circuit are provided. A test apparatus characterized by outputting to an electronic device is provided.
Note that the above summary of the present invention does not list all of the necessary features of the present invention, and a sub-combination of these features may also be an invention.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention according to the claims, and all of the combinations of the features described in the embodiments are not limited thereto. It is not always essential to the solution of the invention.
[0009]
FIG. 1 shows a functional block diagram of the test apparatus 100. The test apparatus 100 tests the electronic device 200 by detecting a value of an output signal output by the electronic device 200 for a plurality of input signals having different timings.
[0010]
The test apparatus 100 includes a timing generator 10, a pattern generator 12, a waveform shaper 14, and a comparison / determination unit 18. The timing generator 10 generates a timing signal for operating the test apparatus 100. For example, the timing generator 10 receives a test set signal indicating the timing of supplying a test pattern to the electronic device 200 from the pattern generator 12, and converts the signal indicating the timing of supplying the test pattern to the electronic device 200 with the waveform shaper 14. To supply. Further, the timing generator 10 generates a reference clock for synchronizing the operation of the test apparatus 100 and supplies the reference clock to each component of the timing generator 10.
[0011]
The pattern generator 12 generates a test pattern for testing the electronic device 200 and supplies the generated test pattern to the waveform shaper 14. Further, the pattern generator 12 supplies a control signal indicating a delay amount for delaying the test pattern to the waveform shaper 14. The waveform shaper 14 shapes the received test pattern, and supplies the shaped test pattern to the electronic device 200 according to the signal received from the timing generator 10. For example, the waveform shaper 14 delays the signal indicating the test pattern received from the pattern generator 12 according to the received control signal and supplies the delayed signal to the electronic device 200; And an adjusting device 30 for adjusting the amount of delay to be set for each of the circuits 16-1 to 16-N. Each of the variable delay circuits 16-1 to 16 -N is provided, for example, corresponding to each pin of the electronic device 200, and delays a signal input to each of the plurality of pins of the electronic device 200. The variable delay circuits 16-2 to 16-N have substantially the same configuration as the variable delay circuit 16-1, and a description thereof will be omitted. The comparison / determination unit 18 determines pass / fail of the electronic device 200 based on an output signal output from the electronic device 200 according to the given test pattern.
[0012]
Further, the electronic device 200 is, for example, a DDR-SDRAM, and the comparison determination unit 18 may receive a data signal of the DDR-SDRAM as an output signal and DQS which is a clock signal output in synchronization with the data signal. . In this case, the comparison determination unit 18 may perform a setup / hold test of the electronic device 200 based on the received data signal and DQS, and determine whether the electronic device 200 is good.
[0013]
FIG. 2 shows a block diagram of the variable delay circuit 16-1. The variable delay circuit 16-1 receives a control signal designating a delay amount in units of 62.5 ps from the pattern generator 12, delays a test pattern received from the pattern generator 12 according to the control signal, and Output to The variable delay circuit 16-1 includes a control unit 120, a decoder 130, a variable delay unit 140, and fixed delay units 150A to 150C. The control unit 120 outputs a 2-bit signal specifying a delay amount from 0 ns to 3 ns in units of 1 ns (nanosecond) to the decoder 130 according to the control signal specifying the delay amount received from the pattern generator 12. At the same time, a 4-bit signal designating a delay amount from 0 ps to 937.5 ps in 62.5 ps units is output to the setting information memory 450.
[0014]
The decoder 130 decodes the 2-bit signal received from the control unit 120, and selects one of the AND gates 132-A to 132D corresponding to 00 (0 ns), 01 (1 ns), 10 (2 ns), and 11 (3 ns). To output a signal "1". Each of the AND gates 132A to 132D outputs the logical product of the signal received from the decoder 130 and the test pattern received from the pattern generator 12 to the OR gate 134C, the OR gate 134B, the OR gate 134A, and the fixed delay unit 150A, respectively. I do.
[0015]
Fixed delay section 150A delays the received test pattern by a predetermined delay amount and outputs the result to OR gate 134A. The OR gate 134A outputs the logical sum of the test patterns received from the AND gate 132C and the fixed delay unit 150A to the fixed delay unit 150B. Fixed delay section 150B delays the received test pattern by a predetermined delay amount and outputs the result to OR gate 134B. The OR gate 134B outputs the logical sum of the test patterns received from the AND gate 132B and the fixed delay unit 150B to the fixed delay unit 150C. Fixed delay section 150C delays the received test pattern by a predetermined delay amount and outputs the result to OR gate 134C. The OR gate 134C outputs the logical sum of the test patterns received from the AND gate 132A and the fixed delay unit 150C to the variable delay unit 140.
As a result, in accordance with the delay amounts 0 ns, 1 ns, 2 ns, and 3 ns specified by the control unit 120, the decoder 130 converts the test pattern supplied from the pattern generator 12 into the fixed delay unit 150 It can be delayed by 1, 2, 3 times. It is desirable that each of the fixed delay units 150A to 150C has a delay amount smaller than 1 ns and about 1 ns. This is because the delay amount can be adjusted by further slightly delaying the test pattern in a step 140 described later.
[0016]
The setting information memory 450 stores the variable delay unit 140 in order to adjust the delay amount in association with each of a plurality of delay amounts to be set in the variable delay circuit 16-1 specified by the control unit 120 in units of 62.5 ps. Stores the setting information specified in. For example, the setting information memory 450 is realized as a storage device called a linearize memory, and is designated from the address output unit 330 in the adjustment device 30 when receiving a write instruction from the writing unit 430 in the adjustment device 30. The data set from the delay amount measurement unit 350 in the adjustment device 30 is stored as the setting information at the specified address. Then, the setting information memory 450 outputs the data stored at the address specified by the control unit 120 to the variable delay unit 140 as setting information.
[0017]
The variable delay unit 140 delays the test pattern received from the OR gate 134C by a delay amount according to the setting information specified by the delay amount measuring unit 350 or the setting information memory 450, and outputs the test pattern to the electronic device 200. For example, the variable delay unit 140 receives an 8-bit control signal designating a delay amount from 0 ps to 2550 ps in units of 10 ps (picoseconds) from the delay amount measurement unit 350 or the setting information memory 450. Then, the variable delay section 140 delays the test pattern received from the OR gate 134C according to the delay amount specified by these control signals. That is, the variable delay unit 140 can further delay the delay amount of the test pattern delayed by the fixed delay units 150A to 150C from 0 ps to 2550 ps every 10 ps.
[0018]
FIG. 3 shows a block diagram of the adjusting device 30. The adjusting device 30 adjusts the setting value of the variable delay unit 140 to be stored in the setting information memory 450 for each of the variable delay circuits 16-1 to 16-N based on the expected value of the delay amount stored in the expected value memory 370. The purpose is to do.
[0019]
The adjustment device 30 includes a sequence control unit 310, an error detection output unit 325, a delay amount storage unit 355, an expected value adjustment unit 360, and an expected value memory 370.
The sequence control section 310 includes an address update section 320, an address output section 330, a pin setting section 340, and a delay amount measurement section 350.
[0020]
The address output unit 330 selects an address of the setting information memory 450 in which the setting information is to be stored according to the target delay amount which is the delay amount to be adjusted, and outputs the selected address to the setting information memory 450. Further, the address output unit 330 sends information indicating the target delay amount to the expected value memory 370. Furthermore, when receiving an instruction to update the address from the address updating unit 320, the address output unit 330 updates the address to be sent to the setting information memory 450. The address output unit 330 adjusts the variable delay circuits 16 corresponding to the other pins of the electronic device 200 when the setting in the setting information memory 450 is completed for all the addresses that can be specified in the setting information memory 450. A pin update instruction indicating this is sent to pin setting section 340.
[0021]
By controlling the address output unit 330 and the delay amount measuring unit 350, the address updating unit 320 sequentially supplies the setting information memory 450 with the address at which the setting information is to be stored and the setting value to be stored at the address. More specifically, the address update unit 320 sets the specification satisfaction notification, which is a notification that the delay amount measured by the variable delay circuit 16-1 satisfies the expected value, from the specification determination unit 440. An instruction to update the address output to the information memory 450 to an address corresponding to another target delay amount is sent to the address output unit 330. On the other hand, when the address updating unit 320 receives a specification unsatisfied notification that is a notification that the delay amount measured by the variable delay circuit 16-1 does not satisfy the expected value, the address updating unit 320 issues an instruction to update the set value to the delay amount. It is sent to the measuring section 350.
[0022]
In addition, when the specification update notification has not been received for all the set values for one target delay amount, the address update unit 320 sends a notification to the effect that an error has occurred to the error detection output unit 325. In response, the error detection output unit 325 sets information indicating that an error has occurred in the circuit to be adjusted (for example, the variable delay circuit 16-1) as a flag in the control memory. In response to this, the adjustment device 30 may output information indicating that an error has occurred to the administrator of the test device 100 or the like.
[0023]
The pin setting unit 340 notifies the delay amount measuring unit 350 of the pin to be adjusted according to the received pin update instruction. The delay amount measuring unit 350 measures the delay amount of the notified pin as follows. First, the delay amount measuring section 350 sequentially sets a plurality of setting values, which are candidates for setting information, to the variable delay section 140 according to an instruction from the address updating section 320. Then, for each set value, the delay amount after inputting a signal to the contact 50 of the variable delay circuit 16-1 and outputting the signal from the contact 60 of the variable delay circuit 16-1 is variable for each set value. It is measured as the delay amount of the delay circuit 16-1 and output to the delay error calculation section 400. Each time the pin update instruction is received, the delay amount measuring section 350 sequentially measures the delay amount for the variable delay circuits 16-2 to 16 -N in the same manner and outputs the same to the delay error calculating section 400. In addition, when detecting a measurement error, the delay amount measurement unit 350 outputs information indicating that an error has occurred to the error detection output unit 325.
If the delay amount of the measurement target is smaller than the delay amount measurement accuracy, the delay amount measurement unit 350 may measure the delay amount for a signal that has passed between the contact 50 and the contact 60 a predetermined number of times. . In this case, the expected value memory 370 may store, as an expected value to be compared with the measured delay amount, the total delay amount that a signal that has passed between the contact 50 and the contact 60 a predetermined number of times should be delayed.
[0024]
The delay amount storage unit 355 stores a change amount of the delay amount of the variable delay circuit 16-1 with respect to the temperature of the variable delay circuit 16-1. The expected value adjustment unit 360 stores in advance the temperature of the variable delay circuit 16-1 when the variable delay circuit 16-1 is used for a test. Then, the expected value adjustment unit 360 measures the current temperature of the variable delay circuit 16-1, that is, the temperature at which the delay amount is adjusted. The expected value adjustment unit 360 determines the amount of delay to be adjusted based on the difference between the temperature when the variable delay circuit 16-1 is used for the test and the temperature when the delay amount is adjusted. , And adjusts the expected value in the expected value memory 370.
[0025]
The expected value memory 370 stores an expected value of the delay amount in association with each of the plurality of target delay amounts. For example, when the delay amount measurement unit 350 measures the delay amount once delayed by the variable delay circuit 16-1, the expected value memory 370 stores the target delay value as the expected value associated with the target delay amount. Store the same value as the quantity. On the other hand, when the delay amount measurement unit 350 measures the delay amount delayed by the predetermined number of times by the variable delay circuit 16-1, the expected value memory 370 stores the target delay amount as the expected value associated with the target delay amount. A value obtained by multiplying the quantity by the predetermined number of times is stored. Then, the expected value memory 370 selects an expected value according to the information indicating the target delay amount received from the address output unit 330, and sends the selected expected value to the delay error calculating unit 400.
[0026]
The difference detection unit 380 includes a delay error calculation unit 400, a minimum value memory 410, a comparison unit 420, a writing unit 430, a specification determination unit 440, and a setting information memory 450. The delay error calculator 400 sequentially receives the delay amount of the variable delay circuit 16-1 for each of the plurality of setting values from the delay amount measuring unit 350. Then, the delay error calculating section 400 sequentially calculates a delay error which is an error between the delay amount and the expected value received from the expected value memory 370, and calculates the minimum value memory 410, the comparing section 420, and the specification determining section 440. Send to
[0027]
The minimum value memory 410 stores the minimum value of the delay error corresponding to the set value obtained by measuring the delay amount before one set value among a plurality of set values. For example, as an initial state, the minimum value memory 410 stores the maximum value that can be stored in the minimum value memory 410 in advance. Then, the minimum value memory 410 stores the delay error received from the delay error calculation unit 400 according to the instruction from the writing unit 430.
[0028]
The comparison unit 420 compares the delay error received from the delay error calculation unit 400 with the minimum value obtained from the minimum value memory 410. Then, comparing section 420 sends a write instruction to writing section 430 when the delay error received from delay error calculating section 400 is smaller than the minimum value obtained from minimum value memory 410. In this case, the writing unit 430 sends a write instruction to write the delay error to the minimum value memory 410 to the minimum value memory 410. In addition, writing section 430 inputs a write instruction to setting information memory 450, and thereby writes one set value output from delay amount measuring section 350 to a data line of setting information memory 450, The data is written to the address output from the address output unit 330 to the address line of the setting information memory 450.
[0029]
The specification determining unit 440 determines whether or not the delay error received from the delay error calculating unit 400 falls within a predetermined allowable range. That is, when the difference between the measured delay amount and the expected value is within an allowable range, the specification determining unit 440 determines that the measured delay amount satisfies the expected value, and transmits the specification satisfaction notification to the address updating unit 320. Send to On the other hand, when the difference between the measured delay amount and the expected value is out of the allowable range, the specification determining unit 440 determines that the measured delay amount does not satisfy the expected value, and updates the address of the specification unsatisfaction notification. To the section 320.
[0030]
When receiving a write instruction from the writing unit 430, the setting information memory 450 writes the set value specified by the delay amount measurement unit 350 to the address specified by the address output unit 330. Thus, the setting information memory 450 stores setting information for adjusting the delay amount in association with each of the plurality of delay amounts to be set in the variable delay circuit 16-1.
[0031]
FIG. 4 illustrates an example of the delay amount storage unit 355. The delay amount storage unit 355 stores a change amount of the delay amount of the variable delay circuit 16-1 with respect to the temperature of the variable delay circuit 16-1. For example, when the temperature of the variable delay circuit 16-1 is 10 ° C., the delay amount storage unit 355 stores that the delay amount of the variable delay circuit 16-1 is 1.0 ns. Further, the delay amount storage unit 355 stores that when the temperature of the variable delay circuit 16-1 is 20 ° C., the delay amount of the variable delay circuit 16-1 is 1.2 ns. The delay amount of the variable delay circuit 16-1 is, for example, an actual delay amount measured when the target delay amount is set to 1 ns. Instead, the delay amount storage unit 355 may store the amount of change in the delay amount of the fixed delay units 150A to 150C shown in FIG. 2 with respect to the temperature.
[0032]
As described above, the expected value adjusting unit 360 adjusts the expected value based on the amount of change in the delay amount of the variable delay circuit 16-1 with respect to the temperature stored in the delay amount storage unit 355. For example, when the delay amount is larger when the electronic device 200 is tested than when the delay amount is adjusted, the expected value adjustment unit 360 stores the expected value in the expected value memory 370. Is adjusted to be smaller than the expected value to be set. Therefore, the adjustment device 30 can adjust the expected value so that the delay amount is correct when the electronic device 200 is being tested.
[0033]
FIG. 5 shows an operation flow of the adjusting device 30. The adjustment device 30 operates by software processing configured by S610 to S630 and hardware processing configured by S640 to S720.
[0034]
The adjustment device 30 performs initialization, for example, software boot processing, initialization of a memory area, and the like (S610). Then, the adjusting device 30 starts the hardware processing (S620). After waiting for the end of the hardware processing described later, the adjustment device 30 performs end processing of the software processing (S630). The sequence control unit 310 receives the start instruction of the hardware processing in S620, and starts the sequence processing (S640). For example, the sequence control unit 310 may initialize a counter used for selecting a pin, setting an address, and outputting a set value. Then, the pin setting section 340 selects a pin to be measured (S650).
[0035]
The address updating unit 320 selects an address corresponding to the target delay amount and outputs the selected address to the setting information memory 450 (S655). Then, the delay amount measuring section 350 sets one set value in the variable delay section 140 (S660), and measures the delay amount (S670). Then, when detecting an error (S680: YES), the delay amount measuring unit 350 sets an error flag indicating that an error has occurred in the control memory (S690). On the other hand, when no error is detected (S680: NO), the address updating unit 320 determines whether all the set values do not satisfy the expected values for one target delay amount to be adjusted (S700). .
[0036]
If none of the set values satisfy the expected value (S700: YES), the error detection output unit 325 sets an error flag (S690). If any set value satisfies the expected value, or if the delay error for all set values has not been measured yet (S700: NO), the specification determination unit 440 determines the one set value measured in S670. It is determined whether or not the delay error with respect to the expected value satisfies the expected value (S710). If the expected value is not satisfied (S710: YES), the address update unit 320 returns to S660, sets another set value in the variable delay unit 140, and again measures the delay amount of the variable delay circuit in the delay amount measurement unit. 350. The address updating unit 320 performs, for example, incrementing a counter that outputs a set value as a process of setting another set value.
[0037]
On the other hand, if the expected value is satisfied (S710: NO), the address output unit 330 determines whether or not the adjustment of the delay amounts for all the target delay amounts has been completed (S715). If the adjustment of the delay amounts for all the target delay amounts has not been completed (S715: NO), the address updating unit 320 returns the processing to S655, and selects an address corresponding to another target delay amount. When the adjustment of the delay amounts for all the target delay amounts has been completed (S715: YES), the pin setting unit 340 determines whether the setting information has been set for all the pins to be adjusted (S720). . If no pin has been set (S720: NO), the pin setting unit 340 returns to S650 and updates the pin to be set. As a process of updating the pin to be set, the pin setting unit 340 increments, for example, a counter indicating the pin number of the pin to be set. When the setting information has been set for all the pins (S720: YES), the adjustment device 30 ends the hardware processing.
[0038]
As is clear from the above description, the adjusting device 30 can appropriately adjust the delay amounts of the variable delay circuits 16-1 to 16-N. Then, the adjusting device 30 performs a series of processes for adjusting the delay amount of the variable delay circuit, that is, a process for sequentially setting a plurality of set values, a determination as to whether or not an expected value is satisfied, and a case where the expected value is satisfied. And the process of writing the set value to the memory can be performed at high speed by hardware.
[0039]
As described above, the present invention has been described using the embodiment. However, the technical scope of the present invention is not limited to the scope described in the embodiment. Various changes or improvements can be added to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention. For example, the test apparatus 100 may include a plurality of adjustment devices 30 in association with a plurality of variable delay circuits 16. In this case, the delay amounts of the variable delay circuits 16 can be adjusted in parallel.
[0040]
【The invention's effect】
As is clear from the above description, according to the present invention, the delay amount of the variable delay circuit can be appropriately adjusted.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of a test apparatus 100.
FIG. 2 is a block diagram of a variable delay circuit 16-1.
FIG. 3 is a block diagram of an adjustment device 30;
FIG. 4 is a diagram illustrating an example of a delay amount storage unit 355;
FIG. 5 is an operation flowchart of the adjusting device 30.
[Explanation of symbols]
10 Timing generator
12 Pattern generator
14 Waveform shaper
16 Variable delay circuit
18 Comparison judgment section
30 Adjustment device
50 contacts
60 contacts
100 test equipment
120 control unit
130 decoder
132 AND gate
134 OR gate
140 Variable delay unit
150 fixed delay unit
200 Electronic Device
310 Sequence control unit
320 Address update unit
325 Error detection output unit
330 Address output unit
340 pin setting section
350 Delay measurement section
355 delay amount storage
360 expected value adjustment unit
370 Expected value memory
380 Difference detection unit
400 Delay error calculator
410 Minimum value memory
420 comparison section
430 Writing unit
440 Specification judgment unit
450 Setting information memory

Claims (5)

An adjusting device for adjusting a delay amount to be set in a variable delay circuit,
A setting information memory that stores setting information for adjusting the delay amount in association with each of a plurality of delay amounts to be set in the variable delay circuit;
An expected value memory storing an expected value of the delay amount in association with each of the plurality of delay amounts;
An address output unit that selects an address of the setting information memory in which the setting information is to be stored, according to a target delay amount that is the delay amount to be adjusted, and outputs the setting information to the setting information memory;
One set value that is a candidate for the setting information, set in the variable delay circuit, a delay amount measurement unit that measures the delay amount of the variable delay circuit,
A writing unit that writes the one set value to the address of the setting information memory;
When the measured delay amount satisfies the expected value, the address output to the setting information memory is updated to an address corresponding to another target delay amount, and the measured delay amount satisfies the expected value. An adjusting unit that sets the other set value in the variable delay circuit when the variable delay circuit does not exist, and causes the delay amount measurement unit to measure a delay amount of the variable delay circuit. A delay amount storage unit that stores a change amount of the delay amount of the variable delay circuit with respect to a temperature;
An expected value adjustment unit that adjusts the expected value by the change amount based on a difference between a temperature when the variable delay circuit is used and a temperature when the delay amount is adjusted. Item 2. The adjusting device according to Item 1. The delay amount measurement unit, each of the plurality of setting values including the one measurement value is sequentially set in the variable delay circuit, to measure the delay amount of the variable delay circuit,
The adjustment device is
For each of the plurality of setting values, a delay error calculation unit that calculates a delay error that is an error with the expected value,
The delay error corresponding to the one set value, and a comparing unit that compares the minimum value of the delay error corresponding to the set value measured delay amount earlier than the one set value in the plurality of set values. Further comprising
2. The writing unit writes the one set value to the address of the setting information memory when the delay error corresponding to the one set value is smaller than the minimum value. Adjustment device. The delay amount measurement unit further outputs each of the plurality of setting values sequentially to the setting information memory,
The writing unit, when the delay error corresponding to the one set value is smaller than the minimum value, inputs a write signal instructing the setting information memory to write data, and 4. The adjusting device according to claim 3, wherein a setting value is written to the address of the setting information memory. A test apparatus for testing an electronic device,
A variable delay circuit that delays each of a plurality of test signals used for testing the electronic device by a delay amount specified according to the test signal,
A setting information memory that stores setting information for adjusting the delay amount in association with each of a plurality of delay amounts to be set in the variable delay circuit;
An expected value memory storing an expected value of the delay amount in association with each of the plurality of delay amounts;
An address output unit that selects an address of the setting information memory in which the setting information is to be stored, according to a target delay amount that is the delay amount to be adjusted, and outputs the setting information to the setting information memory;
One set value that is a candidate for the setting information, set in the variable delay circuit, a delay amount measurement unit that measures the delay amount of the variable delay circuit,
A writing unit that writes the one set value to the address of the setting information memory;
When the measured delay amount satisfies the expected value, the address output to the setting information memory is updated to an address corresponding to another target delay amount, and the measured delay amount satisfies the expected value. If not, setting the other set value in the variable delay circuit, comprising an address update unit that causes the delay amount measurement unit to measure the delay amount of the variable delay circuit,
A test apparatus for outputting the plurality of test signals delayed by the variable delay circuit to the electronic device.

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