JP2004207846A - Spread spectrum clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a spread spectrum clock generating circuit with a simple configuration by which excellent spread spectrum can be attained. <P>SOLUTION: In the spread spectrum clock generating circuit provided with: a frequency phase comparator for detecting a phase difference between a reference clock CLK and a generated clock CK; a charge pump 13 for generating a charging/discharging signal in response to the detected phase difference; a loop filter 14 for generating a difference signal in response to the charging/discharging signal; a spread spectrum modulation circuit 19 for modulating the difference signal to generate a spread spectrum modulation signal; and a clock generator 20 for generating the clock CK with a frequency in response to the spread spectrum signal, the spread spectrum modulation circuit 19 generates the spread spectrum modulation signal whose period is changed into a plurality of different periods. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a spread spectrum clock generation circuit that generates a clock signal whose period fluctuates by a small amount in order to reduce electromagnetic wave radiation.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as semiconductor devices have become faster and more highly integrated, electromagnetic wave radiation from the devices has become a problem. As the operating frequency increases, the wavelength of the signal becomes shorter, and the wiring length inside the connection circuit or the substrate becomes almost the same as the wavelength of the high-frequency signal. Radiation increases rapidly. Electromagnetic radiation of an electronic device using a semiconductor element that operates with a high-speed clock causes adverse effects such as a malfunction due to mutual interference between electronic devices and interference with a communication device.
[0003]
In order to solve such problems, in electronic equipment where electromagnetic radiation is a problem at present, measures such as reducing the electromagnetic radiation by improving the circuit layout etc. and reducing the leakage of electromagnetic waves to the surroundings by shielding the electromagnetic waves, etc. Has been done. However, there is a problem that it is difficult to sufficiently perform shielding for reducing electromagnetic wave radiation since portable devices and the like are required to be reduced in size and weight.
[0004]
Therefore, it has been practiced to spread the clock by slightly changing the operation clock of the semiconductor device to reduce electromagnetic wave radiation, and a spread spectrum clock generation (SSCG) circuit for generating such a clock has been developed. Proposed. (JP-A-2000-101424, etc.)
FIG. 1 is a diagram illustrating a configuration example of a conventional SSCG circuit. This example is a circuit that generates a clock CK having a frequency M / N times that of a reference clock CLK using a PLL (Phase Locked Loop) circuit. This circuit includes a 1 / N divider 11, a frequency phase comparator 12, a charge pump (CP) 13, a loop filter 14, a voltage controlled oscillator (VCO) 17, a 1 / M divider 18, a modulator 15, a voltage It comprises an adder circuit 16. The frequency phase comparator 12 detects the phase difference between the 1 / N frequency-divided CLK and the 1 / M frequency-divided CK, and outputs a signal for controlling the CP 13 according to the phase difference.
The CP 13 outputs a signal for charging and discharging the loop filter 14 according to the phase difference, and a difference voltage corresponding to the phase difference is generated at one end of the loop filter 14. In a conventional clock generation circuit that does not perform spread spectrum, this difference voltage is applied to the VCO 17, and a clock having a constant cycle is generated accordingly. However, in the SSCG circuit, the modulator 15 outputs a spectrum modulation signal that fluctuates at a predetermined cycle with a small amplitude as shown in FIG. 2, and the voltage addition circuit 16 adds the spectrum modulation signal to the difference voltage to add the VCO 17 Is applied. As a result, the cycle of the generated clock CK fluctuates in a predetermined cycle around a cycle M / N times the cycle of the reference clock CLK. The rate of change of the period and the cycle are determined by the spectrum modulation signal generated by the modulator.
[0005]
Generally, a triangular wave as shown in FIG. 2 is used as the spectrum modulation signal. However, when a triangular wave is used, peaks are generated at both ends of the spectrum width generated by diffusion, so that there is a problem that electromagnetic wave radiation in this portion increases.
[0006]
Therefore, JP-A-7-235862 and JP-A-9-98152 disclose using a waveform as shown in FIG. 3 as a spectrum modulation signal. As a result, the above-mentioned peak is reduced, and electromagnetic wave radiation is reduced.
[0007]
Japanese Patent Application Laid-Open No. 8-292820 discloses a configuration in which the period of a spectrum modulation signal is randomly changed. Electromagnetic radiation is reduced by randomly changing the period.
[0008]
[Patent Document 1]
JP-A-2000-101424 (whole)
[Patent Document 2]
JP-A-7-235862 (FIG. 3)
[Patent Document 3]
JP-A-9-98152 (FIG. 3)
[Patent Document 4]
JP-A-8-292820 (whole)
[0009]
[Problems to be solved by the invention]
However, it is not easy to generate a waveform as shown in FIG. 3, and there is a problem that a circuit for generating such a waveform is large in scale and high in cost.
[0010]
Also, if the cycle of the spectrum modulation signal is changed at random, the cycle of the generated clock may change greatly in a short time. This is not preferable in terms of the operation of the SSCG circuit. In addition, when the generated clock is used in a logic circuit or the like, there is no problem in operation if the rate of change with respect to time is small even if the range of change is large. .
[0011]
SUMMARY OF THE INVENTION It is an object of the present invention to realize a spread spectrum clock generation circuit that can further reduce electromagnetic wave radiation with a simple configuration.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a spread spectrum clock generation circuit according to the present invention is characterized in that a spread spectrum modulation circuit modulates a difference signal to generate a spread spectrum modulation signal whose period changes to a plurality of different periods. . It is desirable that the cycle of the spread spectrum modulation signal changes sequentially in each cycle.
[0013]
FIG. 4 is a diagram showing the principle configuration of the spread spectrum clock generation circuit according to the present invention. As shown in FIG. 4, the spread spectrum clock generation circuit of the present invention generates a charge / discharge signal in accordance with a frequency / phase comparator 12 for detecting a phase difference between a reference clock CLK and a generated clock CK, and a detected phase difference. A charge pump 13, a loop filter 14 for generating a difference signal, a spread spectrum modulation circuit 19 for modulating the difference signal to generate a spread spectrum modulation signal, and a clock for generating a generation clock having a frequency corresponding to the spread spectrum modulation signal In the spread spectrum clock generation circuit including the generator 20, the spread spectrum modulation circuit 19 generates a spread spectrum modulation signal whose period changes to a plurality of different periods.
[0014]
FIG. 5 is a diagram illustrating the principle of the present invention. In the conventional SSCG circuit, a spread spectrum modulation signal of a triangular wave that changes at a constant period as shown in FIG. 2 is added to the difference signal. Therefore, for example, when an oscillation frequency of 10 MHz is modulated at 30 kHz, the spectrum components are 9.91 MHz, 9.94 MHz, 9.97 MHz, 10.00 MHz, 10.3 MHz, as shown in FIG. They are arranged at intervals of 30 kHz around 10 MHz, such as 03 MHz, 10.06 MHz, and 10.09 MHz. On the other hand, in the present invention, as shown in FIG. 5, the period (frequency) of the spread spectrum modulation signal is changed such that tm1 = 30 kHz, tm2 = 27 kHz, and tm3 = 33 kHz. In this case, as shown in FIG. 6B, the spectrum components are dispersed and arranged in three groups of every 27 kHz, every 30 kHz and every 33 kHz, so that the height of each spectrum is lower than that of the conventional example. Become.
[0015]
As described above, according to the present invention, since the cycle of the spread spectrum modulation signal changes to a plurality of different cycles, the spectrum is further spread as compared with the case where the cycle is constant, and the electromagnetic wave radiation can be further reduced. In addition, since the cycle of the spread spectrum modulation signal changes in order every cycle, the cycle does not change rapidly in a short time, and the cycle-to-cycle (cycle-to-cycle) which is the difference between the cycles of adjacent clock pulses is used. cycle) Jitter is small. Therefore, even when the generated clock is used for a logic circuit or the like, there is no problem in circuit operation.
[0016]
The period of the spread spectrum modulated signal may be changed at the position where the zero crossing occurs as shown in FIG. 5A, or the period may be changed at the position where the amplitude is minimum as shown in FIG. Various modifications are possible, such as changing the cycle at a position where the amplitude is maximum or at a position where the amplitude is a predetermined value. Also, the change of the cycle may be not only three kinds but also four kinds or more.
[0017]
A voltage controlled oscillator (VCO) can be used as the clock generator. When a VCO is used as a clock generator, a spread spectrum modulation signal generated by a spread spectrum modulation circuit is added to a differential voltage generated at one end of a loop filter to obtain a spread spectrum modulation signal. Apply.
[0018]
When a VCO is used as a clock generator, the spread spectrum modulation circuit can be realized by an analog circuit or a digital circuit. When the spread spectrum modulation circuit is realized by an analog circuit, for example, an analog modulator generates a spread spectrum analog voltage signal that changes at a plurality of different periods, and a voltage addition circuit adds the spread spectrum analog voltage signal to the difference signal. I do. The analog modulator includes a plurality of different capacitors, a plurality of switches for selecting one of the plurality of different capacitors, a constant current source for supplying a constant current to the selected capacitor or flowing a constant current from the selected capacitor, A hysteresis comparator for detecting that the voltage of the selected capacitor has reached the first and second predetermined voltages; and a plurality of switches for detecting that the hysteresis comparator has reached the first and second predetermined voltages. And a switch switching control circuit for switching the selection.
[0019]
When the spread spectrum modulation circuit is implemented by a digital circuit, a digital control circuit generates an output code that changes at a plurality of different periods, and a digital-to-analog conversion voltage circuit generates a spread spectrum voltage signal corresponding to the output code. A spread spectrum voltage signal is added to the difference signal by a voltage adding circuit.
[0020]
The present applicant discloses in Japanese Patent Application No. 2002-266631 that a voltage-current conversion circuit converts a differential voltage into a differential current signal without using a VCO, and a current variable circuit performs spread-spectrum modulation on the differential current signal to obtain a current oscillator. A configuration for applying a spread spectrum modulation signal to (ICO) is disclosed, and the present invention is also applicable to this.
[0021]
When the present invention is applied to the configuration disclosed in Japanese Patent Application No. 2002-266631, a voltage / current conversion circuit for converting a difference voltage into a difference current signal is further provided, and an ICO is used as a clock generator. A spread spectrum modulation circuit is provided between a digital control circuit for generating an output code that changes at a plurality of different cycles and a voltage-current conversion circuit and an ICO, and performs modulation corresponding to the output code on a difference current signal to generate a spread spectrum current. A current variable circuit for generating a modulation signal.
[0022]
The current variable circuit includes a circuit that generates a difference current signal having a predetermined ratio, and a digital-to-analog conversion current circuit that converts an output code into a spread spectrum current signal of an analog signal and adds it to the difference current signal having a predetermined ratio. This is achieved by: It is desirable that the current variable circuit further includes a low-pass filter that removes a high-frequency component.
[0023]
The digital control circuit includes a plurality of frequency dividers having different division ratios for dividing the clock, a switching controller for sequentially selecting outputs of the plurality of frequency dividers, and an up / down counter for counting the selected divided clock. This is realized by providing a counter that counts the frequency-divided clock and switches between the up operation and the down operation of the up / down counter at every predetermined count.
[0024]
Further, the digital control circuit can be realized by a computer system under program control.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 7 is a diagram showing a configuration of a spread spectrum clock generation (SSCG) circuit according to the first embodiment of the present invention. As shown in the drawing, a circuit that generates an M / N-fold clock CK from the reference clock CLK using a PLL circuit in the same manner as the circuit shown in FIG. 1. The spread spectrum modulation signal generated by the modulator 22 is: The difference from the conventional example is that the period changes sequentially as shown in FIG.
[0026]
As shown in FIG. 7, in the SSCG circuit of the first embodiment, the control circuit 21 generates an output code as shown in FIG. The modulator 22 is a voltage analog-to-digital converter (VDAC), and converts an output code into an analog voltage signal. As a result, a spread spectrum modulated analog voltage signal as shown in FIG. If the voltage signal does not change smoothly due to the voltage change width corresponding to the minimum bit of the output code, smoothing is performed using a low-pass filter. The voltage adding circuit 16 adds a spread spectrum modulated analog voltage signal to a difference voltage generated at one end of the loop filter 14. Thus, the voltage applied to the VCO 17 changes with a small amplitude while the cycle changes sequentially, and the clock CK generated by the VCO 17 changes at a predetermined cycle in a small frequency (cycle) range, and the changing cycle is changed. It changes in order.
[0027]
The control circuit 21 can be realized by a digital logic circuit or the like if there is no need to change the generated output code. Those skilled in the art can easily think of such a circuit configuration, and thus the description is omitted here. Further, the control circuit 21 can be realized by a computer system controlled by a program such as a microcomputer or a DSP. In this case, it is possible to change the output code in accordance with external control.
[0028]
FIG. 9 is a diagram showing the configuration of the SSCG circuit according to the second embodiment of the present invention. In the first embodiment, the spread spectrum modulated analog voltage signal is generated by digital processing. In the second embodiment, the spread spectrum modulated analog voltage signal is generated by analog processing.
[0029]
FIG. 10 is a diagram showing a circuit configuration of the switch switching control circuit 31 and the analog circuit modulator 32 of FIG. 9, and FIG. 11 is a diagram showing an operation of the analog modulator. As shown in FIG. 10, in this circuit, three capacitance elements C1 to C3 having different capacitance values are provided, one end of each capacitance element is connected to the ground, and the other end is connected via switches S1 to S3, respectively. Connected in common. The conduction / non-conduction of each switch is controlled by the switch switching control circuit 31. A portion indicated by reference numeral 32 is a current for supplying (charging) or flowing out (discharging) a current equal to the current I flowing from the constant current circuit to the commonly connected terminals of the switches S1 to S3 by the current mirror circuit. The source circuit. The commonly connected terminals of the switches S1 to S3 are the output terminals of the analog modulator, and are connected to the hysteresis comparator 34. The hysteresis comparator 34 compares the input voltage of the commonly connected terminals of the switches S1 to S3 with the first and second reference values, and controls the transistors Tr1 and Tr2 of the current source circuit according to the comparison result. Then, the current source circuit is switched between the charge state and the discharge state.
[0030]
Hereinafter, the operation of the circuit of FIG. 10 will be described with reference to FIG.
[0031]
First, the output of the hysteresis comparator 34 becomes “high (H)”, the transistor Tr1 is turned on, Tr2 is turned off, and the current source circuit is charged. The switch switching control circuit 31 outputs a selection signal for setting S1 to a conductive state and setting S2 and S3 to a non-conductive state. As a result, the current I is supplied to C1, and the analog modulator output voltage increases. When the analog modulator output voltage reaches the first predetermined value, the output of the hysteresis comparator 34 changes to “low (L)”, Tr1 is turned off, Tr2 is turned on, and the current source circuit is turned on. A discharge state occurs. A change in the output of the hysteresis comparator 34 is also transmitted to the switch switching control circuit 31.
As a result, the current I flows out of C1, and the output voltage of the analog modulator decreases.
[0032]
When the output voltage of the analog modulator reaches the second predetermined value, the output of the hysteresis comparator 34 changes to "H", Tr1 becomes conductive, Tr2 becomes nonconductive, and the current source circuit becomes charged. . The switch switching control circuit 31 switches S1 to a non-conductive state and S2 to a conductive state according to a change in the output of the hysteresis comparator 34. S3 remains non-conductive. Thus, as in the case of C1, the charging of C2 is started, and when the output voltage of the analog modulator reaches the first predetermined value, the output of the hysteresis comparator 34 changes to "L" and the current source circuit discharges. State. Then, the analog modulator output voltage reaches the second predetermined value.
[0033]
Since C1 and C2 have different capacitance values, the times required for charging and discharging are different, and triangular waves having different periods can be obtained. The same operation is repeated for C3. In this way, analog modulator outputs having the same amplitude and three different periods as shown in FIG. 11 are obtained.
[0034]
Here, an example in which three capacitance elements are used has been described. However, four or more capacitance elements can be used, and control is performed so that two or more switches are simultaneously turned on. It is also possible to generate triangular waves having different periods by using the sum of the capacitance values of a plurality of capacitance elements.
[0035]
FIG. 12 is a diagram showing a configuration of an SSCG circuit according to a third embodiment of the present invention, which is an embodiment in which the present invention is applied to the configuration disclosed in the aforementioned Japanese Patent Application No. 2002-266631. As shown in FIG. 12, it has a configuration similar to that of the circuit of the first embodiment shown in FIG. 7, and instead of the voltage adding circuit 16, the VCO 17, the control circuit 21, and the modulator (VDAC) 22, the voltage-current conversion (V -I conversion) circuit 42, a current digital-to-analog converter (IDAC) 43, a current oscillator (ICO) 44, and a control circuit 41. The VI conversion circuit 42 converts a terminal voltage (difference voltage) of the loop filter 14 into a difference current signal. The IDAC 43 corresponding to the current variable circuit performs spread spectrum modulation on the difference current signal according to the output code from the control circuit 41, and applies the modulated spread spectrum modulated current signal to the current oscillator (ICO) 44.
[0036]
FIG. 13 is a diagram showing a circuit configuration of the frequency phase comparator, and FIG. 14 is a diagram showing a configuration of the charge pump circuit 13. These circuits can be used in the first to third embodiments. Since these circuits are widely known, description thereof is omitted here.
[0037]
FIG. 15 shows a circuit configuration of a VI conversion circuit used in the third embodiment, FIG. 16 shows a configuration of an ICO circuit used in the third embodiment, and FIG. 17 shows a circuit of an IDAC circuit used in the third embodiment. The configuration is shown. These circuits are disclosed in Japanese Patent Application No. 2002-266631, and a detailed description thereof will be omitted. Only relevant operations will be described later.
[0038]
FIG. 18 is a diagram showing a configuration of the control circuit 41. As shown in the figure, the control circuit 41 includes three frequency dividers 51 to 53 for dividing the control clock at different frequency division ratios (here, 1/9, 1/10, 1/11), Switches 55 to 57 for selecting the output of the frequency divider, a switching control unit 54 for selecting the switch, an up / down counter 58 for counting the selected frequency-divided clock, and a frequency division counter 59 for controlling the up / down counter 58 And The up / down counter 58 outputs the count value in an n-bit binary code.
[0039]
FIG. 19 is a diagram illustrating operations of the switching control unit 54 and the frequency divider. The frequency dividers 51 to 53 output three types of frequency-divided clocks obtained by dividing the control clock by the respective frequency division ratios. As shown in FIG. 19, the switching control unit 54 selects the switch 55 to be conductive while counting the control clock by 9 × 16 clocks. Therefore, during this time, the 1/9 frequency-divided clock is output. After counting the control clock by 9 × 16 clocks, the switching control unit 54 turns on the switch 56 while counting the control clock by 10 × 16 clocks, and then switches by turning on the switch while counting the control clock by 11 × 16 clocks. Then, the same operation is repeated. Thus, the 1/9 frequency-divided clock, the 1/10 frequency-divided clock, and the 1/11 frequency-divided clock are sequentially supplied to the up-down counter 58 and the frequency-divider counter 59 in this order.
[0040]
FIG. 20 is a diagram showing operations of the up / down counter 58 and the frequency dividing counter 59. The frequency dividing counter 59 counts the selected frequency-divided clock, and when the count value reaches a predetermined value, switches between the up-counting operation and the down-counting operation of the up-down counter 58 and repeats this operation. FIG. 20 shows an example of switching between an up-count operation and a down-count operation when 8 counts are performed. If an output code as shown in FIG. 8 is generated, the output code is switched every 14 counts. The up / down counter 58 counts the selected frequency-divided clock and outputs the count value as an n-bit binary code. As described above, since the cycle of the supplied divided clock changes, the length of one cycle (cycle) of the generated code output also differs. The code output from the up / down counter 58 is applied to the IDAC 43.
[0041]
As shown in FIG. 17, the IDAC 43 has a current mirror circuit including transistors Tr11 to Tr15, Tr20, and Tr30 to Tr3n. By appropriately setting the size of the transistor as shown in FIG. A current of 90% of the current Iref output from the I conversion circuit 42 flows, a current of 10% of Iref flows in Tr3n, and a current (20 × 1/2) of Iref in Tr32. ^n-2 )% Of the current flows through Tr31 and (20 × 1/2) of Iref ^n-1 )% Of the current flows, and Tr30 has (20 × 1/2) of Iref. ⁿ )% Current flows. When the Tr4n to Tr40 are turned on by the bit data / D0 to / Dn of the output code, a current flows through the corresponding Tr3n to Tr30. Therefore, when all of Tr4n to Tr40 are made non-conductive, a current amount of 90% of Iref flowing through Tr20 is output. A current flows through Tr3n to Tr30, and a current amount of about 110% of Iref is output. That is, by setting the bit data / D0 to / Dn of the output code to an appropriate value, an appropriate amount of current between 90% and about 110% of Iref is output.
[0042]
Therefore, by applying the output code of the up / down counter 58 changing as shown in FIG. 20 to the IDAC 43 of FIG. 17, Iref is changed in nine steps of about 2.5% from 90% to about 110% in steps of about 2.5%. Is possible, and the change cycle is changed in three stages. In response to this, the ICO 44 repeatedly increases and decreases the frequency (period) by about 2.5% within ± 10%, and generates a clock CK whose changing period changes. If an output code that changes as shown in FIG. 8 is used, a signal that changes in about 1.4% in 15 steps can be obtained.
[0043]
FIG. 21 is a diagram showing the configuration of the SSCG circuit according to the fourth embodiment of the present invention. The SSCG circuit of the fourth embodiment differs from the control circuit 41 of the third embodiment in that a control circuit 45 for generating a code as shown in FIG. 8 by a microcomputer or a DSP is provided. The third embodiment differs from the third embodiment in that an IDAC with a low-pass filter is used.
[0044]
If a computer system controlled by a program such as a microcomputer or a DSP is used, a code as shown in FIG. 8 can be easily generated. If the memory capacity of the computer system is sufficient and a large number of codes can be generated, it is also possible to select a code to be output according to a use situation. Furthermore, it is also possible to rewrite the program according to the use situation and to output a desired code.
[0045]
The IDAC in FIG. 22 is a circuit in which a low-pass filter (LPF) composed of a resistor R and a capacitor C is provided in a current output section of the IDAC in FIG. 17, and the output is further output by a current mirror circuit. . With this circuit, a change in output current caused by a change in the minimum bit / Dn of the output code is smoothed, and glitches (noise) can be reduced. When a current signal having a glitch is supplied to the ICO, the ICO outputs a high-frequency signal according to the glitch. Therefore, a problem occurs in that the PLL is out of the locked state and cannot be converged to the reference frequency. However, if the IDAC with LPF is used, such a problem does not occur.
[0046]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a spread spectrum clock generation circuit capable of performing good spread spectrum with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a conventional spread spectrum clock generation (SSCG) circuit.
FIG. 2 is a diagram showing a modulator output (spread spectrum modulation signal) in a conventional example.
FIG. 3 is a diagram showing another example of a modulator output (spread spectrum modulation signal) in a conventional example.
FIG. 4 is a diagram showing a principle configuration of the present invention.
FIG. 5 is a diagram illustrating the principle of the present invention and is a diagram illustrating an example of a spread spectrum modulation signal according to the present invention.
FIG. 6 is a diagram showing an improvement in spectrum when the present invention is applied.
FIG. 7 is a diagram showing a configuration of an SSCG according to the first embodiment of the present invention.
FIG. 8 is a diagram showing an output (code change) of the control circuit in the first embodiment.
FIG. 9 is a diagram illustrating a configuration of an SSCG according to a second embodiment of the present invention.
FIG. 10 is a diagram illustrating a circuit configuration of an analog modulation circuit according to a second embodiment.
FIG. 11 is a diagram illustrating an operation of the analog modulation circuit according to the second embodiment.
FIG. 12 is a diagram illustrating a configuration of an SSCG according to a third embodiment of the present invention.
FIG. 13 is a diagram illustrating a circuit configuration of a frequency phase comparator.
FIG. 14 is a diagram showing a circuit configuration of a charge pump circuit.
FIG. 15 is a diagram showing a circuit configuration of a voltage-current conversion (VI conversion) circuit.
FIG. 16 is a diagram showing a circuit configuration of a current control oscillation circuit (ICO).
FIG. 17 is a diagram showing a circuit configuration of a current digital-to-analog converter (IDAC).
FIG. 18 is a diagram illustrating a configuration of a control circuit according to a third embodiment.
FIG. 19 is a diagram illustrating generation of a frequency-divided clock in the control circuit according to the third embodiment.
FIG. 20 is a diagram illustrating an operation of an up / down counter in the control circuit according to the third embodiment.
FIG. 21 is a diagram illustrating a configuration of an SSCG according to a fourth embodiment of the present invention.
FIG. 22 is a diagram showing a circuit configuration of an IDAC with a low-pass filter.
[Explanation of symbols]
11 ... 1 / N frequency divider
12 ... frequency phase comparator
13 ... Charge pump circuit
14 ... Loop filter
16 ... Voltage addition circuit
17… VCO
18 1 / M frequency divider
21 ... Control circuit
22 ... Modulator (VDAC)

Claims (10)

A frequency-phase comparator for detecting a phase difference between the reference clock and the generated clock;
A charge pump that generates a charge / discharge signal according to the phase difference detected by the frequency phase comparator,
A loop filter that generates a difference signal according to the charging signal;
A spread spectrum modulation circuit that modulates the difference signal to generate a spread spectrum modulation signal,
A clock generator that generates a generated clock having a frequency corresponding to the spread spectrum modulated signal,
The spread-spectrum modulation circuit according to claim 1, wherein the spread-spectrum modulation circuit generates a spread-spectrum modulation signal whose cycle changes to a plurality of different cycles. 2. The spread spectrum clock generation circuit according to claim 1, wherein said spread spectrum modulation signal has a cycle that changes in order every cycle. 2. The spread spectrum clock generation circuit according to claim 1, wherein said clock generator is a voltage controlled oscillator. The spread spectrum modulation circuit according to claim 3, further comprising: an analog modulator that generates a spread spectrum analog voltage signal that changes at a plurality of different periods; and a voltage addition circuit that adds the spread spectrum analog voltage signal to the difference signal. A spread-spectrum clock generation circuit as described. The analog modulator includes a plurality of different capacitors, a plurality of switches for selecting one of the plurality of different capacitors, and a constant current for supplying a constant current to the selected capacitor or flowing the constant current from the selected capacitor. A source, a hysteresis comparator for detecting that the voltage of the selected capacitor has reached the first and second predetermined voltages, and detecting that the hysteresis comparator has reached the first and second predetermined voltages. 5. The spread spectrum clock generation circuit according to claim 4, further comprising: a switch switching control circuit that switches the selection of the plurality of switches. The spread spectrum modulation circuit includes a digital control circuit that generates an output code that changes at a plurality of different periods; a voltage digital-to-analog conversion circuit that generates a spread spectrum voltage signal corresponding to the output code; 4. The spread spectrum clock generation circuit according to claim 3, further comprising a voltage addition circuit for adding a spread voltage signal. A voltage-current conversion circuit that converts the difference signal, which is a voltage signal, into a difference current signal,
The clock generator is a current controlled oscillator,
The spread spectrum modulation circuit is provided between the voltage-current conversion circuit and the current control oscillator, and a digital control circuit that generates an output code that changes at a plurality of different periods, and the difference current signal corresponds to the output code. A spread-spectrum clock generating circuit according to claim 1, further comprising: a current variable circuit that generates a spread-spectrum current modulation signal by performing modulation. The current variable circuit includes a circuit that generates the difference current signal at a predetermined ratio, and a current digital-to-analog conversion circuit that converts the output code into a spread spectrum current signal of an analog signal and adds the signal to a difference current signal. Item 8. A spread spectrum clock generation circuit according to item 7. The digital control circuit includes a plurality of frequency dividers having different division ratios for dividing a clock, a switching controller for sequentially selecting outputs of the plurality of frequency dividers, and an up / down controller for counting the selected divided clock. 8. The spread spectrum clock generation circuit according to claim 6, further comprising a counter, and a counter that counts the frequency-divided clock and switches between an up operation and a down operation of the up / down counter at every predetermined count. 8. The spread spectrum clock generation circuit according to claim 6, wherein said digital control circuit is a computer system controlled by a program.

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