JP2004206661A - Memory control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control system having a means facilitating a backup process, reducing electric power consumption in a backup, and operating an SDRAM at high speed. <P>SOLUTION: This system has: a power monitoring means 4 detecting a backup state of the SDRAM 3; an SDRAM control means 10 changing over a CKE original signal by self-refresh requirement from an MPU 2 inside an SDRAM controller 1 having a function holding data on the SDRAM 3 by a backup power source in time of a failure of a main power source, issuing a self-refresh command, and starting issue of auto-refresh command by requirement from the MPU 2; a CKE setting flag 15 setting a level of a clock enable CKE signal of the SDRAM 3; and a CKE signal generation means 11 generating the CKE signal from the CKE original signal, an output BUP of the power monitoring means 4, and the CKE setting flag 15. Release of a self-refresh mode can be executed in arbitrary timing, and a rule of a time from the release of the self-refresh mode to the auto-refresh start is satisfied. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory control system having a backup control function for retaining data in a memory with a backup power supply even when a main power supply fails, and particularly to a memory control system utilizing a self-refresh function of a synchronous DRAM (SDRAM). The present invention relates to a memory control system for implementing a backup.
[0002]
[Prior art]
2. Description of the Related Art Memory backup in which data in a memory is retained by a backup power supply such as a battery even when a main power failure occurs has been applied to various systems. In particular, when the amount of data to be backed up is relatively large or when it is desired to reduce the system initialization time after turning on the power, the synchronous SDRAM (SDRAM) as the main memory is often backed up.
[0003]
In the SDRAM, in order to store data in a capacitor element, it is necessary not only to supply power from a backup power supply but also to refresh the stored contents. Recent SDRAMs have a self-refresh function that does not require an external refresh command input. This self-refresh function is also supported in a double data rate SDRAM (DDR-SDRAM) for further accelerating memory access. Therefore, as a backup method for the SDRAM, a backup utilizing a self-refresh function is widely used (for example, see Patent Document 1).
[0004]
This conventional example includes an SDRAM having a self-refresh function, control means having a built-in memory controller, and an external circuit for switching the SDRAM to a self-refresh mode in accordance with monitoring results of a main power supply and a backup power supply. . The external circuit has a built-in register for issuing a self-refresh command.
[0005]
If the main power supply fails, the control means sets this register. Thereafter, when the memory controller issues a refresh command to the SDRAM, the external circuit switches the clock enable CKE signal to Low and switches the SDRAM to the self-refresh mode at the same time as issuing the command. Thereafter, the backup power supply supplies power only to the SDRAM and the external circuit, and stops supplying power to the control means.
[0006]
The main power supply immediately restarts the power supply to the control means when the power returns (return to service). As a result, the external circuit sets the CKE signal to High, and releases the SDRAM from the self refresh mode.
[0007]
[Patent Document 1]
JP 2001-202165 A (FIG. 1 on page 2 of the specification)
[0008]
[Problems to be solved by the invention]
In this conventional example, when the main power is restored, the power supply to the control means is restarted, the CKE signal is set to High, and the SDRAM is released from the self-refresh mode.
[0009]
However, until the power-on reset of the control means is released and the memory controller is initialized, the subsequent auto refresh is not executed.
[0010]
According to the SDRAM standard, the auto-refresh must be started within about 7.8 μsec or about 15.6 μsec after being released from the self-refresh mode. In the above-mentioned conventional example, very strict requirements are imposed on the initialization time of the control means.
[0011]
Further, the power supply by the backup power supply is limited to the SDRAM and the external circuit to reduce the power consumption. However, the scale of an external circuit realized by an FPGA or the like is large, and it has been difficult to further reduce power consumption.
[0012]
Further, coordination between the control means for issuing the self-refresh command and the external circuit is required, and the addition of the external circuit increases the load capacity of the SDRAM interface signal, thereby limiting the high-speed operation of the SDRAM.
[0013]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory control system that facilitates backup processing, reduces power consumption at the time of backup, and includes means for operating an SDRAM at high speed.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller having a built-in SDRAM control means. The memory controller switches a clock enable CKE original signal in response to a self-refresh request from the processor MPU, issues a self-refresh command, and issues an auto-refresh start request from the processor MPU. SDRAM control means for starting issuance, and cleared by power-on reset of the memory controller, after power-on reset is released, and before auto-refresh start request by processor MPU A CKE set flag to be set; and a CKE signal generating means for generating a clock enable CKE signal based on the CKE original signal, the output of the power supply monitoring means, and the CKE set flag. And a memory control system powered by a backup power supply.
[0015]
According to the present invention, in a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller having a built-in SDRAM control means, a power supply monitoring means for detecting whether or not the SDRAM is in a backup state is provided. A reset means for outputting a reset signal which is at a low level when the power supply voltage rises or falls and is at a high level when the power supply is stable, and a logical product of a clock enable CKE signal from the memory controller and a reset signal from the reset means. And an AND gate for outputting to the CKE terminal of the SDRAM. The memory controller switches the clock enable CKE original signal in response to a self-refresh request from the processor MPU and issues a self-refresh command. An SDRAM control means for starting issuance of an auto-refresh command at a predetermined interval in response to an auto-refresh start request from the memory MPU; and a processor MPU which is cleared by a power-on reset of the memory controller and released by the processor MPU before the auto-refresh start request. A CKE set flag to be set; and a CKE signal generating means for generating a clock enable CKE signal based on the CKE original signal, the output of the power supply monitoring means, and the CKE set flag. Only the SDRAM, the power supply monitoring means, and the AND gate are provided. Proposes a memory control system powered by a main power supply and a backup power supply.
[0016]
The CKE signal generating means sets the CKE signal to Low when the CKE original signal is Low, and sets the CKE signal to High when the CKE original signal is High and the power supply monitoring means indicates non-backup. When the signal is High and the power supply monitoring means indicates backup, the CKE signal is set to Low when the CKE set flag is cleared, and the CKE signal is set to High when the CKE set flag is set.
[0017]
An INITSET register for setting various command intervals and address bit widths of the SDRAM, and a REF register for setting an auto-refresh interval of the SDRAM. When the power is restored, the MPU operates in the order of the CKE set flag, the INITSET register, and the REF register. Can be set.
[0018]
The memory controller has a SELF register for issuing a self-refresh command. When the SELF register is switched by writing from the MPU, the SDRAM control unit issues an all-bank precharge command after completing the command currently being executed. It is also possible to issue the SELF command at a prescribed interval with respect to the SDRAM, switch the CKE original signal one clock cycle before the SELF command issuance, switch the CKE signal one clock cycle after the SELF command is issued, and put the SDRAM 3 in the self-refresh state. It is possible.
[0019]
The power supply monitoring means is set by any one of writing by the processor MPU, notification of completion of SDRAM initialization from the memory controller, and notification of self-refresh transition, and is cleared by a voltage drop of the backup power supply at the time of main power failure and writing from the processor MPU. Is done.
[0020]
In a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller having a built-in SDRAM control means, the present invention further comprises a power supply monitoring means for detecting whether or not the SDRAM is in a backup state. SDRAM control in which a memory controller switches a clock enable CKE original signal in response to a self-refresh request from a processor MPU, issues a self-refresh command, and starts issuing an auto-refresh command at a predetermined interval in response to an auto-refresh start request from the processor MPU A backup state SBP flag for setting an output signal to active high when an initialization completion signal INIT becomes high after completion of initialization of the SDRAM; A clock enable CKE signal is generated based on the CKE set flag which is cleared by the power-on reset of the CPU after the power-on reset is released and before the auto-refresh start request is made by the processor MPU, the CKE original signal, the SBP flag and the CKE set flag. And a CKE signal generating unit that supplies power from the main power supply and the backup power supply only to the SDRAM, the power supply monitoring means, and the SBP flag.
[0021]
In this memory control system, the backup state SBP flag is set by one of writing by the processor MPU, notification of completion of SDRAM initialization from the SDRAM control means, and notification of self-refresh transition, and the voltage of the backup power supply at the time of main power failure. Lowered, cleared by writing from the processor MPU.
[0022]
In a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller having a built-in SDRAM control means, the present invention further comprises a power supply monitoring means for detecting whether or not the SDRAM is in a backup state. SDRAM control means for switching a clock enable CKE original signal in response to a self-refresh request from the processor MPU, issuing a self-refresh command, and starting SDRAM initialization in response to an SDRAM initialization request from the processor MPU; A CKE set flag that is cleared by a power-on reset of the memory controller and is set by the processor MPU before the start of SDRAM initialization after the power-on reset is released, a CKE original signal, A CKE signal generating means for generating a clock enable CKE signal based on an output of the monitoring means and a CKE set flag; an SDRAM initialization completion signal for notifying the power supply monitoring means of completion of SDRAM initialization by the SDRAM control means; , An SDRAM self-refresh transition completion signal for notifying the power supply monitoring means of completion of the SDRAM self-refresh transition by the SDRAM control means, and only the SDRAM and the power supply monitoring means are supplied with power from the main power supply and the backup power supply. A memory control system is proposed.
[0023]
The power supply monitoring means determines that the SDRAM is in the backup state when detecting the completion of the SDRAM initialization by the SDRAM initialization completion signal and detecting the completion of the SDRAM self-refresh transition by the SDRAM self-refresh transition completion signal.
[0024]
In a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller having a built-in SDRAM control means, the present invention further comprises a power supply monitoring means for detecting whether or not the SDRAM is in a backup state. SDRAM control means for switching a clock enable CKE original signal in response to a self-refresh request from the processor MPU, issuing a self-refresh command, and starting SDRAM initialization in response to an SDRAM initialization request from the processor MPU; A CKE set flag that is cleared by a power-on reset of the memory controller and is set by the processor MPU before the start of SDRAM initialization after the power-on reset is released, a CKE original signal, CKE signal generation means for generating a clock enable CKE signal based on the output of the monitoring means and the CKE set flag, an SDRAM initialization completion flag indicating that the initialization of the SDRAM has been completed, and the self refresh transition of the SDRAM has been completed A memory in which the processor MPU has at least two digital output ports A and B, and only the SDRAM and the power supply monitoring means are supplied with power from the main power supply and the backup power supply. A control system is proposed.
[0025]
After requesting the memory controller to initialize the SDRAM, the processor MPU detects the completion of the initialization of the SDRAM based on the SDRAM initialization completion flag, and sends the signal to the power supply monitoring unit through the one digital output port A. After notifying the completion of the initialization of the SDRAM, the processor MPU detects the completion of the self-refresh transition of the SDRAM by using the SDRAM self-refresh transition completion flag after requesting the memory controller for the self-refresh transition of the SDRAM. The power supply monitoring unit is notified of the completion of the self-refresh transition of the SDRAM via one digital output port B.
[0026]
The power supply monitoring means determines that the SDRAM is in the backup state when the digital output port A detects the completion of the SDRAM initialization and the digital output port B detects the completion of the SDRAM self-refresh transition.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of a memory control system according to the present invention will be described with reference to FIGS.
[0028]
Embodiment 1
FIG. 1 is a block diagram showing the system configuration of Embodiment 1 of the memory control system according to the present invention. The memory control system includes an SDRAM controller 1, a microprocessor MPU2, a synchronous DRAM (SDRAM) 3, a power supply monitoring unit 4, and a read only memory ROM5.
[0029]
The ROM 5 stores a system initialization program at the time of power recovery, a system termination program at the time of power failure, and the like.
[0030]
The power supply monitoring unit 4 monitors the state of a main power supply and a backup power supply (not shown). When the voltage of the main power supply drops below a predetermined value, the power supply monitoring means 4 determines that the power supply has stopped, sets the non-maskable interrupt NMI_ signal 40 to active low, and notifies the MPU 2 of the same. Further, when the power is restored, the power supply monitoring unit 4 detects that the SDRAM controller 1 has set the initialization completion signal INIT101 to Active High, and sets the DRAM backup BUP signal 41 to Active High.
Further, when the voltage of the backup power supply falls below a predetermined value when the main power supply is cut off and the SDRAM 3 is in the backup state by the backup power supply, the power supply monitoring means 4 determines that the backup has been lost, and the BUP signal 41 Is made inactive Low.
[0031]
The SDRAM controller 1 controls access from the MPU 2 to the SDRAM 3, initialization of the SDRAM 3, and refresh of the SDRAM 3. The SDRAM controller 1 includes an SDRAM control unit 10 for controlling the SDRAM 3, a CKE signal generating unit 11 for generating a clock enable CKE signal 110 for the SDRAM 3, an SDRAM setting register INITSET12, a refresh interval setting register REF13, and self-refresh control, which are internal registers. It has a register SELF14 and a clock enable set register CKESET15. The internal registers 12 to 15 can be written and read from the MPU 2 via the bus 20, respectively.
[0032]
The SDRAM control means 10 outputs an address of the SDRAM 3, a command signal 102, and a clock enable source CKE_S signal 100 in response to a memory access request of the MPU 2 sent via the bus 20 and a setting of the internal registers 12 to 15, and outputs the data 103. Send and receive.
[0033]
The INITSET 12 is a register for setting various command intervals and address bit widths of the SDRAM 3. When the MPU 2 sets INITSET 12, the SDRAM control means 10 initializes the SDRAM 3 with reference to the set value of INITSET 12. When the initialization of the SDRAM 3 is completed, the SDRAM control means 10 switches the INIT signal 101 from Low to High.
[0034]
REF13 is a register for setting an auto-refresh interval of the SDRAM 3. When the MPU 2 sets the REF 13, the SDRAM control means 10 periodically issues an auto-refresh command at set intervals.
[0035]
SELF 14 is a register that issues a self-refresh command. When the MPU 2 sets the SELF 14, the SDRAM control means 10 makes the CKE_S signal 100 inactive Low and issues a self-refresh command.
[0036]
The CKESET 15 is a register for selecting whether the CKE signal 110 of the SDRAM 3 is active or inactive. The CKE signal generation unit 11 determines High / Low of the CKE signal 110 based on the states of the CKESET 15, the BUP signal 41, and the CKE_S signal 100.
[0037]
In the present memory control system, the portion that supplies power from the backup power supply when the main power supply fails is limited to the SDRAM 3 and the power supply monitoring unit 4 surrounded by the dotted line 6. It is not necessary to supply power from the backup power supply to the SDRAM controller 1 having the backup control function.
[0038]
This memory control system may be realized in the form of a system LSI in which the ROM 5 and other modules (not shown) are incorporated in one chip in addition to the MPU 2 and the SDRAM controller 1. Alternatively, in addition to the MPU 2 and the SDRAM controller 1, a multi-chip module in which the ROM 5 and other modules (not shown) and the SDRAM 3 are further incorporated in one package may be realized.
[0039]
FIG. 2 is a table showing the levels of CKE output by the CKE signal generation means 11. That is, it is a chart showing the High / Low level of the CKE signal 110 output by the CKE signal generation means 11.
[0040]
As described above, the level of the CKE signal 110 is determined by the CKE_S signal 100, the BUP signal 41, and the CKESET15.
[0041]
When the CKE_S signal 100 is Low, the CKE signal 110 becomes Low regardless of the states of the BUP signal 41 and the CKESET 15. This case corresponds to a self-refresh command issuance and a subsequent self-refresh state.
[0042]
When the CKE_S signal 100 is High and the BUP signal 41 is Low, the CKE signal 110 becomes High regardless of the state of the CKESET 15. In this case, the SDRAM 3 is not in the backup state, that is, the BUP signal 41 remains Low, which corresponds to the state at the time of power restoration.
[0043]
When the CKE_S signal 100 is High and the BUP signal 41 is High, the CKE signal 110 is Low if CKESET 15 is 0 in the initial state. In this case, the SDRAM 3 is in the backup state, that is, the BUP signal 41 is High, which corresponds to the state when the power is restored.
[0044]
On the other hand, if CKSET15 is 1, that is, if MPU2 is set, the CKE signal 110 becomes High. In this case, the SDRAM 3 is in the backup state, that is, the BUP signal 41 is High, which corresponds to the release of the self-refresh when the power is restored.
[0045]
FIG. 3 is a flowchart showing a basic processing procedure of the SDRAM initialization program executed by the MPU 2 when the power is restored.
[0046]
Regardless of whether or not the SDRAM 3 is in the backup state, that is, whether the BUP signal 41 is High or Low, the basic processing procedure of the SDRAM initialization program is the same.
[0047]
First, CKESET 15 is set (3010). If the SDRAM 3 is in the backup state and the BUP signal 41 is High, the CKE signal 110 changes from Low to High at this time, and the self refresh is released.
[0048]
Next, INITSET 12 is set (3020), and initialization of the SDRAM 3 is started.
[0049]
REF13 is set (3030) so that the auto-refresh is executed at a predetermined interval immediately after the initialization of the SDRAM 3 is completed.
[0050]
FIG. 4 is a time chart showing a procedure for issuing a SELF command executed by setting the self-refresh control register SELF14 during the execution of four burst writes.
[0051]
When the SELF 14 is switched to 1 at T6 by writing from the MPU 2, the SDRAM control means 10 executes the normal 4-burst write in this example, thereafter issues an all-bank precharge command (T 9), and is defined by the SDRAM 3. A SELF command is issued at intervals (T11).
[0052]
The SDRAM control means 10 switches the CKE_S signal 100 from High to Low one clock cycle before the SELF command. The CKE generation means 10 detects that the CKE_S signal 100 has become Low at T10, and switches the CKE signal 110 from High to Low at T11 one clock cycle later. As a result, SDRAM 3 enters a self-refresh state.
[0053]
FIG. 5 is a time chart showing the SDRAM initialization processing procedure after the power is restored and the reset is released when the SDRAM 3 is in the non-backup state.
[0054]
When the SDRAM 3 is in the non-backup state, the BUP signal 41 is Low before the power is turned on, and the CKE_S signal 100 becomes High when the power is turned on. Therefore, the CKE signal 110 becomes High immediately after the power is turned on. Therefore, if the system reset period after turning on the power is made longer than the idle period (several hundred microseconds) before initialization required by the SDRAM 3, the SDRAM 3 can be initialized.
[0055]
After the system reset is released, the MPU 2 executes the SDRAM initialization program shown in FIG. 3 at an arbitrary timing. First, CKESET15 is set (T5). Next, INITSET12 is set (T8). The SDRAM control means 10 starts SDRAM initialization. Initialization of the SDRAM 3 is firstly issued with a PALL command (T9), followed by issuance of a REF command defined in accordance with the SDRAM 3 (T11 and T17), and finally ended with issuance of a mode register set (MRS) command (T23). I do. When the initialization of the SDRAM 3 is completed, the SDRAM control means 10 switches the INIT signal 101 from Low to High (T25).
[0056]
Further, the SDRAM control means 10 issues a REF command at a predetermined interval immediately after the completion of the initialization by setting the REF 13 (T11) (T26).
[0057]
With the above processing procedure, the initialization and the auto-refresh of the SDRAM 3 are realized, and the backup becomes possible.
[0058]
When detecting that the INIT signal 101 has become High, the power supply monitoring unit 4 switches the BUP signal 41 from Low to High at an arbitrary timing.
[0059]
FIG. 6 is a time chart showing the SDRAM initialization processing procedure after the power is restored and the reset is released when the SDRAM 3 is in the backup state.
[0060]
When the SDRAM 3 is in the backup state, since the BUP signal 41 is High and the CKESET 15 is cleared to 0 before the power is turned on, even if the CKE_S signal 100 becomes High with the power on, the CKE signal 110 remains high. , The Low state is maintained immediately after the power is turned on. Therefore, the self-refresh of the backed up SDRAM 3 can be maintained until an arbitrary timing.
[0061]
After the system reset is released, the MPU 2 executes the SDRAM initialization program shown in FIG. 3 at an arbitrary timing. First, CKSET15 is set (T5), and the self-refresh of the backed up SDRAM 3 is released. Next, INITSET12 is set (T8), and the SDRAM control means 10 executes SDRAM initialization. Further, by setting REF13 (T11), a REF command is issued at a predetermined interval immediately after the initialization is completed (T26).
[0062]
Therefore, the period from the release of the self-refresh of the SDRAM 3 to the execution of the auto-refresh is within a range that sufficiently satisfies the definition of the SDRAM 3.
[0063]
Embodiment 2
FIG. 7 is a block diagram showing the system configuration of Embodiment 2 of the memory control system according to the present invention. The second embodiment has a system configuration in which a reset unit 7 and an AND gate 111 are added to the first embodiment. The memory control system includes an SDRAM controller 1, a microprocessor MPU2, a synchronous DRAM (SDRAM) 3, a power supply monitoring unit 4, a read only memory ROM 5, a reset unit 7, and an AND gate 111. I have.
[0064]
The reset means 7 outputs a reset signal 71 which is at a low level when the power supply voltage rises or falls and becomes a high level when the power supply is stable.
[0065]
The AND gate 111 calculates the logical product of the CKE signal 110 output from the CKE signal generation means 11 and the reset signal 71 output from the reset means 7, and outputs the result to the CKE terminal of the SDRAM 3. Power is supplied to the AND gate 111 from both the main power supply and the backup power supply.
[0066]
The ROM 5 stores a system initialization program at the time of power recovery, a system termination program at the time of power failure, and the like.
[0067]
The power supply monitoring unit 4 monitors the state of a main power supply and a backup power supply (not shown). When the voltage of the main power supply drops below a predetermined value, the power supply monitoring means 4 determines that the power supply has stopped, sets the non-maskable interrupt NMI_ signal 40 to active low, and notifies the MPU 2 of the same. Further, when the power is restored, the power supply monitoring unit 4 detects that the SDRAM controller 1 has set the initialization completion signal INIT101 to Active High, and sets the DRAM backup (BUP) signal 41 to Active High.
Further, when the voltage of the backup power supply falls below a predetermined value when the main power supply is cut off and the SDRAM 3 is in the backup state by the backup power supply, the power supply monitoring means 4 determines that the backup has been lost, and the BUP signal 41 Is made inactive Low.
[0068]
The SDRAM controller 1 controls access from the MPU 2 to the SDRAM 3, initialization of the SDRAM 3, and refresh of the SDRAM 3. The SDRAM controller 1 includes an SDRAM control unit 10 for controlling the SDRAM 3, a CKE signal generating unit 11 for generating a clock enable CKE signal 110 for the SDRAM 3, an SDRAM setting register INITSET12, a refresh interval setting register REF13, and self-refresh control, which are internal registers. It has a register SELF14 and a clock enable set register CKESET15. The internal registers 12 to 15 can be written and read from the MPU 2 via the bus 20, respectively.
[0069]
The SDRAM control means 10 outputs an address of the SDRAM 3, a command signal 102, and a clock enable source CKE_S signal 100 in response to a memory access request of the MPU 2 sent via the bus 20 and a setting of the internal registers 12 to 15, and outputs the data 103. Send and receive.
[0070]
The INITSET 12 is a register for setting various command intervals and address bit widths of the SDRAM 3. When the MPU 2 sets INITSET 12, the SDRAM control means 10 initializes the SDRAM 3 with reference to the set value of INITSET 12. When the initialization of the SDRAM 3 is completed, the SDRAM control means 10 switches the INIT signal 101 from Low to High.
[0071]
REF13 is a register for setting an auto-refresh interval of the SDRAM 3. When the MPU 2 sets the REF 13, the SDRAM control means 10 periodically issues an auto-refresh command at set intervals.
[0072]
SELF 14 is a register that issues a self-refresh command. When the MPU 2 sets the SELF 14, the SDRAM control means 10 makes the CKE_S signal 100 inactive Low and issues a self-refresh command.
[0073]
The CKESET 15 is a register for selecting whether the CKE signal 110 of the SDRAM 3 is active or inactive. The CKE signal generation unit 11 determines High / Low of the CKE signal 110 based on the states of the CKESET 15, the BUP signal 41, and the CKE_S signal 100.
[0074]
In the present memory control system, the part that supplies power from the backup power supply when the main power supply fails is limited to the SDRAM 3, the power supply monitoring means 4, and the AND gate 111 surrounded by the dotted line 6. It is not necessary to supply power from the backup power supply to the SDRAM controller 1 having the backup control function.
[0075]
This memory control system may be realized in the form of a system LSI in which the ROM 5, the reset means 7, and other modules (not shown) are incorporated in one chip in addition to the MPU 2 and the SDRAM controller 1. Alternatively, in addition to the MPU 2 and the SDRAM controller 1, a multi-chip module in which the ROM 5, the reset means 7, other modules (not shown), and the SDRAM 3 are further incorporated in one package may be realized.
[0076]
When the SDRAM controller 1 including the CKE signal generation means 11 is realized by a C-MOS LSI, there may be a case where it is desired to omit a dedicated means for stabilizing the CKE signal 110 when the power supply voltage rises or falls.
[0077]
Accordingly, in the second embodiment, the reset signal 71 from the reset means 7 which is at the low level when the power supply voltage rises or falls and becomes the high level when the power supply is stable is used. , The CKE of the SDRAM 3 is fixed at Low.
[0078]
The AND gate 111 calculates the logical product of the CKE signal 110 output from the CKE signal generation unit 11 and the reset signal 71 output from the reset unit 7, and outputs a signal 112 to the CKE terminal of the SDRAM 3.
[0079]
As a result, a stable backup function can be realized without providing a dedicated means for stabilizing the CKE signal 110 when the power supply voltage rises or falls.
[0080]
The basic processing procedure of the second embodiment is the same as that of the first embodiment, and a description thereof will not be repeated.
[0081]
Embodiment 3
FIG. 8 is a block diagram showing a system configuration of Embodiment 3 of the memory control system according to the present invention. The third embodiment has a system configuration in which a function of outputting a DRAM backup (BUP) signal 41 of the power supply monitoring unit 4 of the first embodiment is provided to a backup state flag SBP16 built in the SDRAM controller 1.
[0082]
The memory control system includes an SDRAM controller 1, a microprocessor MPU2, a synchronous DRAM (SDRAM) 3, a power supply monitoring unit 4, and a read only memory ROM5.
[0083]
The backup status flag SBP16 of the third embodiment is a flag that can be read and written from the MPU 2 via the bus 20. The SBP 16 is built in the SDRAM controller 1, but is electrically separated from other parts of the SDRAM controller 1, and is supplied with power from both a main power supply and a backup power supply.
[0084]
The ROM 5 stores a system initialization program at the time of power recovery, a system termination program at the time of power failure, and the like.
[0085]
The power supply monitoring unit 4 monitors the state of a main power supply and a backup power supply (not shown). When the voltage of the main power supply drops below a predetermined value, the power supply monitoring means 4 determines that the power supply has stopped, sets the non-maskable interrupt NMI_ signal 40 to active low, and notifies the MPU 2 of the same. Further, when the power is restored, the SDRAM controller 10 in the SDRAM controller 1 sets the initialization completion signal INIT101 to Active High after the initialization of the SDRAM 3 is completed, the backup status flag (SBP) 16 is set, and the output signal 160 is set. Active High.
[0086]
The SDRAM controller 1 controls access from the MPU 2 to the SDRAM 3, initialization of the SDRAM 3, and refresh of the SDRAM 3. The SDRAM controller 1 includes an SDRAM control unit 10 for controlling the SDRAM 3, a CKE signal generating unit 11 for generating a clock enable CKE signal 110 for the SDRAM 3, an SDRAM setting register INITSET12, a refresh interval setting register REF13, and self-refresh control, which are internal registers. It has a register SELF14 and a clock enable set register CKESET15. The internal registers 12 to 15 can be written and read from the MPU 2 via the bus 20, respectively.
[0087]
In response to the initialization completion signal INIT101, the SBP 16 outputs a backup signal 160 indicating that the SDRAM 3 is in the backup state, like the DRAM backup (BUP) signal 41 of the first embodiment. Since power is supplied to the SBP 16 from both the main power supply and the backup power supply, the state can be maintained even when the main power supply fails. Also, even if the SDRAM controller 1 is reset, the SBP 16 can be maintained without being cleared.
[0088]
The SBP 16 is set when the SDRAM control means 10 changes the INIT signal 101 from Low to High after the initialization of the SDRAM 3 is completed.
[0089]
The SDRAM control means 10 outputs an address of the SDRAM 3, a command signal 102, and a clock enable source CKE_S signal 100 in response to a memory access request of the MPU 2 sent via the bus 20 and a setting of the internal registers 12 to 15, and outputs the data 103. Send and receive.
[0090]
The INITSET 12 is a register for setting various command intervals and address bit widths of the SDRAM 3. When the MPU 2 sets INITSET 12, the SDRAM control means 10 initializes the SDRAM 3 with reference to the set value of INITSET 12. When the initialization of the SDRAM 3 is completed, the SDRAM control means 10 switches the INIT signal 101 from Low to High.
[0091]
REF13 is a register for setting an auto-refresh interval of the SDRAM 3. When the MPU 2 sets the REF 13, the SDRAM control means 10 periodically issues an auto-refresh command at set intervals.
[0092]
SELF 14 is a register that issues a self-refresh command. When the MPU 2 sets the SELF 14, the SDRAM control means 10 makes the CKE_S signal 100 inactive Low and issues a self-refresh command.
[0093]
The CKESET 15 is a register for selecting whether the CKE signal 110 of the SDRAM 3 is active or inactive. The CKE signal generation unit 11 determines High / Low of the CKE signal 110 based on the state of the output signal 160 of the CKESET 15, the SBP 16, and the CKE_S signal 100.
[0094]
In the present memory control system, the portion that supplies power from the backup power supply when the main power supply fails is limited to the SDRAM 3 and the power supply monitoring unit 4 surrounded by the dotted line 6. It is not necessary to supply power from the backup power supply to the SDRAM controller 1 having the backup control function.
[0095]
This memory control system may be realized in the form of a system LSI in which the ROM 5 and other modules (not shown) are incorporated in one chip in addition to the MPU 2 and the SDRAM controller 1. Alternatively, in addition to the MPU 2 and the SDRAM controller 1, a multi-chip module in which the ROM 5 and other modules (not shown) and the SDRAM 3 are further incorporated in one package may be realized.
[0096]
The basic processing procedure of the third embodiment is the same as that of the first and second embodiments, and a description thereof will be omitted.
[0097]
Embodiment 4
FIG. 9 is a block diagram showing the system configuration of Embodiment 4 of the memory control system according to the present invention. The fourth embodiment has a system configuration in which a SELFR signal 104 is added to the first embodiment. The memory control system includes an SDRAM controller 1, a microprocessor MPU2, a synchronous DRAM (SDRAM) 3, a power supply monitoring unit 4, and a read only memory ROM5.
[0098]
The SELFR signal 104 is a signal for notifying the power supply monitoring means 4 from the SDRAM control means 10 of the self-refresh transition of the SDRAM.
[0099]
The SDRAM control means 10 switches the SELFR signal 104 from inactive low to active high at the same time as or after issuing the self-refresh command.
[0100]
The ROM 5 stores a system initialization program at the time of power recovery, a system termination program at the time of power failure, and the like.
[0101]
The power supply monitoring unit 4 monitors the state of a main power supply and a backup power supply (not shown). When the voltage of the main power supply drops below a predetermined value, the power supply monitoring means 4 determines that the power supply has stopped, sets the non-maskable interrupt NMI_ signal 40 to active low, and notifies the MPU 2 of the same. When the MPU 2 detects that the NMI_ signal 40 has been switched to the active low state, the MPU 2 executes necessary processing before the power failure, finally sets the SELF 14 and puts the SDRAM 3 in a self-refresh state.
[0102]
Further, the power supply monitoring unit 4 detects that the initialization completion signal INIT signal 101 is active high and the SELFR signal 104 is switched to active high, and sets the DRAM backup (BUP) signal 41 to active high.
[0103]
Further, when the voltage of the backup power supply falls below a predetermined value when the main power supply is cut off and the SDRAM 3 is in the backup state by the backup power supply, the power supply monitoring means 4 determines that the backup has been lost, and the BUP signal 41 Is made inactive Low.
[0104]
The SDRAM controller 1 controls access from the MPU 2 to the SDRAM 3, initialization of the SDRAM 3, and refresh of the SDRAM 3. The SDRAM controller 1 includes an SDRAM control unit 10 for controlling the SDRAM 3, a CKE signal generating unit 11 for generating a clock enable CKE signal 110 for the SDRAM 3, an SDRAM setting register INITSET12, a refresh interval setting register REF13, and self-refresh control, which are internal registers. It has a register SELF14 and a clock enable set register CKESET15. The internal registers 12 to 15 can be written and read from the MPU 2 via the bus 20, respectively.
[0105]
The SDRAM control means 10 outputs an address of the SDRAM 3, a command signal 102, and a clock enable source CKE_S signal 100 in response to a memory access request of the MPU 2 sent via the bus 20 and a setting of the internal registers 12 to 15, and outputs the data 103. Send and receive.
[0106]
The INITSET 12 is a register for setting various command intervals and address bit widths of the SDRAM 3. When the MPU 2 sets INITSET 12, the SDRAM control means 10 initializes the SDRAM 3 with reference to the set value of INITSET 12.
[0107]
When the initialization of the SDRAM 3 is completed, the SDRAM control means 10 switches the INIT signal 101 from inactive low to active high.
[0108]
REF13 is a register for setting an auto-refresh interval of the SDRAM 3. When the MPU 2 sets the REF 13, the SDRAM control means 10 periodically issues an auto-refresh command at set intervals.
[0109]
SELF 14 is a register that issues a self-refresh command. When the MPU 2 sets the SELF 14, the SDRAM control means 10 changes the CKE_S signal 100 to the inactive Low, issues a self-refresh command, and switches the SELFR signal 104 from the inactive Low to the active High.
[0110]
The CKESET 15 is a register for selecting whether the CKE signal 110 of the SDRAM 3 is active or inactive. The CKE signal generation unit 11 determines High / Low of the CKE signal 110 based on the states of the CKESET 15, the BUP signal 41, and the CKE_S signal 100.
[0111]
In the present memory control system, the part that supplies power from the backup power supply when the main power supply fails is limited to the SDRAM 3 and the power supply monitoring unit 4 surrounded by the dotted line 6. It is not necessary to supply power from the backup power supply to the SDRAM controller 1 having the backup control function.
[0112]
This memory control system may be realized in the form of a system LSI in which the ROM 5, the SDRAM 3, and other modules (not shown) are incorporated in one chip in addition to the MPU 2 and the SDRAM controller 1. Alternatively, in addition to the MPU 2 and the SDRAM controller 1, a multi-chip module in which the ROM 5 and other modules (not shown) and the SDRAM 3 are further incorporated in one package may be realized.
[0113]
In the power supply monitoring means 4, the condition for judging whether or not the SDRAM 3 can be backed up is not only that the initialization of the SDRAM 3 has been completed but also that the self-refresh transition of the SDRAM 3 has been completed. Sometimes you want to add.
[0114]
Therefore, in the fourth embodiment, the SDRAM control unit 10 notifies the power supply monitoring unit 4 of the completion of the initialization of the SDRAM 3 by the INIT signal 101, and further notifies the self-refresh transition of the SDRAM 3 by the SELFR signal 104.
[0115]
Further, the power supply monitoring unit 4 detects that the INIT signal 101 is active high and the SELFR signal 104 is switched to active high, and changes the BUP signal 41 to active high.
[0116]
As a result, the BUP signal 41 becomes active high only when the SDRAM 3 is in the self refresh state, and a stable backup function can be realized.
[0117]
Note that the power supply monitoring unit 4 in the fourth embodiment may detect that the SELFR signal 104 has been switched to Active High, and change the BUP signal 41 to Active High, regardless of the state of the INIT signal 101. In this case, it is assumed that the SDRAM 3 has been initialized before entering the self-refresh state. This function makes the INIT signal 101 unnecessary.
[0118]
The basic processing procedure of the fourth embodiment is the same as that of the first embodiment, and a description thereof will not be repeated.
[0119]
Embodiment 5
FIG. 10 is a block diagram showing a system configuration of Embodiment 5 of the memory control system according to the present invention. The fifth embodiment has a system configuration in which an initialization completion flag register INITS16, a self-refresh transition completion flag register SELFS17, and digital output ports DOA201 and DOB202 are added to the first embodiment. The memory control system includes an SDRAM controller 1, a microprocessor MPU2, a synchronous DRAM (SDRAM) 3, a power supply monitoring unit 4, and a read only memory ROM5.
[0120]
The digital output ports DOA201 and DOB202 are signals that can be switched to High or Low by writing to a register of the MPU 2 (not shown). In the fifth embodiment, the MPU 2 notifies the power supply monitoring unit 4 of the completion of the initialization of the SDRAM 3 via the DOA 201, and the MPU 2 notifies the power supply monitoring unit 4 of the completion of the self-refresh transition of the SDRAM 3 via the DOB 202.
[0121]
The ROM 5 stores a system initialization program at the time of power recovery, a system termination program at the time of power failure, and the like.
[0122]
The power supply monitoring unit 4 monitors the state of a main power supply and a backup power supply (not shown). When the voltage of the main power supply falls below a predetermined value, the power supply monitoring means 4 determines that the power supply has failed, sets the non-maskable interrupt NMI_ signal 40 to Active Low, and notifies the MPU 2 of the same. When the MPU 2 detects that the NMI_ signal 40 has been switched to the active low state, the MPU 2 executes necessary processing before the power failure, finally sets the SELF 14 and puts the SDRAM 3 in a self-refresh state.
[0123]
Further, the power supply monitoring means 4 detects that the digital output port DOA 201 is active high and the digital output port DOB 202 is switched to active high, and sets the DRAM backup (BUP) signal 41 to active high.
[0124]
Further, when the voltage of the backup power supply falls below a predetermined value when the main power supply is cut off and the SDRAM 3 is in the backup state by the backup power supply, the power supply monitoring means 4 determines that the backup has been lost, and the BUP signal 41 Is made inactive Low.
[0125]
The SDRAM controller 1 controls access from the MPU 2 to the SDRAM 3, initialization of the SDRAM 3, and refresh of the SDRAM 3. The SDRAM controller 1 includes an SDRAM control unit 10 for controlling the SDRAM 3, a CKE signal generation unit 11 for generating a clock enable CKE signal 110 for the SDRAM 3, an SDRAM setting register INITSET12, a refresh interval setting register REF13, and self-refresh control, which are internal registers. It has a register SELF14, a clock enable set register CKESET15, an initialization completion flag INITS16, and a self-refresh transition completion flag SELFS17. The internal registers 12 to 17 can be written and read from the MPU 2 via the bus 20, respectively.
[0126]
The SDRAM control means 10 outputs an address of the SDRAM 3, a command signal 102, and a clock enable source CKE_S signal 100 in response to a memory access request of the MPU 2 sent via the bus 20 and a setting of the internal registers 12 to 15, and outputs the data 103. Send and receive.
[0127]
The INITSET 12 is a register for setting various command intervals and address bit widths of the SDRAM 3. When the MPU 2 sets INITSET 12, the SDRAM control means 10 initializes the SDRAM 3 with reference to the set value of INITSET 12.
[0128]
When the initialization of the SDRAM 3 is completed, the SDRAM control means 10 switches the INIT signal 101 from inactive low to active high.
[0129]
REF13 is a register for setting an auto-refresh interval of the SDRAM 3. When the MPU 2 sets the REF 13, the SDRAM control means 10 periodically issues an auto-refresh command at set intervals.
[0130]
SELF 14 is a register that issues a self-refresh command. When the MPU 2 sets the SELF 14, the SDRAM control means 10 changes the CKE_S signal 100 to the inactive Low, issues a self-refresh command, and switches the SELFR signal 104 from the inactive Low to the active High.
[0131]
The CKESET 15 is a register for selecting whether the CKE signal 110 of the SDRAM 3 is active or inactive. The CKE signal generation unit 11 determines High / Low of the CKE signal 110 based on the states of the CKESET 15, the BUP signal 41, and the CKE_S signal 100.
[0132]
The INITS 16 is a flag register indicating that the initialization of the SDRAM 3 executed by the setting of the INITSET 12 has been completed. The initial state of the INITS 16 is 0, and the SDRAM control means 10 switches the INITS 16 to 1 after the initialization of the SDRAM 3 is completed.
[0133]
The SELFS 17 is a flag register indicating that the self-refresh transition of the SDRAM 3 executed by the setting of the SELF 14 has been completed. The initial state of the SELFS 17 is 0, and the SDRAM control unit 10 switches the SELFS 17 to 1 after the self-refresh transition of the SDRAM 3 is completed.
[0134]
In the present memory control system, the part that supplies power from the backup power supply when the main power supply fails is limited to the SDRAM 3 and the power supply monitoring unit 4 surrounded by the dotted line 6. It is not necessary to supply power from the backup power supply to the SDRAM controller 1 having the backup control function.
[0135]
This memory control system may be realized in the form of a system LSI in which the ROM 5, the SDRAM 3, and other modules (not shown) are incorporated in one chip in addition to the MPU 2 and the SDRAM controller 1. Alternatively, in addition to the MPU 2 and the SDRAM controller 1, a multi-chip module in which the ROM 5 and other modules (not shown) and the SDRAM 3 are further incorporated in one package may be realized.
[0136]
In this memory control system, the completion of the initialization of the SDRAM 3 and the completion of the self-refresh transition of the SDRAM 3 are notified to the power supply monitoring means 4 by using the digital output port of the MPU 2. 20 may be used, or serial communication means or parallel communication means may be used instead of the digital output port.
[0137]
In the present memory control system, the completion of the initialization of the SDRAM 3 and the completion of the self-refresh transition of the SDRAM 3 are notified to the power supply monitoring means 4 by using the digital output port of the MPU 2, but the INIT signal 101 or the SELFR signal shown in the fourth embodiment is used. One of the completion of the initialization of the SDRAM 3 and the completion of the self-refresh transition of the SDRAM 3 may be notified to the power supply monitoring unit 4 by using 104.
[0138]
Note that the power supply monitoring unit 4 in the fifth embodiment may detect that the digital output port DOB 202 has been switched to Active High and change the BUP signal 41 to Active High regardless of the state of the digital output port DOA 201. In this case, it is assumed that the SDRAM 3 has been initialized before entering the self-refresh state. This function eliminates the need for the digital output port DOA201.
[0139]
FIG. 11 is a flowchart showing a basic processing procedure of the SDRAM initialization program executed by the MPU 2 when the power is restored.
[0140]
Regardless of whether the SDRAM 3 is in the backup state, that is, whether the BUP signal 41 is High or Low, the basic processing procedure of the SDRAM initialization program is the same.
[0141]
First, CKESET 15 is set (1110). If the SDRAM 3 is in the backup state and the BUP signal 41 is High, the CKE signal 110 changes from Low to High at this time, and the self refresh is released.
[0142]
Next, INITSET 12 is set (1120), and initialization of the SDRAM 3 is started.
[0143]
Next, the INITS 16 is periodically read (1130), and it is confirmed that 1 has been set in the INITS 16, that is, that the initialization of the SDRAM 3 has been completed, and the digital output port DOA 201 is switched from inactive low to active high (1130). 1140).
[0144]
Finally, the REF 13 is set (1150), and the auto-refresh of the SDRAM 3 is started. The setting of the REF 13 (1150) may be executed after the setting of the INITSET 12 (1120).
[0145]
FIG. 12 is a flowchart showing a basic processing procedure of an SDRAM self-refresh transition program executed by the MPU 2 before a power failure.
[0146]
When the power supply monitoring unit 4 detects a voltage drop of the main power supply, the power supply monitoring unit 4 sets the non-maskable interrupt MNI_ signal 40 to Active Low and notifies the MPU 2 of the signal. The MPU 2 determines that the main power supply is interrupted, and executes the SDRAM self-refresh transition program.
[0147]
First, the SELF 14 is set (1210), and the self-refresh transition of the SDRAM 3 is started.
[0148]
Next, the SELFS 17 is periodically read (1220), and 1 is set in the SELFS 17, that is, it is confirmed that the self-refresh transition of the SDRAM 3 has been completed, and the digital output port DOB 202 is switched from inactive low to active high. (1230).
[0149]
【The invention's effect】
According to the present invention, in the SDRAM controller having the backup control function of the SDRAM, the level of the CKE signal is determined from the original signal of the CKE signal, the signal BUP indicating the backup state, and the CKE set flag. In addition to the transition, the self-refresh mode can be released from the self-refresh mode at an arbitrary timing, so that the backup control that satisfies the regulation on the time from the release of the self-refresh mode to the start of the auto-refresh can be easily realized.
[0150]
Further, since it is not necessary to supply power from a backup power supply to an SDRAM controller having a backup control function, power consumption can be further reduced.
[0151]
Further, as a result of incorporating a circuit necessary for backup control, an external circuit is not required, and the SDRAM can be operated at high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a system configuration of a first embodiment of a memory control system according to the present invention;
FIG. 2 is a table showing CKE levels output by CKE signal generation means 11;
FIG. 3 is a flowchart showing a basic processing procedure of an SDRAM initialization program executed by the MPU 2 when the power is restored.
FIG. 4 is a time chart showing a process of issuing a SELF command executed by setting a self-refresh control register SELF14 during execution of 4-burst write.
FIG. 5 is a time chart showing an SDRAM initialization processing procedure after the power is restored and the reset is released when the SDRAM 3 is in the non-backup state.
FIG. 6 is a time chart showing an SDRAM initialization processing procedure after the power is restored and the reset is released when the SDRAM 3 is in a backup state.
FIG. 7 is a block diagram showing a system configuration of a second embodiment of the memory control system according to the present invention;
FIG. 8 is a block diagram showing a system configuration of a third embodiment of the memory control system according to the present invention;
FIG. 9 is a block diagram showing a system configuration of a memory control system according to a fourth embodiment of the present invention.
FIG. 10 is a block diagram showing a system configuration of a memory control system according to a fifth embodiment of the present invention.
FIG. 11 is a flowchart showing a basic processing procedure of an SDRAM initialization program executed by the MPU 2 when power is restored in the fifth embodiment of the memory control system according to the present invention.
FIG. 12 is a flowchart showing a basic processing procedure of an SDRAM self-refresh transition program executed by the MPU 2 before a power failure in Embodiment 5 of the memory control system according to the present invention.
[Explanation of symbols]
1 SDRAM controller
2 Microprocessor MPU
3 Synchronous DRAM (SDRAM)
4 Power supply monitoring means
5 Read only memory ROM
6 dotted line
7 Reset means
10 SDRAM control means
11 Clock enable CKE signal generating means
12 SDRAM setting register INITSET
13 Refresh interval setting register REF
14 Self-refresh control register SELF
15 Clock enable set register CKESET
16 Backup status flag SBP
111 AND gate

Claims (30)

In a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller incorporating SDRAM control means,
Power monitoring means for detecting whether the SDRAM is in a backup state,
An SDRAM in which the memory controller switches a clock enable CKE original signal in response to a self-refresh request from the processor MPU, issues a self-refresh command, and starts issuing an auto-refresh command at a predetermined interval in response to an auto-refresh start request from the processor MPU Control means, a CKE set flag that is cleared by a power-on reset of the memory controller and is set by the processor MPU after the power-on reset is released and before an auto-refresh start request, CKE signal generation means for generating a clock enable CKE signal based on the CKE set flag,
A memory control system wherein only the SDRAM and the power supply monitoring means are supplied with power from a main power supply and a backup power supply. The memory control system according to claim 1,
The CKE signal generating means sets the CKE signal to Low when the CKE original signal is Low, and sets the CKE signal to High when the CKE original signal is High and the power supply monitoring means indicates non-backup, When the CKE original signal is High and the power supply monitoring means indicates backup, the CKE signal is set to Low when the CKE set flag is cleared, and the CKE signal is set when the CKE set flag is set. Is set to High. The memory control system according to claim 1,
An INITSET register for setting various command intervals and address bit widths of the SDRAM; and a REF register for setting an auto-refresh interval of the SDRAM.
A memory control system wherein the MPU sets the CKE set flag, the INITSET register, and the REF register in this order when power is restored. The memory control system according to claim 1,
The memory controller includes a SELF register that issues a self-refresh command;
When the SELF register is switched by writing from the MPU, the SDRAM control means issues an all bank precharge command after completing the command currently being executed, and issues a SELF command at a specified interval with respect to the SDRAM. And a CKE signal is switched one clock cycle before the SELF command is issued, and a CKE signal is switched one clock cycle after the SELF command is issued, thereby setting the SDRAM 3 in a self-refresh state. The memory control system according to claim 1,
The power supply monitoring means is set by any one of writing by the processor MPU, notification of completion of SDRAM initialization from the memory controller, and notification of self-refresh transition, and a voltage drop of the backup power supply at the time of power failure of the main power supply. A memory control system characterized by being cleared by writing from a memory. In a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller incorporating SDRAM control means,
Power supply monitoring means for detecting whether or not the SDRAM is in a backup state, reset means for outputting a reset signal which is at a low level when the power supply voltage rises or falls and becomes a high level when the power supply is stable, AND gate for calculating the logical product of the clock enable CKE signal of the above and the reset signal from the reset means and outputting the result to the CKE terminal of the SDRAM;
An SDRAM in which the memory controller switches a clock enable CKE original signal in response to a self-refresh request from the processor MPU, issues a self-refresh command, and starts issuing an auto-refresh command at a predetermined interval in response to an auto-refresh start request from the processor MPU Control means, a CKE set flag that is cleared by a power-on reset of the memory controller and is set by the processor MPU after the power-on reset is released and before an auto-refresh start request, CKE signal generation means for generating a clock enable CKE signal based on the CKE set flag,
A memory control system wherein only the SDRAM, the power supply monitoring means, and the AND gate are supplied with power from a main power supply and a backup power supply. The memory control system according to claim 6,
The CKE signal generating means sets the CKE signal to Low when the CKE original signal is Low, and sets the CKE signal to High when the CKE original signal is High and the power supply monitoring means indicates non-backup, When the CKE original signal is High and the power supply monitoring means indicates backup, the CKE signal is set to Low when the CKE set flag is cleared, and the CKE signal is set when the CKE set flag is set. Is set to High. The memory control system according to claim 6,
An INITSET register for setting various command intervals and address bit widths of the SDRAM; and a REF register for setting an auto-refresh interval of the SDRAM.
A memory control system wherein the MPU sets the CKE set flag, the INITSET register, and the REF register in this order when power is restored. The memory control system according to claim 6,
The memory controller includes a SELF register that issues a self-refresh command;
When the SELF register is switched by writing from the MPU, the SDRAM control means issues an all bank precharge command after completing the command currently being executed, and issues a SELF command at a specified interval with respect to the SDRAM. And a CKE signal is switched one clock cycle before the SELF command is issued, and a CKE signal is switched one clock cycle after the SELF command is issued, thereby setting the SDRAM 3 in a self-refresh state. The memory control system according to claim 6,
The power supply monitoring means is set by any one of writing by the processor MPU, notification of completion of SDRAM initialization from the memory controller, and notification of self-refresh transition, and a voltage drop of the backup power supply at the time of power failure of the main power supply. A memory control system characterized by being cleared by writing from a memory. In a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller incorporating SDRAM control means,
Power monitoring means for detecting whether the SDRAM is in a backup state,
An SDRAM in which the memory controller switches a clock enable CKE original signal in response to a self-refresh request from the processor MPU, issues a self-refresh command, and starts issuing an auto-refresh command at a predetermined interval in response to an auto-refresh start request from the processor MPU Control means, a backup state SBP flag for setting an output signal to active high when an initialization completion signal INIT becomes high after completion of initialization of the SDRAM, and a processor which is cleared by a power-on reset of the memory controller and is released by a power-on reset. A CKE set flag set by the MPU before the auto-refresh start request, the CKE original signal, the SBP flag, and the CKE set flag; Based a CKE signal generating means for generating a clock enable CKE signal,
A memory control system, wherein only the SDRAM, the power supply monitoring means, and the SBP flag are supplied with power from a main power supply and a backup power supply. The memory control system according to claim 11,
The CKE signal generating means sets the CKE signal to Low when the CKE original signal is Low, and sets the CKE signal to High when the CKE original signal is High and the power supply monitoring means indicates non-backup, When the CKE original signal is High and the power supply monitoring means indicates backup, the CKE signal is set to Low when the CKE set flag is cleared, and the CKE signal is set when the CKE set flag is set. Is set to High. The memory control system according to claim 11,
An INITSET register for setting various command intervals and address bit widths of the SDRAM; and a REF register for setting an auto-refresh interval of the SDRAM.
A memory control system wherein the MPU sets the CKE set flag, the INITSET register, and the REF register in this order when power is restored. The memory control system according to claim 11,
The memory controller includes a SELF register that issues a self-refresh command;
When the SELF register is switched by writing from the MPU, the SDRAM control means issues an all bank precharge command after completing the command currently being executed, and issues a SELF command at a specified interval with respect to the SDRAM. And a CKE signal is switched one clock cycle before the SELF command is issued, and a CKE signal is switched one clock cycle after the SELF command is issued, thereby setting the SDRAM 3 in a self-refresh state. The memory control system according to claim 11,
The backup state SBP flag is set by one of writing by the processor MPU, notification of completion of SDRAM initialization from the SDRAM control means, and notification of self-refresh transition. A memory control system which is cleared by writing from a processor MPU. In a memory control system including a processor MPU, an SDRAM having a self-refresh function, and a memory controller incorporating SDRAM control means,
Power monitoring means for detecting whether or not the SDRAM is in a backup state and notifying the memory controller;
A memory control system, wherein the memory controller selects a clock invalidation period of the SDRAM at the time of system power-on based on a notification from the power supply monitoring unit. The memory control system according to claim 16,
When the memory controller detects that the SDRAM is not in the backup state, it enables the clock of the SDRAM after system power-on or after reset release, and when it detects that the SDRAM is in the backup state, A memory control system which invalidates the clock of the SDRAM even after system power-on, and validates the clock of the SDRAM when a request from the processor is detected. The memory control system according to claim 16,
An SDRAM control unit for issuing a command to the SDRAM and generating a CKE source signal which is a source of a clock enable CKE signal of the SDRAM; a CKE set flag set by the processor MPU; A memory control system comprising: a CKE signal generation unit that generates a clock enable CKE signal for the SDRAM based on a notification from a monitoring unit, the CKE original signal, and the CKE set flag. The memory control system according to claim 18,
The CKE signal generating means sets the CKE signal to Low when the CKE original signal is inactive, and sets the CKE signal to High when the CKE original signal is active and the power supply monitoring means indicates non-backup. When the CKE original signal is active and the power supply monitoring means indicates backup, the CKE signal is set to Low when the CKE set flag is cleared, and the CKE signal is set when the CKE set flag is set. A memory control system wherein a signal is set to High. The memory control system according to claim 18,
An initialization register for issuing a command necessary for initialization of the SDRAM,
A memory control system, wherein the MPU sets the CKE set flag and the initialization register in this order when power is restored. The memory control system according to claim 16,
The memory controller notifies the power supply monitoring unit of the completion of the SDRAM initialization when the initialization of the SDRAM is completed,
A memory control system, wherein, when the power supply monitoring unit detects the SDRAM initialization completion notification from the memory controller, the power supply monitoring unit notifies the memory controller that the SDRAM is in a backup state. The memory control system according to claim 16,
When the memory controller notifies the power supply monitoring unit of the completion of the SDRAM self-refresh transition when the self-refresh transition of the SDRAM is completed, and the power supply monitoring unit detects the SDRAM self-refresh transition completion notification from the memory controller, A memory control system for notifying the memory controller that the SDRAM is in a backup state. The memory control system according to claim 16,
The memory controller notifies the power supply monitoring means of the completion of the SDRAM initialization when the initialization of the SDRAM is completed, and notifies the power supply monitoring means of the completion of the SDRAM self-refresh transition to the power supply monitoring means when the self-refresh transition of the SDRAM is completed. ,
When the power supply monitoring means detects an SDRAM initialization completion notification from the memory controller and further detects an SDRAM self-refresh transition completion notification, the power supply monitoring means notifies the memory controller that the SDRAM is in a backup state. Memory control system. The memory control system according to claim 16,
An initialization register for issuing a command necessary for initialization of the SDRAM, and an SDRAM initialization completion flag set when the initialization of the SDRAM is completed,
When the processor MPU detects that the SDRAM initialization completion flag is set after setting the initialization register, the processor MPU notifies the power supply monitoring unit of the completion of SDRAM initialization,
A memory control system, wherein when the power supply monitoring unit detects the SDRAM initialization completion notification from the processor MPU, the power supply monitoring unit notifies the memory controller that the SDRAM is in a backup state. The memory control system according to claim 16,
A self-refresh transition register for issuing a command necessary for the self-refresh transition of the SDRAM; and an SDRAM self-refresh transition completion flag set when the self-refresh transition of the SDRAM is completed.
When the processor MPU detects that the SDRAM self-refresh transition completion flag is set after setting the self-refresh transition register, the processor MPU notifies the power supply monitoring unit of the completion of the SDRAM self-refresh transition,
A memory control system, wherein when the power supply monitoring means detects the SDRAM self-refresh transition completion notification from the processor MPU, it notifies the memory controller that the SDRAM is in a backup state. The memory control system according to claim 16,
An initialization register for issuing a command necessary for initializing the SDRAM, an SDRAM initialization completion flag set when the initialization of the SDRAM is completed, and a self-register for issuing a command necessary for self-refresh transition of the SDRAM. A refresh transition register, and an SDRAM self-refresh transition completion flag set when the self-refresh transition of the SDRAM is completed;
When the processor MPU detects that the SDRAM initialization completion flag is set after setting the initialization register, the processor MPU notifies the power supply monitoring unit of the completion of SDRAM initialization,
When the processor MPU detects that the SDRAM self-refresh transition completion flag is set after setting the self-refresh transition register, the processor MPU notifies the power supply monitoring unit of the completion of the SDRAM self-refresh transition,
When the power supply monitoring unit detects the SDRAM initialization completion notification from the processor MPU and further detects the SDRAM self-refresh transition completion notification, the power supply monitoring unit notifies the memory controller that the SDRAM is in a backup state. Memory control system. The memory control system according to claim 16,
A self-refresh transition register for issuing a command necessary for the self-refresh transition of the SDRAM; and an SDRAM self-refresh transition completion flag set when the self-refresh transition of the SDRAM is completed.
When the processor MPU detects that the SDRAM self-refresh transition completion flag is set after setting the self-refresh transition register, the processor MPU notifies the power supply monitoring unit of the completion of the SDRAM self-refresh transition,
The memory controller notifies the power supply monitoring unit of the completion of the SDRAM initialization when the initialization of the SDRAM is completed,
When the power supply monitoring unit detects the SDRAM initialization completion notification from the memory controller and further detects the SDRAM self-refresh transition completion notification from the processor MPU, the power monitoring unit notifies the memory controller that the SDRAM is in the backup state. A memory control system. The memory control system according to claim 16,
An initialization register for issuing a command necessary for initialization of the SDRAM, and an SDRAM initialization completion flag set when the initialization of the SDRAM is completed,
When the processor MPU detects that the SDRAM initialization completion flag is set after setting the initialization register, the processor MPU notifies the power supply monitoring unit of the completion of SDRAM initialization,
The memory controller notifies the power supply monitoring means of the completion of the SDRAM self-refresh transition when the self-refresh transition of the SDRAM is completed;
When the power supply monitoring unit detects the SDRAM initialization completion notification from the processor MPU and further detects the SDRAM self-refresh transition completion notification from the memory controller, the power monitoring unit notifies the memory controller that the SDRAM is in the backup state. A memory control system. The memory control system according to claim 16,
A memory control system, wherein the power supply monitoring means, when detecting a voltage drop of the backup power supply at the time of the main power failure, notifies the memory controller that the SDRAM is in a non-backup state. The memory control system according to claim 16,
A memory control system, wherein the power supply monitoring unit notifies the memory controller that the SDRAM is in a backup state or a non-backup state in response to a request from the MPU.

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