JP2004206138A - Apparatus and method for image processing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and a method for image processing that can display an image which is not inferior to a normal raster image even when the memory capacity of a memory incorporated display is reduced. <P>SOLUTION: The image processing apparatus when inputting a raster image 1 to a memory 2 performs multi-valued dither processing at an image processing part front stage 4 and processes a raster image outputted from the memory 2 reversely to the multi-valued dither processing at an image processing part rear stage 5. Consequently, a feeling of granularity and false colors can be suppressed and a display device of high picture quality can be obtained. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus and an image processing method, and more particularly, to an image processing apparatus and an image that improve image quality in image processing of a display having a memory for storing a raster image and improve transmission efficiency of a raster image from a computer to a display. Regarding the processing method.

  At present, as a method of transmitting an image from a computer to a display, a method of transmitting a raster image for each frame frequency is used. This method has a large amount of data transmission and is wasteful when a still image is displayed.

  As a method of reducing the amount of data transmission, a method of transmitting an image by compressing the image into a file format such as JPEG or GIF can be considered. However, performing a compression and decompression process for each frame requires an arithmetic processing unit that operates at high speed, which leads to an increase in cost.

  On the other hand, as a method of reducing the waste of transmission in displaying a still image, a method of mounting a frame memory which is a memory for storing a raster image built in the display side and interrupting data transmission when a still image is displayed is considered. Can be This is particularly effective in portable information devices and the like because power consumption can be reduced at the same time.

  For a display mounted on a portable information device, it is particularly important to reduce power consumption and chip area. In order to satisfy this demand, it is desirable that the image stored in the memory is displayed in the still image display, and that the capacity of the memory unit that occupies a large area in the chip area is small. As described above, the power consumption during data transmission is reduced by storing images in the memory, and the chip area is reduced by reducing the memory capacity.

  To reduce the memory capacity, a method of compressing image data can be considered. However, an image compression method such as the JPEG format or the GIF format requires an image processing unit for decompression, and the effects of reducing the chip area and power consumption are diminished.

  As another method, it is conceivable to reduce the number of bit planes of the raster image. Here, the number of bit planes is the number n of bits of data representing the gradation in a digital image quantized by the power of 2 n, and indicates the number n of bits. Methods for reducing the number of bit planes include a multi-valued dither method and a fixed threshold method, the details of which are disclosed in Non-Patent Document 1. Unlike the image compression methods such as the JPEG format and the GIF format, the multi-value dither method and the fixed threshold method do not need to expand a compressed image.

  FIG. 38 is a block diagram showing a schematic configuration of a conventional image processing apparatus. Referring to FIG. 38, as a bit plane compression example of a raster image using a conventional multi-valued dither method, a configuration is provided in which a raster image of 6 bits for each color of RGB is transmitted from a computer and performs a 6-bit display for each color. Will be described.

  First, the lower 2 bits of the raster image 1 of 6 bits for each color are sent to the comparator 12. The threshold generation unit 11 generates a dither matrix based on organized dither, and outputs a 2-bit value uniquely determined from pixels (XY coordinate values) of the input image to the comparator 12.

  The comparator 12 compares the lower 2 bits sent from the raster image 1 with the 2-bit value sent from the threshold generator 11, and when the value sent from the threshold generator 11 is larger, “ 1 is output to the selector 13 in other cases.

  The selector 13 outputs to the memory 2 a value obtained by subtracting 1 from the upper 4 bits of the raster image 1 as it is, based on the output value from the comparator 12. The 4-bit image of each color stored in the memory 2 is added by the bit adding unit 14 with the value of the higher 2 bits of the 4 bits as the lower bit of the input 4-bit value, and is converted into a 6-bit image by the image display unit 3. Output to

  With such a configuration, the number of bit planes is reduced by the multi-value dither method, and a 6-bit image of each color is displayed in a pseudo manner.

  On the other hand, Patent Document 1 discloses that a digital signal which is obtained by level-compressing a digitized input signal and which expands the level of the transmitted compressed signal, detects a maximum value, and adds a dither value according to the maximum value. A digital signal processing device (hereinafter, referred to as a first related art) including circuits for performing a level compression after performing a level expansion, and subtracting a dither value after performing a level expansion is disclosed.

With such a configuration, an output with less error is obtained in a digitized audio signal that is a one-dimensional signal.
Japanese Patent Publication No. 2-8493 Image Electronics Society of Japan, "New Edition Image Electronics Handbook", First Edition, Corona, March 31, 1993, pp. 41-51

However, in the conventional multi-valued dither method and the fixed threshold value method, there is a problem that, by reducing the number of bit planes, false contours, false colors, graininess, etc. are observed, and the image quality is reduced. Was.
As a display form on a display, there is a technique called superimposition. This is a technique in which different screens such as "characters" are superimposed and displayed on a certain display screen. In this case, since a plurality of screens (for example, images and characters) must be prepared as the input image, the data capacity of the input image becomes large, and the input image is stored in the memory or the bus width is limited. Transmission via a certain transmission path becomes difficult.
Further, in a display having a small maximum resolution of a display screen such as a mobile terminal, it is necessary to scroll an image when displaying a large image such as a map. This scroll display is a simple operation at first glance, but there is a problem in that the amount of rewriting of the display memory increases and the power consumption increases accordingly.

  When an image is displayed on a display device such as a display as shown in FIG. 39A, an image signal is input to each pixel along a line in the main scanning direction, and the image signal is input to the sub-scanning direction. The image signal is input to all the pixels by repeating a plurality of lines.

Here, a case is considered in which the first related art is applied to image display. In this example, the dither cycle is 4 bits.
As shown in (b), when the number of pixels in the main scanning direction of the display device is 4n + 1, the dithering appears in both the main scanning direction and the sub-scanning direction. small. This is the same when the number of pixels in the main scanning direction of the display device is 4n + 2 or 4n + 3. That is, when the number of pixels in the main scanning direction of the display device does not include the dither cycle as a factor, deterioration of image quality due to image compression / expansion is small.
However, when the number of pixels in the main scanning direction of the display device is 4n, in other words, when the number of pixels in the main scanning direction of the display device includes the dither cycle as a factor, as shown in FIG. , The dither periodicity appears, but the dither periodicity is not seen in the sub-scanning direction, and the image quality is greatly deteriorated due to the compression and expansion of the image.

In the case of dither processing on a raster image, the smaller the dither cycle is, the higher the frequency of minute noise is obtained, so that deterioration in image quality can be reduced. However, in general, the number of pixels in the main scanning direction of the display device is a number including “2” to “6” as factors (480, 720, 840, etc.). When applied, the state shown in FIG. 39C is reached, and the image quality is degraded as the image is compressed and expanded.
If the period of dither is increased so as not to be a factor of the number of pixels in the main scanning direction of the display device, high-frequency minute noise, which is the original purpose of dither processing, cannot be obtained. Image quality is degraded.

Further, if the first prior art is applied as it is, a maximum value detection circuit is provided on the compression side in order to specify which digit of the digital signal to be added with the dither value, and then the maximum value A signal indicating the number of the most significant digit bit must be transmitted to the receiving side together with the digital signal at any time. Further, when storing the compressed digital signal in a memory or the like, it is necessary to store a signal indicating the number of the maximum available digit bit together with the digital signal.
However, a configuration for performing such processing is not preferable as a configuration applied to an image processing apparatus such as a display because a circuit becomes complicated and power consumption and a chip area increase.

Further, the first prior art does not suggest any processing method using the maximum value and the minimum value of the digital signal. For this reason, in an image processing apparatus such as a display which frequently displays a maximum value of “white” (for example, a character output or a display of a geometric figure) or a minimum value of “black”, the image quality is high. Will be deteriorated. This is because graininess is more likely to be seen in “black” and “white” displays.
As described above, when the first related art is directly applied to the image processing, the image quality is deteriorated due to the compression and expansion of the image.

  Therefore, when the first related art is applied to image display, it is necessary to apply a dither matrix configuration suitable for a raster image which is a two-dimensional signal. Further, since the gradation value of the pixel is biased depending on the type (character display or natural image display) of the image, it is desirable to perform image processing more suitable for a raster image.

  Furthermore, in the image display of the display device, not all images are compressed. For example, in the case of displaying a moving image, the image is subjected to compression / expansion processing for each frame, which increases power consumption and the amount of calculation. Therefore, it is not desirable to compress / expand the image.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and performs image processing that is comparable to that of a normal raster image even when the memory capacity is reduced. It is another object of the present invention to provide an image processing apparatus and an image processing method capable of reducing transmission capacity while suppressing image quality deterioration. It is a further object of the present invention to provide an image processing apparatus and an image processing method which can use such image processing to transmit an image and efficiently use a memory to reduce power consumption and the amount of calculation.

In order to achieve the above object, the present invention provides, as a first aspect, a case where an input raster image cannot be stored in a storage means in the state of the original image as it is or cannot be displayed on a display device. It is intended to provide an image processing apparatus that performs compression / expansion.
A fourth aspect of the present invention is an image processing apparatus that stores input image data in a storage unit and causes a predetermined display device to display an image based on the image data read from the storage unit. First image processing means for compressing a first raster image as an image to generate a compressed raster image, means for accumulating the compressed raster image in the accumulating means, and reading the compressed raster image accumulated in the accumulating means. A second image processing unit that expands the image to generate a second raster image; and a unit that outputs the second raster image to a display device. The data amount of the first raster image is stored in the storage capacity of the storage unit. An image processing apparatus characterized in that a compressed raster image is generated when the size is larger than the threshold value. In the first aspect of the present invention, the first and second image processing means perform image processing so that the maximum value and the minimum value of the element components of the first raster image and the second raster image match. It is preferred to do so.
In any configuration of the first aspect of the present invention, when the data amount of the first raster image is equal to or less than the storage capacity of the storage unit, the first raster image is stored in the storage unit without compression. It is preferable that the apparatus further comprises means for selecting whether to perform the processing by the first image processing means and store the processed data in the storage means. A means for outputting the first raster image to the display device without passing through the first image processing means, the storage means, and the second image processing means; and a means for outputting the first raster image and the second raster image to the display device. Preferably, the image processing apparatus further includes a unit for selecting which one of the images is to be output. In addition to this, when the first raster image is output to the display device, the first image processing unit, the storage unit, and the It is more preferable to further include means for stopping the operation of the second image processing means. Further, it is preferable that the second image processing means is formed on the same substrate as the drive circuit of the display device. Further, it is preferable that the first image processing means is formed on the same substrate as the drive circuit of the display device.

According to the first aspect of the present invention, when the input raster image cannot be stored in the storage means in the state of the original image as it is or cannot be displayed on the display device, the original image is compressed and decompressed. Is performed, the input original image can be stored in the storage unit regardless of the data amount and size. That is, the second raster image can be generated and output to the display device regardless of the data amount or the image size of the original image.
For example, the image processing apparatus according to this aspect performs a 1-bit compression / expansion process on a natural image, and applies the obtained 1-bit capacity to character information, so that the memory capacity is not increased and a super It is possible to perform an imposition process.
Also, when displaying an image larger than the maximum resolution of a display device such as a map, the image can be saved with a small memory capacity by compressing / expanding the number of bit planes, and the image is reacquired from outside. Scroll display can be performed on the display device without the need. As a result, it is possible to reduce power consumption associated with image display.
Note that in the case where the image processing device of this embodiment is applied to a display device in which a driver circuit is formed over a substrate (for example, a glass substrate), the image processing device can be formed over the substrate by the same process. Therefore, if the image processing device of this aspect is applied to a display device, it is possible to realize a reduction in area due to memory saving and low power consumption.

In order to achieve the above object, the present invention provides, as a second aspect, the case where the input raster image cannot be stored in the storage means as it is in the original image or cannot be displayed on the display device. An image processing method for compressing / expanding an image is provided.
An eleventh aspect of the present invention is an image processing method that stores input image data in a storage unit and causes a predetermined display device to display an image based on the image data read from the storage unit. A first image processing step of compressing the first raster image to generate a compressed raster image when the data amount of the first raster image as the image is larger than the storage capacity of the storage unit; Storing the image in the storage means, reading and expanding the compressed raster image stored in the storage means, generating a second raster image, and transmitting the second raster image to the display device. Outputting the image.
In the second aspect of the present invention, before the first image processing step, if the data amount of the first raster image is equal to or less than the storage capacity of the storage means, the first raster image is stored without compression. A step of selecting whether the first raster image is to be stored in the storage means or to compress the first raster image in the storage means. It is preferable to execute the image processing in the first image processing step also for the first raster image having the storage capacity equal to or less than.
In any of the image processing methods according to the second aspect of the present invention, an output switching step of selecting which of the first raster image and the second raster image to output to the display device is further provided at the forefront. Preferably, in addition to this, after the output switching step, when the first raster image is selected in the output switching step, the image by the first image processing step and the second image processing step More preferably, the method further includes a processing stop step of stopping the processing.

According to the second aspect of the present invention, when the input raster image cannot be stored in the storage means as it is in the original image or cannot be displayed on the display device, the original image is compressed and decompressed. Is performed, the input original image can be stored in the storage unit regardless of the data amount and size. That is, the apparatus that executes the image processing method of the present embodiment can generate the second raster image regardless of the data amount and the image size of the original image and output the second raster image to the display device.
For example, even when displaying an image larger than the maximum resolution of a display device such as a map, the image can be saved with a small memory capacity by compressing / expanding the number of bit planes, and the image is reacquired from outside. Scroll display can be performed on the display device without the need. As a result, it is possible to reduce power consumption associated with image display. Further, an image in which the data amount of a map or the like is larger than the storage capacity of the storage means can be compressed and stored in the storage means, and can be displayed on the display device without reacquiring the image from outside.

  According to the present invention, compression / expansion of a bitmap image to be sent to a display device can be performed with a small number of logics, and the memory capacity and the transmission capacity can be reduced.

  Further, according to the present invention, since an error in the bit-added image is smaller than that in the original image in comparison with the multi-value dither method, it is possible to suppress graininess and false color appearing when the error is large, High quality display is obtained.

  Further, according to the present invention, for example, a compressed image can be selected at the time of displaying a still image, and can be displayed without performing image processing at the time of displaying a moving image. Therefore, when a moving image is displayed, the moving image can be displayed without the intervention of the storage unit (for example, a memory). Therefore, it is possible to stop the operation of the storage unit and reduce power consumption.

Further, according to the present invention, in the superimposed display, compression / expansion processing for one bit is performed on a natural image, and the obtained one-bit capacity is applied to character information, thereby increasing the memory capacity. , It is possible to perform the superimposing process without inducing.
Also, when displaying an image larger than the maximum resolution of a display device such as a map, the image can be saved with a small memory capacity by compressing / expanding the number of bit planes, and the image is reacquired from outside. Scroll display can be performed on the display device without the need. As a result, it is possible to reduce power consumption associated with image display.

  Further, according to the present invention, it is possible to obtain an image transmission device and an image processing method that achieve an efficient transmission capacity. For example, when it is desired to transmit raster image data of 6 bits for each of RGB (18 bits in total) using a transmission path having a bus width of only 16 bits, the data is parallelized by performing bit plane compression on the raster image. It becomes possible to transmit.

Further, according to the present invention, it is possible to obtain an image receiving apparatus that achieves efficient transmission capacity in a transmission path for receiving an image.
In other words, by receiving an image with the number of bit planes reduced compared to the original image, it is possible to reduce the number of transmission paths for receiving images and to increase the transmission efficiency It becomes. Further, by increasing the number of bit planes of the received image, it is possible to obtain an image having the same image quality as the original image.

  Further, according to the present invention, in a display device in which a drive circuit is formed over a substrate (for example, a glass substrate), an image processing device can be formed over the substrate by using the same process. Therefore, when the present invention is applied to a display device, it is possible to achieve a reduction in area due to memory saving and low power consumption.

  The principle of the present invention is to increase the number of bit planes by performing processing opposite to the noise addition processing on an image in which the number of bit planes is reduced by performing noise addition processing called dither processing. This minimizes the error component caused by the above. By doing so, the graininess can be reduced, and false colors can be suppressed.

For example, consider a case where a 6-bit signal is converted into a 4-bit signal by multi-value dither processing, and the 4-bit signal is expanded into a 6-bit signal. Here, if the dither matrix in the multi-level dither processing is based on the systematic dither, which is 6-4 = 2 bits of dither, any one of the dither components of 00, 01, 10, and 11 in binary is input signal. Is added to Assuming that the input 6-bit signal is X and the dither component is D, the multilevel dither processing can be represented by the following equation.
Y = int ((X−D) / 4)

  Here, int (X) indicates an integer component of X. Division by 4 corresponds to conversion from 6 bits to 4 bits. For example, if the input signal is 37 (100101 in binary), the multi-level dither processing performs 9 (1001) when the dither component is 00, 9 (1001) when the dither component is 01, and 8 (1000) when the dither component is 10. ), 11 is converted to 8 (1000), and so on.

Next, the 4-bit signal is expanded into a 6-bit signal. The conversion formula at that time is shown below.
Z = 4 × Y + D + 2

  Here, excluding the constant 2, Y = (Z−D) / 4, which indicates that the process is the reverse of the multi-value dither process. When the above-mentioned input signal is converted into a signal of 37 (100101 in binary) based on the above conversion formula, 38 (100110) when the dither component is 00, 39 (100111) when the dither component is 01, and 36 when the dither component is 10 In the case of (100100) and 11, it becomes 37 (100101). The constant 2 in the conversion formula is an offset value added so that the average value of the converted signal takes a value closest to the input signal.

  When this conversion result is compared with the conventional multi-bit dither 6-bit conversion, according to the conventional conversion, the upper 2 bit components of the 4 bits are added as the lower 2 bits. 100110), 01 is 38 (100110), 10 is 34 (100010), 11 is 34 (100010), and so on.

  As is clear from this, according to the conversion processing of the present invention, it is understood that the overall value takes a value close to the input signal. This indicates that the graininess can be reduced and the false color can be suppressed in the present invention.

  Here, the raster image converted from the 6-bit signal to the 4-bit signal is expanded to 6 bits, but is not limited to this, and may be expanded to 5 bits. In this case, arithmetic processing is performed using the upper bits of the dither component. Specifically, an operation of Z = 2 × Y + int (D / 2) +1 is performed. With such a configuration, it is possible to reduce the graininess and the false color even for a raster image expanded to 5 bits.

Further, as processing by multi-valued dither, here, the dither value is subtracted, quantization is performed, and then the dither value is added. By adding the dither value, the error near the maximum gray scale "white" is minimized. This is because, as shown in FIG. 6 later, as a result of addition of the dither value, all grayscale outputs larger than the grayscale for displaying “white” (grayscale value 63 in FIG. 6) display “white”. Since the gradation is rounded, the error near “white” is minimized in all the gradations. With such a configuration, it is possible to minimize the error of “white” display, which is the maximum gradation, to eliminate the granularity peculiar to dither, and to suppress the gradation loss near the “white” display.
In geometrical figures such as characters and maps, all signal components have the maximum gradation, "white", and one of the signal components has the maximum gradation, "red", "blue", "green", "yellow". Are often used. Therefore, the present invention improves the display quality of such an image. This is a novel effect / action unique to the present invention, which cannot be obtained by the first prior art.

  According to the present invention, image quality can be improved by performing a very simple process on a par with a multi-valued dither for each pixel.

The signal configuration of the raster image in the present invention includes, in addition to the above-described RGB signals, a signal composed of a luminance signal such as YCbCr and a chrominance signal, a luminance signal such as an HSV or LCH signal, a chroma signal, and a hue signal. Various signals, such as the generated signal, can be applied.
Here, multi-value dither processing has been described as an example of image processing, but the present invention is not limited to this, and any image processing capable of achieving the above-described operation can be used. In particular, an image processing method in which image processing is performed in reverse when the number of bit planes decreases and increases is effective.

  Hereinafter, an image processing apparatus, an image transmission apparatus, and an image processing method according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 to 37 show preferred embodiments of the image processing apparatus, the image transmission apparatus, and the image processing method according to the present invention.

<First embodiment>
FIG. 1 is a flowchart showing the flow of processing of the image processing method according to the first embodiment of the present invention.

An image processing method according to the present embodiment will be described. When a raster image is input to the image processing apparatus (step S1), a process for reducing the number of bit planes is performed on the input raster image (step S2). The raster image with the reduced number of bit planes is input to a memory and accumulated (step S3). Thereafter, the raster image stored in the memory is read out, and a process for increasing the number of bit planes is performed on the raster image (step S4).
At this time, it is desirable that the process of decreasing the number of bit planes and the process of increasing the number of bit planes can be performed with a small number of logics. Furthermore, it is desirable that the number of logics in image processing be sufficiently smaller than the number of logics in the memory (such as the number of transistors and the number of cells) that can be reduced by this processing. Normally, the number of required logics in the process of reducing and increasing the number of bit planes is small, so that the number of bit planes can be suitably reduced or increased. For example, as a process for reducing the number of bit planes, there is "bit dropping", so-called "predetermined bit truncation", but in that case, there is no need to perform arithmetic processing.

  With the above image processing method, it is possible to reduce the memory capacity in the image display processing. Furthermore, since the compression ratio ((data capacity before compression−data capacity after compression) / data capacity before compression) becomes constant when the number of bit planes decreases or increases, the image data of the original image is compressed and stored in the memory. And an image processing apparatus (display system) that expands the stored image data and displays the image data.

Further, in the present embodiment, the case where the process of storing the image data of the raster image in the memory during the process of decreasing and increasing the number of bit planes has been described as an example, but is not limited thereto. Instead, instead of storing the image data of the raster image in the memory, a process of transmitting the image data of the raster image via a transmission path having a predetermined bus width may be performed.
For example, the transmission path between the function unit that performs the bit plane number reduction process and the function unit that performs the bit plane number increase process does not have a sufficient bus width to transmit the raster image in the original image state. Consider the case. In this case, the number of bit planes of the raster image is reduced to the number of transmittable bit planes by the bit plane number reduction process, and the raster image with the reduced number of bit planes is transmitted. Thereafter, the raster image can be displayed on the image display unit or the like by increasing the number of bit planes of the raster image and then outputting it to the image display unit or the like by the bit plane number increase process.
As described above, an image processing method that performs processing that cannot be performed on a raster image when the number of bit planes is the original image between the bit plane number reduction processing and the bit plane number increase processing is the same as described above. The effect of is obtained.

  The method of decreasing and increasing the number of bit planes has been described with some examples in other embodiments. However, dither processing is used as a method of decreasing the number of bit planes, and reduction processing is used as a method of increasing the number of bit planes. It is preferable to perform the reverse process of the above because image compression / decompression with little deterioration in image quality can be performed.

<Second embodiment>
FIG. 2 is a block diagram illustrating a schematic configuration of an image processing apparatus according to a second embodiment of the present invention. In FIG. 2, after a raster image 1 of 6 bits for each color of RGB sent from a computer is processed in the former stage 4 of the image processing section, a raster image of 4 bits for each color is stored in a memory 2 and the stored raster image of 4 bits for each color is stored. The image is converted into 6 bits for each color by the image processing unit rear stage 5 and output to the image display unit 3 capable of displaying 6 bits. Although FIG. 2 shows a block configuration for one of the RGB colors, the same configuration is also provided in parallel for the other two colors.

  The first stage of the image processing unit 4 includes a threshold value generation unit 11A, a comparator 12, a selector 13, and a subtractor. The lower 2 bits of the input 6-bit gradation data of the raster image 1 are sent to the comparator 12, where the comparator 12 compares the lower 2 bits with the 2-bit signal output from the threshold generator 11A.

FIG. 3 is a plan view illustrating a method of generating an output signal of the threshold value generation unit.
Here, a matrix of organized dither is used as the threshold. The threshold generation unit 11A generates an output signal based on the xy coordinate values (x, y) of the input pixels. In FIG. 3, [xmod 2] indicates a remainder obtained by dividing the X coordinate value (x) of the pixel by 2, and [ymod 2] indicates a remainder obtained by dividing the Y coordinate value (y) of the pixel by 2. An output value is generated from the results of [xmod 2] and [ymod 2].

  The comparator 12 outputs the value of A when the value of the lower 2 bits of the input 6-bit gradation data of the raster image 1 is B, and the output value of the threshold value generation unit 11a is B, where A <B. In other cases, 0 is output to the selector 13 as a SEL signal. This SEL signal becomes a select signal of the selector 13.

  The selector 13 receives the value of the upper 4 bits of the input 6-bit gradation data of the raster image 1 and the value obtained by subtracting 1 from the subtractor, and outputs the SEL signal of 0 from the comparator 12 to 0. If the SEL signal is 1, the value obtained by subtracting 1 with the subtractor is output, and the 4-bit output signal of the image processing unit front stage 4 is output.

FIG. 4 is a schematic diagram illustrating a process in a preceding stage of the image processing unit.
Here, for each pixel (image position) on the horizontal axis, a process of converting a 6-bit input gray scale indicated by the left vertical axis to a 4-bit output gray scale indicated by the right vertical axis is performed. For example, “◆” at the leftmost pixel position indicates that the input gradation is “011110”. Since the value is between the threshold values “011111” and “011011”, it is thinned out between the horizontal lines drawn therebetween. The output gradation is indicated by “■”, and the output gradation at this time is “0110”. The above process is performed for each pixel position, and the raster image 1 which is 6-bit gradation data is converted into 4-bit output gradation.
If the threshold value is the same as the input gradation value, the value is converted to a 4-bit value that is higher and closest to the threshold value. In other words, when the threshold value and the input gradation value are the same, the value closest to the threshold value among the 4-bit gradation values higher than the threshold value in the figure is set as the output gradation value. Selected.
In FIG. 4, the first stage of the image processing unit 4 converts the pixel into a 4-bit gradation based on a threshold value that changes according to the xy coordinate value (x, y) of the input pixel. By converting 6 bits for each color into 4 bits for each color in this manner, a raster image with a reduced number of bit planes is stored in the memory 2.

  The raster image in which the number of bit planes stored in the memory 2 is reduced is converted into 6 bits for each color in the latter stage of the image processing unit 5 and sent to the image display unit 3. The latter stage of the image processing unit 5 includes a bit adding unit 14 and a threshold value generating unit 11B. Here, the threshold generator 11B has the same configuration as the threshold generator 11A.

FIG. 5 is a circuit diagram showing the internal configuration of the bit addition unit.
The bit adding unit 14 adds the OR of all the 4-bit signals output from the memory 2 as lower bits and adds the 2-bit signal to the 5-bit signal, thereby adding the 2-bit signal output from the threshold generation unit 11B. Are added by the adder 17. Further, the 5-bit signal obtained from the adder 17 is set as the upper bit, and the 6-bit signal to which the lower bit signal output from the threshold value generator 11 is added is output to the image display unit 3.

  One specific example will be described. In the case of the memory signal 1000 and the threshold signal 11, the 5-bit signal input to the adder 17 is 10001 and the 1-bit signal is 1, so the output of the adder 17 is 10010. A 6-bit output signal obtained by adding the lower-order bit signal 1 of the threshold signal thereto becomes 100101.

The reason why all ORs of the 4-bit signal are taken and added as lower bits is to minimize a signal error between input and output. FIG. 6 shows a signal (4-bit value) and an output signal (6-bit value) stored in the memory 2 with respect to the input signal and the output value of the threshold value generation unit.
In the figure, each input signal and the signal value in the threshold generation unit are shown in decimal numbers. The signal stored in the memory is a decimal representation of a 4-bit gradation value, and each output signal is a decimal representation of a 6-bit gradation value.
It can be seen that the maximum error is 2 when the input signal is 7 or more, and 3 when the input signal is 6 or less. Further, an output signal by multi-level dither (prior art), an average value for each input signal, a difference between the average value and the input signal value, and a standard deviation of the output signal are also shown.

  It can be said that the smaller the difference between the average value and the input signal, the smaller the color change and the change in luminance, and the better the gradation, and the smaller the standard deviation as a whole, the less graininess. Compared with the error of the prior art, the difference between the average value and the input signal value of the present embodiment is almost improved, the standard deviation is reduced at most gradations, and has a stable low value. You can see that. This indicates that in the present embodiment, color errors and graininess appear in the prior art, but are suppressed in the present embodiment.

  In the case where only the output from the memory 2 is combined with the upper 4 bits and the output from the threshold generator 11 as the lower 2 bits without combining all of the 4-bit signals into 6 bits, the average value and The difference between the input signal values is -1.5, and a color change and a luminance change appear as compared with the case of ORing. However, for the input signals 2 to 40, there is an effect that the difference from the input signal is smaller than that of the related art.

  In the case of the input signals 0 to 3 in FIG. 6, the output signals are the same, because the signals stored in the memory are the same. If it is desired to obtain the gradation reproducibility of the input signal, it is preferable to read the gradation of the input signal. The gradation read of the input signal is performed by converting the input signal into, for example, (new input signal) = INT ((input signal before read) × 60/63 + 3), where INT (A) is used. Represents an integer component of A.

  It is desirable that the maximum gradation and the minimum gradation have the same value for all dither values before and after the above processing. For example, this can be realized by adding a condition that, when the signal value stored in the memory is 0, the dither value is not added to the output value, in addition to the above-described reading of the gradation. Of course, other processing methods may be used as long as the processing satisfies the above conditions.

  Further, although the former stage 4 of the image processing unit is expressed by using the selector 13 and the comparator 12, the same output can be obtained by expressing by the subtractor and the quantizer 18 as shown in FIG. . The quantizer 18 has a function of outputting the upper 4 bits of the input 6 bits as they are.

  5 and FIG. 7, a series of processing in the image processing unit front stage 4 and the image processing unit rear stage 5 is performed by subtracting the output from the threshold value generation unit 11A in the image processing unit front stage 4 by the image processing unit rear stage 5. It can be seen that the addition is performed. Thus, it can be seen that by minimizing the effect of the dither processing on the image quality, it is possible to suppress the occurrence of graininess and false colors.

  In the present embodiment, the threshold value generation unit uses organized dither, but the present invention is not limited to this. In other words, if the two-dimensional dither matrix is such that the same pattern is repeated with a minute length as one cycle in both the vertical and horizontal directions of the image, the above-described effect can be obtained. Note that the smaller the cycle of the dither matrix is, the higher the frequency of the periodic noise becomes, and the less noticeable the noise becomes. Therefore, a two-dimensional dither matrix having a two-pixel cycle in both the vertical and horizontal directions is most preferable.

  The threshold generation unit 11B has the same configuration as the threshold generation unit 11A. Therefore, as shown in FIG. 8, as a configuration in which the threshold generation units 11A and 11B are switched and used, only one threshold generation unit 11 may be provided as a whole. In this case, it suffices to control whether the output of the threshold generation unit 11 is an input to the comparator 12 or an input to the bit addition unit 14. FIG. 8 shows an example of the control method.

  8, a control signal SEL2 input to the selector 13A and the demultiplexer 15 is output from the input / output switching control unit 16. The input / output switching control section 16 selects and outputs 0 as SEL2 when sending the output of the threshold value generating section 11 to the comparator 12, and selects and outputs 1 when sending it to the bit adding section 14.

  As described above, as the second embodiment of the present invention, the image processing unit first stage 4 that performs image processing on the raster image 1 to reduce the number of bit planes and the output signal (raster image) of the image processing unit front stage are stored. And a second image processing unit 5 for returning the number of bit planes of the raster image from the memory 2 to the original number of bit planes. The reverse processing is performed between the first image processing unit 4 and the second image processing unit 5. The image processing apparatus that performs the above has been described. With the above configuration, it is possible to reduce the chip area and the power consumption while minimizing the influence on the image quality.

  Also, by increasing or decreasing the number of bit planes in the former stage 4 of the image processing unit and the latter stage 5 of the image processing unit by a multi-valued dither method, an image processing apparatus with a simplified configuration of the image processing unit can be obtained.

Note that a configuration in which image processing is performed by software is also possible.
FIG. 9 is a flowchart illustrating an example of an image processing method in the first stage of the image processing unit according to the present embodiment, and FIG. 10 is a flowchart illustrating an example of an image processing method in the second stage of the image processing unit in the present embodiment. In FIG. 9 and FIG. 10, both processes of the former stage of the image processing unit and the latter stage of the image processing unit are configured as software, but there is no problem if only one of them is configured as software and the other is configured as hardware.

  FIG. 9 shows an image processing method when the input signal is 6 bits and the number of bit planes at the time of compression is b bits (where b is an integer of 2 to 6). The input signal gradation I (6 bits), the X coordinate x of the pixel, and the Y coordinate y of the pixel are input to the former stage 4 of the image processing unit (step S11). Next, a dither matrix required to generate a threshold is defined (step S12). Here, in the dither matrix of the 4 × 4 systematic dither, it is called a Bayer array, [[10,4,6,8], [12,0,2,14], [7,9,11,5], [3,15,13,1]].

  Then, a threshold value is generated based on the pixel coordinate values x and y (step S13). The method of generating the threshold is as shown in the figure. xmod4 indicates the remainder of dividing x by 4. Here, the reason why the dither matrix is divided by a power of 2 is that the threshold value differs depending on the number of bits b of the output gradation and is set to a value corresponding to each number of bits. For example, if b = 4, the threshold takes a 2-bit value. Since the value of the dither matrix is 4 bits, it is divided by 2 ^ (4-2) = 4 to make it 2 bits.

  In step S14, the threshold value d is subtracted from the input signal gradation, and lower bits are discarded. In the above example, since b = 4, the lower 2 bits are truncated at 6-4 = 2, and the upper 4 bits are output.

  In FIG. 10, in the latter stage 5 of the image processing unit, the input signal gradation I is b bits, and the X coordinate x of the pixel and the Y coordinate y of the pixel are input (Step S21). In steps S22 and S23, those having the same configuration as the former stage 4 of the image processing unit are used. If the input signal I is 0, the output Iout = d. Otherwise, as shown in step S24, I is the upper bit and d is the lower bit, and 2 ＾ is used to reduce the error from the original signal. The one with (5-b) added is output. This 2 ＾ (5-b) corresponds to the OR component shown in FIG.

With the above algorithm, an image processing apparatus equivalent to the image processing apparatus shown in FIG. 2 can be realized as a configuration in which image processing is performed by software.
Note that the flowcharts shown in FIG. 9 and FIG. 10 are examples, and the present invention is not limited to this as long as the configuration satisfies the present embodiment.

<Third embodiment>
FIG. 11 is a block diagram illustrating a first configuration example of an image processing apparatus according to a third embodiment of the present invention. The difference from the second embodiment of the present invention is that the raster image 1 is directly sent to the image display unit 3 or the raster image from the memory 2 is displayed between the image processing unit 5 and the image display unit 3. And a selector 13B for selecting whether to send the data to the unit 3 and a memory use switching control unit 6 for performing selection control in the selector 13B.

  The memory switching control unit 6 controls the selector 13B according to an image to be sent to the image display unit 3. For example, when a still image is displayed, since the image is not rewritten, "1" is output from the memory use switching control unit 6 to display the image stored in the memory 2, and the selector 13B Sends the raster image output from the image processing unit rear stage 5 to the image display unit 3. On the other hand, when a moving image is displayed, the raster image 1 is not stored in the memory, but is displayed on the image display unit 3 as it is. Therefore, “0” is output from the memory use switching control unit 6 to the selector 13B.

  With the above-described configuration, switching display between a moving image and a still image is possible, and in still image display, image display with reduced power consumption can be performed with a small chip area.

  FIG. 12 is a block diagram illustrating a second configuration example of the image processing apparatus according to the third embodiment of the present invention. In FIG. 12, when the output signal of the memory use switching control unit 6 is “0”, that is, when displaying the raster image 1 on the image display unit 3 without passing through the memory 2, the process ON / OFF control unit 7 The control is performed so as to stop the processing of the former stage 4 of the image processing unit, the memory 2 and the latter stage 5 of the image processing unit. As described above, by stopping the processes of the first stage of the image processing unit 4, the memory 2, and the second stage of the image processing unit 5, power consumption can be reduced.

<Fourth embodiment>
FIG. 13 is a block diagram illustrating a schematic configuration of an image processing apparatus according to a fourth embodiment of the present invention. The difference from the third embodiment of the present invention shown in FIG. 11 is that the configuration of the bit addition unit 14A and the output from the memory use switching control unit 6 are input to the gradation control unit 7, and the gradation control unit 7 is that gradation control of the image display unit 3 is performed.

  FIG. 14 is a block diagram illustrating a schematic configuration of a bit adding unit according to the fourth embodiment of the present invention. The bit addition unit 14A performs bit combination with the output from the memory 2 as the upper 4 bits and the output from the threshold value generator 11B as the lower 2 bits, and outputs the result to the selector 13B. This is a very simplified configuration as compared with the bit adding unit 14 in the second embodiment of the present invention shown in FIG.

  FIG. 15 is a diagram illustrating values of an input signal, a signal stored in a memory, and an output signal from a subsequent stage of an image processing unit according to the fourth embodiment of the present invention. As shown in FIG. 15, it can be seen that by changing the configuration of FIG. 5 to FIG. 14, the average value of the output signal is smaller than that of the input signal. In this state, when the display is switched by the selector 13B, a difference occurs in the brightness of the display image. Therefore, the gradation control unit 7 controls the change of the display gradation. That is, when the output of the memory use switching display unit 6 is “0”, the gradation control unit 7 performs normal gradation control, but when the output is “1”, the gradation control unit 7 performs the operation shown in FIG. As described above, the adjustment is performed so that the output gradation becomes a value larger than the output signal of FIG. Thus, an image having substantially the same brightness can be obtained even when the display is switched by the selector 13B (that is, when the memory 2 is used).

  Several configurations can be considered for the configuration of the tone control unit 7. For example, a look-up table may be formed, and input signals may be read. In the hardware configuration, when the image display unit is an analog gradation type LCD (liquid crystal display) or organic EL (electroluminescent) display, the VT characteristic of the liquid crystal is changed according to the value of the memory use switching control unit 6. There is a method of changing the value of the gradation voltage of the liquid crystal so as to change.

  With the above-described configuration, it is possible to provide an image processing apparatus having a configuration in which there is almost no processing in the second stage of the image processing unit as compared with the first and second embodiments of the present invention.

<Fifth embodiment>
FIG. 17 is a block diagram illustrating a schematic configuration of an image processing apparatus according to a fifth embodiment of the present invention. The difference from the third embodiment of the present invention shown in FIG. 11 is that the number of bit planes stored in the memory 2 is 4, 5, and 3 for each of R, G, and B gradations. This configuration has the same memory capacity as the third embodiment of the present invention.

  The reason why a large number of bit planes is assigned to G and a small number of bit planes are assigned to B is that the granularity that causes image quality deterioration in the multi-value dither processing is largely due to the luminance difference rather than the color difference. G has the greatest effect on the luminance component, and B has the least effect. With such a configuration, the granularity can be further suppressed. If the number of bit planes is set as described above in the ordinary multi-value dither processing, the color error of B becomes large, and the image quality of flesh color deteriorates.

  FIG. 18 is a diagram illustrating values of an input signal, a signal stored in a memory, and an output signal from a subsequent stage of an image processing unit in a pixel gradation B according to the fifth embodiment of the present invention. Further, an output signal by multi-level dither (prior art), an average value for each input signal, a difference between the average value and the input signal value, and a standard deviation of the output signal are also shown. It can be seen that the standard deviation of the present embodiment is reduced in most gradations and has a stable low value compared to the error of the related art. This indicates that even if the number of bit planes changes, color errors and graininess are suppressed in the present embodiment.

  In FIG. 17, since a 4-bit memory is used for the R component of the raster image, the same processing as the image processing unit front stage 4 and the image processing unit rear stage 5 shown in the second embodiment of the present invention is performed. However, the G component and the B component are different in the configuration of the threshold value generation unit and the bit width sent to each unit. FIG. 19 shows a configuration of the former stage 4G and 4B of the image processing unit and the latter stage 5G and 5B of the image processing unit. In FIG. 19, the threshold generation units 11G and 11B generate output signals by the generation method shown in FIG.

  With the above-described configuration, it is possible to reduce the luminance error in the RGB color display, and it is possible to obtain an image with little graininess and an image quality comparable to that of a normal 6-bit display.

  Further, in FIG. 17, similarly to the second embodiment of the present invention, it is also possible to adopt a configuration in which only one threshold value generation unit is provided as a whole. FIG. 21 shows an example of the configuration. The threshold generation unit 11 shown in FIG. 21 uses the generation method of the threshold generation unit 11B shown in FIG. 20 to output the R component to the upper 2 bits and output the G component to the upper 1 bit. Use only bits. Thus, it is not necessary to provide a threshold value generation unit for each of the RGB components, and efficiency can be improved.

<Sixth embodiment>
So far, an image processing apparatus has been described in which a 6-bit raster image of each color is stored in a 4-bit memory, and based on the data, a high-quality image is displayed on an image display unit capable of displaying 6 bits of each color. Here, an image processing apparatus capable of displaying 6 bits equivalent by using FRC (Frame Rate Control) for an image display unit capable of displaying 4 bits for each color will be described.

  The FRC is a method of increasing a displayable gray scale by periodically changing the gray scale in an image display device of a limited gray scale display. For example, in an image display device capable of displaying from 0 to 15 gray scales, if the display gray scale is periodically changed as 14, 14, 14, 15 with four frames as one cycle, the displayable gray scale is 15 × 4 + 1 = 61 gradations, which is almost equivalent to 6-bit display.

  FIG. 22 is a block diagram illustrating a schematic configuration of an image processing apparatus according to a sixth embodiment of the present invention. The difference from the second embodiment of the present invention shown in FIG. 2 is that an FRC image processing unit rear stage 9 is provided instead of the image processing unit rear stage 5 in FIG. This point is that VSync is input, and that the image display unit 3A can display 4 bits for each color. Here, only one block of RGB is shown for convenience.

  Hereinafter, the description will be focused on the latter stage 9 of the FRC image processing unit. The rear stage 9 of the FRC image processing unit includes a threshold generation unit 11B for generating a threshold based on the XY coordinates of the pixel, a 2-bit counter 19 for counting VSync, a threshold generation unit 11B and a 2-bit counter 19 And a carry generation unit 20 for generating a carry based on the output of the memory 2, and a value obtained by adding 1 to the output according to the carry value among the outputs from the memory 2 is output to the image display unit 3, or And a selector 13 for setting whether to output a value to the image display unit 3.

  The threshold generation unit 11B performs an output as shown in FIG. This is the same as the output value of the second embodiment of the present invention. The 2-bit counter 19 is counted every time VSync is input, and its output value changes from 00 → 11 → 01 → 10 → 00 →. FIG. 23 shows the state transition table. As shown in FIG. 23, the next state and the output value are set to be the same.

  Carry generating section 20 sets a carry value based on the threshold value output from threshold value generating section 11B and the output value of 2-bit counter 19. FIG. 24 shows the relationship among the threshold value, the counter output value, and the carry output value. "1" is output when (threshold value)> (counter output value), and "0" is output otherwise. In this manner, four frames are defined as one cycle, and a carry corresponding to the threshold value is generated in the four frames.

  Then, the selector 13 selects a signal to be output based on the carry value. When the carry value is “0”, the output value from the memory 2 is output to the image display unit 3 when the carry value is “1”.

  FIG. 25 shows the values of the input signal, the signal stored in the memory, and the output signal from the subsequent stage of the FRC image processing unit in the sixth embodiment of the present invention. Further, an output signal by multi-level dither (prior art), an average value for each input signal, a difference between the average value and the input signal value, and a standard deviation of the output signal are also shown. Here, the output signal is originally 4 bits, but a value converted from 4 bits to 6 bits is used to compare an error with the input signal. The output signal from the latter stage 9 of the FRC image processing unit is an average value for four frames (one cycle) obtained by the latter stage 9 of the FRC image processing unit. It can be seen that the standard deviation of the present embodiment is reduced in most gradations and has a stable low value compared to the error of the related art. In addition, it can be seen that the standard deviation is almost comparable to the result of FIG. From this, it can be seen that even with an image display device capable of displaying 4-bit memory and 4-bit, an image having an image quality equivalent to 6 bits can be obtained by using the present invention.

  With the above configuration, it is possible to obtain an image processing apparatus that has higher image quality than conventional multi-value dither processing and does not require a memory for 6 bits unlike the conventional FRC.

<Seventh embodiment>
A description will be given of a seventh embodiment in which the present invention is preferably implemented. FIG. 26 is a block diagram illustrating a configuration example of an image processing apparatus according to a seventh embodiment of the present invention. The difference from the third embodiment of the present invention lies in that a compression processing unit 4A and a decompression processing unit 5A are provided instead of the image processing unit front stage 4 and the image processing unit rear stage 5.

  The memory switching control unit 6 controls the selector 13B according to an image to be sent to the image display unit 3. For example, when a still image is displayed, since the image is not rewritten, "1" is output from the memory use switching control unit 6 to display the image stored in the memory 2, and the selector 13B Sends the raster image output from the expansion processing unit 5A to the image display unit 3. On the other hand, when a moving image is displayed, the raster image 1 is not stored in the memory 2 but is displayed on the image display unit 3 as it is. Therefore, “0” is output from the memory use switching control unit 6 to the selector 13B.

With the above-described configuration, switching display between a moving image and a still image is possible, and in still image display, image display with reduced power consumption can be performed with a small chip area. In this switching display, it is possible to apply any compression processing unit 4A and expansion processing unit 5A, instead of the specific compression / expansion processing such as the image processing unit front stage 4 and the image processing unit rear stage 5, Moreover, it has a great effect.
In other words, the compression processing unit 4A and the decompression processing unit 5A have a specific relationship (for example, the two-dimensional dither matrix is the same) with respect to the image signal input to the memory 2 and the image signal read from the memory 2. It is not necessary to perform the compression / decompression processing of.
For example, the compression processing unit 4A and the expansion processing unit 5A perform compression and expansion processing on the image signal input to the memory 2 and the image signal read from the memory 2 using different two-dimensional dither matrices. Is also good. That is, the compression processing unit 4A and the decompression processing unit 5A may include threshold generation units having different configurations.
Further, it is apparent that the same effects as described above can be obtained even if the compression / expansion processing performed by the compression processing unit 4A and the expansion processing unit 5A is not a processing using a two-dimensional dither matrix but another processing method. .

<Eighth embodiment>
An eighth preferred embodiment of the present invention will be described. FIG. 27 is a block diagram illustrating a configuration example of an image processing apparatus according to an eighth embodiment of the present invention. This image processing apparatus further includes a processing ON / OFF control unit 7 in addition to the configuration of the image processing apparatus according to the seventh embodiment. When the output signal of the memory use switching control unit 6 is “0”, that is, when the raster image 1 is displayed on the image display unit 3 without passing through the memory 2, the processing ON / OFF control unit 7 4A, the memory 2, and the processing of the decompression processing unit 5A are controlled to be stopped.

  In the image processing apparatus according to the present embodiment, when the memory use switching control unit 6 outputs “0”, that is, when the memory 2 is not used, the processing ON / OFF control unit 7 sets the compression processing unit 4A and the memory 2 Then, the processing of the decompression processing unit 5A is stopped. Thus, in addition to obtaining the same effects as the image processing apparatus according to the tenth embodiment, it is possible to further reduce the power consumption.

<Ninth embodiment>
A ninth preferred embodiment of the present invention will be described. FIG. 28 is a block diagram illustrating a configuration example of an image processing apparatus according to a ninth embodiment of the present invention. The image processing apparatus according to the third embodiment is different from the image processing apparatus according to the third embodiment in that the resolution is X * Y and the image has the same capacity as the display capacity of the image display unit 3 capable of displaying 6 bits each (that is, an image of X * Y pixels). In that it has a memory 2 that can store
In the present specification, the “resolution of the display device” indicates the maximum number of pixels that the display device (for example, the image display unit 3) can display on one screen in the horizontal and vertical directions. For example, a display device having a resolution of 640 × 480 has 640 pixels in the horizontal direction and 480 pixels in the vertical direction, and can display an image of less than 640 pixels on one screen.
The “resolution of an image” represents the total number of pixels constituting the image as the product of the number of pixels in the vertical direction and the number of pixels in the horizontal direction. Is an image occupying an area represented by a rectangle having 640 horizontal pixels and 480 vertical pixels.

  In such a case, for example, as shown in FIG. 28, when an image (X * 2Y) twice as long as the resolution (X * Y) of the image display unit 3 in the vertical direction is input as the raster image 1, All the images can be stored in the memory 2 by compressing the data at the compression ratio 前 in the former stage 4 of the processing unit, that is, by halving the number of bit planes. In other words, all the images input as the raster image 1 and having pixels in the vertical direction having twice the resolution of the image display unit 3 can be stored in the memory 2. Then, expansion processing is performed in the latter stage of the image processing section 5 on an arbitrary area of X * Y size of the input image, and the image display section 3 can display an arbitrary area of an image larger than the resolution. As described above, even if an image is not input from the outside in each frame period, the image stored in the memory 2 is converted into an image having a large resolution such as a scroll image (in other words, the number of pixels is smaller than the resolution of the image display unit 3). Many images can be displayed.

  When an image is displayed without passing through the memory 2, the resolution of the input image is X * Y at the maximum. In other words, when the input image input as the raster image 1 is smaller than X * Y pixels, the memory use switching control unit 6 outputs “0” to the selector 13B, and directly outputs the raster image 1 without passing through the memory 2. The image is displayed on the image display unit 3.

Although the input image in this example is an image for two continuous screens, the present invention is not limited to this, and it goes without saying that the same effect can be obtained with images of two or more different screens.
In other words, for example, even when two raster images of X * Y pixels are stored in the memory 2, each raster image can be stored in the memory 2 by performing the same compression processing in the former stage of the image processing unit 4. It is possible. It is also possible to read out each raster image from the memory 2, perform expansion processing in the subsequent stage 5 of the image processing unit, and then display it on the image display unit 3.

As described above, according to the present embodiment, when an image having a resolution of m times (m is an arbitrary positive number) of the image display unit 3 is input as the raster image 1, the input image is compressed to 1 / m. And store it in the memory 2. Therefore, even if the input image is a raster image having a larger number of pixels than the resolution of the image display unit 3, it can be stored in the memory 2.
In addition, by performing expansion processing on the image signal of the image stored in the memory 2 in the subsequent stage 5 of the image processing unit, the image display unit 3 can display an arbitrary area of the image larger than the resolution.
Furthermore, even if an image is not input from the outside in each frame cycle, the image stored in the memory 2 has a larger number of pixels than the resolution of the image display unit 3 such as a scroll image. Image)).

<Tenth embodiment>
A tenth preferred embodiment of the present invention will be described. FIG. 29 is a block diagram illustrating a configuration example of an image processing apparatus according to a tenth embodiment of the present invention. The image processing apparatus according to the present embodiment includes a selector 13C between the former stage 4 of the image processing unit and the memory 2, a selector 13D between the latter stage 5 of the image processing unit and the selector 13B, and further controls the selectors 13C and 13D. The image processing apparatus according to the ninth embodiment differs from the image processing apparatus according to the ninth embodiment in having a memory input signal switching control unit 27 for performing

  The memory input signal switching control unit 27 selects an image stored in the memory 2 as a compressed image or a non-compressed image with reference to the resolution of the input image. In the following description, the compressed image or the non-compressed image is selected by referring to the resolution. However, the present invention is not limited to this, and the compressed image or the non-compressed image is selected by referring to the data capacity of the image such as the number of bit planes. It goes without saying that a selection may be made.

  For example, when the number of pixels of the raster image 1 is X * Y and the memory 2 is used, the memory input signal switching control unit 27 outputs “0” to the selectors 13C and 13D, and the memory use switching unit 6 13B is output as "1". As a result, the uncompressed image is stored in the memory 2, and the uncompressed image is displayed on the image display unit 3.

  When the number of pixels of the raster image 1 is X * 2Y and the memory 2 is used, the memory input signal switching unit 27 outputs “1” to the selectors 13C and 13D, and the memory use switching unit 6 outputs “1” to the selector 13B. 1 "is output. Thus, the image compressed in the former stage 4 of the image processing unit is stored in the memory 2, and the image read out from the memory 2 and expanded in the latter stage 5 of the image processing unit is displayed on the image display unit 3.

  When the number of pixels of the raster image 1 is X * Y and the memory 2 is not used, the operation is the same as in the first configuration example of the present embodiment, and the memory use switching control unit 6 outputs “0” to the selector 13B. Then, the raster image 1 is directly displayed on the image display unit 3 without going through the memory 2.

  With the above configuration, it is possible to select a compressed image or a non-compressed image as an image to be stored in the memory 2. When the size of the displayable image is prioritized over the image quality, by selecting a compressed image, it is possible to accumulate an image such as a map that does not fit on one screen. In the case where priority is given to image quality as in the case of a still image of a natural image, by selecting an uncompressed image, it is possible to obtain an adaptive image processing apparatus which is excellent in image quality and memory efficiency.

<Eleventh embodiment>
An eleventh preferred embodiment of the present invention will be described. FIG. 30 is a block diagram illustrating a configuration example of an image processing apparatus according to an eleventh embodiment of the present invention. In the present embodiment, a raster image 1, which is an original image, is divided into an image 1A and character information 1B and input to an image processing apparatus.
The image processing apparatus according to the present embodiment is different from the image processing apparatus according to the ninth embodiment in having an image combining unit 28. The image synthesizing unit 28 generates a synthesized image of the image 1A whose number of bit planes has been increased in the subsequent stage 5 of the image processing unit and the character information 1B.

  It is assumed that a raster image, which is an input image, is divided into two layers of an image 1A (pixel number X * Y; 6 bits) and character information 1B (pixel number X * Y; 1 bit) and input. The synthesized image in the uncompressed state is data of 6 bits + 1 bit = 7 bits in each of X * Y pixels. Since the maximum amount of data that can be stored in the memory 2 is 6-bit data for each pixel of X * Y, a composite image in an uncompressed state cannot be stored in the memory 2.

  In such a case, the memory use switching control unit 6 outputs “1” to the selector 13B and inputs the image 1A to the former stage 4 of the image processing unit. In the former stage 4 of the image processing unit, the same compression processing as described above is performed on the image 1A, and the number of bit planes of the image 1A is reduced from “6” to “5”. Since the total data amount of the image 1A and the character information 1B with the reduced number of bit planes is the data amount of 5 bits + 1 bit = 6 bits in each of X * Y pixels, it can be stored in the memory 2. It becomes.

  The image 1A read from the memory 2 with the number of bit planes reduced to “5” is subjected to the same decompression processing in the latter stage of the image processing unit 5, and the number of bit planes is changed from “5” to “6”. Will be increased. The image synthesizing unit 28 generates a synthesized image of the image 1A whose number of bits has been increased in the subsequent stage 5 of the image processing unit and the character information 1B read from the memory 2. This composite image is displayed on the image display unit 3.

As described above, the image processing apparatus according to the present embodiment compresses the data of at least one of the layers when the raster image is divided into two layers and input, and when they cannot be stored in the memory 2 without compression. The number of bit planes is reduced and stored in the memory 2, and two layers obtained by decompression or increase of the number of bit planes can be combined and displayed.
For example, as shown in FIG. 30, when the image 1A is a normal 6-bit image and the character information 1B is 1-bit character information, the image combining unit 28 can realize the overlay display of the character. . Further, an image can be displayed without providing a new memory for overlay display.

  Further, the image processing apparatus according to the present embodiment can change the image 1A and the character information 1B independently. For example, assuming a clock that displays a time as a still image as character information 1B as image 1A, only character information 1B is acquired at predetermined intervals (for example, every second and every minute) and input to memory 2. This makes it possible to omit the processing in the former stage 4 of the image processing unit, the memory 2 and the latter stage 5 of the image processing unit. This makes it possible to reduce power consumption when displaying the raster image 1 on the image display unit 3.

  In the present embodiment, the multi-tone image and the character information have been described as examples of the two layers constituting the raster image. However, the present invention is not limited to this. Such a configuration is also applicable.

<Twelfth embodiment>
A twelfth preferred embodiment of the present invention will be described. FIG. 31 is a block diagram illustrating a configuration example of an image processing apparatus according to a twelfth embodiment of the present invention. In the present embodiment, a signal for displaying the raster image 1 is divided into two layers of an image 1A and a control signal 29 for each pixel, and is input to the image processing device.
The image processing apparatus according to the present embodiment is different from the image processing apparatus according to the ninth embodiment in that when the image 1A and the control signal 29 cannot be stored in the memory 2 without compression, the image 1A is compressed or bit-planed. The number is stored in the memory 2 with the number reduced, and the image obtained by decompression or the increase in the number of bit planes is displayed on the image display unit 3 based on the control signal 29.

  It is assumed that a signal for displaying the raster image 1 is input after being divided into two layers of an image 1A (the number of pixels X * Y; 6 bits) and a control signal 29 (1 bit) for each pixel. The total data amount of the image 1A and the control signal 29 is 6 bits + 1 bit = 7 bits of data in each of X * Y pixels. Since the maximum amount of data that can be stored in the memory 2 is 6 bits of data for each pixel of X * Y, a signal for displaying the raster image 1 cannot be stored in the memory 2 in an uncompressed state.

  In such a case, the memory use switching control unit 6 outputs “1” to the selector 13B, and inputs a signal for displaying the raster image 1 to the image processing unit front stage 4. In the former stage 4 of the image processing unit, the same compression processing as described above is performed on the image 1A, and the number of bit planes of the image 1A is reduced from “6” to “5”. Since the total data amount of the image 1A with the reduced number of bit planes and the control signal 29 of each pixel is 5 bits + 1 bit = 6 bits in each pixel of X * Y, it is accumulated in the memory 2. It becomes possible.

  The image 1A read from the memory 2 with the number of bit planes reduced to “5” is subjected to the same decompression processing in the latter stage of the image processing unit 5, and the number of bit planes is changed from “5” to “6”. Will be increased. The image 1A with the increased number of bit planes is displayed on the image display unit 3 based on the control signal 29 for each pixel read from the memory 2.

  As described above, in the image processing apparatus according to the present embodiment, the signal for displaying the raster image 1 is divided into at least one image and at least one control signal, and is input. When possible, at least one image can be compressed or stored in the memory 2 with a reduced number of bit planes, and an image obtained by decompression or an increase in the number of bit planes can be displayed based on a control signal.

  Further, the image processing apparatus according to the present embodiment can change the image 1A and the control information 29 independently. This is the same as in the fourteenth embodiment. For example, by updating only the control information 29 of the image 1A and the control information 29 stored in the memory 2, the former stage 4, the memory 2, and the image processing unit The processing in the post-stage 5 can be omitted. This makes it possible to reduce power consumption when displaying the raster image 1 on the image display unit 3.

<Thirteenth embodiment>
In the above-described configuration having a memory up to the twelfth embodiment of the present invention, an image processing apparatus has been described in which a memory capacity is reduced, power consumption is reduced, and an image quality comparable to that of the related art is obtained. In addition, in the thirteenth and fourteenth embodiments of the present invention, it is possible to reduce the transmission capacity in the transfer of the raster image from the first device to the second device. The configuration will be described below.

  FIG. 32 is a block diagram illustrating a schematic configuration of an image transmission device according to a thirteenth embodiment of the present invention. In FIG. 32, the image transmission device according to the thirteenth embodiment of the present invention includes a first device 7 for transmitting a raster image and a second device 8 for receiving a raster image, In the first device 7, the raster image 1 having 6-bit gradation for each color is converted into 4-bit gradation for each color by the former stage 4 of the image processing unit, and is transmitted to the second device 8. In the second device 8, the raster image received from the first device 7 is processed in the latter stage of the image processing unit 5, returned to a raster image of 6-bit gradation for each color, and output to the image display unit 3.

  Here, the former stage 4 of the image processing unit and the latter stage 5 of the image processing unit have the same configuration as that described in each of the above embodiments.

  With the above configuration, it can be seen that image quality is hardly degraded in transmission of a raster image from the first device 7 to the second device 8, and image transmission can be performed with a small transmission capacity. This is effective in the case where the image transmission capacity is insufficient, and in reducing the number of transmission paths between the first device and the second device.

Note that the second device 8 included in the image transmission device according to the present embodiment also shows a preferred embodiment of the image receiving device according to the present invention.
The image receiving apparatus according to the present invention, like the second apparatus 8, receives a raster image having a smaller number of bit planes than the original image and increases the number of bit planes of the received image to compare with the original image. As a result, it is possible to obtain an image comparable in image quality. Further, since the transmitting side receives an image in a state where the number of bit planes is smaller than that of the original image, the image can be efficiently received.
For example, in a case where a transmission line for receiving an image has only a 16-bit bus width and wants to receive a raster image of 6 bits for each color (18 bits in total), the number of bit planes is reduced on the transmission side. By receiving the raster image in the state and increasing the number of bit planes of the image, it is possible to receive an image having the same image quality as the original image in parallel with each color.

<Fourteenth Embodiment>
FIG. 33 shows an image transmission apparatus according to a fourteenth embodiment of the present invention. This image transmission device has a first device 7 for transmitting a raster image and second devices 8a, 8b, 8c for receiving a raster image. The bus width of the transmission path between the first device 7 and the second devices 8a, 8b, 8c is 15 bits, 12 bits, and 9 bits, respectively.
The first device 7 includes a former stage 4 of the image processing unit, a bit plane reduction number control unit 50, a selector 51, and a demultiplexer 52. The image processing unit front stage 4 reduces the number of bit planes (6-bit gradation for each color) of the raster image 1 to a predetermined value, and selects a raster image of the number of bit planes according to the instruction from the bit plane reduction number control unit 50. 51. The bit plane reduction number control unit 50 controls the selector 51 according to which of the second devices 8a to 8c the raster image 1 is to be transmitted, and performs image processing on the image with the number of bit planes suitable for the receiving device. Output to the front stage 4 Also, by controlling the demultiplexer 52, the image processing unit front stage 4 selects the transmission path of the raster image in which the number of bit planes is reduced.
The second device 8a has an image processing unit rear stage 8a and an image display unit 3a. The subsequent stage 5a of the image processing unit performs the same processing as described above on the 5-bit raster image of each color transmitted from the first device 7, and restores the raster image of 6 bits for each color. The image display unit 3 displays a raster image restored to 6 bits for each color.
The second device 8b restores the 4-bit raster image of each color to 6 bits of each color in the subsequent stage 5b of the image processing unit, and the second device 8c converts the 3-bit raster image of each color into each color in the subsequent stage 5c of the image processing unit. Except for restoring to 6 bits, it is the same as the second device 8a.

The operation of the image transmission device according to the present embodiment will be described. Here, a case where the raster image 1 is transmitted to the second device 8a will be described as an example. The first stage of the image processing unit 4 performs processing on the raster image 1 of 6 bits for each color to generate a raster image of 5 bits, 4 bits, and 3 bits for each color. The bit plane reduction number control unit 50 controls the selector 51 to input a raster image corresponding to the device on the receiving side, that is, a 5-bit raster image for each color to the demultiplexer 52. At this time, the bit plane reduction number control unit 50 sends the control signal to the selector 51 as “a”. Since the control signal output from the bit plane reduction number control unit 50 is “a”, the raster image input to the demultiplexer 52 is output to the transmission path to the second device 8a.
In the second device 8a, the raster image received from the first device 7 is processed in the latter stage of the image processing unit 5 to return to a raster image of 6-bit gradation for each color and displayed on the image display unit 3a.

  As described above, the image transmission device according to the present embodiment can select how much the number of bit planes of a raster image is reduced according to the device on the receiving side. Therefore, raster images can be transmitted with the number of bit planes according to the bus width of the transmission path to the receiving-side device and the capabilities of the subsequent stages 5a to 5c of the image processing unit, so that the transmission capacity can be made more efficient. .

<Fifteenth embodiment>
Since the present invention aims at reducing the chip area and the power consumption, the image processing unit does not require complicated processing and has a simple configuration. Therefore, the present invention is mounted on a driver or a controller chip of a display device having a built-in memory to obtain the above-mentioned effect, and further, a polysilicon circuit mounting these drivers and a controller on a glass substrate is provided. Is also applicable.

  FIG. 34 shows a liquid crystal display device according to a fifteenth embodiment of the present invention in which an image processing unit and a driving circuit unit are formed using a polysilicon thin film transistor circuit on a glass substrate. The input signal is 6 bits for each color of RGB, the memory is 4 bits for each color of RGB, and the output is 6 bits for each color of RGB. The external raster image 1 is displayed on the liquid crystal display unit 10. The liquid crystal display unit 10 includes a plurality of pixels 31 and thin film transistors 32 arranged in a matrix, and a plurality of data lines 33 and a plurality of gate lines 34 arranged in a lattice for a set of the pixels 31 and the thin film transistors 32. Are connected one by one. In each pixel 31, when the thin film transistor 32 is turned on by a signal from the gate line 34, a signal of the data line 33 connected to the thin film transistor 32 is written.

  The raster image 1 is sent to the former stage 4 of the image processing unit and the data register 23. The raster image input to the former stage 4 of the image processing unit is subjected to the image processing as described up to the twelfth embodiment of the present invention, and is stored in the memory 2 of 12 bits in RGB. Then, data is read from the memory 2 as necessary, and image processing is performed in the subsequent stage 5 of the image processing unit. The output of the latter stage 5 of the image processing unit is sent to the selector 13B. Here, the processing in the first stage of the image processing unit, the memory 2, and the second stage of the image processing unit are performed by the method described up to the twelfth embodiment of the present invention. Therefore, the control signals to be input to the former stage 4 and the latter stage 5 of the image processing unit need the XY coordinates of the pixel when writing or reading to or from the memory 2. Instead of the XY coordinates of the pixel, a control signal that can derive the XY coordinates of the pixel, for example, VSync, HSync, or CLK may be used. The memory 2 is controlled by the memory control unit 26 to switch between reading and writing, and to control data input / output addresses. The XY coordinates of at least the pixel are input to the memory control unit 26 as in the former stage 4 and the latter stage 5 of the image processing unit.

  FIG. 35 is a circuit diagram showing a configuration of the shift register 21A and the data register 22 in the liquid crystal display device. The raster image input to the data register 22 is sequentially accumulated with 6-bit data based on the output signal from the S / R (shift register) 21A and latched by the latch 23. The output from the latch 23 is sent to the selector 13B.

FIG. 36 is a circuit diagram showing a configuration of the selector 13B in the liquid crystal display device.
The selector 13B sends the image stored in the memory 2 from the latter stage of the image processing unit 5 to the DAC 24 based on the control data from the memory use switching control unit 6, depending on whether to display the image stored in the memory 2 or the image from the outside as it is. Select data. The DAC 24 converts a 6-bit digital signal for each color from the selector 13B into an analog signal, and outputs the analog signal to a desired data line by the data line selector 25.

  The output from the data line selector 25 is sent to the liquid crystal display unit 10, and is written to the pixel 31 via the thin film transistor 32 in the row of the gate line 34 selected by the shift register 21B.

  With such a configuration, in the fifteenth embodiment of the present invention, it is possible to obtain a liquid crystal display device in which the image processing circuit shown in the twelfth embodiment of the present invention is built in a glass substrate. Further, the former stage 4 of the image processing unit and the latter stage 5 of the image processing unit can each be configured with a small number of transistors.

  FIG. 37 shows an example of the logic configuration of the former stage 4 and the latter stage 5 of accumulating a 6-bit signal in a 4-bit memory and expanding it into 6 bits. In FIG. 37, only a two-input, three-input NAND and an inverter are used. Therefore, it is understood that the area of the image processing circuit is sufficiently smaller than the memory area, and the area of the circuit unit can be reduced.

  Each of the embodiments described above is an example of a preferred embodiment of the present invention, and can be variously modified and implemented without departing from the gist of the present invention.

  For example, in each of the embodiments described above, as the image processing method, multi-value dither processing using a two-dimensional dither matrix and bit addition based on the two-dimensional dither matrix are performed. The image processing is not limited, and any image processing can be applied as long as the above-described false color, false contour, and graininess are not seen.

  Further, in each of the above embodiments, when reducing the number of bit planes of the raster image, multi-value dither processing is performed using a two-dimensional dither matrix, and when increasing the number of bit planes, multi-value dither processing is used. Bit addition is performed based on the existing two-dimensional dither matrix, but when the number of bit planes decreases and increases, such as when multi-value dither processing is performed using random dither instead of the two-dimensional dither matrix, images are reversed. Other image processing methods for performing processing may be applied.

Furthermore, in the second embodiment, the configuration in the case where the image processing is performed by software processing has been described. However, the image processing apparatus and the image transmission apparatus according to the other embodiments may perform the image processing similarly to the second embodiment. Can be performed by software processing.
As described above, the present invention can be variously modified.

4 is a flowchart illustrating a flow of processing of an image processing method according to the first embodiment of the present invention. FIG. 6 is a block diagram illustrating a schematic configuration of an image processing apparatus according to a second embodiment of the present invention. FIG. 3 is a plan view illustrating a method of generating an output signal of a threshold value generation unit in FIG. 2. FIG. 3 is a schematic diagram illustrating a process at a preceding stage of an image processing unit in FIG. 2; FIG. 3 is a circuit diagram illustrating an internal configuration of a bit addition unit in FIG. 2. 9 is a table showing input signals and output signals according to the second embodiment of the present invention. FIG. 4 is a block diagram illustrating another configuration of the preceding stage of the image processing unit in FIG. 2. FIG. 11 is a block diagram illustrating another configuration of the image processing apparatus according to the second embodiment of the present invention. 9 is a flowchart illustrating an image processing method performed by a former stage of the image processing unit. 9 is a flowchart illustrating an image processing method performed by a subsequent stage of the image processing unit. It is a block diagram showing the composition of the image processing device which is a 3rd embodiment of the present invention. FIG. 13 is a block diagram illustrating another configuration of the image processing apparatus according to the third embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is a 4th embodiment of the present invention. FIG. 12 is a circuit diagram illustrating an internal configuration of a bit addition unit in FIG. 11. 11 is a table showing input signals and output signals according to a fourth embodiment of the present invention. FIG. 12 is a diagram illustrating a change in gradation based on the type of an input signal by the gradation control unit in FIG. 11. It is a block diagram showing the composition of the image processing device which is a 5th embodiment of the present invention. 15 is a table showing an input signal and an output signal of a B component according to a fifth embodiment of the present invention. FIG. 16 is a block diagram illustrating a detailed configuration of a former stage of the image processing unit and a latter stage of the image processing unit in FIG. 15. 16 is a list showing input / output signal values in the threshold generation unit of FIG. It is a block diagram showing other composition of the image processing device which is a 5th embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is a 6th embodiment of the present invention. FIG. 21 is a state transition diagram of the 2-bit counter of FIG. 20. 21 is a list showing input / output signal values of the carry generation unit in FIG. 20. 15 is a table showing input signals and output signals according to a sixth embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is a 7th embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is an 8th embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is a 9th embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is a 10th embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is an 11th embodiment of the present invention. It is a block diagram showing the composition of the image processing device which is a 12th embodiment of the present invention. FIG. 39 is a block diagram illustrating a schematic configuration of an image transmission device according to a thirteenth embodiment of the present invention. FIG. 21 is a block diagram illustrating a schematic configuration of an image transmission device according to a fourteenth embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration of a liquid crystal display device. FIG. 35 is a block diagram showing a configuration of a shift register and a data register in FIG. 34. FIG. 35 is a circuit diagram showing the internal configuration of the selector of FIG. 34. FIG. 35 is a logic configuration diagram of the liquid crystal display device of FIG. 34 in a stage preceding the image processing unit and a stage following the image processing unit. FIG. 10 is a block diagram illustrating a conventional image processing device. FIG. 9 is a diagram illustrating a problem when the invention described in Japanese Patent Publication No. 2-8473 is applied to image processing.

Explanation of reference numerals

1 raster image 1A raster image (image)
1B raster image (character information)
Reference Signs List 2 Display image memory 3, 3A Image display unit 4 Pre-stage of image processing unit 4A Compression processing unit 5 Post-stage of image processing unit 5A Decompression processing unit 6 Memory use switching control unit 7 Raster image transmission side (first device)
8 Raster image receiving side (second device)
9 FRC image processing unit subsequent stage 10 Liquid crystal display unit 11, 11A, 11B Threshold generation unit 12 Comparator 13, 13A, 13B, 13C, 13D, 51 Selector 14, 14A Bit addition unit 15, 52 Demultiplexer 16 Input / output switching Control unit 17 Adder 18 Quantizer 19 Counter 20 Carry generation unit 21A, 21B Shift register 22 Data register 23 Latch 24 D / A converter 25 Data line selector 26 Memory control unit 27 Memory input signal switching control unit 28 Image synthesis unit 29 Control signal 31 Pixel 32 Thin film transistor 33 Data line 34 Gate line 50 Bit plane reduction number control unit

Claims (11)

An image processing apparatus that stores input image data in a storage unit and causes a predetermined display device to perform image display based on the image data read from the storage unit,
First image processing means for generating a compressed raster image by compressing a first raster image as an original image;
Means for storing the compressed raster image in the storage means;
Second image processing means for reading and decompressing the compressed raster image stored in the storage means to generate a second raster image;
Means for outputting the second raster image to the display device,
The image processing apparatus according to claim 1, wherein the compressed raster image is generated when a data amount of the first raster image is larger than a storage capacity of the storage unit.   2. The image processing device according to claim 1, wherein the first and second image processing units perform image processing such that maximum and minimum values of element components of the first raster image and the second raster image match. 2. The image processing device according to 1.   When the data amount of the first raster image is equal to or less than the storage capacity of the storage unit, the first raster image is stored in the storage unit without compression or subjected to processing by the first image processing unit. 3. The image processing apparatus according to claim 1, further comprising: means for selecting whether to store the data in the storage means. Means for outputting the first raster image to the display device without passing through the first image processing means, the storage means, and the second image processing means;
4. The image processing apparatus according to claim 1, further comprising: a unit configured to select which of the first raster image and the second raster image is to be output to the display device. 5. apparatus.   When outputting the first raster image to the display device, further comprising means for stopping the operations of the first image processing means, the accumulation means, and the second image processing means. Item 5. The image processing device according to Item 4.   The image processing apparatus according to claim 1, wherein the second image processing unit is formed on a same substrate as a driving circuit of the display device.   The image processing apparatus according to claim 1, wherein the first image processing unit is formed on a same substrate as a drive circuit of the display device. An image processing method that stores input image data in a storage unit and causes a predetermined display device to display an image based on the image data read from the storage unit,
A first image processing step of compressing the first raster image to generate a compressed raster image when the data amount of the first raster image as the original image is larger than the storage capacity of the storage unit;
Storing the compressed raster image in the storage unit;
A second image processing step of reading and decompressing the compressed raster image stored in the storage unit and generating a second raster image;
Outputting the second raster image to the display device. Before the first image processing step,
When the data amount of the first raster image is equal to or less than the storage capacity of the storage unit, the user selects whether to store the first raster image in the storage unit without compression or to store it in the storage unit after compression. Further comprising a selection step,
If it is selected in the selecting step that the first raster image is compressed, the first image processing step also applies to the first raster image whose data amount is equal to or less than the storage capacity of the storage means. The image processing method according to claim 8, wherein image processing is performed.   10. The image processing method according to claim 8, further comprising an output switching step of selecting which of the first raster image and the second raster image is output to the display device. .   After the output switching step, if the first raster image is selected in the output switching step, stop the image processing in the first image processing step and the second image processing step The image processing method according to claim 10, further comprising a step.

Images