JP2004201066A - Receiver - Google Patents

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Publication number
JP2004201066A
JP2004201066A JP2002367809A JP2002367809A JP2004201066A JP 2004201066 A JP2004201066 A JP 2004201066A JP 2002367809 A JP2002367809 A JP 2002367809A JP 2002367809 A JP2002367809 A JP 2002367809A JP 2004201066 A JP2004201066 A JP 2004201066A
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JP
Japan
Prior art keywords
received signal
output
agc circuit
error rate
agc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002367809A
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Japanese (ja)
Inventor
Yasuyuki Tomita
泰行 富田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Kokusai Electric Inc
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Hitachi Kokusai Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP2002367809A priority Critical patent/JP2004201066A/en
Publication of JP2004201066A publication Critical patent/JP2004201066A/en
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  • Circuits Of Receivers In General (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver capable of obtaining accurate reception signal data even when received signal fluctuates fast outside the range and even when the received signal includes modulation of an amplitude component. <P>SOLUTION: Respective systems for reception signal processing hold amplifiers 11, 21, AGC (automatic gain control) circuits 12 and 22 for performing automatic gain control with mutually different response speeds and AD converters 13 and 23, respectively, and a digital signal processor 30 which receives signals that pass through the systems selects digital data with the lowest error rate between the systems. Then, the reception signal data which has the lowest error rate can be obtained. For example, when the received signal is disturbed by fast level fluctuations such as fading, the output of a system comprising an AGC circuit with a fast response speed is selected, and when the received signal takes a modulation system with an amplitude component, it is enough that the output of a system comprising an AGC circuit with a slow response speed is selected. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は受信装置に関し、特に、フェージング等にできるだけ影響を受けないようにAGC回路を用いる受信装置に関する。
【0002】
【従来の技術】
従来の受信装置においては、アナログ入力回路の部分にAGC回路を配置しているが、そのAGC回路の特性(応答速度)は固定的であって、状況に合わせてAGC特性の働きを切り替えることをしていない。したがって、入力信号の状態が設計上で予想されている正常な範囲では正確な受信動作を行うことができるが、設定された範囲を超えた場合には、正確な受信動作を行うことができない。すなわち、AGC回路の応答速度が遅く設定されている場合、フェージングのように早いレベル変動を含む受信信号に対しては、その変動速度に追従できずに受信信号データに多くの誤りを発生させる。また、逆にAGC回路の応答速度が早く設定されている場合、受信信号に振幅成分の変調が含まれているような変調方式の受信信号を受ける場合、AGC回路が信号レベルを一定にしようと動作するために振幅成分に誤りを発生させ受信信号が正常なレベルで受信されていても、受信信号データに多くの誤りを発生させる(例えば、ユニークワード領域のレベルと、データ領域のレベルが異なる場合)。
【0003】
【発明が解決しようとする課題】
上述の従来の受信装置においては、AGC回路の特性が固定的に設定されているので、受信信号が範囲外の早い変動をしたり、受信信号に振幅成分の変調が含まれている場合に、いずれか一方において、正確な受信信号データが得られないという問題がある。
【0004】
本発明は、上記の問題を解決するためになされたものであって、受信信号が範囲外の早い変動をしたり、受信信号に振幅成分の変調が含まれているような場合でも正確な受信信号データを得ることができる受信装置を提供することを目的とする。
【0005】
【課題を解決するための手段】
前述した課題を解決するために、本発明は、受信信号をそれぞれ増幅する複数の増幅回路と、各増幅回路の出力に応答速度の異なる自動利得制御を行う複数のAGC回路と、各AGC回路の出力をそれぞれA/D変換する複数のADコンバータと、各ADコンバータの出力における受信信号データの誤り率を計算し、最も誤り率の低いADコンバータの出力を選択出力するデジタル信号処理装置とを有する。
【0006】
このような構成によれば、信号処理のための各系統は、応答速度の異なる自動利得制御を行うAGC回路を保持することになり、デジタル信号処理装置は、これらの系統の中から最も誤り率の低いデジタルデータを選択することができ、ひいては、誤り率の最も低い受信信号データを得ることができる。たとえば、受信信号がフェージングなどのレベル変動の早い妨害を受けているときには、応答速度の速いAGC回路を具備する系統の出力を選択し、受信信号が振幅成分のある変調方式を取っているときには、応答速度の遅いAGC回路を具備する系統の出力を選択すればよい。
【0007】
【発明の実施の形態】
以下、本発明の実施の形態について添付図面に基づいて説明する。図1は、本発明の受信装置の実施の形態を示すブロック図である。アンテナ(不図示)等からのアナログ形態の受信信号S0は、2系統に分かれて処理される。第1の系統において、受信信号S0は、増幅器11によって増幅され、信号S11としてAGC回路12に引き渡され、自動利得制御を受ける。自動利得制御を受けたAGC回路12から出力される信号S12は、ADコンバータ13に引き渡される。第2の系統において、受信信号S0は、増幅器21によって増幅され、信号S21としてAGC回路22に引き渡され、自動利得制御を受ける。自動利得制御を受けたAGC回路22から出力される信号S22は、ADコンバータ23に引き渡される。この場合、AGC回路12は、応答速度が速く設定されており、AGC回路12は、応答速度が遅く設定されており、信号S1,S2にそれぞれのAGC特性に従って自動利得制御を行う。
【0008】
ADコンバータ13,23は、AGC回路12,22によって自動利得制御を加えられた信号S12,S22を受け取り、受け取った信号をAD変換し、デジタルデータS13,S23として出力する。デジタル信号処理装置(DSP)30は、ADコンバータ13,23からのデジタルデータS13,S23に基づき、それぞれのデジタルデータS13,S23の誤り率を計算し、第1,第2の系統のうち、誤り率の低い方のデジタルデータを選択受信信号デジタルデータS30として後続段に出力する。なお、図1の波形の表示においては、等化機能つきの変調方式におけるユニークワード部分と、データ部分とでレベルが異なるように設定されている場合の受信信号の変化を示している。
【0009】
したがって、受信信号S0がフェージングなどのレベル変動の早い妨害を受けているときには、第1の系統の増幅器11,AGC回路12,ADコンバータ13を経てきた信号が選択受信信号デジタルデータS30として後続段に出力され、受信信号S0が振幅成分のある変調方式を取っているときには、第2の系統の増幅器21,AGC回路22,ADコンバータ23を経てきた信号が選択受信信号デジタルデータS30として後続段に出力されるので、現状に適合するAGC特性を選択でき、ひいては正確な受信信号データを選択受信信号デジタルデータS30として後続段に出力することができる。上述の例では、信号処理を行うのは2系統としたが、3系統あるいはそれ以上であってもよく、これら複数の系統のうちの誤り率が最も低い系統のデジタルデータを選択受信信号デジタルデータS30として後続段に出力するようにすればよい。
【0010】
【発明の効果】
本発明の受信装置は、以上において説明したように構成されているので、
増幅回路と、AGC回路と、ADコンバータとからなる信号処理のための各系統において、それぞれのAGC回路は、応答速度の異なる自動利得制御を行う。したがって、デジタル信号処理装置は、これらの系統の中から最も誤り率の低いデジタルデータを選択することによって、誤り率の最も低い受信信号データを得ることができる。たとえば、受信信号がフェージングなどのレベル変動の早い妨害を受けているときには、応答速度の速いAGC回路を具備する系統の出力を選択し、受信信号が振幅成分のある変調方式を取っているときには、応答速度の遅いAGC回路を具備する系統の出力を選択する。
【図面の簡単な説明】
【図1】本発明の受信装置の実施の形態を示すブロック図である。
【符号の説明】
11,21 増幅器
12,22 AGC回路
13,23 ADコンバータ
30 デジタル信号処理装置(DSP)
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a receiving apparatus, and more particularly, to a receiving apparatus using an AGC circuit so as to be as little affected by fading or the like.
[0002]
[Prior art]
In the conventional receiving apparatus, an AGC circuit is arranged in a part of an analog input circuit. However, the characteristic (response speed) of the AGC circuit is fixed, and the function of the AGC characteristic is switched according to the situation. I haven't. Therefore, an accurate receiving operation can be performed when the state of the input signal is within a normal range expected in design, but an accurate receiving operation cannot be performed when the state exceeds the set range. That is, when the response speed of the AGC circuit is set to be slow, a received signal including a fast level fluctuation such as fading cannot follow the fluctuation speed and causes many errors in the received signal data. Conversely, when the response speed of the AGC circuit is set to be fast, or when a received signal of a modulation method in which the received signal includes the modulation of the amplitude component is received, the AGC circuit tries to keep the signal level constant. In order to operate, even if an error is generated in the amplitude component and the received signal is received at a normal level, many errors are generated in the received signal data (for example, the level of the unique word area is different from the level of the data area). Case).
[0003]
[Problems to be solved by the invention]
In the above-described conventional receiving apparatus, since the characteristics of the AGC circuit are fixedly set, when the received signal fluctuates quickly outside the range or when the received signal includes amplitude component modulation, In either case, there is a problem that accurate received signal data cannot be obtained.
[0004]
The present invention has been made in order to solve the above-described problem, and it is possible to accurately receive a received signal even when the received signal fluctuates rapidly and the amplitude of the received signal is modulated. It is an object of the present invention to provide a receiving device capable of obtaining signal data.
[0005]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a plurality of amplifier circuits for amplifying received signals, a plurality of AGC circuits for performing automatic gain control with different response speeds on the outputs of the respective amplifier circuits, and a plurality of AGC circuits. A plurality of A / D converters for respectively A / D converting the outputs; and a digital signal processing device for calculating the error rate of the received signal data at the output of each A / D converter and selecting and outputting the output of the A / D converter having the lowest error rate. .
[0006]
According to such a configuration, each system for signal processing has an AGC circuit that performs automatic gain control with different response speeds, and the digital signal processing device has the highest error rate among these systems. , Digital data with a low error rate can be selected, and as a result, received signal data with the lowest error rate can be obtained. For example, when the received signal is disturbed by a fast level fluctuation such as fading, an output of a system having an AGC circuit having a fast response speed is selected. What is necessary is just to select the output of the system provided with the AGC circuit whose response speed is slow.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the receiving apparatus of the present invention. An analog reception signal S0 from an antenna (not shown) or the like is processed separately in two systems. In the first system, the received signal S0 is amplified by the amplifier 11, delivered to the AGC circuit 12 as a signal S11, and subjected to automatic gain control. The signal S12 output from the AGC circuit 12 that has been subjected to the automatic gain control is transferred to the AD converter 13. In the second system, the received signal S0 is amplified by the amplifier 21, delivered to the AGC circuit 22 as the signal S21, and subjected to automatic gain control. The signal S22 output from the AGC circuit 22 that has been subjected to the automatic gain control is transferred to the AD converter 23. In this case, the response speed of the AGC circuit 12 is set to be fast, and the response speed of the AGC circuit 12 is set to be slow. The AGC circuit 12 performs automatic gain control on the signals S1 and S2 in accordance with the respective AGC characteristics.
[0008]
The A / D converters 13 and 23 receive the signals S12 and S22 to which the automatic gain control has been applied by the AGC circuits 12 and 22, AD convert the received signals, and output them as digital data S13 and S23. The digital signal processor (DSP) 30 calculates an error rate of each of the digital data S13 and S23 based on the digital data S13 and S23 from the AD converters 13 and 23, and calculates an error rate among the first and second systems. The digital data with the lower rate is output to the succeeding stage as the selected reception signal digital data S30. Note that the waveform display of FIG. 1 shows a change in the received signal when the level is set to be different between the unique word part and the data part in the modulation method with the equalization function.
[0009]
Therefore, when the received signal S0 is disturbed by a fast fluctuation such as fading, the signal that has passed through the amplifier 11, the AGC circuit 12, and the AD converter 13 of the first system is transmitted to the subsequent stage as the selected received signal digital data S30. When the received signal S0 has a modulation method having an amplitude component, the signal having passed through the second-system amplifier 21, AGC circuit 22, and AD converter 23 is output to the subsequent stage as selected reception signal digital data S30. Therefore, it is possible to select an AGC characteristic suitable for the present situation, and to output accurate received signal data to the subsequent stage as selected received signal digital data S30. In the above example, two systems are used for signal processing. However, three or more systems may be used, and digital data of the system having the lowest error rate among these multiple systems is selected reception signal digital data. What is necessary is just to output it to the succeeding stage as S30.
[0010]
【The invention's effect】
Since the receiving device of the present invention is configured as described above,
In each system for signal processing including an amplifier circuit, an AGC circuit, and an AD converter, each AGC circuit performs automatic gain control with a different response speed. Therefore, the digital signal processing device can obtain the received signal data with the lowest error rate by selecting the digital data with the lowest error rate from these systems. For example, when the received signal is disturbed by a fast level fluctuation such as fading, an output of a system having an AGC circuit having a fast response speed is selected, and when the received signal employs a modulation method having an amplitude component, An output of a system including an AGC circuit having a low response speed is selected.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an embodiment of a receiving device of the present invention.
[Explanation of symbols]
11, 21 Amplifier 12, 22 AGC circuit 13, 23 AD converter 30 Digital signal processor (DSP)

Claims (1)

受信信号をそれぞれ増幅する複数の増幅回路と、
各増幅回路の出力に応答速度の異なる自動利得制御を行う複数のAGC回路と、
各AGC回路の出力をそれぞれA/D変換する複数のADコンバータと、
各ADコンバータの出力における受信信号データの誤り率を計算し、最も誤り率の低いADコンバータの出力を選択出力するデジタル信号処理装置とを有する受信装置。
A plurality of amplifier circuits for respectively amplifying the received signal,
A plurality of AGC circuits that perform automatic gain control with different response speeds on the output of each amplifier circuit;
A plurality of AD converters for A / D converting the output of each AGC circuit,
A digital signal processing device that calculates an error rate of received signal data at an output of each AD converter and selects and outputs an output of the AD converter with the lowest error rate.
JP2002367809A 2002-12-19 2002-12-19 Receiver Withdrawn JP2004201066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002367809A JP2004201066A (en) 2002-12-19 2002-12-19 Receiver

Publications (1)

Publication Number Publication Date
JP2004201066A true JP2004201066A (en) 2004-07-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002367809A Withdrawn JP2004201066A (en) 2002-12-19 2002-12-19 Receiver

Country Status (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461681B1 (en) 2013-12-10 2016-10-04 Hitachi Kokusai Electric Inc. Receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461681B1 (en) 2013-12-10 2016-10-04 Hitachi Kokusai Electric Inc. Receiver

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Effective date: 20060307