JP2004200763A - Clock generating apparatus, communication apparatus, clock generating method, program, and computer-readable recording medium with recorded program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid jumping of the RTS value and reduce the jitter quantity of a clock recovered from the RTS value. <P>SOLUTION: The clock generating apparatus comprises an input unit for inputting a communication signal having specified information at a specified position to be transferred in an asynchronous transfer system as a plurality of asynchronous transfer system cells; a cell processor 7 which outputs the specified information that a specified asynchronous transfer system cell among the plurality of asynchronous transfer system cell has at the specified position as clock information, complements the clock information, if needed, using the specified information that a different asynchronous transfer system cell from the specified asynchronous transfer system cell among the plurality of asynchronous transfer system cell has at the specified position; and outputs the complemented clock information; and a clock generator 50 for generating the clock signal, using the clock information. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transfer unit during communication when using an unstructured mode (hereinafter, referred to as UDT Mode) in an ATM adaptation layer type 1 (AAL type 1) transmission of an ATM (Asynchronous Transfer Mode). The present invention relates to the use of Convergence Sublayer Indication (CSI) bits, and more particularly to the use of CSI bits when the sequence number (Sequence Count: SC) is an even number.
[0002]
[Prior art]
The following means are known for the purpose of enabling detection of a dropped cell which cannot be detected from a sequence counter included in an ATM cell. A multi-frame synchronization pattern determined so as to be able to detect a bit loss of a multiple of 8 in succession is assigned to CS indication bits not used in the UDT mode of the AAL type 1 protocol. At the time of assembly, one bit of the multi-frame synchronization pattern is inserted into the CS indication bit of each ATM cell. At the time of reassembly, the bit pattern extracted from the CS indication bit of each ATM cell is compared with the multi-frame synchronization pattern. If they do not match, an alarm is issued. As a result, even a cell drop of a multiple of 8 is detected, and the communication quality can be monitored in detail. (See Patent Document 1)
[0003]
Further, in the transmission of RTS information of ATM communication, the period of the differential sequence is obtained without knowing the clock differential sequence on the transmitting side in advance, and when the RTS value is lost due to cell loss or the like, the lost RTS value is complemented. The following means are known for the purpose. Utilizing that the difference sequence information obtained from the received RTS has a cycle substantially corresponding to the frequency fluctuation of fs, the cycle is obtained, and when the RTS is lost, the RTS value is predicted from the cycle and the difference sequence information. (See Patent Document 2)
[0004]
[Patent Document 1]
JP 2001-339395 A
[Patent Document 2]
JP-A-10-303918
[0005]
[Problems to be solved by the invention]
In the related art described in Patent Document 1, the region of interest can be used for only one purpose (detection of cell omission of a multiple of 8). In this case, there is a problem that the amount of clock jitter described later cannot be suppressed.
In the related art described in Patent Document 2, when the RTS (Residual Time Stamp) value is lost, the current RTS value is predicted from the previous RTS value, but there is a problem in more accurate clock reproduction. .
[0006]
According to the present invention, when one ATM cell having an odd SC value in the RTS cycle = 0 to 7 is lost, recovery is performed without discarding the RTS value extracted in the RTS cycle. Accordingly, it is possible to avoid jumping of the RTS value when discarded, and to suppress the amount of jitter of the clock reproduced from the RTS value.
[0007]
Further, one of the ATM cells having an odd SC value in the SC value = 0 to 7 which is the RTS cycle has an SAR-PDU (Segmentation And Reassembly sublayer-Protocol Data Unit) header which is erroneous due to an event such as an order reversal of eight cells. , The number of error determination items in the SAR-PDU header is increased, or the error correction is performed on the RTS value extracted in the RTS cycle, thereby suppressing the jitter amount of the clock reproduced from the RTS value. The purpose is to be able to.
[0008]
Furthermore, assuming the transfer of a new special format, four ATM cells having an even SC value among SC values = 0 to 7 which are RTS periods are set so that format information is transferred without reducing the data area. An object of the present invention is to insert format information into CSI bits so that the receiving side can restore the original format information from the CSI bits.
[0009]
It is another object of the present invention to enable more accurate clock reproduction.
[0010]
[Means for Solving the Problems]
A clock generation device according to the present invention is a clock generation device that generates a clock signal for receiving the communication signal using clock information included in the received communication signal,
An input unit that has predetermined information at a predetermined position and inputs the communication signal transferred by the asynchronous transfer method as a plurality of asynchronous transfer method cells,
Among the plurality of asynchronous transfer method cells input by the input unit, a predetermined asynchronous transfer method cell outputs the predetermined information having the predetermined position as the clock information, and when the clock information needs to be complemented, Among the plurality of asynchronous transfer method cells, the asynchronous transfer method cell different from the predetermined asynchronous transfer method cell uses the predetermined information having the predetermined position to supplement the clock information, and the complemented clock is used. A complement output unit for outputting information,
A clock generation unit that generates the clock signal using the clock information output by the complement output unit;
It is characterized by having.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
First, AAL1 is described in ITU-T (International Telecommunication Union, Telecommunication Standardization Sector) Recommendation I.T. 363.1 (ITU-T Recommendation I.363.1: "B-ISDN ATM Adaptation Layer (AAL) specification, types 1 AAL").
FIG. 1 shows ITU-T Recommendation I. FIG. 2 is a diagram showing the structure of a cell defined in 363.1.
The information field in FIG. 1 includes a SAR-PDU header in the first byte and a SAR-PDU payload. The SAR-PDU header is roughly divided into an SN (Sequence Number) field and an SNP (Sequence Number Protection) field. The SN field is composed of a 1-bit CSI (Convergence Sublayer Indication) field and a 3-bit SC (Sequence Count) field. The SNP field is composed of a 3-bit CRC (Cyclic Redundancy Check) field and a 1-bit EP (Even Parity). It is configured.
[0012]
Next, the SC field in the SAR-PDU header will be described.
FIG. 2 is a diagram for explaining an AAL1 ATM cell to be transmitted.
As shown in FIG. 2, numbers 0 to 7 indicating the transmission order are assigned to each ATM cell as the SC value of the SC field in the SAR-PDU header shown in FIG. On the transmitting side, the SC value is periodically assigned by modulo 8 for each cell. On the receiving side, by checking the continuity of the SC value, it is possible to detect a loss of the ATM cell or an erroneous distribution of the ATM cell.
As a method for checking the 4-bit SN value of the SN field including the SC value on the receiving side, ITU-T Recommendation I.T. Uses the SequenceNumber check algorithm defined in 363.1. Here, an even parity check is performed based on the EP value of the EP field in the SAR-PDU header of the received ATM cell, and a CRC check is performed based on the CRC value of the CRC field, to determine whether the SN is a valid SN or an invalid SN. judge. Also, based on the result of the determination and the SC value extracted from the received SC field, it is determined whether to accept (receive) the received ATM cell, accept dummy data by inserting, or discard (discard).
[0013]
Next, the CSI field in the SAR-PDU header will be described. The CSI field is used in different ways depending on the operation of the CS (Convergence Sublayer). The CS operation using the CSI field includes transfer of a frame structure of a user signal, transfer of clock information of a user signal, and detection and correction of a bit error in a transmission path.
The protocol of SDT (Structured Data Transfer: Structured Data Transfer) is defined for the purpose of transferring the frame structure of a user signal. In the SDT, a pointer is used to indicate the first byte of the frame of the user signal. The pointer is inserted into the first byte of the SAR-PDU payload. If a pointer is inserted, the cell is called a P format, and if no pointer is inserted, the cell is called a non-P format.
FIG. 3 is a diagram showing each format of the P format and the non-P format.
The P format is limited to cells having an even number of SCs, whereas the non-P format is used whether the number of SCs is odd or even. The discrimination between the P format and the non-P format in the even-numbered SC cell is made by the CSI bit of the SAR-PDU header. When the CSI bit is “1”, the P format is used, and when the CSI bit is “0”, the non-P format is used. is there.
As a method for transferring clock information of a user signal, an SRTS (Synchronous Residual Time Stamp) method is described in ITU-T Recommendation I. 363.1. As shown in FIG. 2, the CSI value of the odd SC value (SC = 1, 3, 5, 7) is extracted from the CSI value in the SAR-PDU header, that is, the CSI value is transferred by the SRTS method by extracting a total of 4 bits. The generated RTS (Residual Time Stamp) value can be generated. Thus, the RTS value is composed of four bits from the MSB to the LSB. Since the SRTS method uses the CSI bits of the odd-numbered SC cells, it can coexist with the SDT that uses the CSI bits of the even-numbered SC cells, but can also be used alone.
[0014]
FIG. 4 is a diagram for explaining the SRTS method in the AAL1 process.
In the SRTS system, a P-bit counter (P = 4) is driven by a network clock fox on the transmission side, and an output of the P-bit counter is latched every N counts of a transfer clock fs of a signal to be communicated. Then, the latched RTS value is set to the CSI value in the ATM cell and transmitted. On the receiving side, the RTS value is extracted from the received ATM cell, and a clock fr serving as a reproduction signal of the clock fs is generated by a PLL (Phase Lock Loop).
That is, the transmitting side uses the network clock fox as a reference clock to drive the P-bit counter based on the clock information at the time of transmission. The bit counter value is latched, the RTS value of 4 bits is set to the CSI value in the four ATM cells, mapped in the SAR-PDU header, and transmitted. For example, in FIG. 4, 13, 11, 9, 7, 5,... Are obtained as RTS values, and these values are converted to binary numbers and transmitted by 4 bits. On the receiving side, a counter is operated in the same manner using the network clock fox as a reference clock, and the output result of the counter is compared with the RTS value extracted from the ATM cell to transmit one RTS value. A 3008 bit period can be reproduced.
Thus, the clock on the clock transmitting side can be reproduced on the receiving side by the SRTS method. In particular, a signal such as a CBR (Constant Bit Rate) signal that constantly transfers a fixed amount of data at a fixed speed is premised on synchronization on a network. If the speed is different, for example, the speed on the transmission side is low. When the speed of the receiving side is high, data cannot be transferred faithfully due to the speed difference. For this reason, it is important to synchronize clocks on the transmission side and the reception side.
However, as shown in FIG. 4, the lack of the RTS value (= 9) causes the RTS cycle, which is 4720 + 14 = 4734 counts in the counter based on the normal fox, to increase the number of RTS periods to be counted to 9 to 7 due to the lack. Since only counting is performed, it becomes 4732, which is a frequency fluctuation, that is, a jitter component. Here, 4720 is the number to be fully counted by the 4-bit counter, and 14 is the remainder. As described above, when one RTS value is lost, the frequency is corrected at the timing when the next RTS cycle is input, and the frequency is shifted from the frequency of fs for about 2 ms. Is very large.
[0015]
Hereinafter, the first embodiment will be described with reference to the drawings.
FIG. 5 is a block diagram showing a configuration of an ATM cell disassembly / assembly apparatus for performing AAL1 processing according to the first embodiment.
FIG. 6 is a block diagram showing the internal configuration of the SN sequencer unit.
FIG. 7 is a diagram showing a state transition of the check of the SNP field related to the AAL1 process.
FIG. 8 is a diagram illustrating an error check state transition of the Sequence Number check regarding the AAL1 processing unit.
FIG. 9 is a diagram illustrating a state transition of the Sequence Number check related to the AAL1 process.
FIG. 10 is a table showing the state transition of the Sequence Number check for the AAL1 processing unit.
FIG. 11 is a block diagram showing the inside of the RTS processing unit shown in FIG.
In FIG. 5, an ATM cell disassembly / assembly device (an example of a clock generation device and a communication device) includes an EP inspection unit 2, a CRC inspection unit 3, an SN sequencer unit 4, a cell processing unit 6, an RTS processing unit 7, a clock The generation unit 50 includes an input unit (not shown). The input unit has a SAR-PDU header extraction unit 1 and a cell buffer unit 5. The ATM cell disassembly / assembly device is also a communication device that supports AAL1.
In FIG. 6, the SN sequencer unit 4 includes an SNP inspection unit 8 and an SN inspection unit 9.
11, the RTS processing unit 7 includes an SN buffer unit 10, an RTS buffer unit 11, an RTS value output control unit 12, and a selector unit 13.
Here, this control is performed when the SC is 0, 1, 2, 4, 5,..., That is, when SC is lost due to cell loss of SC = 3, that is, Sync → Out of Seq → Sync in FIG. This control operates in the case of the transition and the transition of Rs + 1.
[0016]
As an example of a clock generation device, an ATM cell disassembly / assembly device generates a clock signal for receiving the communication signal using clock information included in the received communication signal.
The input unit inputs the communication signal, which has predetermined information at a predetermined position and is transferred by the asynchronous transfer method, as a plurality of cells of the asynchronous transfer method.
As an example of the complementary output unit, the RTS processing unit 7 uses, as clock information, the predetermined information that a predetermined asynchronous transfer method cell has in the predetermined position among the plurality of asynchronous transfer method cells input by the input unit. Output, when the clock information needs to be complemented, among the plurality of asynchronous transfer method cells, a predetermined asynchronous transfer method cell different from the predetermined asynchronous transfer method cell uses the predetermined information which is provided at the predetermined position. , Complements the clock information and outputs the complemented clock information.
The clock generator 50 generates the clock signal using the clock information output from the complementary output unit.
In addition, the input unit includes a first asynchronous transfer method cell having clock information at the predetermined position, and a second asynchronous transfer method cell having clock alternative information serving as alternative information of the clock information at the predetermined position. And will enter
The clock generation unit 50 generates a clock signal of the communication signal using clock information of the first asynchronous transfer system cell,
As an example of the selection unit, the selector unit 13 is configured to input the second asynchronous transfer mode cell when the second asynchronous transfer mode cell is input without inputting the first asynchronous transfer mode cell that is to be input by the input unit. Is selected instead of the clock information included in the first asynchronous transfer method cell, which is input by the second asynchronous transfer method cell.
As an example of the clock information output unit, the RTS buffer unit 11 outputs the clock alternative information selected by the selection unit instead of the clock information of the first asynchronous transfer mode cell.
Here, the clock information is an RTS value constituted by the CSI value,
The SAR-PDU header extraction unit 1 extracts a 1-byte SAR-PDU header 102 from the input 53-byte ATM cell 101. The extracted SAR-PDU header 102 is output to the EP inspection unit 2, and the CRC value 104 and the SN value 105 included in the extracted SAR-PDU header 102 are output to the CRC inspection unit 3. Further, the SN value 105 included in the extracted SAR-PDU header 102 is output to the RTS processing unit 7, and the SC value 107 is output to the SN sequencer unit 4. In other words, the SAR-PDU header extraction unit 1, which is an example of the input unit, inputs the plurality of asynchronous transfer method cells to the input unit, and performs the above-described asynchronous transfer method cell of the plurality of input asynchronous transfer method cells. Extract the SAR-PDU header.
The EP inspection unit 2 performs an even parity check on the 8-bit SAR-PDU header 102 based on the 1-bit EP value included in the SAR-PDU header 102, and outputs an EP inspection result 103 as an OK / NG check result.
The CRC checking unit 3 performs a CRC check on a total of 7 bits of a 4-bit SN value 105 and a 3-bit CRC value based on the 3-bit CRC value 104 included in the SAR-PDU header 102, and a CRC as an OK / NG check result. The inspection result 106 is output.
The SN sequencer 4 includes a 3-bit SC value 107 included in the extracted SAR-PDU header 102, an EP check result 103 as a check result by the EP checker 2, and a CRC check result 106 as a check result by the CRC checker 3. And outputs a decision result 108 of whether to accept the input ATM cell 101, to accept the dummy by inserting the Dummy, or to discard the received ATM cell 101, and to output the odd SC value 107 = 1, 3, 5, 7 If it is determined that the SN has been lost due to any bit error or loss, the clear control signal 109 is output. On the other hand, any of the odd SC values 107 = 1, 3, 5, and 7 has a bit error. And a write control signal 110 when all SNs are determined to be valid without any missing And outputs a 14. More specifically, in the SN sequencer unit 4, the SNP inspection unit 8 inputs the EP inspection result 103 as a check result by the EP inspection unit 2 and the CRC inspection result 106 as a check result by the CRC inspection unit, and FIG. In accordance with the state transition shown in FIG. 8, it is determined whether the SN is a valid SN or an invalid SN, and the SNP inspection result 121 is output as the result. The SN inspection unit 9 inputs the 3-bit SC value 107 included in the extracted SAR-PDU header 102 and the SNP inspection result 121 as the check result by the SNP inspection unit 8 according to the state transition of FIGS. 9 and 10. A decision result 108 indicating whether the accepted ATM cell 101 is to be Accepted, Accepted by inserting Dummy or Accepted is output, and any one of the odd SC values 107 = 1, 3, 5, and 7 When it is determined that the SN is lost due to an error or lack, a clear control signal 109 is output, or a write control signal 110 is output when all SNs are determined to be valid. In other words, the SN sequencer unit 4 checks the 3-bit SC value of the SAR-PDU header extracted by the SAR-PDU header extraction unit 1 and the parity check result of the parity check performed by the EP inspection unit 2. It is determined whether the predetermined SN value having an odd SC value is invalid or valid based on the CRC check result of the CRC check performed by the CRC checking unit 3 and a predetermined SN value having an odd SC value. When the predetermined SN value is determined to be invalid due to at least one of a bit error and a missing value, a clear signal indicating an instruction to delete the CSI value of the predetermined SN value determined to be invalid is transmitted. Output, and when the predetermined SN value is determined to be valid, write the CSI value of the predetermined SN value as the RTS value And outputs the order of the write control signal.
The cell buffer unit 5 inputs the ATM cell 101 and stores the input ATM cell 101.
The cell processing unit 6 reads and processes the ATM cells 101 stored in the cell buffer unit 5 by the read control signal 111 based on the determination result 108 from the SN sequencer unit 4, and processes the SAR-PDU payload 112 of 47 bytes. Output.
The RTS processing unit 7 inputs the 4-bit SN value 105 included in the extracted SAR-PDU header 102, the clear control signal 109, the write control signal 110, and the cycle completion signal 114 from the SN sequencer unit 4, and The bit RTS value 113 is output. Specifically, as an example of the complementary output unit, the RTS processing unit 7 is extracted by the SAR-PDU header extraction unit when the SN sequencer unit 4 determines that the predetermined SN value is invalid. A 4-bit SN value 105 included in the SAR-PDU header and a clear control signal 109 as an example of a clear signal output by the SN sequencer unit 4 are input, and based on the input clear signal, the predetermined The CSI value of the SN value having an even-numbered SC value different from the SC value of the SN value is written as the RTS value. When the SN sequencer unit 4 determines that the predetermined SN value is valid, Based on the write control signal output from the sequencer unit, the CSI value of the predetermined SN value is written as the RTS value and written. And outputs the Mareta RTS value.
The details are described below.
The RTS value output control unit 12 receives the error signal 115 and the error SC value 116, the clear control signal 109, and the write control signal 110 from the SN sequencer unit 4, and sends the read control signal 136 and the SNB clear signal 135 to the SN buffer unit 10. Then, a selection control signal 137 for the complemented SC value is output to the selector unit 13, and an output control signal 146 is output to the RTS buffer unit 11. In other words, the RTS value output control unit 12 inputs the SC value 107 from the SAR-PDU header extraction unit 1 and, when the SN sequencer unit 4 determines that the predetermined SN value is invalid, the SN sequencer A read control signal for prompting to read a CSI value of the SN value having the SC value based on the input clear signal and the SC value, and the predetermined SN value; Is selected based on the selection control signal and the selection control signal prompting to select a CSI value having an SN value having an even SC value different from the SC value having the predetermined SN value instead of the CSI value having An output control signal for prompting the output of the generated CSI value as the RTS value is generated, and the generated read control signal, selection control signal, and output control signal are output. When the SN value is determined to be valid by the SN sequencer unit 4, the CSI value of the SN value having the SC value is determined based on the write control signal output by the SN sequencer unit 4. Outputting a read control signal prompting to read, a selection control signal prompting to select a CSI value of the SN value having the SC value, and a CSI value selected based on the selection control signal as the RTS value. An output control signal for prompting is generated, and the generated read control signal, selection control signal, and output control signal are output.
The SN buffer unit 10 receives the 4-bit SN value 105 extracted by the SAR-PDU header extraction unit 1 and converts the CSI values 131 to 134 and 138 to 141 of the SC value 107 included in the SN value 105 into the SC value. 107 is maintained. The SN buffer unit 10 outputs a total of 8 bits of CSI values 131 to 134 and 138 to 141 to the selector unit 13 by a read control signal 136 from the RTS value output control unit 12, or clears the SNB from the RTS value output control unit 12. The CSI values 131 to 134 and 138 to 141 held by the signal 135 are cleared. In other words, the SN buffer unit 10 inputs each SN value included in the SAR-PDU header extracted by the SAR-PDU header extraction unit 1 and performs the above-described operation in accordance with the SC value of each of the input SN values. Each CSI value held by each SN value is held, and when the predetermined SN value is determined to be invalid by the SN sequencer unit 4, the clear signal and the RTS value output control unit 12 are output from the RTS value output control unit 12. The read control signal generated by the above is input, and based on the input clear signal, the CSI value of the predetermined SN value determined to be invalid among the held CSI values is deleted and input. Reading the respective CSI values of the respective SN values having the respective SC values from the respective CSI values retained after the deletion based on the read control signal read out, and When it is determined that the predetermined SN value is valid, a read control signal generated by the RTS value output control unit is input, and based on the input read control signal, each of the held CSI values is The CSI value of each SN value having each SC value is read from the data.
The selector section 13 selects the odd-numbered SC value CSI values 138 to 141 or the even-numbered SC value CSI values 131 to 134 in accordance with the selection control signal 137 from the RTS value output control section 12 and outputs the same to the RTS buffer section 11. In other words, the selector unit 13 inputs each CSI value read by the SN buffer unit 10 and the selection control signal generated by the RTS value output control unit 12, and based on the input selection control signal, When the SN sequencer unit 4 determines that the predetermined SN value is invalid, an even SC value different from the SC value of the predetermined SN value is used instead of the CSI value of the predetermined SN value. If the SN sequencer section 4 determines that the predetermined SN value is valid, the CSI value of the SN value having an odd SC value among the SC values is selected. Select
The RTS buffer unit 11 outputs the RTS value 113 according to the output control signal 146 from the RTS value output control unit 12. In other words, the RTS buffer unit 11 stores the CSI value of the SN value having an even SC value different from the SC value of the predetermined SN value selected by the selector unit 13 and the odd number of the SC values. And input the output control signal generated by the RTS value output control unit 12, and hold the input CSI value as the RTS value, The held RTS value is output based on the input output control signal.
[0017]
As described above, the problem that the RTS value 113 is lost when even one of the four ATM cells 101 having the odd SC value is lost does not occur. A method for dealing with the RTS value 113 when one ATM cell 101 is lost is described in ITU-T Recommendation I.T. 363.1 does not specify a clear method.
[0018]
When this method is applied to an interface of DS1 (1.544 Mb / s), which is a kind of transmission speed hierarchy, in order to generate one RTS value 113, it is accommodated in eight cells. Assuming that the number of bits of a signal is 3008, the number of bits of one frame of DS1 is 193, and the period of one frame of DS1 is 0.125 ms,
3008/193 × 0.125 = about 2 ms
, It is understood that the effect of the loss of one ATM cell 101 on the SRTS scheme is very large.
[0019]
As a specific example in the present embodiment, for example, when the cell with SC = 3 is lost, that is, when the SN sequencer unit 4 indicates that there is an error in the cell with SC = 3, the RTS value output control unit 12 In order to output the CSI value of SC = 2 to the RTS buffer unit 11 instead of outputting the CSI value of SC = 3 to the RTS buffer unit 11, the CSI value 139 of SC = 2 is output to the selector unit 13 by the SC = The selector is switched so that the CSI value of 3 is output to the RTS buffer unit 11. Then, the RTS value 113 complemented according to the output control signal 146 is output from the RTS buffer unit 11.
[0020]
As described above, the ATM cell assembling / disassembling device of the clock reproducing device according to the present embodiment converts a CBR (Constant Bit Rate) signal into an ATM cell by the AAL1 Unstructured Mode at the transmission source. 7 and the CBR clock information is mapped to the RTS (Residual Time Stamp) value in the SAR-PDU header, which is the AAL1 header, by the SRTS (Synchronous Residual Time Stamp) method. A device for reproducing a clock of a transmission source CBR signal from RTS information together with a Sequence Number check on a receiving side, wherein the RTS value is corrected using a CSI bit. That.
[0021]
Further, the ATM cell assembling / disassembling apparatus of the clock recovery apparatus according to the present embodiment tries to extract the RTS information from four cells having an odd sequence count, but the sequence count is lost due to the lack of one cell. If 4 bits cannot be extracted, or if it is determined that the error check (even parity check and CRC check) of one cell is invalid, the CSI bit of the cell having the even sequence count is added to complement the RTS value of the cell. This is an ATM cell assembling / disassembling apparatus having means for complementing the RTS value of the cell and making the RTS information valid without discarding, and using the clock for reproduction.
In other words, the present ATM cell disassembly / assembly apparatus determines that one of the plurality of ATM cells in the RTS cycle is missing, and that the ATM cells before and after the missing ATM cell are valid. In this case, the previous SC value complements the currently extracted RTS value using the CSI value of the even-numbered ATM cell. That is, when data is transferred using the AAL1 protocol, there is an SRTS method as a method of transferring clock information of a transmission source. In the SRTS system, RTS information is transferred using a plurality of ATM cells. Conventionally, the operation at the time of the loss of the RTS method is not particularly specified, and even one cell is lost, so that the RTS information in the RTS cycle is discarded. However, in the case of one cell loss, the other RTS information is valid, so that the RTS information is made valid by losing from the CSI bit of the even SC value and complementing the bit. .
[0022]
As described above, the present RTS complementation method does not invalidate all the RTS values extracted in the RTS cycle even when one odd-numbered SC cell in the SC = 0 to 7 in the RTS cycle is lost. Since it is valid, skipping of the RTS value at the time of discarding can be avoided, and the jitter amount of the line clock reproduced from the RTS value due to this can be suppressed.
[0023]
Embodiment 2 FIG.
Hereinafter, Embodiment 2 will be described with reference to the drawings. This control operates when the error signal is received once or less in the RTS cycle.
FIG. 12 is a block diagram showing the RTS complement method according to the second embodiment for the inside of the RTS processing unit 7 shown in FIG.
12, the RTS processing unit 7 has an RTS error correction unit 14 instead of the selector unit 13 in FIG. Other configurations are the same as those of the first embodiment.
[0024]
The input unit has a clock information at the predetermined position and further inputs an asynchronous transfer system cell having an error correction code at a position different from the predetermined position.
As an example of the error correction unit, the RTS error correction unit 14 corrects the clock information based on the error correction code of the asynchronous transfer system cell input from the input unit.
As an example of the clock information output unit, the RTS buffer unit 11 outputs the clock information corrected by the error correction unit to the clock generation unit.
[0025]
Here, the SAR-PDU header of the asynchronous transfer system cell has a 1-bit EP value, a 3-bit CRC value, a 4-bit SN value, and an error correction code. Then, as in the first embodiment, the clock information is an RTS value constituted by the CSI value.
The SN sequencer 4 includes a 3-bit SC value 107 included in the extracted SAR-PDU header 102, an EP check result 103 as a check result by the EP checker 2, and a CRC check result 106 as a check result by the CRC checker 3. And outputs a decision result 108 of whether to accept the input ATM cell 101, to accept the dummy by inserting the Dummy, or to discard the received ATM cell 101, and to output the odd SC value 107 = 1, 3, 5, 7 If it is determined that the SN has been lost due to any bit error or loss, the clear control signal 109 is output. On the other hand, any of the odd SC values 107 = 1, 3, 5, and 7 has a bit error. Output a write control signal 110 when all SNs are determined to be valid without any And outputs an error signal 115 and the error SC value 116 if there is any bit errors or omissions 7 = 0-7. In other words, the SN sequencer unit 4 determines the 3-bit SC value of the SAR-PDU header extracted by the SAR-PDU header extraction unit 1 and the check result of the parity check performed by the EP check unit. It is determined whether a predetermined SN value having an odd SC value is valid or invalid based on the result of the CRC check performed by the CRC checker, and further extracted by the SAR-PDU header extractor. It is determined whether or not there is an error based on the error correction code of the SAR-PDU header, and the predetermined SN value having an odd SC value is determined by at least one of a bit error and a missing bit. The SAR-PDU header extracted by the SAR-PDU header extraction unit while being determined to be valid is A clear signal indicating an instruction to delete the CSI value of the predetermined SN value determined to have an error when an error correction code determines that there is an error, and an error signal indicating an error and an error And outputting the error SC value of the predetermined SN value determined to be present. If the predetermined SN value is not determined to be incorrect, the CSI value of the predetermined SN value is used as the RTS value. It outputs a write control signal for writing.
The RTS processing unit 7 uses the 4-bit SN value 105 included in the extracted SAR-PDU header 102, the clear control signal 109, the write control signal 110, the error signal 115, and the SC value with an error from the SN sequencer unit 4. An error SC value 116 is input, and a 4-bit RTS value 113 is output.
[0026]
The details are described below.
The RTS value output control unit 12 receives the error signal 115 and the error SC value 116, the clear control signal 109, and the write control signal 110 from the SN sequencer unit 4, outputs a read control signal 136 to the SN buffer unit 10, and outputs an RTS error. An error correction execution signal 151, a clear control signal 152, and an output control signal 153 are output to the correction unit 14. In other words, the RTS value output control unit 12 inputs each SC value from the SAR-PDU header extraction unit 1 and, when the SN sequencer unit 4 determines that there is an error, the SN sequencer unit 4 An error that inputs the output clear signal, error signal, and error SC value, and that prompts the user to correct the CSI value of the predetermined SN value based on the input clear signal, error signal, and error SC value. A correction execution signal and an output control signal for prompting to output a CSI value corrected based on the error correction execution signal as the RTS value are generated, and the output control signal having the SC value is provided based on each input SC value. A read control signal for prompting to read the CSI value of the SN value is generated.
The SN buffer unit 10 holds the CSI value extracted by the SAR-PDU header extraction unit 1 according to the SC value similarly extracted by the SAR-PDU header extraction unit 1. The SN buffer unit 10 outputs the 8-bit CSI value to the RTS error correction unit 14 according to the read control signal 136 from the RTS value output control unit 12. In other words, the SN buffer unit 10 inputs each SN value included in the SAR-PDU header extracted by the SAR-PDU header extraction unit 1 and performs the above-described operation in accordance with the SC value of each of the input SN values. Each CSI value held by each SN value is held, a read control signal generated by the RTS value output control unit 12 is input, and each held CSI value is read based on the input read control signal.
The RTS error correction unit 14 receives the 8-bit CSI value from the SN buffer unit 10 and the error correction execution signal 151 from the RTS value output control unit 12, and outputs the RTS value 113 after error detection and correction to the RTS buffer unit 11. Further, the RTS error correction unit 14 clears the held CSI value when the clear control signal 109 is input from the RTS value output control unit 12, and when the output control signal 153 is input, the RTS error correction unit 14 determines that the error correction execution result is normal. When it is determined that a proper RTS value can be restored, the output signal 154 indicating an output instruction is output to the RTS buffer unit 11. If the data cannot be restored, the CSI value and the RTS value in the RTS error correction unit 14 are cleared. In other words, as an example of the error correction unit, the RTS error correction unit 14 includes the CSI values read by the SN buffer unit 10, the clear signal generated by the RTS value output control unit 12, and the error correction execution signal. And corrects the CSI value of the predetermined SN value based on the input error correction execution signal, and corrects the CSI value of the predetermined SN value based on the input error correction execution signal If not, the CSI value of the predetermined SN value is deleted based on the input clear signal.
The RTS buffer unit 11 outputs an RTS value 113 according to the output signal 154 from the RTS error correction unit 14. In other words, when corrected by the error correction unit, the RTS buffer unit 11 inputs the CSI value of the predetermined SN value corrected by the error correction unit and generates the CSI value by the RTS value output control unit 12. The received output control signal is input, the input CSI value is held as the RTS value, and based on the input output control signal, the held RTS value is output. , Does not output the RTS value.
[0027]
As described above, the ATM cell assembling / disassembling device of the clock reproducing device according to the present embodiment converts a CBR (Constant Bit Rate) signal into an ATM cell by the AAL1 Unstructured Mode at the transmission source. No. 7 (Sequence Count) and the clock information of the CBR thereof are converted to an AAL1 header by using an SRTS (Synchronous Residual Time Stamp) method and a CRC-3 code which is an error correction code for an RTS (Residual Time Stamp) value and an RTS value. An ATM cell of a device that maps and transfers in a SAR-PDU header that is a CBR signal of a transmission source from the RTS information together with a Sequence Number check on the receiving side. In the stand-cracking unit,
An attempt was made to extract RTS information from four cells having an odd sequence count, but the error check (even parity check and CRC check) of one cell failed despite the error in the SAR-PDU header of one cell. This ATM cell assembling / disassembling apparatus has means for correcting the RTS value of the cell when it is determined to be valid, thereby using normal RTS information for clock recovery.
[0028]
The present ATM cell disassembly / assembly apparatus is capable of detecting an error when the CSI value of one ATM cell among the plurality of ATM cells in the RTS cycle is incorrect and the error control of the SAR-PDU header fails to detect an error. When it is determined that the RTS value is valid, the RTS value can be protected by adding, for example, a CRC-3 code as an error correction code to the 4-bit RTS value.
In addition, since the RTS cycle is monitored, it is possible to avoid that the cell having the odd SC value has an erroneous RTS value by inverting the order of eight cells, and thereby the line clock of the line clock reproduced from the RTS value can be prevented. It is possible to suppress the amount of jitter.
[0029]
Embodiment 3 FIG.
Hereinafter, the third embodiment will be described with reference to the drawings.
FIG. 13 is a block diagram showing a configuration inside the SN sequencer unit according to the third embodiment.
In FIG. 13, the SN sequencer unit 4 includes an SNP inspection unit 8, an SN inspection unit 9, an OP inspection unit 15, and a comprehensive inspection unit 16. Other configurations are the same as those in FIG.
As an example of a clock generation device, an ATM cell disassembly / assembly device generates a clock signal using clock information included in a received communication signal. Here, the clock information is an RTS value constituted by the CSI value, as in the first embodiment.
The input unit inputs a first asynchronous transfer method cell having a first predetermined information at a predetermined position and a second asynchronous transfer method cell having a second predetermined information at the predetermined position.
The SNP inspection unit 8 receives the EP inspection result 103 from the EP inspection unit 2 and the CRC inspection result 106 from the CRC inspection unit 3 and outputs an SNP inspection result 121 as a result of determining whether the SN is valid SN or invalid SN.
The SN inspection unit 9 inputs the 3-bit SC value 107 included in the extracted SAR-PDU header 102 and the SNP inspection result 121 as a check result by the SNP inspection unit 8, and either accepts the ATM cell 101 or selects Dummy. Is inserted, and an SN inspection result 122 is output as a result of determining whether to Accept or Discard.
The OP checking unit 15 performs an Odd Parity check on CSI bits of two consecutive cells having an even SC value and an odd SC value based on the CSI bits and the SC values included in the extracted SAR-PDU header 102. , RTS cycle number is extracted and output. In other words, as an example of the exclusive OR operation unit, the OP checking unit 15 inputs the SN values of the SAR-PDU headers extracted by the SAR-PDU header extraction unit 1 and inputs the input SN values. Are exclusive of a CSI value of a predetermined SN value having an odd SC value and a CSI value of a predetermined SN value having an even SC value before or after the odd SC value. Perform a logical sum operation. Furthermore, in other words, as an example of the operation unit, the OP checking unit 15 includes the first predetermined information of the first asynchronous transfer system cell input by the input unit and the second predetermined information of the second asynchronous transfer system cell. The calculation is performed using the second predetermined information.
When the SN inspection result 122 as the determination result from the SN inspection unit 9 and the RTS cycle number as the OP inspection result 123 from the OP inspection unit 15 are input, the SN comprehensive inspection unit 16 determines that the RTS cycle is normal. If it is determined, a write control signal 110 is output, and if it is determined that the RTS cycle is incorrect, a clear control signal 109 is output. In addition, the SN comprehensive inspection unit 16 outputs the check result 122 by the SN inspection unit 9 as the determination result 108 as it is. In other words, as an example of the detecting unit, when the value of the exclusive OR operation performed by the exclusive OR operation unit becomes 1 as an example of the detecting unit, the SN total checking unit 16 corrects the reception order of the asynchronous transfer system cells. If the value does not become 1, the receiving order of the cells of the asynchronous transfer method is detected as being erroneous. Further, in other words, as an example of the detection unit, the SN comprehensive inspection unit 16 detects whether the clock information is correct or not based on a result calculated by the calculation unit based on a predetermined reference.
As an example of the complementary output unit, the RTS processing unit 7 writes and writes the CSI value of the predetermined SN value having the odd SC value as the RTS value when the detection unit detects the positive value. Outputs RTS value. In other words, as an example of the output unit, the RTS processing unit 7 is configured to, when the clock information is detected by the detection unit to be positive, to output the first predetermined value of the first asynchronous transfer mode cell input by the input unit. Is output as clock information, and when the clock information is erroneously detected by the detection unit, the first predetermined information included in the first asynchronous transfer mode cell input by the input unit is output to the clock information. Do not output as
When the output unit outputs the first predetermined information as clock information, the clock generation unit 50 inputs the clock information and generates a clock signal using the input clock information.
[0030]
As a specific example in the present embodiment, for example, a 2-bit XOR of a CSI bit of a cell having an SC value of 107 = 0 (even SC value) and a CSI bit of a cell having an SC value of 107 = 1 (odd SC value) And if the result is “1”, the RTS cycle is “1”. During one RTS cycle, since the same RTS cycle is used, the number of RTS cycles has the same value. However, if the RTS numbers are different, it is possible that the order of 8 cells has been reversed, so that an erroneous RTS value is generated. Therefore, a clear control signal 109 is output to the RTS processing unit 7 instead of the write control signal 110 so as not to output an incorrect RTS value.
[0031]
As described above, the ATM cell assembling / disassembling device of the clock reproducing device according to the present embodiment converts a CBR (Constant Bit Rate) signal into an ATM cell by the AAL1 Unstructured Mode at the transmission source. The RTS value and the 1-bit identifier (RTS Loop Indication) for determining the RTS value and its cycle are mapped in the SAR-PDU, which is the AAL1 header, by using the continuous number 7 (Sequence Count) and the CBR clock information by the SRTS method. In the apparatus for reproducing the clock of the transmission source CBR signal from the RTS information together with the Sequence Number check on the receiving side,
An ATM cell assembling / disassembling apparatus having means for using RTS Loop Indication so as not to extract erroneous RTS information when RTS information is extracted from four cells having odd-numbered Sequence Counts.
[0032]
The present ATM cell disassembly / assembly apparatus determines that, among a plurality of ATM cells in a continuous 2RTS cycle, when the order is reversed for one RTS cycle (8 cells), all the ATM cells are valid. In this case, an output of an erroneous RTS value due to the inversion of the order of eight cells can be avoided by adding an identification code for identifying two consecutive RTS periods to an ATM cell having an even SC value.
In addition, since the RTS cycle is monitored, it is possible to avoid that the cell having the odd SC value has an erroneous RTS value by inverting the order of eight cells, and thereby the line clock of the line clock reproduced from the RTS value can be prevented. It is possible to suppress the amount of jitter.
[0033]
Embodiment 4 FIG.
Hereinafter, Embodiment 4 will be described. Each configuration is the same as in FIG.
The input unit has a SAR-PDU header extraction unit 1 and a cell buffer unit 5. The input unit inputs a first asynchronous transfer method cell having a first predetermined information at a predetermined position and a second asynchronous transfer method cell having a second predetermined information at the predetermined position.
As an example of the output unit, the RTS processing unit 7 outputs, as clock information, first predetermined information of the first asynchronous transfer mode cell input by the input unit, and outputs the second predetermined information by the second unit input by the input unit. And outputs the second predetermined information of the asynchronous transfer type cell as format information of the communication signal.
The clock generation unit 50 receives the first predetermined information output from the output unit as clock information, and generates a clock signal using the input clock information.
The cell processing unit 6 inputs the second predetermined information output from the output unit as format information of the communication signal, and based on the input format information, the first asynchronous transfer system cell and the second With the asynchronous transfer method cell.
[0034]
The RTS process is the same as the conventional technology. The difference is that the number of CSI bit extraction and format identification processes for ATM cells having even SC values has been increased. The extraction of CSI bits is similar to that of ATM cells with odd SC values, and the format is determined from the four CSI bits. After that, the ATM cell is processed according to the format.
[0035]
As described above, the ATM cell assembling / disassembling apparatus of the apparatus for reproducing a clock according to the present embodiment converts the CBR signal into an ATM cell by using the Unstructured Mode of AAL1 at the transmission source, and in this case, a continuous number of 0 to 7 ( Sequence Count) and the clock information of the CBR by the SRTS method by mapping the RTS value into the SAR-PDU which is the AAL1 header and transferring the same. The receiving side together with the Sequence Number check checks the clock of the transmission source CBR signal from the RTS information. Device for reproducing
An ATM cell assembling / disassembling apparatus having means for using RTS information for clock recovery and using a 4-cell SAR-PDU header having an even-numbered Sequence Count in order to restore a special format incorporated when converting to an ATM cell. .
[0036]
This ATM cell disassembly / assembly apparatus can insert format information into CSI bits of an ATM cell having an even SC value on the transmitting side, and restore the original format from the information on the receiving side.
Further, by using the CSI bit of the ATM cell having the even SC value, it is possible to incorporate a new special format without reducing the data area.
[0037]
In the description of the above embodiment, what is described as “—unit” can be partially or entirely configured by a computer-operable program. These programs can be created in C language, for example. Alternatively, HTML, SGML, or XML may be used. Alternatively, the screen display may be performed using JAVA (registered trademark).
In addition, what is described as “-unit” in the description of the embodiments may be realized by firmware stored in a ROM (Read Only Memory). Alternatively, the present invention may be implemented by software, hardware, or a combination of software, hardware, and firmware.
Further, a program for executing the above embodiments is recorded on a recording medium. As a recording medium, a recording device using another recording medium such as a magnetic disk device, an FD (flexible disk), an optical disk, a CD (compact disk), an MD (mini disk), and a DVD (Digital Versatile Disk) may be used.
[0038]
【The invention's effect】
According to the present invention, even when an odd SC cell in SC = 0 to 7 in the RTS cycle loses one cell, the RTS values extracted in the RTS cycle are made valid rather than invalid. The jump of the RTS value when discarded can be avoided, and the jitter amount of the line clock reproduced from the RTS value due to this can be suppressed.
[Brief description of the drawings]
FIG. 1 shows ITU-T Recommendation I. FIG. 2 is a diagram showing the structure of a cell defined in 363.1.
FIG. 2 is a diagram illustrating an AAL1 ATM cell to be transmitted.
FIG. 3 is a diagram showing each format of a P format and a non-P format.
FIG. 4 is a diagram illustrating an SRTS method in AAL1 processing.
FIG. 5 is a block diagram illustrating a configuration of an ATM cell disassembly / assembly apparatus that performs AAL1 processing according to the first embodiment.
FIG. 6 is a block diagram showing an internal configuration of an SN sequencer unit.
FIG. 7 is a diagram showing a state transition of a check of an SNP field relating to AAL1 processing.
FIG. 8 is a diagram illustrating an error check state transition of a Sequence Number check regarding the AAL1 processing unit;
FIG. 9 is a diagram illustrating a state transition of a Sequence Number check related to the AAL1 process.
FIG. 10 is a table showing a state transition of a Sequence Number check regarding the AAL1 processing unit.
FIG. 11 is a block diagram showing the inside of an RTS processing unit shown in FIG. 5;
FIG. 12 is a block diagram showing an RTS complementing method according to a second embodiment for the inside of the RTS processing unit 7 shown in FIG. 5;
FIG. 13 is a block diagram showing a configuration inside an SN sequencer unit according to a third embodiment.
[Explanation of symbols]
1 SAR-PDU header extraction unit, 2 EP inspection unit, 3 CRC inspection unit, 4 SN sequencer unit, 5 cell buffer unit, 6 cell processing unit, 7 RTS processing unit, 8 SNP inspection unit, 9 SN inspection unit, 10 SN Buffer unit, 11 RTS buffer unit, 12 RTS value output control unit, 13 selector unit, 14 RTS error correction unit, 15 OP inspection unit, 16 comprehensive inspection unit, 50 clock generation unit.

Claims (12)

A clock generation device that generates a clock signal for receiving the communication signal using clock information included in the received communication signal,
An input unit that has predetermined information at a predetermined position and inputs the communication signal transferred by the asynchronous transfer method as a plurality of asynchronous transfer method cells,
Among the plurality of asynchronous transfer method cells input by the input unit, a predetermined asynchronous transfer method cell outputs the predetermined information having the predetermined position as the clock information, and when the clock information needs to be complemented, Among the plurality of asynchronous transfer method cells, the asynchronous transfer method cell different from the predetermined asynchronous transfer method cell uses the predetermined information having the predetermined position to supplement the clock information, and the complemented clock is used. A complement output unit for outputting information,
A clock generator configured to generate the clock signal using the clock information output from the complementary output unit. The input unit includes: a first asynchronous transfer method cell having clock information at the predetermined position; and a second asynchronous transfer method cell having clock alternative information serving as alternative information of the clock information at the predetermined position. Will be entered,
The clock generation unit generates a clock signal of the communication signal using clock information of the first asynchronous transfer method cell,
The above-mentioned complementary output unit,
If the first asynchronous transfer mode cell that is to be input by the input unit is not input and the second asynchronous transfer system cell is input, the second asynchronous transfer system cell input by the input unit A selection unit that selects the clock alternative information included in place of the clock information included in the first asynchronous transfer mode cell;
2. The clock generation device according to claim 1, further comprising: a clock information output unit that outputs the clock alternative information selected by the selection unit instead of the clock information included in the first asynchronous transfer mode cell. The input unit has clock information at the predetermined position, and further inputs an asynchronous transfer system cell having an error correction code at a position different from the predetermined position,
The above-mentioned complementary output unit,
An error correction unit that corrects the clock information based on an error correction code of the asynchronous transfer system cell input by the input unit,
2. The clock generation device according to claim 1, further comprising a clock information output unit that outputs the clock information corrected by the error correction unit to the clock generation unit. A clock generation device that generates a clock signal using clock information included in a communication signal to be received,
An input unit for inputting a first asynchronous transfer method cell having a first predetermined information at a predetermined position, and a second asynchronous transfer method cell having a second predetermined information at the predetermined position;
An operation unit that performs an operation using the first predetermined information of the first asynchronous transfer system cell and the second predetermined information of the second asynchronous transfer system cell input by the input unit;
Based on the result calculated by the calculation unit, a detection unit that corrects the clock information on a predetermined basis based on a predetermined reference, and when the clock information is detected to be correct by the detection unit, 1st asynchronous transfer mode, the first predetermined information included in the cell is output as clock information, and when the clock information is erroneously detected by the detection unit, the first asynchronous transfer mode input by the input unit is output. An output unit that does not output first predetermined information included in the cell as clock information;
And a clock generation unit that, when the first predetermined information is output as clock information by the output unit, inputs the clock information and generates a clock signal using the input clock information. A clock generation device characterized by the following. An input unit for inputting a first asynchronous transfer method cell having a first predetermined information at a predetermined position, and a second asynchronous transfer method cell having a second predetermined information at the predetermined position;
The first predetermined information included in the first asynchronous transfer method cell input by the input unit is output as clock information, and the second predetermined information included in the second asynchronous transfer method cell input by the input unit is output. An output unit that outputs information as format information of the communication signal,
A clock generation unit that inputs the first predetermined information output from the output unit as clock information, and generates a clock signal using the input clock information;
The second predetermined information output by the output unit is input as format information of the communication signal, and based on the input format information, the first asynchronous transfer method cell and the second asynchronous transfer method cell And a cell processing unit for processing the data. The asynchronous transfer method cell is an 8-bit SAR-PDU (Segmentation And Reassembly) having a 1-bit EP (Even Parity) value, a 3-bit CRC (Cyclic Redundancy Check) value, and a 4-bit SN (Sequence Number) value. sub-Protocol Data Unit) header,
The SN value has a 1-bit Convergence Sublayer Indication (CSI) value and a 3-bit SC (Sequence Count) value,
The clock information is an RTS (Residual Time Stamp) value composed of the CSI value,
The input unit has a SAR-PDU header extraction unit that inputs a plurality of asynchronous transfer method cells and extracts the SAR-PDU header from each of the asynchronous transfer method cells of the input plurality of asynchronous transfer method cells,
The clock generation device further includes:
An EP inspection unit that performs an even parity check on an 8-bit SAR-PDU header based on the 1-bit EP value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, and outputs a parity check result. When,
Based on the 3-bit CRC value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, a 4-bit SN value and a 3-bit CRC value are subjected to a CRC check for a total of 7 bits. A CRC inspection unit to output;
The 3-bit SC value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, the check result of the parity check performed by the EP check unit, and the CRC check by the CRC check unit are performed. It is determined whether the predetermined SN value having an odd SC value is invalid or valid based on the check result of the CRC check, and the predetermined SN value having the odd SC value is at least one of a bit error and a loss. When the predetermined SN value is determined to be invalid, a clear signal indicating an instruction to delete the CSI value of the predetermined SN value determined to be invalid is output, and the predetermined SN value is determined to be valid. The SN sequence that outputs a write control signal for writing the CSI value of the predetermined SN value as the RTS value when the And a support portion,
The supplementary output unit, when the SN sequencer unit determines that the predetermined SN value is invalid, the 4-bit SN value of the SAR-PDU header extracted by the SAR-PDU header extraction unit; The clear signal output by the SN sequencer unit is input, and the CSI value of the SN value having an even SC value different from the SC value of the predetermined SN value is converted to the RTS based on the input clear signal. If the predetermined SN value is determined to be valid by the SN sequencer unit, the CSI value of the predetermined SN value is converted to the RTS based on the write control signal output by the SN sequencer unit. 2. The clock generation device according to claim 1, wherein the RTS value is written as a value and the written RTS value is output. The above-mentioned complementary output unit,
The SC value is input from the SAR-PDU header extraction unit, and when the predetermined SN value is determined to be invalid by the SN sequencer unit, the clear signal output by the SN sequencer unit is input and input. Based on the clear signal and the SC value, a read control signal prompting to read the CSI value of the SN value having the SC value, and the SC having the predetermined SN value instead of the CSI value of the predetermined SN value A selection control signal for prompting selection of a CSI value of an SN value having an even SC value different from the value, and output control for prompting output of the CSI value selected based on the selection control signal as the RTS value. And outputs the generated read control signal, selection control signal, and output control signal, and the SN sequencer section has the predetermined SN value. When it is determined that the read control signal prompting to read the CSI value of the SN value having the SC value and the SN value having the SC value are based on the write control signal output by the SN sequencer section, A selection control signal that prompts the user to select a CSI value having the output signal and an output control signal that prompts the user to output the CSI value selected based on the selection control signal as the RTS value. An RTS value output control unit that outputs a selection control signal and an output control signal;
Each SN value of the SAR-PDU header extracted by the SAR-PDU header extraction unit is input, and each CSI value of each SN value is held corresponding to the SC value of each input SN value. When the predetermined SN value is determined to be invalid by the SN sequencer unit, a clear signal and a read control signal generated by the RTS value output control unit are input from the RTS value output control unit. The CSI value of the predetermined SN value determined to be invalid is deleted from each of the stored CSI values based on the cleared signal that has been stored, and stored after being deleted based on the input read control signal. Read out each CSI value of each SN value having each SC value from the obtained CSI values, and when the predetermined SN value is determined to be valid by the SN sequencer unit, A read control signal generated by the RTS value output control unit is input, and based on the input read control signal, each CSI value of each SN value having each SC value is selected from among the held CSI values. An SN buffer unit for reading
Each of the CSI values read by the SN buffer unit and the selection control signal generated by the RTS value output control unit are input, and the predetermined SN is output by the SN sequencer unit based on the input selection control signal. When the value is determined to be invalid, a CSI value having an even SC value different from the SC value having the predetermined SN value is selected instead of the CSI value having the predetermined SN value. A selector unit that selects a CSI value of an SN value having an odd SC value among the SC values when the predetermined SN value is determined to be valid by the SN sequencer unit;
A CSI value of an SN value having an even SC value different from the SC value of the predetermined SN value selected by the selector unit, and a CSI value of an SN value having an odd SC value among the SC values Value, an output control signal generated by the RTS value output control unit is input, the input CSI value is held as the RTS value, and the output CSI value is held based on the input output control signal. 7. The clock generation device according to claim 6, further comprising an RTS buffer unit that outputs the RTS value obtained. The asynchronous transfer system cell includes a SAR-PDU (Segmentation And) having a 1-bit EP (Even Parity) value, a 3-bit CRC (Cyclic Redundancy Check) value, a 4-bit SN (Sequence Number) value, and an error correction code. A Reassembly sublayer-Protocol Data Unit) header,
The SN value has a 1-bit Convergence Sublayer Indication (CSI) value and a 3-bit SC (Sequence Count) value,
The clock information is an RTS (Residual Time Stamp) value composed of the CSI value,
The input unit has a SAR-PDU header extraction unit that inputs a plurality of asynchronous transfer method cells and extracts the SAR-PDU header from each of the asynchronous transfer method cells of the input plurality of asynchronous transfer method cells,
The clock generation device further includes:
An EP inspection unit that performs an even parity check on an 8-bit SAR-PDU header based on the 1-bit EP value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, and outputs a parity check result. When,
Based on the 3-bit CRC value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, a 4-bit SN value and a 3-bit CRC value are subjected to a CRC check for a total of 7 bits. A CRC inspection unit to output;
The 3-bit SC value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, the check result of the parity check performed by the EP check unit, and the CRC check by the CRC check unit are performed. Based on the check result of the CRC check, it is determined whether a predetermined SN value having an odd SC value is valid or invalid. Further, the error correction of the SAR-PDU header extracted by the SAR-PDU header extraction unit is performed. It is determined whether there is an error based on the code, and the SAR-PDU header is determined while the predetermined SN value having an odd SC value is determined to be valid by at least one of a bit error and a missing bit. The SAR-PDU header extracted by the extraction unit determines that there is an error due to the error correction code of the header. In this case, a clear signal indicating an instruction to delete the CSI value of the predetermined SN value determined to have an error, an error signal indicating an error, and the predetermined SN determined to have an error. An error SC value included in the SN value, and if the predetermined SN value is not determined to be erroneous, an SN for outputting a write control signal for writing the CSI value included in the predetermined SN value as the RTS value With a sequencer section,
The above-mentioned complementary output unit,
Each SC value is input from the SAR-PDU header extraction unit, and when it is determined that there is an error by the SN sequencer unit, a clear signal, an error signal, and an error SC value output by the SN sequencer unit are output. The correction is performed based on the input clear signal, the error signal, and the error SC value, based on the error correction execution signal and the error correction execution signal that prompt the correction of the CSI value of the predetermined SN value. And an output control signal for prompting to output the read CSI value as the RTS value, and a read control signal for prompting to read the CSI value of the SN value having the SC value based on each of the input SC values. RTS value output control unit for generating
Each SN value of the SAR-PDU header extracted by the SAR-PDU header extraction unit is input, and each CSI value of each SN value is held corresponding to the SC value of each input SN value. An SN buffer unit that inputs a read control signal generated by the RTS value output control unit and reads out each held CSI value based on the input read control signal;
Each of the CSI values read by the SN buffer unit, the clear signal and the error correction execution signal generated by the RTS value output control unit are input, and the predetermined SN is executed based on the input error correction execution signal. The CSI value of the predetermined value is corrected based on the input error correction execution signal, and the predetermined SN value of the predetermined SN value is determined based on the input clear signal when the CSI value of the predetermined SN value cannot be corrected. An error correction unit for deleting a CSI value;
When the error is corrected by the error correction unit, a CSI value of the predetermined SN value corrected by the error correction unit is input, and an output control signal generated by the RTS value output control unit is input. And an RTS buffer unit that outputs the held RTS value based on the input output control signal, and outputs no RTS value when the error cannot be corrected by the error correction unit. The clock generation device according to claim 1, further comprising: The asynchronous transfer method cell is an 8-bit SAR-PDU (Segmentation And Reassembly) having a 1-bit EP (Even Parity) value, a 3-bit CRC (Cyclic Redundancy Check) value, and a 4-bit SN (Sequence Number) value. sub-Protocol Data Unit) header,
The SN value has a 1-bit Convergence Sublayer Indication (CSI) value and a 3-bit SC (Sequence Count) value,
The clock information is an RTS (Residual Time Stamp) value composed of the CSI value,
The input unit has a SAR-PDU header extraction unit that inputs a plurality of asynchronous transfer method cells and extracts the SAR-PDU header from each of the asynchronous transfer method cells of the input plurality of asynchronous transfer method cells,
The clock generation device further includes:
An EP inspection unit that performs an even parity check on an 8-bit SAR-PDU header based on the 1-bit EP value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, and outputs a parity check result. When,
Based on the 3-bit CRC value of the SAR-PDU header extracted by the SAR-PDU header extraction unit, a 4-bit SN value and a 3-bit CRC value are subjected to a CRC check for a total of 7 bits. A CRC inspection unit to output;
An SN value included in each SAR-PDU header extracted by the SAR-PDU header extraction unit is input, and among the input SN values, a CSI value included in a predetermined SN value having an odd SC value and the odd number are input. An exclusive-OR operation unit that performs an exclusive-OR operation on a CSI value of a predetermined SN value having an even SC value before or after the SC value of
As a result of the exclusive OR operation performed by the exclusive OR operation unit, when the value becomes 1, the receiving order of the asynchronous transfer system cell is detected as positive. When the value does not become 1, the asynchronous transfer system cell is detected. A detection unit for detecting that the reception order of the
The complement output unit writes the CSI value of the predetermined SN value having the odd SC value as the RTS value and outputs the written RTS value when the detection unit detects the positive value. The clock generation device according to claim 1, wherein A clock generation method for generating a clock signal for receiving the communication signal using clock information included in the received communication signal,
An input step of inputting the communication signal transferred by an asynchronous transfer method as a plurality of asynchronous transfer method cells, having predetermined information at a predetermined position,
Among the plurality of asynchronous transfer method cells input by the input step, a predetermined asynchronous transfer method cell outputs the predetermined information having the predetermined position as the clock information, and when the clock information needs to be complemented, Among the plurality of asynchronous transfer method cells, the asynchronous transfer method cell different from the predetermined asynchronous transfer method cell uses the predetermined information having the predetermined position to supplement the clock information, and the complemented clock is used. A complementary output step of outputting information,
A clock generation step of generating the clock signal using the clock information output in the complementary output step. A program that causes a computer to execute a process of generating a clock signal for receiving the communication signal using clock information included in the received communication signal,
Having predetermined information at a predetermined position, input processing for inputting the communication signal transferred by the asynchronous transfer method as a plurality of asynchronous transfer method cells,
Among the plurality of asynchronous transfer method cells input by the input process, a predetermined asynchronous transfer method cell outputs the predetermined information having the predetermined position as clock information, and when the clock information needs to be complemented, Among the plurality of asynchronous transfer method cells, the asynchronous transfer method cell different from the predetermined asynchronous transfer method cell uses the predetermined information having the predetermined position to supplement the clock information, and the complemented clock is used. Complementary output processing to output information,
A program for causing a computer to execute a clock generation process of generating the clock signal using the clock information output by the complementary output process. A computer-readable recording medium that records a program that causes a computer to execute a process of generating a clock signal for receiving the communication signal using the clock information included in the received communication signal,
Having predetermined information at a predetermined position, input processing for inputting the communication signal transferred by the asynchronous transfer method as a plurality of asynchronous transfer method cells,
Among the plurality of asynchronous transfer method cells input by the input process, a predetermined asynchronous transfer method cell outputs the predetermined information having the predetermined position as clock information, and when the clock information needs to be complemented, Among the plurality of asynchronous transfer method cells, the asynchronous transfer method cell different from the predetermined asynchronous transfer method cell uses the predetermined information having the predetermined position to supplement the clock information, and the complemented clock is used. Complementary output processing to output information,
A computer-readable recording medium recording a program for causing a computer to execute a clock generation process of generating the clock signal using the clock information output by the complementary output process.

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