JP2004199804A - Reference potential generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory of an 1T1C constitution in which the operation margin of a reference circuit can be expanded and which demonstrates a high yield and high reliability. <P>SOLUTION: A reference potential generating circuit of a ferroelectric memory is provided with memory cells CR00 to CR02, CR10 to CR12 storing m pieces of high level data and memory cells CR03 to CR13 storing n pieces of low level data. Here, m and n are set to an arbitrary number being not identical. A reference potential is generated by averaging these memory cells. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a reference potential generation circuit for a ferroelectric memory.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a ferroelectric memory device that realizes non-volatility of stored data by using a ferroelectric material for a capacitor of a memory cell has been devised. The ferroelectric capacitor has a hysteresis characteristic, and even when the electric field is zero, remnant polarization having different polarities according to the history remains. A nonvolatile memory device is realized by expressing stored data by remanent polarization of a ferroelectric capacitor.
[0003]
U.S. Pat. No. 4,873,664 discloses two types of ferroelectric memory devices. The first type is one in which a memory cell is constituted by one transistor and one capacitor (1T1C) per bit. For example, every 256 ferroelectric capacitors for a main body memory cell (normal cells) One ferroelectric capacitor for reference memory cells is provided.
[0004]
In the second type, a memory cell is constituted by two transistors and two capacitors (2T2C) per bit without providing a ferroelectric capacitor for a reference memory cell. Is stored in the pair of ferroelectric capacitors for the main body memory cell.
[0005]
The 1T1C type is advantageous in increasing the capacity of the memory. At this time, the ferroelectric capacitor for the reference cell should be designed with respect to the ferroelectric capacitor for the main memory cell for low-voltage operation and long-life operation. It becomes important.
[0006]
As a ferroelectric material constituting a capacitor, KNO _Three , PbLa _Two O _Three -ZrO _Two -TiO _Two And PbTiO _Three -PbZrO _Three Etc. are known. According to PCT International Publication WO 93/12542, PbTiO suitable for a ferroelectric memory device is used. _Three -PbZrO _Three Ferroelectric materials with extremely low fatigue as compared with are also known.
[0007]
Hereinafter, a conventional reference potential generating circuit of a ferroelectric memory will be briefly described with reference to FIG. 10 (for example, Patent Document 1).
[0008]
In the configuration of the conventional example, C00 to C37 are ferroelectric capacitors for main body memory cells, and CD00 to CD31 are ferroelectric capacitors for reference memory cells. CPD is a cell plate driver, and REW0 to REW1 are reference memory cell rewrite signal lines. The reference memory cell ferroelectric capacitors CD00 and CD20 store "H" (high) data, and the reference memory cell ferroelectric capacitors CD10 and CD30 store "L" (low) data. Shall be recorded. "H" (high) data is stored in the ferroelectric capacitors CD01 and CD21 for reference memory cells, and "L" (low) data is stored in the ferroelectric capacitors CD11 and CD31 for reference memory cells. Shall be recorded. Also, EQ0 to EQ1 are reference potential signal lines, SA0 to SA3 are sense amplifiers, and CP is a cell plate signal line. WL0 to WL7 are word lines, RWL0 to RWL1 are reference word lines, and BL0 to BL3 and / BL0 to / BL3 are bit lines. BP is a bit line precharge signal, and / SAP and SAN are sense amplifier control signals. VSS is a ground voltage, and VDD is a power supply voltage. The reference potential signal lines EQ0 to EQ1 are signal lines that generate a reference potential when the reference word lines RWL0 to RWL1 are selected, respectively. Further, as shown in the figure, the word lines for selecting the ferroelectric capacitor for the main memory cell and the bit lines for reading the potential are arranged in a matrix. Further, a memory cell array to be described later is constituted by the ferroelectric capacitors for the main body memory cells and the like.
[0009]
In the memory cell array configuration, bit lines BL0 to BL3 and / BL0 to / BL3 are connected to sense amplifiers SA0 to SA3. The ferroelectric capacitors C00, C10, C20, and C30 for the main memory cell are connected to the bit lines BL0 to BL3 via N-channel MOS transistors having the word line WL0 as a gate. The ferroelectric capacitors for reference memory cells are connected to the bit lines / BL0, / BL1, / BL2, / BL3 via N-channel MOS transistors Tr2, Tr4, Tr7, Tr9 having the reference word line RWL0 as a gate. CD00, CD10, CD20, and CD30 are respectively connected. The equalizing circuit is a circuit composed of N-channel MOS transistors Tr0, Tr3, Tr6, Tr8 and the like. That is, the equalizing circuit reads the various data stored in the ferroelectric capacitors for reference memory cell CD00, CD10, CD20, and CD30 as various potentials from the bit lines / BL0, / BL1, / BL2, / BL3. When averaging, these circuits average those potentials. The potential averaged by the equalizing circuit is a reference potential used for amplifying data read from the main memory cell ferroelectric capacitor by the sense amplifier. The ferroelectric capacitors C00 to C37 and CD00 to CD31 are connected to a cell plate signal line CP driven by a cell plate driver CPD. The bit line BL0 and the ferroelectric capacitor for reference memory cell CD00 are connected via an N-channel MOS transistor Tr5 having the gate of the reference memory cell rewrite signal line REW0. The other bit lines / BL0, BL2, / BL2 are also connected to the reference memory cell ferroelectric capacitors CD10, CD20, CD30 via the respective N-channel MOS transistors, similarly to the bit line BL0. . The sense amplifier SA0 is controlled by sense amplifier control signals / SAP and SAN, and has a circuit configuration in which bit lines BL0 to BL3 and / BL0 to / BL3 are precharged by a bit line precharge signal BP.
[0010]
Four ferroelectric capacitors of approximately the same size as the main memory cell ferroelectric capacitor are used, and two of them read "H" data and the remaining two read "L" data. And averaging these data. In this conventional example, a plurality of H data and the same number of L data are averaged to obtain a reference potential.
[0011]
In the four ferroelectric capacitors for reference memory cells (CD00 to CD30), the number of H data and the number of L data are equalized, and the reference potential is intermediate between H level and L level. Set to value. Further, in the conventional example, since the charges of many reference capacitors are averaged, the variation can be reduced.
[0012]
[Patent Document 1]
JP-A-9-836300
[0013]
[Problems to be solved by the invention]
As described above, in the conventional reference potential generation circuit, the reference potential is set to an intermediate value between the H level and the L level, but may not be set to the median value between the H level and the L level. The read potential is determined by the capacitance ratio between the bit line capacitance and the ferroelectric capacitor. It should be noted here that the bit line capacitance is a part of the diffusion capacitance. The diffusion capacitance decreases as the voltage is applied. Therefore, as the potential of the H level increases as the potential of the bit line increases, the bit line capacitance decreases, and the potential of the bit line becomes higher. Since the potential of the L level does not increase the potential of the bit line, the bit line capacitance does not decrease so much and the potential of the bit line does not increase so much.
[0014]
Therefore, when the same number of H-level and L-level bit lines are averaged, the potential used as the reference potential is lower than the potential obtained by simply averaging the H-level potential and the L-level potential. . For this reason, when the reference potential and the potential from the main body memory cell are compared by the sense amplifier, there is a problem that the determination of the L level may become severe. For this reason, there has been a problem that the operation becomes more severe when the readout charge in the low-voltage operation or the like is reduced.
[0015]
Conversely, with respect to the variation between the H level and the L level of each ferroelectric capacitor, there is a problem that, for example, the variation is larger at the H level with polarization inversion. Since the reference potential needs to be set so as to have a margin for the worst value of the variation of each ferroelectric capacitor, when the H level and the L level are simply averaged, the H level becomes severe. There was a problem.
[0016]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a ferroelectric memory in which the operation margin of a reference circuit can be increased, the yield is high, and the reliability is high.
[0017]
[Means for Solving the Problems]
In the present invention, in order to solve the above-mentioned problem, a reference potential generating circuit as described below is provided.
[0018]
As a first means, a ferroelectric capacitor for averaging a plurality of m high-level reference potential generating ferroelectric capacitors and a plurality of n low-level reference potential generating ferroelectric capacitors is stored. It is assumed that the reference potential generating circuit of the body memory is set to an arbitrary number where m and n are not the same.
[0019]
As a second means, in the first means, the ferroelectric capacitor for generating a reference potential in which the plurality of m high levels are stored and the ferroelectric capacitor for generating a reference potential in which a plurality of n low levels are stored M is smaller than n.
[0020]
As a third means, in the first means, the ferroelectric capacitor for generating a reference potential storing the plurality of m high levels and the ferroelectric capacitor for generating a reference potential storing a plurality of n low levels is provided. Is a reference potential generating circuit in which n is smaller than m.
[0021]
As a fourth means, in the first means, the reference potential generating circuit is such that the number of m and n can be arbitrarily variably set other than the same number.
[0022]
As a fifth means, in the fourth means, the variable setting of the number of m and n is a reference potential generating circuit which is set by changing the number of wiring layers in a semiconductor manufacturing process.
[0023]
According to a sixth aspect, in the fourth aspect, the reference potential generating circuit includes a register, and the number of m and n is variably set by data stored in the register.
[0024]
According to a seventh aspect, in the fourth aspect, the reference potential generating circuit includes a non-volatile memory, and the variable setting of the number of m and n is performed by data stored in the non-volatile memory.
[0025]
As an eighth means, in the fourth means, a control circuit for arbitrarily setting the number of m and n variably is provided, wherein the control circuit has a function of detecting an optimum reference potential, and the control circuit A reference potential generating circuit for setting the number of m and n so as to obtain the optimum reference potential.
[0026]
As a ninth means, in the first means, one electrode of the ferroelectric capacitor for the main body memory cell is connected to a bit line via a transistor whose gate is controlled by a main body word line, The other electrode of the ferroelectric capacitor is connected to the body plate line, and one electrode of the ferroelectric capacitor for generating the reference potential is connected to a bit line via a transistor whose gate is controlled by a reference word line. The other electrode of the ferroelectric capacitor for generating the reference potential is connected to a reference plate line, and changes the potential of the main body plate line and the reference plate line from a first potential to a second potential; When an electric field is applied to the ferroelectric capacitors for the memory cells and for generating the reference potential, The reference potential generated by averaging the reference potential generating ferroelectric capacitors storing n high levels and the reference potential generating ferroelectric capacitors storing a plurality of n low levels is the main memory cell. And a reference potential generating circuit in which the values of m and n are set to be substantially intermediate between the high level potential and the low level potential.
[0027]
As a tenth means, in the first means, one electrode of a ferroelectric capacitor for the main body memory cell is connected to a bit line via a transistor whose gate is controlled by a main body word line, The other electrode of the ferroelectric capacitor is connected to the body plate line, and one electrode of the ferroelectric capacitor for generating the reference potential is connected to a bit line via a transistor whose gate is controlled by a reference word line. The other electrode of the ferroelectric capacitor for generating the reference potential is connected to a reference plate line, and the main plate line and the reference plate line are changed from a first potential to a second potential after the potential is changed. 1 to the ferroelectric capacitor for the main body memory cell and for generating the reference potential. Is applied, and a plurality of m high-level reference potential generating ferroelectric capacitors and a plurality of n low-level reference potential generating ferroelectric capacitors are stored. A reference potential generating circuit in which the values of m and n are set such that the reference potential of the main memory cell is substantially intermediate between the high level potential and the low level potential of the main memory cell.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
A first embodiment of the present invention will be described with reference to FIGS.
[0029]
The circuit configuration is almost the same as that of the conventional example. However, in this embodiment, one cell plate line corresponds to a ferroelectric capacitor connected to one word line. In particular, the present invention can be implemented even in a conventional structure of a cell plate line common to adjacent word lines. The point of the present invention is that the same number of H-level and L-level bit lines are conventionally averaged, but in the present invention, the H-level is set so that the averaged reference potential is substantially intermediate between the H-level and L-level. And the number of reference memory cells in which the L level is written is set to different numbers. When the same number of H level and L level bit lines are actually averaged, the potential used as the reference potential is lower than the potential obtained by simply averaging the H level potential and the L level potential. In order to make the potential approximately intermediate, the number of reference memory cells to which the H level is written is set to be larger than the number of reference memory cells to which the L level is written.
[0030]
In the present embodiment, three H levels and one L level are averaged. C00 to C73 are ferroelectric capacitors for main body memory cells, CR00 to CR13 are ferroelectric capacitors for reference memory cells, WL0 to WL7 are word lines, CP is a cell plate signal line, RWL0 to RWL1 are reference word lines, and RCP is Reference cell plate signal lines, BL0 to BL3, / BL0 to / BL3 are bit lines, SA0 to SA3 are sense amplifiers, EQ0 to EQ1 are equalization control signal lines, BP0 is a bit line precharge signal line, VSS is a ground voltage, VDD Is the power supply voltage.
[0031]
As for the operation, the word line WL0 and the reference word line RWL0 are selected, the cell plate signal line CP0 and the reference cell plate signal line RCP0 are operated, and the ferroelectric capacitor And the information of the ferroelectric capacitor for the reference memory cell is read. At this time, "H" data is read from three CR10, CR11, and CR12 of the ferroelectric capacitors for reference memory cells, and "L" data is read from CR13. These four data are averaged.
[0032]
When the same number of H level and L level bit lines are averaged, the potential used as the reference potential is lower than the potential obtained by simply averaging the H level potential and the L level potential. In the embodiment, since there is more “H” data, the value is just an intermediate value between “H” data and “L” data. In this embodiment, the average value of the three “H” data and one “L” data is a just intermediate value, but an optimal value is set according to the bit line capacity and the bit line potential. do it. Since the larger the number to be averaged, the smaller the variation, the average of 20 “H” data and 12 “L” data is set in another embodiment. In the present embodiment, data is written to the ferroelectric capacitor for the reference memory cell through a bit line.
[0033]
(Second embodiment)
A second embodiment of the present invention will be described with reference to FIG.
[0034]
The circuit configuration is almost the same as that of the first embodiment. However, in this embodiment, data writing to the ferroelectric capacitor for the reference memory cell is performed not to the bit line but to the ferroelectric capacitor for the reference memory cell. In this configuration, the power supply voltage VDD for writing the H level and the ground voltage VSS for writing the L level are connected via a switching transistor.
[0035]
The point of the present invention is the same as that of the first embodiment. Conventionally, the same number of H level and L level bit lines were averaged. However, in the present invention, the averaged reference potential is H level and L level. In this configuration, the number of reference memory cells to which the H level is written and the number of reference memory cells to which the L level is written are set to different numbers so as to be approximately halfway between the two.
[0036]
As the actual setting of the present embodiment, the H level and the L level of the individual ferroelectric capacitors are simply considered in consideration of the fact that the H level with polarization inversion has a larger variation than the H level and the L level of the individual ferroelectric capacitors. The number of reference memory cells to which the L level has been written is set to be larger than the number of reference memory cells to which the H level has been written in order to set the level to the L level side when the levels are averaged.
[0037]
In the present embodiment, three L levels and one H level are averaged. C00 to C73 are ferroelectric capacitors for main body memory cells, CR00 to CR13 are ferroelectric capacitors for reference memory cells, WL0 to WL7 are word lines, CP is a cell plate signal line, RWL0 to RWL1 are reference word lines, and RCP is Reference cell plate signal lines, BL0 to BL3, / BL0 to / BL3 are bit lines, SA0 to SA3 are sense amplifiers, EQ0 to EQ1 are equalization control signal lines, BP0 is a bit line precharge signal line, VSS is a ground voltage, VDD Is the power supply voltage.
[0038]
As for the operation, as in the first embodiment, as shown in FIG. 2, the word line WL0 and the reference word line RWL0 are selected, and the cell plate signal line CP0 and the reference cell plate signal line RCP0 are operated. The information of the ferroelectric capacitor for the main body memory cell and the ferroelectric capacitor for the reference memory cell is read. In addition, the bit lines forming a pair are set to have the H level and the L level as much as possible, and the necessary number of the bit lines is arranged so as to increase the L level, so that the balance at the time of writing is improved. Of course, the larger the number to be averaged, the smaller the variation. Therefore, in another embodiment, the average of 20 “L” data and 12 “H” data is used. In the present embodiment, data is written to the ferroelectric capacitor for the reference memory cell through a bit line.
[0039]
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG.
[0040]
The configuration of the memory cell array is almost the same as that of the first embodiment, but the feature of this embodiment is that data written to the ferroelectric capacitor for the reference memory cell is stored in the latch circuit connected to the bit line. Configuration. In this embodiment, the data set in the latch circuit is written into the ferroelectric capacitor for the reference memory cell, and the average of the written H-level and L-level data is used as the reference potential.
[0041]
A feature of this embodiment is that data corresponding to obtaining a desired reference potential can be arbitrarily set by storing the data in a latch circuit. Incidentally, any data can be set to each of the bit lines BL0 and / BL0 from the register 1 which is the latch circuit of FIG. 4 of the present embodiment. The register may have a configuration in which data stored in the nonvolatile memory is automatically transferred when the power is turned on. In the present embodiment, it is possible to set an optimal reference potential for each device or each memory cell array.
[0042]
(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG.
[0043]
The configuration of the memory cell array is almost the same as that of the first embodiment, except that the register, which is the latch circuit of the third embodiment, is constituted by a nonvolatile memory. The feature of the present embodiment is that, similarly to the third embodiment, data to be written to the ferroelectric capacitor for the reference memory cell is stored in the latch circuit connected to the bit line. In the present embodiment, data set in a latch circuit composed of a nonvolatile memory is written into a ferroelectric capacitor for a reference memory cell, and an average of the written H-level and L-level data is used as a reference potential. It is to be.
[0044]
A feature of this embodiment is that data corresponding to obtaining a desired reference potential can be arbitrarily set by storing the data in a latch circuit. Any data can be set to each of the bit lines BL0 and / BL0 from the nonvolatile memory of FIG. 5 of the present embodiment. By storing data to be written to the reference memory cell ferroelectric capacitor in the nonvolatile memory, for example, the data stored in the nonvolatile memory is automatically written to the reference memory cell ferroelectric capacitor when power is turned on. can do.
[0045]
(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIG.
[0046]
The circuit configuration is almost the same as that of the first embodiment. However, in this embodiment, data writing to the ferroelectric capacitor for the reference memory cell is performed not to the bit line but to the ferroelectric capacitor for the reference memory cell. This configuration has a latch circuit for writing H level or L level via a switching transistor. This latch circuit can be constituted by a nonvolatile memory. The data writing to the latch circuit is performed via a bit line in the drawings of this embodiment, but another writing circuit may be provided.
[0047]
The point of the present invention is the same as that of the first embodiment. Conventionally, the same number of H level and L level bit lines were averaged. However, in the present invention, the averaged reference potential is H level and L level. In this configuration, the number of reference memory cells in which the H level is written and the number of reference memory cells in which the L level is written are set to different numbers so as to be almost in the middle including the variation in the H level and the L level. The number is set in the latch circuit.
[0048]
As the actual setting of the present embodiment, the H level and the L level of the individual ferroelectric capacitors are simply considered in consideration of the fact that the H level with polarization inversion has a larger variation than the H level and the L level of the individual ferroelectric capacitors. The number of reference memory cells to which the L level has been written is set to be larger than the number of reference memory cells to which the H level has been written in order to set the level to the L level side when the levels are averaged.
[0049]
In the present embodiment, three L levels and one H level are averaged. C00 to C73 are ferroelectric capacitors for main body memory cells, CR00 to CR13 are ferroelectric capacitors for reference memory cells, WL0 to WL7 are word lines, CP is a cell plate signal line, RWL0 to RWL1 are reference word lines, and RCP is Reference cell plate signal lines, BL0 to BL3, / BL0 to / BL3 are bit lines, SA0 to SA3 are sense amplifiers, EQ0 to EQ1 are equalization control signal lines, BP0 is a bit line precharge signal line, VSS is a ground voltage, VDD Is the power supply voltage.
[0050]
As in the first embodiment, the operation is performed by selecting the word line WL0 and the reference word line RWL0 and operating the cell plate signal line CP0 and the reference cell plate signal line RCP0 as in the first embodiment. The information of the ferroelectric capacitor for the memory cell and the ferroelectric capacitor for the reference memory cell is read. In addition, the bit lines forming a pair are set to have the H level and the L level as much as possible, and the necessary number of the bit lines is arranged so as to increase the L level, so that the balance at the time of writing is improved. Of course, the larger the number to be averaged, the smaller the variation. Therefore, in another embodiment, the average of 20 “L” data and 12 “H” data is used.
[0051]
(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIG.
[0052]
The present embodiment relates to a reference cell setting circuit. First, the reference cell setting circuit writes a certain ratio of H level and L level data to the reference cell. Next, this data is read and the generated reference potential is compared with the separately written data of the main body memory cell, and the result is determined. If there is an error in the determination, the ratio of the H level data and the L level data to be written to the reference cell is changed again, and the same read determination is performed. This makes it possible to determine the ratio of H-level and L-level data to be written to the reference cell so that a normally operating reference potential can be obtained. As for the actual setting, setting the middle setting value within the range of the setting value in which the reading determination is determined to be normal increases the margin. The main memory cell to be determined here may be performed for all the memory cells. However, when the main memory cell has already been used as the non-volatile data, the main memory cell dedicated to the determination for this operation is prepared and operated. It is also possible.
[0053]
In the present embodiment, an operation is performed between the actually set reference potential and the main body memory cell to make a determination, and an optimum reference potential can be set, and a stable operation can be expected.
[0054]
(Seventh embodiment)
A seventh embodiment of the present invention will be described with reference to FIG.
[0055]
This embodiment is the same as the first embodiment, but describes the operation of the memory cell capacitor. In the present embodiment, a word line and a reference word line are selected, and the respective cell plate lines and reference cell plate lines are changed from L level to H level. At this time, data is read out to bit lines precharged to L level. The potential is amplified by a sense amplifier.
[0056]
As described in the first embodiment, when the same number of H level and L level bit lines are averaged, the potential used as the reference potential is simply the average of the H level potential and the L level potential. Since the potential is lower than the converted potential, more “H” data is set. The actual setting is to set the potential to be optimal including the operation method and its variation.
[0057]
(Eighth embodiment)
An eighth embodiment of the present invention will be described with reference to FIG.
[0058]
This embodiment is a method of operating a memory cell capacitor that can be implemented as a combination of the first to sixth embodiments. In the present embodiment, a word line and a reference word line are selected, and the respective cell plate lines and reference cell plate lines are changed from L level to H level, and then changed from H level to L level. The potential read to the read bit line is amplified by a sense amplifier.
[0059]
Since the variation in the initial polarization amount is less likely to appear in the read potential in the read method of the present embodiment than in the operation method of the seventh embodiment, the read method may have less variation. Therefore, by using this reading method and setting an appropriate reference potential, a ferroelectric memory with a larger operation margin can be provided.
[0060]
Although the first to eighth embodiments have been described, the present invention is not limited to these, and combinations of the respective embodiments are also possible, and these are included in the present invention.
[0061]
【The invention's effect】
As described above, as in the reference potential generation circuit of the present invention, the operation margin can be expanded by averaging the H level and L level reference cells by an arbitrary number and generating an optimal reference potential, There is an effect that a ferroelectric memory with high yield and high reliability can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a reference potential generation circuit according to a first embodiment of the present invention;
FIG. 2 is a reference potential signal diagram according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a reference potential generating circuit according to a second embodiment of the present invention;
FIG. 4 is a diagram showing a reference cell setting circuit of a reference potential generation circuit according to a third embodiment of the present invention.
FIG. 5 is a diagram illustrating a reference cell setting circuit of a reference potential generation circuit according to a fourth embodiment of the present invention.
FIG. 6 is a diagram showing a reference cell setting circuit of a reference potential generation circuit according to a fifth embodiment of the present invention.
FIG. 7 is a diagram showing a reference cell setting circuit of a reference potential generation circuit according to a sixth embodiment of the present invention.
FIG. 8 is a control signal diagram of a reference potential generation circuit according to a seventh embodiment of the present invention.
FIG. 9 is a control signal diagram of a reference potential generation circuit according to an eighth embodiment of the present invention.
FIG. 10 is a diagram showing a conventional reference potential generation circuit.
[Explanation of symbols]
C00-C73 Ferroelectric capacitor for main body memory cell
CR00-CR13 Ferroelectric capacitor for reference memory cell
WL0-WL7 Word line
CP cell plate signal line
RWL0-RWL1 Reference word line
RCP reference cell plate signal line
BL0 to BL3, / BL0 to / BL3 bit lines
SA0-SA3 sense amplifier
EQ0 to EQ1 Equalization control signal line
BP0 bit line precharge signal line
VSS ground voltage
VDD power supply voltage

Claims (10)

Reference potential generation of a ferroelectric memory for averaging ferroelectric capacitors for generating reference potentials storing a plurality of m high levels and ferroelectric capacitors for generating reference potentials storing a plurality of n low levels A reference potential generation circuit, wherein the number of m and n is set to an arbitrary number that is not the same in the circuit. The m of the reference potential generating ferroelectric capacitors storing the plurality of m high levels and the reference potential generating ferroelectric capacitors storing the plurality of n low levels are smaller than n. Item 2. The reference potential generation circuit according to Item 1. The n of the reference potential generating ferroelectric capacitors storing a plurality of m high levels and the reference potential generating ferroelectric capacitors storing a plurality of n low levels is smaller than m. Item 2. The reference potential generation circuit according to Item 1. 2. The reference potential generating circuit according to claim 1, wherein the number of m and n can be variably set to any number other than the same number. 5. The reference potential generating circuit according to claim 4, wherein the variable setting of the number of m and n is changed by changing the number of wiring layers in a semiconductor manufacturing process. 5. The reference potential generating circuit according to claim 4, further comprising a register, wherein the variable setting of the number of m and n is made by data stored in the register. 5. The reference potential generating circuit according to claim 4, further comprising a nonvolatile memory, wherein the variable setting of the number of m and n is performed by data stored in the nonvolatile memory. A control circuit for arbitrarily setting the number of m and n, wherein the control circuit has a function of detecting an optimal reference potential, and the m and n are set so that the optimal reference potential detected by the control circuit is obtained. 5. The reference potential generation circuit according to claim 4, wherein the number of n is set. One electrode of the ferroelectric capacitor for the main body memory cell is connected to the bit line via a transistor whose gate is controlled by the main body word line, and the other electrode of the ferroelectric capacitor for the main body memory cell is connected to the main body plate. Connected to the wire,
One electrode of the ferroelectric capacitor for generating a reference potential is connected to a bit line via a transistor whose gate is controlled by a reference word line, and the other electrode of the ferroelectric capacitor for generating a reference potential is connected to a reference electrode. Connected to the plate wire,
The potential of the main body plate line and the reference plate line is changed from a first potential to a second potential, and when an electric field is applied to the ferroelectric capacitors for the main body memory cell and the reference potential generation, a plurality of The reference potential generated by averaging the reference potential generating ferroelectric capacitors storing m high levels and the reference potential generating ferroelectric capacitors storing a plurality of n low levels is stored in the main memory. 2. The reference potential generating circuit according to claim 1, wherein the values of m and n are set to be substantially intermediate between the high-level potential and the low-level potential of the cell. One electrode of the ferroelectric capacitor for the main body memory cell is connected to the bit line via a transistor whose gate is controlled by the main body word line, and the other electrode of the ferroelectric capacitor for the main body memory cell is connected to the main body plate. Connected to the wire,
One electrode of the ferroelectric capacitor for generating a reference potential is connected to a bit line via a transistor whose gate is controlled by a reference word line, and the other electrode of the ferroelectric capacitor for generating a reference potential is connected to a reference electrode. Connected to the plate wire,
After changing the potential of the main body plate line and the reference plate line from the first potential to the second potential, the potential is changed again to the first potential, and the ferroelectric material for the main body memory cell and for generating the reference potential is used. Averaging of a plurality of m high-level reference potential generating ferroelectric capacitors and a plurality of n low-level reference potential generating ferroelectric capacitors after the application of an electric field to the capacitor 2. The reference potential according to claim 1, wherein the values of m and n are set such that the reference potential generated by the threshold voltage is approximately intermediate between the high-level potential and the low-level potential of the main memory cell. Generator circuit.

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