JP2004199795A - Semiconductor memory device, and control method of semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device and a control method of a semiconductor memory device by which a testing time can be shortened at the time of a test, while keeping low current consumption operation at the time of normal access operation. <P>SOLUTION: Selecting signals S0-Sn selecting each column block CB0-CBn are generated by block selecting circuits CBS0-CBSn. A strobe signal SS indicating activation timing and column block addresses CAq to CAq+k are inputted to the block selecting circuits CBS0-CBSn. Many block selecting circuits CBS0-CBSn are selected by test block signals ST0-STn from a test block specifying means 1 activated at the time of test access operation comparing with the block selecting circuits CBS0-CBSn selected by the column block addresses CAq-CAq+k, thus more column blocks CB0-CBn can be activated. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a reduction in test time in a semiconductor memory device, and more particularly to a semiconductor memory device for reducing test time while maintaining low current consumption during a normal access operation, and a method of controlling the semiconductor memory device. Things.
[0002]
[Prior art]
In order to reduce the current consumption that increases with the recent increase in capacity of semiconductor memory devices, the semiconductor memory device disclosed in Patent Document 1 selectively activates a column block during an access operation as shown in FIG. Configuration. Unlike a semiconductor memory device that drives a plurality of sense amplifier blocks 204, only one sense amplifier block 204 is operated by a column block selection circuit 208. The sense amplifier control circuit 205 and the sub-word decoder control circuit 206 are controlled in accordance with the column address read at the time of row access, so that only the sense amplifier block 204 of the selected column block is driven, and the sub-word is generated only in the selected column block. Line 214 is connected to main word line 213 and activated. By limiting the column blocks to be selected, the driving load of the circuit is reduced and the current consumption is reduced.
[0003]
[Patent Document 1]
JP-A-11-25669 (paragraph 0008-0010, FIG. 11)
[0004]
[Problems to be solved by the invention]
However, in the semiconductor memory device that performs an access operation using a selectively activated column block as a unit as exemplified in Patent Document 1, similarly, at the time of a test, the access operation is performed using a selectively activated column block as a unit. Will do. Here, one unit of the column block to be selectively activated may be a small unit in order to realize a low current consumption operation at the time of the access operation. Therefore, when testing the entire area of the semiconductor memory device, it is necessary to frequently switch the column blocks to be selectively activated, and the overhead of the switching time in the test time becomes large. This is a problem because the test time cannot be sufficiently reduced.
[0005]
Here, the switching time includes an active time from the start of access to the start of actual data reading / writing, and a precharge time performed after the end of access.
[0006]
Taking a page operation as an example of the access operation, the active time indicates a predetermined number of nop operations (a cycle in which no signal change is performed after the active command (ACT) is issued, and NOP indicating No Operation). Abbreviated.) Until a read command or a write command is issued. The precharge time is a time from the issuance of the precharge command (PRE) to the issuance of the active command (ACT) in the next cycle through a predetermined number of nop operations (NOP). A specific time is required for these switching times depending on technologies such as processes, devices, circuits, and the like that constitute the semiconductor memory device. When the size of the column block to be selectively activated is limited and the cycle time (tRC) is reduced, the overhead due to the switching time may be large.
[0007]
Similarly, in the case of the burst operation, the active time until the row operation is performed and the storage cell can be connected to the data line, and the precharge operation performed for the next cycle access operation after the access operation is completed is completed. And a precharge time until the power supply is completed. These switching times require a specific time depending on the technology of processes, devices, circuits, and the like that constitute the semiconductor memory device. The size of the column block to be selectively activated is limited, and the cycle time (tCRC) is reduced. In this case, the overhead due to the switching time may be large.
[0008]
With the increase in the capacity of semiconductor memory devices in the future, it is conceivable that the switching time of the column block to be selectively activated will increase with the increase in the test area, which will require more test time. It is.
[0009]
SUMMARY An advantage of some aspects of the invention is to solve at least one of the problems of the related art, and to maintain a low current consumption operation in a normal access operation and a column block selectively activated in a test. An object of the present invention is to provide a semiconductor memory device capable of reducing a test time by enlarging a size or a continuous access area in a page operation, and a method of controlling the semiconductor memory device.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor memory device according to claim 1, wherein a column direction is divided into a plurality of column blocks as an activation unit of an access operation, and a block selection circuit provided for each column block in a normal access operation. At least one of them is activated, and at least one column block is selected as an active area. At the time of a test access operation, a larger number of block select circuits are required than at the time of a normal access operation. It is characterized by being activated.
[0011]
In the semiconductor memory device according to the first aspect, at the time of the test access operation, a larger number of block selection circuits are activated than at the time of the normal access operation, and a larger number of column blocks are selected as the active region than at the time of the normal access operation. .
[0012]
According to a ninth aspect of the present invention, in a semiconductor memory device in which a column direction is divided into a plurality of column blocks as an activation unit of an access operation, at least one column block serves as an activation region. A normal access operation step is selected, and a test access operation step is performed in which a larger number of column blocks are selected as active regions than the column blocks selected in the normal access operation step.
[0013]
In the method of controlling a semiconductor memory device according to the ninth aspect, the number of column blocks selected as the active area in the test access operation step is larger than the number of column blocks selected as the active area in the normal access operation step. is there.
[0014]
As a result, the number of column blocks that are activated and controlled in the access operation can be increased during the test access operation. Therefore, the column block that is activated and controlled during the test access operation has a larger access area than in the normal access operation. Will have. When testing the entire area of the semiconductor memory device, the switching frequency of the column blocks to be activated can be reduced as compared with the normal access operation. The total switching time required for switching the column blocks is reduced, and the overhead of the switching time in the test time is reduced, so that the test time can be reduced.
[0015]
According to a second aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein activation is controlled by a test signal and a test block signal for specifying a column block selected at the time of a test access operation is generated. A block designating circuit is provided, and the block selecting circuit is activated based on a test block signal.
[0016]
In the semiconductor memory device according to the second aspect, the test block designating circuit is activated and controlled by the test signal to generate a test block signal. A block selection circuit is activated based on a test block signal, and designates a column block selected at the time of a test access operation. Thus, the test block designating circuit is activated and controlled by the test signal, so that the number of column blocks selected at the time of the test access operation is determined according to the circuit configuration of the test block designating circuit.
[0017]
According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the test block designating circuit receives a column block address for identifying a column block, and inputs the column block address during the test access operation. Among them, at least one of a predetermined upper address and a predetermined lower address is identified as a selected state. Here, upper and lower addresses indicate the size of the test access operation area specified by the address in the test access operation, and a larger area is specified from the lower address to the upper address. In an address bit string when considered as a sequence of binary numbers, it is common to specify a narrow access area by the address of the lower bit and specify a wider access area as the bit becomes higher, but due to layout restrictions, In some cases, the order of the address bit strings does not match the magnitude relationship between the access areas.
[0018]
As a result, at least one of the predetermined upper address and the predetermined lower address of the column block address for identifying the column block is in a selected state regardless of the logic level of the signal. The column blocks identified by either one are selected simultaneously. This selection state is performed when the test block designating circuit is activated and controlled by the test signal, so that a large number of column blocks can be selected during the test access operation.
[0019]
According to a fourth aspect of the present invention, in the semiconductor memory device according to the first aspect, the block selection circuit is activated by a test signal. Thus, at the time of the test access operation, all the column selection circuits are activated according to the test signal supplied at the time of the test access operation, without depending on the activation control at the time of the normal access operation. At the time of the test access operation, a plurality of column blocks divided in the column direction are simultaneously activated.
[0020]
According to a fifth aspect of the present invention, in the semiconductor memory device according to the first aspect, a block address storage section storing a column block address for identifying a column block is activated and controlled by a test signal, and the test is performed. A capture signal generation unit for generating a capture signal in accordance with a transition of a selected block address for identifying a column block selected at the time of an access operation, wherein a column block address including at least the selected block address is stored based on the capture signal. It is characterized in that it is taken into a part.
[0021]
In the semiconductor memory device according to the fifth aspect, the capture signal generator is activated and controlled by the test signal to generate the capture signal. A column block address including a selected block address for identifying a column block selected at the time of the test access operation based on the fetch signal is fetched into the block address storage unit according to the transition of the selected block address.
[0022]
Thereby, in response to the transition of the selected block address to the column block selected in the test access operation without being selected in the normal access operation, a column block address including at least the selected block address is taken into the block address storage unit and selected. Column blocks can be identified.
[0023]
Here, it is preferable to include an address transition detection unit as a capture signal generation unit that generates a capture signal according to the transition of the selected block address.
[0024]
According to a sixth aspect of the present invention, in the semiconductor memory device according to the first aspect, a block address storage unit for storing a column block address for identifying a column block and a column direction address in the column block are identified. And a capture signal generation unit for generating a capture signal in accordance with the transition of the first address to be performed, wherein a column block address is loaded into the block address storage unit based on the capture signal during the test access operation.
[0025]
In the semiconductor memory device according to the sixth aspect, the capture signal generation unit generates the capture signal according to the transition of the first address for identifying the column direction address in the column block. Based on the fetch signal, the column block address is fetched into the block address storage.
[0026]
Thereby, at the time of the test access operation, the column block address is also taken in at the same time that the first address is taken in accordance with the transition of the first address. Since the column block address for identifying the column block is an upper address of the first address for identifying the column direction address in the column block, the column block address is also changed along with the first address making a round and transition to the initial address. Transition. Therefore, when the first address makes a cycle and shifts access to the next column block, the column block address can be captured according to the transition of the first address, and a dedicated capture signal according to the transition of the column block address is generated. No need to generate.
[0027]
Here, it is preferable to include an address transition detection unit as a capture signal generation unit that generates a capture signal according to the transition of the first address.
[0028]
The semiconductor memory device according to claim 7, wherein during a normal access operation, a continuous access operation is performed in response to a transition of a first address, wherein the address transition detection unit detects a transition of the first address. A first address storage unit into which a first address is fetched based on a detection signal from the address transition detection unit, and a higher address of the first address based on a detection signal from the address transition detection unit during a test access operation. A second address storage unit for receiving the second address.
[0029]
In the semiconductor memory device according to the seventh aspect, in the continuous access operation based on the address transition, the transition of the first address is detected by the address transition detection unit, and the first address is taken into the first address storage unit based on the detection signal. Further, at the time of the test access operation, the second address, which is an upper address of the first address, is taken into the second address storage unit based on the detection signal.
[0030]
A control method of a semiconductor memory device according to a tenth aspect is a control method of a semiconductor memory device in which a continuous access operation is performed according to a transition of a first address during a normal access operation. An address transition detecting step to detect, a first address storing step in which a first address is taken in based on the address transition detecting step, and a second address which is an upper address of the first address based on the address transition detecting step in a test access operation. And a second address storing step of taking in the address.
[0031]
According to a tenth aspect of the present invention, in the continuous access operation based on the address transition, the transition of the first address is detected by the address transition detecting step, and the first address is fetched by the first address storing step. Further, at the time of the test access operation, a second address which is an upper address of the first address is fetched based on the address transition detecting step. Here, upper and lower addresses indicate the size of the test access operation area specified by the address in the test access operation, and a larger area is specified from the lower address to the upper address. In an address bit string when considered as a sequence of binary numbers, it is common to specify a narrow access area by the address of the lower bit and specify a wider access area as the bit becomes higher, but due to layout restrictions, In some cases, the order of the address bit strings does not match the magnitude relationship between the access areas.
[0032]
Thereby, in the continuous access operation by the address transition, at the time of the test access operation, the second address is also taken in at the same time as the first address is taken in accordance with the transition of the first address. Since the second address is an upper address of the first address, the second address also transits at the same time as the first address makes a circuit transition to the initial address. Therefore, when performing a continuous access operation in accordance with the transition of the first address, the second address can be fetched together with the first address, and a continuous access operation can be performed in an area extending over the column block. At this time, there is no need to generate a dedicated capture signal according to the transition of the second address.
[0033]
According to a eighth aspect of the present invention, in the semiconductor memory device according to the seventh aspect, activation is controlled by a test signal, and the second address is taken into the second address storage section based on the detection signal. A capture control unit for generating a capture signal is provided.
[0034]
According to the semiconductor memory device of the present invention, the capture signal for capturing the second address into the second address storage section is based on the detection signal from the address transition detection section by the capture control section activated and controlled by the test signal. Generated.
[0035]
Thus, the capture control unit is activated by the test signal during the test access operation, and the detection signal for detecting the transition of the first address can be used for the capture control of the second address.
[0036]
Here, the first principle of the present invention will be described with reference to FIG. The column direction of the semiconductor memory device is divided into a plurality of column blocks CB0 to CBn in order to partition an activation region, and at least one column block CB0 to CBn is selected as a minimum unit for activation. You. FIG. 1 shows a circuit configuration for selecting column blocks CB0 to CBn. The selection signals S0 to Sn for selecting the column blocks CB0 to CBn are generated by block selection circuits CBS0 to CBSn. To the block selection circuits CBS0 to CBSn, a strobe signal SS indicating the activation timing of the column blocks CB0 to CBn is input, and column block addresses CAq to CAq + k for identifying the column blocks CB0 to CBn are input.
[0037]
In the normal access operation, the column block addresses CAq to CAq + k are taken into the block selection circuits CBS0 to CBSn at the time of input of the strobe signal SS. Only the block selection circuits CBS0 to CBSn for the column blocks CB0 to CBn identified by the input column block addresses CAq to CAq + k are activated, and corresponding selection signals S0 to Sn are output. In the normal access operation, column blocks CB0 to CBn identified by column block addresses CAq to CAq + k are selected as activation regions.
[0038]
According to the first principle, test block signals ST0 to STn output from the test block designating means 1 are further input to the block selection circuits CBS0 to CBSn. The test block designating means 1 is activated during a test access operation and outputs test block signals ST0 to STn. The output test block signals ST0 to STn activate a larger number of block select circuits CBS0 to CBSn than the block select circuits CBS0 to CBSn activated by the column block addresses CAq to CAq + k. A larger number of column blocks CB0 to CBn are selected as activation regions.
[0039]
As a method of selecting the test block signals ST0 to STn in the test block designating means 1, as for a predetermined upper address or a predetermined lower address of the column block addresses CAq to CAq + k, a larger number of column blocks CB0 to CBn are always selected. It is conceivable that the state is selected. Further, by setting the test signals input at the start of the test access operation to the test block signals ST0 to STn, all the column blocks CB0 to CBn can be selected regardless of the column block addresses CAq to CAq + k. Conceivable.
[0040]
FIG. 2 shows a second principle of the present invention. For the column blocks CB0 to CBn selected as the activation area, it is necessary to identify individual storage cell columns arranged in the column block. FIG. 2 shows a circuit configuration related to an address storage circuit when an individual storage cell column in a column block is selected. Addresses Ap, Ap + 1,... For identifying storage cell columns in the column block are stored in address storage circuits AL0, AL1,... In response to an address strobe signal SS1 for storing addresses. The stored addresses Ap, Ap + 1,... Are supplied to an internal control circuit (not shown) as column addresses CAp, CAp + 1,. At the time of the normal access operation, the access operation is performed for each storage cell column identified by column addresses CAp, CAp + 1,. At this time, the selected column block is fixed, and an access operation is performed within the column block.
[0041]
According to the second principle, addresses Aq to Aq + k for identifying a column block, which are further selected at the time of the test access operation, are stored in the address storage circuits 3 and 4 according to the strobe signals SST0 to SSTk output from the capture signal generation means 2. Is done. The stored addresses Aq to Aq + k are supplied to an internal control circuit (not shown) as column block addresses CAq to CAq + k. At the time of the test access operation, an access operation is performed on the column block identified by the column block addresses CAq to CAq + k. That is, during the normal access operation, fixed column blocks can be sequentially selected, and in addition to the access within the column block, the access can be sequentially performed while switching the column block.
[0042]
The strobe signals SST0 to SSTk in the capture signal generating means 2 can be output in response to detecting a transition of a logic level with respect to addresses Aq to Aq + k for identifying a column block, and can be substituted by an address strobe signal SS1. Conceivable.
[0043]
FIG. 3 shows a third principle of the present invention. In a continuous address access operation such as a page mode or a burst mode, a new page address needs to be fetched in accordance with a transition of the page address. FIG. 3 shows a circuit configuration for fetching a page address according to an address transition. The page addresses A10 to A1m at which continuous address accesses such as the page mode and the burst mode are performed are input to the address input circuits AIN0 to AINm and then input to the address storage circuits AL10 to AL1m as column page addresses CA10 to CA1m. And input to the address transition detection circuit ATD. Each column page address CA10 to CA1m is stored in each of the address storage circuits AL10 to AL1m based on a transition detection signal SD output from the address transition detection circuit ATD in response to the address transition. The stored column page addresses CA10 to CA1m are supplied to an internal control circuit (not shown), and continuous address access is performed. At the time of the normal access operation, continuous address access is performed for the number of addresses identified by the column page addresses CA10 to CA1m.
[0044]
According to the third principle, the transition detection signal SD is further input to the address storage circuits ALB0 to ALBn, and the addresses AB0 to ABn input via the address input circuits BIN0 to BINn are stored as column block addresses CAB0 to CABn. Here, the column block addresses CAB0 to CABn are identification addresses of the column blocks selected at the time of the test access operation. The stored column block addresses CAB0 to CABn are supplied to an internal control circuit (not shown), and continuous address access is performed over the column blocks. In the test access operation, in addition to the column page addresses CA10 to CA1m, the column block addresses CAB0 to CABn are identified, and continuous address access is performed.
[0045]
Here, the operation of storing the column block addresses CAB0 to CABn in the address storage circuits ALB0 to ALBn can be always performed by directly inputting the transition detection signal SD to the address storage circuits ALB0 to ALBn. By supplying a signal through the capture control unit 5, it is possible to perform the test access operation as needed.
[0046]
The transition detection signal SD controls the address storage circuits AL10 to AL1m for storing the column page addresses CA10 to CA1m and the address storage for storing the column block addresses CAB0 to CABn selected during the test access operation. Only for circuits ALB0 to ALBn.
[0047]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments embodying a semiconductor memory device and a method of controlling the semiconductor memory device of the present invention will be described in detail with reference to the drawings based on FIGS.
[0048]
FIG. 4 is an example of a conceptual view of the arrangement of column blocks in a semiconductor memory device. One of the semiconductor memory devices CHIP divided into a plurality of row blocks WL0, WL1, WL2,... Storage cell areas MC are arranged on the left and right sides of the sense amplifier area SA. The column direction is divided into four divided blocks A to D, and each divided block A to D is further divided into four to form column blocks CB0 to CB3. Each of the divided blocks A to D operates in parallel, and FIG. 4 illustrates a case where the column block CB3 in each of the divided blocks A to D is activated. In each of the divided blocks A to D, activation control of a column block is performed by an equivalent control circuit.
[0049]
FIG. 5 shows a first specific example of the first embodiment. A control circuit that outputs selection signals S0 to S3 for selecting column blocks CB0 to CB3 in each of the divided blocks A to D is shown.
[0050]
The block selection circuits CBS0 to CBS3 have the same circuit configuration. The strobe signal SS instructing the activation timing of the column block is input to the NOR gate in each of the block selection circuits CBS0 to CBS3. The block selection circuits CBS0 to CBS3 are set in a selectable state of the column block by the low-level strobe signal SS. The selection signals S0 to S3 are output from the NOR gate through two-stage inverter gates.
[0051]
Selection of the column blocks CB0 to CB3 is controlled by an output signal from the NAND gate input to the NOR gate. To the NAND gate, column block addresses CAq and CAq + 1 for identifying a column block and their inverted signals are appropriately combined and input. That is, an inverted signal of the block addresses CAq and CAq + 1 is input to the NAND gate of the block selection circuit CBS0, and a low-level signal is output from the NAND gate when both the block addresses CAq and CAq + 1 are at the low level. Similarly, when the block address CAq is at the high level and the block address CAq + 1 is at the low level for the block selection circuit CBS1, the block address CAq is at the low level and the block address CAq + 1 is at the high level for the block selection circuit CBS2. In this case, when both the block addresses CAq and CAq + 1 are at the high level, a low-level signal is output from each NAND gate to the block selection circuit CBS3.
[0052]
At the time of the normal access operation, as described later, the PMOS transistors MP0 to MP3 become conductive, the power supply voltage VDD is supplied to the NAND gate, and the NMOS transistors MN0 to MN3 maintain the non-conductive state. Therefore, the output logic level of the NAND gate is input to the NOR gate, and one of the selection signals S0 to S3 is activated to a high level by the low level signal from the NAND gate, and the corresponding column block CB0 to CB3 is activated. Is selected.
[0053]
The control circuit of FIG. 5 further includes a test block designating circuit 1A. In the test block designating circuit 1A, a test signal TEST that is activated to a high level during a test is input to two sets of NAND gates NA1 and NA2, and a column block address CAq + 1, which is an upper address of the column block addresses, is supplied to the NAND gate. The inverted signal is input to the NAND gate NA1 by the inverter gate, and the inverted signal is input to the NAND gate NA1. Signals from NAND gates NA1 and NA2 are output as output signals via inverter gates. The output signals are input to the gate terminals of the PMOS / NMOS transistors MP0 / MN0 and MP1 / MN1 of the block selection circuits CBS0 and CBS1, and the PMOS / NMOS transistors MP2 / MN2 and MP3 / MN3 of the block selection circuits CBS2 and CBS3, respectively. .
[0054]
Here, the PMOS transistors MP0 to MP3 function as switch circuits for supplying the power supply voltage VDD to the NAND gates provided in the block selection circuits CBS0 to CBS3. The NMOS transistors MN0 to MN3 are provided between the output terminal of each NAND gate and the ground potential. The gate terminals of the PMOS / NMOS transistors MP0 / MN0 to MP3 / MN3 are controlled by the same signal, supply the power supply voltage VDD to each NAND gate by a low level signal, and make the output terminal of the NAND gate non-conductive between the ground potential. I do. Thereby, one of the output signals of the NAND gate is activated to a low level according to the combination of the logic levels of the column block addresses CAq and CAq + 1. When the signal to the gate terminal is a high level signal, the supply of the power supply voltage VDD to each NAND gate is cut off, and the output terminal of the NAND gate is fixed to the ground potential. Thus, the output signal of the NAND gate is activated to a low level regardless of the logic level of the column block addresses CAq and CAq + 1.
[0055]
In the test access operation, the conduction control of the PMOS / NMOS transistors MP0 / MN0 to MP3 / MN3 is controlled by the test block designating circuit 1A so that the PMOS / NMOS transistors MP0 / MN0 and MP1 / MN1, and MP2 / MN2 and MP3 / MN3 are controlled. Performed as a pair.
[0056]
In the test block designating circuit 1A activated by the high-level test signal TEST, one of the output signals from the NAND gates NA1 and NA2 via the inverter gate becomes a high level in accordance with the logical level at the column block address CAq + 1. That is, for the low level column block address CAq + 1, the output signal via the NAND gate NA1 becomes high level, and the block selection circuits CBS0 and CBS1 are activated. The selection signals S0 and S1 become low level, and the column blocks CB0 and CB1 are selected. For the high-level column block address CAq + 1, the output signal via the NAND gate NA2 goes high, and the block selection circuits CBS2 and CBS3 are activated. The selection signals S2 and S3 become low level, and the column blocks CB2 and CB3 are selected.
[0057]
The layout conceptual diagram of the column blocks shown in FIG. 5 shows a case where the column block address CAq + 1 is at the high level in the test access operation. This indicates that the column blocks CB2 and CB3 are activated in each of the divided blocks A to D irrespective of the logical level of the block address CAq which is the lower address, and only the column block CB3 is activated during the normal access operation. As shown in FIG. 4, twice as many column blocks are activated. Although not shown, when the column block address CAq + 1 is at a low level, the column blocks CB0 and CB1 are activated.
[0058]
In the second specific example of the first embodiment shown in FIG. 6, a test block designating circuit 1B is provided instead of the test block designating circuit 1A. In test block designating circuit 1B, column block address CAq, which is a lower address, is input instead of column block address CAq + 1.
[0059]
Regarding the output signal of the test block designating circuit 1B, the output signal via the NAND gate NA1 is input to the PMOS / NMOS transistors MP0 / MN0 and MP2 / MN2 instead of MP1 / MN1, and the output signal via the NAND gate NA2 is The PMOS / NMOS transistors MP3 / MN3 are input to MP1 / MN1 instead of MP2 / MN2.
[0060]
As a result, for the low-level block address CAq, the output signal via the NAND gate NA1 becomes high, and the block selection circuits CBS0 and CBS2 are activated. The selection signals S0 and S2 become low level, and the column blocks CB0 and CB2 are selected. For the high-level block address CAq, the output signal via the NAND gate NA2 goes high, and the block selection circuits CBS1 and CBS3 are activated. The selection signals S1 and S3 become low level, and the column blocks CB1 and CB3 are selected.
[0061]
The column block layout conceptual diagram shown in FIG. 6 shows a case where the block address CAq is at the high level in the test access operation. This indicates that the column blocks CB1 and CB3 are activated in each of the divided blocks A to D regardless of the logical level of the block address CAq + 1 which is the upper address, and only the column block CB3 is activated during the normal access operation. As shown in FIG. 4, twice as many column blocks are activated. Although not shown, when the block address CAq is at a low level, the column blocks CB0 and CB2 are activated.
[0062]
In the third specific example of the first embodiment shown in FIG. 7, a test signal TEST is directly applied to each of the PMOS / NMOS transistors MP0 / MN0 to MP3 / MN3 instead of the output signals output from the test block designating circuits 1A and 1B. Is entered.
[0063]
As a result, the test signal TEST attains a high level during the test access operation, so that the block selection circuits CBS0 to CBS3 are both activated. The selection signals S0 to S3 are all at the low level, and the column blocks CB0 to CB3 are all selected.
[0064]
The column block layout conceptual diagram shown in FIG. 7 shows that all the column blocks CB0 to CB3 of each of the divided blocks A to D are activated in the test access operation. Four times as many column blocks are activated as when only the column block CB3 is activated during the normal access operation (FIG. 4).
[0065]
As described above in detail, according to the first embodiment, during the test access operation, the number of column blocks CB0 to CB3 that are activated and controlled in the access operation is compared with the number of column blocks CB0 to CB3 during the normal access operation. In the second specific example, it can be increased twice, and in the third specific example, it can be increased four times. It is possible to have a larger access area in the test access operation than in the normal access operation. When testing the entire area of the semiconductor memory device, the switching frequency of the column blocks CB0 to CB3 controlled to be activated is reduced to half in the first and second specific examples and to the third specific example in comparison with the normal access operation. In the example, it can be reduced to 1/4. The total switching time required for switching between the column blocks CB0 to CB3 is reduced, and the overhead of the switching time in the test time is reduced, so that the test time can be shortened.
[0066]
In the first and second specific examples, the test block designating circuits 1A and 1B are activated and controlled by the test signal TEST, and the number of column blocks selected at the time of the test access operation is determined.
[0067]
Specifically, with respect to column block addresses CAq and CAq + 1 for identifying a column block selected at the time of the test access operation, the block address CAq which is a predetermined lower address or the block address CAq + 1 which is a predetermined upper address is set to a logical level of a signal. Regardless, it is selected. Thus, the column blocks CB0 and CB1, CB2 and CB3, CB0 and CB2, CB1 and CB3 both selected by the column block address CAq + 1 or the block address CAq are selected. This selection state is performed when the test block designating circuits 1A and 1B are activated by the test signal TEST, so that a larger number of column blocks can be selected in the test access operation than in the normal access operation. .
[0068]
In the first and second specific examples, a 2-bit address of CAq and CAq + 1 has been described as an example of the column block address selected at the time of the test access operation. However, the present invention is not limited to this. Needless to say, the present invention can be similarly applied to a case where a column block address of 3 bits or more is provided. In this case, the predetermined upper address or the predetermined lower address to be selected regardless of the logic level of the signal can be set to 2 bits or more.
[0069]
It is also possible to adopt a configuration in which the first and second specific examples are mixed. The column block can be set to the selected state regardless of the predetermined upper address and the predetermined lower address.
[0070]
Further, in the test access operation, the address to be selected regardless of the logic level of the signal is replaced with the predetermined upper address or the predetermined lower address, or together with these addresses, the address in the middle of the predetermined upper / lower address. It is also possible.
[0071]
In the third specific example, at the time of the test access operation, all the column selection circuits CBS0 to CBS3 are activated in accordance with the test signal TEST. In the test access operation, a plurality of column blocks CB0 to CB3 divided in the column direction are activated together.
[0072]
In the third specific example, the case where all the column selection circuits CBS0 to CBS3 are activated is shown. However, there is a case where the power supply voltage supply capability is limited, such as when an internal power supply or the like is provided in the semiconductor memory device. In this case, it is preferable to set an activation region of a column block to be activated within a range of a power supply voltage supply capability. When the internal power supply is specified by the power supply capability required for the refresh operation, the column block area activated in the test access operation is equal to or less than the column block area activated in the refresh operation. Is preferred. As a result, in the test access operation, the power supply voltage is not reduced due to the shortage of the power supply voltage, and an efficient test can be performed while activating the maximum number of column blocks with an appropriate power supply voltage. .
[0073]
The second embodiment shown in FIG. 8 is a circuit diagram relating to taking in addresses Aq and Aq + 1 for identifying a column block selected during a test access operation according to the first embodiment.
[0074]
With respect to the column blocks selected as the activation area in the first embodiment, the addresses Aq and Aq + 1 for identifying the column blocks are stored in the address storage circuits 31 and 41 in order to access the individual memory cell columns in each column block. It is necessary to capture. In the address storage circuits 31 and 41, the signal fetched via the transfer gate is latched by a latch circuit composed of two inverter gates, and is output via the inverter gate.
[0075]
It is desirable that the fetching of the addresses Aq and Aq + 1 into the address storage circuits 31 and 41 be performed in accordance with the column blocks selected according to the first to third specific examples of the first embodiment.
[0076]
FIG. 8A corresponds to a first specific example (FIG. 5) of the first embodiment. In this case, since column blocks CB0 and CB1 or CB2 and CB3 are selected, the column block is selected depending on which of the selected column blocks CB0 and CB1 or CB2 and CB3 is accessed. It is necessary to take in the address Aq as the address CAq. By providing the address transition detection circuit ATD for detecting the transition of the address Aq, the transfer gate can be controlled using the detection signal as the strobe signal, and the address Aq can be stored in the address storage circuit 31.
[0077]
Similarly, FIG. 8B corresponds to a second specific example (FIG. 6) of the first embodiment. In this case, since the column blocks CB0 and CB2 or CB1 and CB3 are selected regardless of the column block address CAq + 1, it is necessary to take in the address Aq + 1 as the column block address CAq + 1 according to the access to each column block. . By providing the address transition detection circuit ATD for the address Aq + 1, the transfer gate can be controlled using the detection signal as the strobe signal, and the address Aq + 1 can be stored in the address storage circuit 41.
[0078]
Further, FIG. 8C corresponds to a third specific example (FIG. 7) of the first embodiment. In this case, since all the column blocks CB0 to CB3 are selected regardless of the column block addresses CAq and CAq + 1, the addresses Aq and Aq + 1 are set as the column block addresses CAq and CAq + 1 according to the access to each column block. Need to capture. By providing the address transition detection circuit ATD for each of the addresses Aq and Aq + 1, it is possible to control the transfer gate using the detection signal as a strobe signal and store the respective addresses Aq and Aq + 1 in the address storage circuits 31 and 41. it can.
[0079]
As described above, according to the second embodiment, the transition is detected by the address transition detection circuit ATD for the column block address for the column block selected in the test access operation but not in the normal access operation, and the address storage circuit Column blocks 31 and 41, which are selected and can be selected, can be identified.
[0080]
In the second embodiment, the case where the taking in of the addresses Aq and Aq + 1 is performed in response to detecting the own signal transition is described. However, the present invention is not limited to this, and the column block address CAq , CAq + 1, it is also possible to adopt a configuration in which the address is taken in according to the transition of the first address for identifying each memory cell column in each column block. Thereby, at the time of the test access operation, the addresses Aq and Aq + 1 are also taken in with the first address taken in accordance with the transition of the first address. The column block addresses CAq and CAq + 1 for identifying the column blocks are upper addresses of the first addresses for identifying the column direction addresses in each column block, so that the first address makes a round and transitions to the initial address. The addresses Aq and Aq + 1 also transition. Therefore, the addresses Aq and Aq + 1 can be captured by the capture signal generated according to the transition of the first address, and there is no need to generate a dedicated capture signal according to the transition of the addresses Aq and Aq + 1.
[0081]
FIG. 9 shows that in a continuous address access operation such as a page mode or a burst mode, in the test access operation, in addition to newly taking in the page addresses A0 and A1 in accordance with the transition of the page addresses A0 and A1, the test access operation is performed. In this configuration, an address A2 for identifying a column block which is sometimes selected is also taken.
[0082]
The addresses A0 to An are input to the address input circuits AIN0 to AINn, and the addresses A0 to An are input according to the high level of the enable signal EN. The input addresses A0 to An are input to the address storage circuits AL0 to ALn as column addresses CA0 to CAn. Of the column addresses CA0 to CAn, the column addresses CA0 and CA1 are page addresses when a continuous address access such as a page operation is performed, and the column address CA2 is a column block enlarged and selected during a test access operation. Column block address for identifying The column page addresses CA0 and CA1 are input to the address transition detection circuit ATD.
[0083]
The address transition detection circuit ATD includes signal transition detection units TD1 and TD2 for each column address. Here, the signal transition detection unit TD1 is a circuit that detects a transition from a low level to a high level of the column page addresses CA0 and CA1, which are input signals. In response to detecting a signal transition, a low-level pulse having a pulse width corresponding to the delay time of the odd-numbered stages of inverter gate rows is output. The signal transition detection unit TD2 is a circuit that detects a transition from a high level to a low level of an input signal. In response to detecting a signal transition, a high-level pulse having a pulse width corresponding to the delay time of the odd-numbered stages of inverter gate rows is output. This high-level pulse signal is supplied to the NAND gate as a low-level pulse signal via the inverter gate.
[0084]
The low-level pulse signal output according to the transition between the logic levels is input to the NAND gate for each of the column page addresses CA0 and CA1. From the NAND gate, a high-level pulse signal is output according to the transition. The output signal of the NAND gate is ORed by the NOR gate and output as a high-level pulse signal via the inverter gate. This pulse signal is the address transition detection signal SD1. Further, the output pulse signal SD2 of the signal transition detection circuit STD for detecting the transition of the control signal / CE1 from the high level to the low level is input to the NOR gate. When control signal / CE1 transitions to a low level to activate an access operation, signal transition detection circuit STD outputs a high-level output pulse signal SD2.
[0085]
The address storage circuits AL0 to ALn have the same circuit configuration as the address storage circuits 31 and 41 shown in FIG. Among the column addresses CA0 to CAn, the address storage circuits AL0 and AL1 to which the column page addresses CA0 and CA1 are input are used as strobe signals for taking in the respective addresses CA0 and CA1 and the detection signal SD1 output from the address transition detection circuit ATD. , An output pulse signal SD2 output from the signal transition detection circuit STD is supplied via a NOR gate and an inverter.
[0086]
The address storage circuit AL2, to which the column block address CA2 is input, receives the detection signal SD1 via the capture control unit 51 and the output pulse signal SD2 as strobe signals for capturing the column block address CA2 via a NOR gate and an inverter. Supplied.
[0087]
Output pulse signal SD2 is supplied to other address storage circuits ALn as an input strobe signal for column address CAn.
[0088]
Switching of the capture control unit 51 is controlled by a test signal TEST. During the test, a detection signal SD1 output from the address transition detection circuit ATD is supplied to the NOR gate as an additional strobe signal to the address storage circuit AL2. During normal operation, the supply line of the detection signal SD1 is fixed to the ground potential, and the detection signal SD1 is not supplied as a strobe signal to the address storage circuit AL2.
[0089]
FIG. 10 shows operation waveforms of the third embodiment (FIG. 9). FIG. 10A shows a normal access operation. The detection signal SD1 is supplied only to the address storage circuits AL0 and AL1, and functions as a strobe signal for taking in the column page addresses CA0 and CA1 together with the output pulse signal SD2 from the signal transition detection circuit STD. In this case, the strobe signal to the address storage circuit AL2 is only the output pulse signal SD2.
[0090]
The output pulse signal SD2 outputs a high-level pulse in response to the low-level transition of the control signal / CE1 indicating the start of the access operation. The column addresses CA0 to CA2 are taken into the address storage circuits AL0 to AL2 by the high level pulse of the output pulse signal SD2. At this time, the logical level of each address taken in is CA0, CA1 = 0, and CA2 = 0. Thereafter, the column page addresses CA0 and CA1 are sequentially incremented at a predetermined timing, and the page operation is started. A high-level pulse detection signal SD1 is generated according to the transition of the column page addresses CA0 and CA1. In response to the detection signal SD1 of the high-level pulse, the column page addresses CA0 and CA1 are taken into the address storage circuits AL0 and AL1. Here, the column page addresses CA0 and CA1 are 2-bit addresses, and can identify four addresses. After CA0, CA1 = 0, four addresses 1, 2, and 3 are fetched, the control signal / CE1 transitions to a high level, and the page operation ends.
[0091]
In the test access operation shown in FIG. 10B, the capture control unit 51 also supplies the detection signal SD1 to the address storage circuit AL2 as a strobe signal. Then, in accordance with the timing when the page operation continues and the column page addresses CA0 and CA1 return to the initial addresses (CA0 and CA1 = 0), the column block address CA2 which is the upper address thereof is transited (in FIG. 10B). Increments from CA2 = 0 to CA2 = 1.) Thus, the transitioned column block address CA2 is taken into the address storage circuit AL2 by the detection signal SD1 corresponding to the address transition when the column page addresses CA0, CA1 return to the initial address (CA0, CA1 = 0). The page operation can be continued even for a newly fetched block address, and the page operation can be continued for an address area twice as long as in the normal access operation.
[0092]
As described above in detail, according to the third embodiment, during the test access operation, the column page addresses CA0 and CA1 are taken in according to the transition of the column address CA0 and CA1 as the first address. The column block address CA2 as the second address is also taken in. Since the column block address CA2 is an upper address of the column page addresses CA0 and CA1, the column block address CA2 also transits in synchronization with the transition of the column page addresses CA0 and CA1 to the initial address (CA0, CA1 = 0). I do. Therefore, when performing a continuous access operation in accordance with the transition of the column page addresses CA0 and CA1, the column block address CA2 can be taken together with the column page addresses CA0 and CA1, and a continuous access operation is performed in an area across the column blocks. be able to. At this time, there is no need to generate a dedicated capture signal according to the transition of the column block address CA2.
[0093]
Further, the capture control unit 51 is activated during the test access operation by the test signal TEST, and the detection signal SD1 for detecting the transition of the column page addresses CA0 and CA1 can also be used for the capture control of the column block address CA2. .
[0094]
It should be noted that the present invention is not limited to the above embodiment, and it is needless to say that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, a column block in one row block WL0 has been described as an example. However, the present invention is not limited to this, and a plurality of row blocks can be operated simultaneously. Needless to say.
Also, the case where the column direction is divided into four divided blocks A to D has been described, but it goes without saying that the division mode of the column blocks can be set as appropriate.
[0095]
Here, means for solving the problems in the prior art based on the technical idea of the present invention are listed below.
(Supplementary Note 1) The column direction is divided into a plurality of column blocks as an activation unit of the access operation, and at the time of the normal access operation, at least one of the block selection circuits provided for each of the column blocks is activated and at least one of the block selection circuits is activated. A semiconductor memory device in which the column block is selected as an activation region,
A semiconductor memory device wherein a larger number of the block selection circuits are activated during a test access operation than the block selection circuits activated during a normal access operation.
(Supplementary Note 2) A test block specifying circuit that is activated and controlled by the test signal and generates a test block signal that specifies a column block selected at the time of a test access operation,
2. The semiconductor memory device according to claim 1, wherein the block selection circuit is activated based on the test block signal.
(Supplementary Note 3) The test block designating circuit receives a column block address for identifying the column block,
3. The semiconductor memory device according to claim 2, wherein at least one of a predetermined upper address and a predetermined lower address of the column block addresses is identified as a selected state during the test access operation.
(Supplementary Note 4) The semiconductor memory device according to supplementary note 1, wherein the block selection circuit is activated by a test signal.
(Supplementary Note 5) A block address storage unit that stores a column block address for identifying the column block,
Activation signal is controlled by a test signal, and a capture signal generation unit that generates a capture signal according to a transition of a selected block address that identifies the column block selected at the time of a test access operation,
2. The semiconductor memory device according to claim 1, wherein the column block address including at least the selected block address is loaded into the block address storage unit based on the capture signal.
(Supplementary Note 6) A block address storage unit that stores a column block address for identifying the column block,
A capture signal generation unit that generates a capture signal in response to a transition of a first address for identifying a column direction address in the column block,
2. The semiconductor memory device according to claim 1, wherein the column block address is fetched into the block address storage unit based on the fetch signal during a test access operation.
(Supplementary Note 7) An address transition detection unit that detects a transition of the selected block address or the first address and outputs a detection signal,
7. The semiconductor memory device according to claim 5, wherein the address transition detection section is the capture signal generation section, and the detection signal is the capture signal.
(Supplementary Note 8) A semiconductor memory device in which a continuous access operation is performed according to a transition of a first address during a normal access operation,
An address transition detection unit that detects a transition of the first address;
A first address storage unit that receives the first address based on a detection signal from the address transition detection unit;
A semiconductor memory device, comprising: a second address storage unit for taking in a second address, which is an upper address of the first address, based on a detection signal from the address transition detection unit during a test access operation.
(Supplementary Note 9) The apparatus further includes a capture control unit that is activated by a test signal and generates a capture signal that captures the second address into the second address storage unit based on the detection signal. 9. The semiconductor memory device according to 8.
(Supplementary Note 10) The semiconductor memory device according to supplementary note 8, wherein the first address is a page address.
(Supplementary Note 11) A control method of a semiconductor memory device in which a column direction is divided into a plurality of column blocks as an activation unit of an access operation,
A normal access operation step in which at least one of the column blocks is selected as an active area;
A test access operation step in which a greater number of the column blocks are selected as active areas than the column blocks selected in the normal access operation step.
(Supplementary Note 12) A test block specifying step is provided, in which activation is controlled by a test signal activated in the test access operation step and a test block signal specifying a column block selected in the test access operation step is generated. 12. The method for controlling a semiconductor memory device according to supplementary note 11, wherein
(Supplementary Note 13) In the test block designating step, the test block signal is generated by selecting at least one of a predetermined upper address and a predetermined lower address among column block addresses for identifying the column blocks. 13. The method for controlling a semiconductor memory device according to supplementary note 12, wherein
(Supplementary note 14) The control method of a semiconductor memory device according to supplementary note 11, wherein a column block selected in the test access operation step is specified based on a test signal activated in the test access operation step. .
(Supplementary Note 15) The column block address including at least the selected block address in accordance with the transition of the selected block address for identifying the column block selected in the test access operation step among the column block addresses for identifying the column block. 12. The control method of a semiconductor memory device according to claim 11, further comprising a block address fetching step for fetching a block address.
(Supplementary note 16) The supplementary note 11, further comprising a block address fetching step in which a column block address for identifying the column block is fetched in response to a transition of a first address for identifying a column direction address in the column block. The control method of the semiconductor memory device described in the above.
(Supplementary Note 17) An address transition detecting step of detecting a transition of the selected block address or the first address,
17. The method of controlling a semiconductor memory device according to claim 15, wherein the block address fetching step is performed in response to the address transition detecting step.
(Supplementary Note 18) A method of controlling a semiconductor memory device in which a continuous access operation is performed according to a transition of a first address during a normal access operation,
An address transition detecting step of detecting a transition of the first address;
A first address storing step of receiving the first address based on the address transition detecting step;
And a second address storing step of taking in a second address, which is an upper address of the first address, based on the address transition detecting step during a test access operation.
(Supplementary note 19) The method of controlling a semiconductor memory device according to supplementary note 18, wherein the first address is a page address.
[0096]
【The invention's effect】
According to the present invention, it is possible to expand a column block area to be selectively activated during a test or to expand a continuous access area in a page operation while maintaining a low current consumption operation during a normal access operation. Accordingly, it is possible to provide a semiconductor memory device capable of reducing the test time and a method of controlling the semiconductor memory device.
[Brief description of the drawings]
FIG. 1 is a first principle diagram of the present invention.
FIG. 2 is a second principle diagram of the present invention.
FIG. 3 is a third principle diagram of the present invention.
FIG. 4 is a conceptual diagram showing a column block in a semiconductor memory device.
FIG. 5 is a diagram showing a first specific example of the first embodiment.
FIG. 6 is a diagram showing a second specific example of the first embodiment.
FIG. 7 is a diagram illustrating a third specific example of the first embodiment.
FIG. 8 is a circuit diagram showing a second embodiment.
FIG. 9 is a circuit diagram showing a third embodiment.
FIG. 10 is an operation waveform diagram showing a third embodiment.
FIG. 11 is a diagram showing a configuration for selectively activating a column block.
[Explanation of symbols]
1 Test block designating means
1A, 1B test block designating circuit
2 Capture signal generation means
3, 4, 31, 41, AL0 to ALn, AL10 to AL1m, ALB0 to ALBn Address storage circuit
5, 51 Capture control unit
ATD address transition detection circuit
CB0 to CBn Column block
CBS0 to CBSn block selection circuit
MP0 to MP3 PMOS transistors
MN0 to MN3 NMOS transistors
STD signal transition detection circuit

Claims (10)

The column direction is divided into a plurality of column blocks as an activation unit of the access operation. At the time of the normal access operation, at least one of the block selection circuits provided for each column block is activated, and at least one of the column blocks is activated. A semiconductor memory device selected as an activation region,
A semiconductor memory device wherein a larger number of the block selection circuits are activated during a test access operation than the block selection circuits activated during a normal access operation. A test block designating circuit that is controlled to be activated by a test signal and generates a test block signal that designates a column block selected during a test access operation;
2. The semiconductor memory device according to claim 1, wherein said block selection circuit is activated based on said test block signal. The test block designating circuit receives a column block address for identifying the column block,
3. The semiconductor memory device according to claim 2, wherein at the time of a test access operation, at least one of a predetermined upper address and a predetermined lower address of the column block addresses is identified as a selected state. 2. The semiconductor memory device according to claim 1, wherein said block selection circuit is activated by a test signal. A block address storage unit for storing a column block address for identifying the column block,
Activation signal is controlled by a test signal, and a capture signal generation unit that generates a capture signal according to a transition of a selected block address that identifies the column block selected at the time of a test access operation,
2. The semiconductor memory device according to claim 1, wherein said column block address including at least said selected block address is taken into said block address storage section based on said take-in signal. A block address storage unit for storing a column block address for identifying the column block,
A capture signal generation unit that generates a capture signal in response to a transition of a first address for identifying a column direction address in the column block,
2. The semiconductor memory device according to claim 1, wherein at the time of a test access operation, said column block address is fetched into said block address storage section based on said fetch signal. A semiconductor memory device in which a continuous access operation is performed according to a transition of a first address during a normal access operation,
An address transition detection unit that detects a transition of the first address;
A first address storage unit that receives the first address based on a detection signal from the address transition detection unit;
A semiconductor memory device, comprising: a second address storage unit for taking in a second address, which is an upper address of the first address, based on a detection signal from the address transition detection unit during a test access operation. 8. The apparatus according to claim 7, further comprising: a capture control unit that is activated by a test signal and generates a capture signal for capturing the second address into the second address storage unit based on the detection signal. Semiconductor storage device. A method of controlling a semiconductor memory device in which a column direction is divided into a plurality of column blocks as an activation unit of an access operation,
A normal access operation step in which at least one of the column blocks is selected as an active area;
A test access operation step in which a greater number of the column blocks are selected as active areas than the column blocks selected in the normal access operation step. A method for controlling a semiconductor memory device in which a continuous access operation is performed in response to a transition of a first address during a normal access operation,
An address transition detecting step of detecting a transition of the first address;
A first address storing step of receiving the first address based on the address transition detecting step;
And a second address storing step of taking in a second address, which is an upper address of the first address, based on the address transition detecting step during a test access operation.

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