JP2004193487A - Exposure method and aligner - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an exposure method, capable of highly accurately aligning a mask when performing exposure by using a complementary divided mask or a combined mask, consisting of a plurality of masks. <P>SOLUTION: In a step S<SB>1</SB>of the exposure method, preceding exposure is performed. All offset parameters of an exposure device, a superposition measuring instrument, etc. are reset to 0, and a test wafer is precedently exposed by using a complementary divided mark, in which a design pattern is divided into M blocks. In step S<SB>2</SB>, the positions of alignment marks of a target layer X<SB>n</SB>(1≤n≤M) and an alignment layer Y<SB>n</SB>are measured, by using the superposition measuring instrument to obtain measured data A<SB>n</SB>. In step S<SB>3</SB>, the mark information of the target layer X<SB>n</SB>and that of the alignment layer Y<SB>n</SB>are imparted to the measured data A<SB>n</SB>as layer data. In step S<SB>4</SB>, positional information is calculated so that an alignment deviation is minimized, on the basis of the measured data A<SB>n</SB>of n-th block only, when the layer data imparted in the step S<SB>3</SB>are the same data (X<SB>n</SB>=Y<SB>n</SB>) for preparing the preceding information A<SB>n</SB>. In a step S<SB>5</SB>, an offset value is determined, on the basis of the precedent information A<SB>n</SB>and inputted to the exposure device, the alignment layer Y<SB>n</SB>and the target layer X<SB>n</SB>are re-aligned, and then regular exposure is performed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an exposure method used in a manufacturing process of a semiconductor device or the like, and more particularly, to a method of performing exposure with high precision using a complementary division mask or a combination mask including a plurality of masks.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the increase in the degree of integration and the reduction in chip size of semiconductor devices, it has become necessary to further miniaturize components such as wirings constituting the semiconductor device.
At the time of lithography processing for forming a resist pattern necessary for patterning a component of a semiconductor device, for example, a wiring layer, light exposure using KrF, ArF, or the like as exposure light is mainly used at present, but in the future, miniaturization will be performed. In response to the request, the photolithography required for patterning when the line width of the circuit pattern becomes 100 nm or less_TwoVarious exposure methods to which an electron beam exposure technology, an X-ray exposure technology, EUV (extreme ultraviolet light), etc. are applied have been proposed.
[0003]
Originally, from the viewpoint of extension of optical lithography, F_TwoHowever, it is difficult to control the corrosion of the components of the exposure apparatus, and because of its short wavelength of 157 nm, it is easily absorbed in air. It is difficult to construct an exposure apparatus by using it as it is. As a result, F_TwoIs being developed as a candidate for a next-generation exposure technology.
[0004]
As for the electron beam exposure technology, in addition to the direct writing method which is currently being developed, development of a low energy electron beam lithography technology devised by Takao Utsumi in 1998 and disclosed in Patent Publication No. 2951947 has begun. ing. The method invented by Takao Utsumi is a method called LEEPL, in which close-exposure is performed with an equal-size stencil mask using an acceleration voltage of about 2 keV, and is a powerful method for patterning semiconductor devices with a line width of 100 nm or less. It is attracting attention as a method.
In addition, an EPL technology or the like for performing exposure using an acceleration voltage of 100 keV using an electron optical system reduced to 1/4 times has been developed.
Furthermore, EUV is a method of exposing using 13 nm extreme ultraviolet light, and is being developed in Japan mainly by ASET.
[0005]
In next-generation electron beam lithography such as LEEPL or EPL, instead of the quartz mask used so far, a thin film of Si, SiC, diamond or the like is used as a material of a membrane area as a drawing area, and the thin film is directly applied to the membrane area. A stencil mask having grooves or openings is used.
[0006]
When a stencil mask is used, the electron beam passes through a groove (opening) of the stencil mask, reaches the resist film on the wafer, and exposes the resist material. If the resist material is a positive resist material, the portion drawn by the electron beam is dissolved in alkali and removed, and the portion not drawn is formed as a pattern made of a resist film.
By the way, with a stencil mask, a donut-shaped pattern or a pattern that is easily deformed cannot be formed in order to form a groove or an opening in a membrane region.
Therefore, one pattern based on the design data is divided into two or more blocks, and a complementary division stencil mask which is separated and separately arranged on one mask is used. A complementary division technique for superposing and exposing each block on the upper exposure area is essential.
[0007]
Here, an example in which patterning cannot be performed according to design data when patterning is performed by electron beam lithography using a normal stencil mask other than the complementary division stencil mask will be described with reference to FIG. FIGS. 4A to 4C are conceptual perspective views for explaining that even if an annular pattern and a U-shaped pattern are transferred by electron beam lithography using one stencil mask, they cannot be transferred.
When the pattern design data is a rectangular annular pattern 12 and a U-shaped pattern 14 as shown in FIG. 4A, a stencil mask 16 having an opening pattern of the annular pattern 12 and the U-shaped pattern 14 is formed. I can't.
[0008]
That is, in the case of the annular pattern 12, as shown in FIG. 4B, although the opening pattern of only the outer contour 12 a or the inner contour 12 b of the annular pattern 12 can be formed, both the outer contour 12 a and the inner contour 12 b are formed. Cannot be formed on the mask surface 13.
When the wafer W is exposed with a stencil mask 16 having an opening pattern of only the outer contour 12a or the inner contour 12b, the transferred pattern 18 is different from the design data pattern 12, as shown in FIG. It becomes.
[0009]
Further, when the design data of the pattern is a U-shaped pattern 14 as shown in FIG. 4A, even if the opening pattern of the U-shaped pattern 14 is formed on the stencil mask 16, As shown in ()), the portion 14b forming the inner contour 14a of the U-shaped pattern 14 is deformed because it is long. Therefore, the portion 14b forming the inner contour 14a must be shortened.
When the portion 14b forming the inner contour 14a is exposed on the wafer W with the stencil mask 16 having a short pattern opening, as shown in FIG. 4C, the transferred pattern 20 becomes the U-shaped pattern 14 of the design data. Is a different pattern.
[0010]
Therefore, the complementary division stencil mask described above has been developed. FIGS. 5A to 5D are conceptual perspective views illustrating steps when transferring a circular pattern and a U-shaped pattern by electron beam lithography using a complementary division stencil mask.
In the complementary division type stencil mask, the annular pattern 12 and the U-shaped pattern 14 shown in FIG. 5A correspond to the first block 22 shown in FIG. The first block 22 and the second block 24 are separated from each other and provided on separate complementary stencil masks at separate positions.
As shown in FIG. 5B, the first block 22 includes upper and lower two band-shaped openings 26 a and 26 b of a pattern obtained by dividing the annular opening of the annular pattern 12, and a U-shaped pattern 14. It has a pattern 34 composed of two strip-shaped openings 28a and 28b of the pattern obtained by dividing the U-shaped opening.
[0011]
On the other hand, as shown in FIG. 5 (c), the second block 24 includes, in the pattern obtained by dividing the annular opening of the annular pattern 12, the opening pattern of the two left and right band-shaped openings 30a and 30b, and the U-shaped pattern. There is provided an opening pattern 36 including a band-shaped opening 32 that connects two band-shaped openings 28a and 28b among the patterns obtained by dividing the 14 U-shaped openings.
At the time of exposure, first, the first block 22 of the complementary division stencil mask is aligned with the exposure position, and the pattern 34 of the first block is exposed and transferred, and then the complementary division stencil mask is moved. Then, the second block 24 is aligned with the exposure position, and the pattern 36 of the second block 24 is exposed and transferred.
Thus, the annular pattern 12 and the U-shaped pattern 14 of the design data can be exposed on the wafer W as shown in FIG.
[0012]
Furthermore, apart from the complementary division stencil mask used in electron beam lithography, even with current optical lithography, patterns with different pattern densities have been It is becoming difficult to carry out under the above exposure conditions.
Therefore, exposure may be performed using a combination mask composed of two or more masks depending on the pattern density, even though it is one exposure step. For example, when the pattern density of one mask differs for each region, two combined masks of a mask having a high pattern density and a mask having a low pattern density are used.
[0013]
When exposure is performed using a complementary division type stencil mask (hereinafter, referred to as a complementary division mask) or a combination mask including a plurality of masks, mask alignment is performed in addition to the normal overlay with the underlying layer. The superposition of layers, that is, the superposition of target layers or alignment layers, must be considered.
Here, the target layer refers to a base layer when the mask and the base layer are aligned, that is, when the second block of the complementary division mask is aligned with the first block, or when the second block of the combination mask is aligned. When the mask is aligned with the first mask, it refers to the first block or the first mask.
In addition, the alignment layer refers to a layer that is aligned with the target layer, that is, a mask when aligning the mask and the underlying layer, and when aligning blocks or masks, for example, the second of a complementary division mask is used. When the block is aligned with the first block, or when the second mask of the combination mask is aligned with the first mask, it refers to the second block or the second mask.
Here, for example, assuming that the required overlay accuracy is ± 20 nm, in the case of a single mask, the alignment process is only a target process of performing overlay of ± 20 nm. In some cases, it is necessary to suppress the misalignment within ± 20 nm in consideration of the overlay accuracy of the same layer. Therefore, more accurate superposition is required.
[0014]
The alignment method is roughly classified into a global alignment method and a chip alignment (die-by-die alignment) method.
The global alignment method is a method in which after a wafer is loaded, alignment measurement is performed on a plurality of wafers in advance, and the result is statistically processed to determine the alignment position on the entire surface of the wafer.
In the global alignment method, when a specific chip, for example, a wafer shown in FIG. 6 is taken as an example, alignment is performed at CMs at four corners of a thick-lined chip, and the wafer is turned back and exposed in stripes. The number of chips to be aligned and the positions of the chips are arbitrary. The CM is an alignment mark of each chip.
[0015]
In the global alignment method, since the number of detection marks at the time of alignment is small, the efficiency of exposure operation is high, and high throughput can be realized. Further, since the accuracy of the alignment coefficient can be increased by the statistical processing, there is an advantage that even when the measurement reproducibility of the alignment mark is poor, it can be dealt with.
Disadvantages of the global alignment method are that it cannot cope with changes over time during writing, such as thermal expansion and wafer slip, and that accuracy cannot be improved if the chip arrangement of the underlying wafer is complicatedly shifted.
[0016]
On the other hand, the chip alignment method is a method in which, as shown in FIG. 7, all chips on a wafer are aligned with CMs at four corners of each chip, and the chip is exposed.
The chip alignment method has an advantage that it can cope with a temporal change during writing such as thermal expansion and wafer slip, and can cope with a case where the chip arrangement of the underlying wafer is complicatedly shifted.
Disadvantages of the chip alignment method are that the number of detection marks during alignment is large, so that the time required for mark detection is long, and that the effect is large when the measurement reproducibility of alignment marks is poor. .
[0017]
[Problems to be solved by the invention]
By the way, usually, the alignment is corrected by a displacement between a box mark (alignment mark) of a base layer (hereinafter, referred to as a target layer) and a box mark of an exposed layer (hereinafter, referred to as an alignment layer). Is measured, and the offset, rotation, magnification, etc. are obtained. The alignment mark includes a bar mark in addition to the box mark.
However, when a complementary division mask and a combination mask composed of a plurality of masks are used, for example, in the case of a complementary division mask composed of X blocks or a combination mask composed of X sheets, one exposure area is used. A maximum of X layers are overlapped, and even if the superposition of any of the X layers results in a displacement exceeding an allowable value, it prevents high precision of alignment and causes electrical failure as a semiconductor device. Occurs.
[0018]
At present, research on alignment of a combination mask composed of a complementary division mask and a plurality of masks has just started, and a breakthrough that can realize a highly accurate alignment technique is desired.
Therefore, an object of the present invention is to provide an exposure method including an alignment method capable of aligning a mask with high accuracy when performing exposure using a complementary division mask or a combination mask including a plurality of masks. is there.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, an exposure method according to the present invention (hereinafter, referred to as a first invention method) is a method of performing exposure using a complementary division mask or a combination mask including a plurality of masks, When aligning for exposure,
A preliminary exposure step of exposing the wafer using a complementary division mask or a combination mask,
Using an overlay measurement device, the position of an alignment mark transferred onto a wafer of a complementary division mask or a combination mask (hereinafter referred to as an alignment layer) is measured, and alignment of the target layer corresponding to the alignment layer with the alignment mark is performed. A shift amount detecting step of detecting a shift amount;
Calculating an offset value based on the amount of misalignment, and inputting the offset value to the exposure apparatus during exposure to compensate for misalignment;
It is characterized by having.
[0020]
In the displacement amount detecting step of the preferred embodiment of the first invention method, of the combinations of the alignment layer and the target layer,
In the exposure using the complementary division mask, the position measurement values of the alignment mark of one alignment layer composed of any one block constituting the complementary division mask and the alignment mark of the target layer corresponding to the one alignment layer are used. To calculate the amount of misalignment,
In the exposure using the combination mask, the alignment is performed by using the position measurement values of the alignment mark of one alignment layer composed of any one of the masks constituting the combination mask and the alignment mark of the target layer corresponding to the one alignment layer. Calculate the amount of deviation.
[0021]
That is, in the displacement amount detecting step of the above-described embodiment of the first invention method, when the design pattern is divided into the first to Xth blocks and a complementary division mask having X blocks in one mask is used. , An alignment mark (box mark or bar mark) of an object block of an arbitrary block, ie, a target layer of an n-th (1 ≦ n ≦ X) block, that is, an underlayer or a layer to which an (n−1) -th block is transferred Is measured only for the alignment mark of the block, and the correction is performed based on the value. The alignment mark includes a bar mark in addition to the box mark. The same applies to the following alignment marks.
When using a combination mask composed of X masks obtained by dividing the design pattern into first to X-th masks, an arbitrary mask, that is, a target target layer of the n-th (1 ≦ n ≦ X) mask, In other words, only the alignment marks (box marks) of the base layer or the layer to which the (n-1) th mask has been transferred and the alignment marks of the nth mask are measured, and correction is performed based on the values. Do.
[0022]
Another exposure method according to the present invention (hereinafter, referred to as a second invention method) is a method of performing exposure using a complementary division mask or a combination mask including a plurality of masks.
A preliminary exposure step of exposing the wafer using a complementary division mask or a combination mask,
Among the combinations of one alignment layer consisting of any one block constituting the complementary division mask and a target layer corresponding to one alignment layer,
In the exposure using the complementary division mask, the alignment layer and the target layer each composed of two or more blocks constituting the complementary division mask are grouped into a group, and the position of each alignment mark in the group is measured using an overlay measuring device. To determine the amount of misalignment,
In the exposure using the combination mask, the alignment layer and the target layer each including at least two or more masks constituting the combination mask are grouped into a group, and the position of each alignment mark in the group is measured using an overlay measuring device. Performing a misalignment amount detecting step of obtaining an misalignment amount;
Calculating an offset value based on the amount of misalignment, and inputting the offset value to the exposure apparatus during exposure to compensate for misalignment;
It is characterized by having.
[0023]
In the shift amount detecting step of the preferred embodiment of the second invention method, in the shift amount detecting step, the number of combinations of the alignment layer and the target layer in the group is started from 1, and the alignment shift amount is within the allowable shift amount. The number of combinations of the alignment layer and the target layer in the group is increased by one until the alignment deviation amount is obtained, and the minimum number of alignment layers in the group when the alignment deviation amount is within the allowable deviation amount. And the amount of misalignment between the target layer and
In the input step, an offset value is calculated based on the amount of alignment deviation, and the offset value is input to the exposure apparatus during exposure to compensate for the alignment deviation.
[0024]
In a preferred embodiment of the first and second invention methods, before the input step, there is a step of determining by simulation whether or not the amount of misalignment is within an allowable amount of misalignment.
[0025]
In order to perform alignment with higher precision than usual, an exposure apparatus that performs the first and second invention methods has alignment functions such as a die-by-die alignment method and a global alignment method, as well as an actual exposure exposure method. This is an exposure apparatus that can improve the accuracy by pre-exposing the wafer beforehand, performing alignment measurement using an overlay measuring device, and inputting the amount of alignment deviation as an offset during actual exposure. .
[0026]
The first and second invention methods can be applied without limitation to the shape of the mask pattern. Further, the algorithms of the first and second invention methods can be introduced as software into a conventional exposure apparatus and an overlay measuring instrument. Furthermore, high-precision management can be realized by alignment in the total overlay, and the line width management margin increases.
In addition, by applying the first and second invention methods, in electron beam drawing, alignment can be performed by correcting the incident angle of the electron beam for each complementary block.
In the first and second invention methods, the overlay measuring device is a concept including an overlay measuring device and a measuring device equivalent to the overlay measuring device.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the accompanying drawings by way of example embodiments.
Embodiment 1
This embodiment is an example of an embodiment of an exposure method according to the first invention, and FIG. 1 is a flowchart showing an alignment procedure when performing exposure according to the embodiment.
In the present embodiment, as shown in FIG.₁To step S_FiveThe alignment at the time of exposure is performed according to the procedure described above.
[0028]
(1) Step S₁In the above, the test wafer is preliminarily exposed using a complementary division mask having M blocks from the first block to the Mth block obtained by dividing the design pattern into M blocks.
In the pre-exposure, all offset parameters of the exposure apparatus, the overlay measurement device, and the like are reset to 0 in order to obtain the amount of misalignment between the target layer and the alignment layer derived from the exposure apparatus, the overlay measurement device, and the like. .
(2) Step S_TwoThen, using the overlay measurement device, the target layer X_n(N: 1, 2,..., M) alignment mark position and alignment layer Y_n(N: 1, 2,..., M) alignment mark positions are measured, and measurement data A_n(N: 1, 2, ..., M).
Here, the target layer X_nMeans the target layer region of the n-th (1 ≦ n ≦ M) block of the complementary division mask, and the alignment layer Y_nMeans the alignment layer region of the n-th block of the complementary division mask.
[0029]
(3) Step S_ThreeAnd the measurement data A of the position of the alignment mark_nTarget layer X to identify_nMark information and alignment layer Y_nMeasurement data A using the mark information of_nAttached to.
As a result, measurement data A_nCan be identified by the layer data.
[0030]
(4) Step S_FourThen, step S_ThreeWith the same layer data (X_n= Y_n) Alone, that is, the target layer X exposed in the n-th block_nAnd alignment layer Y_nMeasurement data A of the alignment mark_nIs calculated based on the position information so as to minimize the amount of misalignment, and the leading information A regarding the alignment is calculated._nCreate Here, the positional information refers to a relative positional shift between the target layer and the alignment layer.
[0031]
(5) Step S_FiveThen, step S_FourInformation A obtained in_nThe offset value on the wafer is determined on the basis of_nTo target layer X_nAnd the actual exposure is performed on the wafer.
Advance information A_nIs the target layer X_nMark information and alignment layer Y_nIs an exposure file composed of data such as offset values such as shift, magnification, rotation, and orthogonality for each combination with the mark information, and is capable of inputting and correcting information.
[0032]
In the present embodiment, the above step S₁To step S_FiveSince the alignment necessary for the actual exposure is performed through the above procedure, the alignment layer can be aligned with the target layer with high accuracy.
[0033]
Embodiment 2
This embodiment is an example of an embodiment of an exposure method according to the second invention, and FIGS. 2 and 3 are flowcharts showing an alignment procedure when performing exposure according to this embodiment.
In the present embodiment, as shown in FIG.₁To step S₁₄The alignment at the time of exposure is performed according to the procedure described above.
[0034]
(1) Step S₁Then, a required specification (specification) for the overlay accuracy of the complementary division mask is input in advance to an exposure apparatus or an overlay measuring instrument.
(2) Step S_TwoIn the method, the test wafer is preliminarily exposed using one complementary division mark having M blocks from the first block to the Mth block obtained by dividing the design pattern into M blocks.
In the pre-exposure, all offset parameters of the exposure apparatus are reset to 0 in order to obtain the amount of alignment deviation between the target layer and the alignment layer derived from the exposure apparatus, the overlay measurement device, and the like.
[0035]
(3) Step S_ThreeThen, using the overlay measurement device, the target layer X_n(N: 1, 2,... M) alignment mark and alignment layer Y_n(N: 1, 2,..., M)_n(N: 1, 2,... M).
Here, the target layer X_nMeans the target layer region of the n-th (1 ≦ n ≦ M) block of the complementary division mask, and the alignment layer Y_nMeans the alignment layer region of the n-th block of the complementary division mask.
[0036]
(4) Step S_FourAnd the measurement data B of the position of the alignment mark_nTarget layer X_nMark information and alignment layer Y_nMark information of measurement data B_nAttached to.
[0037]
(5) Step S_FiveThen, step S_FourIs the same layer data given in_m= Y_m, X_{m + 1}= Y_{m + 1}, X_{m + 2}= Y_{m + 2}... X_{m + k}= Y_{m + k}(M> m + k, m and k are arbitrary numbers), that is, the measured value B of the alignment mark for the m-th block, the (m + 1) -th block,..._m, B_{m + 1}, B_{m + 2}・ ・ ・ ・ ・ ・ B_{m + k}Is used to calculate the amount of misalignment of the m-th block, the (m + 1) -th block,..., The (m + k) -th block.
[0038]
(6) Step S₆Then, step S_FiveInformation (correction value) B based on the alignment deviation amount obtained in_m, B_{m + 1}, B_{m + 2}............ B_{m + k}And the alignment layer Y is determined based on the obtained preceding information._m, Y_{m + 2}............ Y_{m + k}The superposition accuracy G between the two is calculated by simulation.
[0039]
(7) Step S₇Then, step S₆The overlay accuracy G obtained in step S is₁It is determined whether or not the required specifications for alignment set in the step are satisfied.
If the overlay accuracy G satisfies the required specifications for alignment, step S₈If it is determined that the required specifications for alignment are not satisfied, step S₉Move to
(8) Step S₈In the preceding information B_m, B_{m + 1}, B_{m + 2}............ B_{m + k}The offset value on the wafer is determined on the basis of the above, input to the exposure apparatus, alignment is performed on the wafer, and actual exposure is performed.
[0040]
(9) Step S₉Then X_m, X_{m + 1}, Y_m, Y_{m + 1}Is the same group as the preceding information B_m, B_{m + 1}, And B_m, B_{m + 1}Based on the alignment layer Y_m, Y_{m + 1}A superimposition accuracy amount G ′ between them is obtained.
(10) Step S_TenAnd the overlay accuracy G 'is equal to the step S₁It is determined whether or not the required specifications for alignment set in the step are satisfied.
If the overlay accuracy G 'satisfies the required specifications for alignment, step S₁₁If it is determined that the required specifications for alignment are not satisfied, step S₁₂Move to
(11) Step S₁₁Then, advance information B_m, B_{m + 1}The offset value on the wafer is determined on the basis of the above, input to the exposure apparatus, alignment is performed on the wafer, and actual exposure is performed.
[0041]
(12) Step S₁₂Then, layer data of another target layer and layer data of an alignment layer are further added to the group, and for example, X_m, X_{m + 1}, X_{m + 2}, Y_m, Y_{m + 1}, Y_{m + 2}As the same group, leading information B_m, B_{m + 1}, B_{m + 2}Is calculated to determine the amount of alignment deviation G '.
(13) Step S₁₃And the overlay accuracy G 'is equal to the step S₁It is determined whether or not the required specifications for alignment set in the step are satisfied.
If the overlay accuracy G 'satisfies the required specifications for alignment, step S₁₁Returning to step S, if the required specifications for alignment are not satisfied, step S₁₄Move to
[0042]
(14) Step S₁₄Then, the layer data of another target layer and the layer data of the alignment layer are further added to the group, and step S₁₂And the overlay accuracy G ′ is determined in step S₁Step S until the required specifications for the alignment set in₁₃And step S₁₄repeat.
[0043]
The preceding information includes the exposure group setting (X_n...., Y_n...) Is an exposure file including specification offset values such as shift, magnification, rotation, orthogonality, etc., for each of which the information can be input and corrected.
If the overlay accuracy cannot be determined by simulation, a separate method such as exposure and confirmation is also conceivable.
[0044]
In this embodiment, first, the overlay accuracy G between the alignment layers is calculated by simulation, and if the overlay accuracy of the specification is satisfied, the process proceeds to the next stage, so that the alignment accuracy is increased.
Step S₁To step S₁₄By performing alignment at the time of exposure according to the procedure described above, high-precision alignment can be performed when performing exposure using a complementary division mask or a combination mask including a plurality of masks.
Further, in the present embodiment, the method of the present invention is described using a complementary division mask as an example. However, when a combination mask is used, M blocks are read as M masks and blocks are read as masks. Thereby, the method of the present invention can be applied.
In the embodiment, the overlay measurement device is a concept including an overlay measurement device and a measurement device similar to the overlay measurement device.
[0045]
【The invention's effect】
According to the first and second invention methods, when performing alignment using a complementary division mask or a combination mask including a plurality of masks, the wafer is exposed in advance before the actual exposure, and the overlay measurement is performed. The accuracy can be improved by performing alignment measurement using a device and inputting the amount of misalignment as an offset during actual exposure.
According to the first and second invention methods, not only the overlay accuracy of the target layer and the alignment layer, but also the alignment accuracy of the complementary divided masks or the combined masks is improved. Overlap equivalent to mask alignment can be achieved.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating an alignment procedure when performing exposure according to a first embodiment.
FIG. 2 is a flowchart showing an alignment procedure when performing exposure according to a second embodiment.
FIG. 3 is a flowchart showing an alignment procedure when performing exposure according to a second embodiment, following FIG. 2;
FIGS. 4 (a) to 4 (c) are conceptual perspective views for explaining that even if an attempt is made to transfer an annular pattern and a U-shaped pattern by electron beam lithography using one stencil mask, transfer cannot be performed. FIG.
FIGS. 5 (a) to 5 (d) are conceptual perspective views illustrating steps in transferring an annular pattern and a U-shaped pattern by electron beam lithography using a complementary division mask.
FIG. 6 is a wafer diagram illustrating a global alignment method.
FIG. 7 is a wafer diagram illustrating a chip alignment method.
[Explanation of symbols]
12: square annular pattern, 14: U-shaped pattern, 16: stencil mask, 18, 20: transferred pattern.

Claims (5)

Complementary division mask, or a method of exposing using a combination mask consisting of a plurality of masks, in the alignment at the time of exposure,
A preliminary exposure step of exposing the wafer using the complementary division mask or the combination mask,
The position of the alignment mark transferred onto the wafer of the complementary division mask or the combination mask (hereinafter, referred to as an alignment layer) is measured using an overlay measurement device, and alignment of a target layer corresponding to the alignment layer is performed. A shift amount detecting step of detecting an alignment shift amount with respect to the mark;
An input method for calculating an offset value based on the amount of alignment deviation, and inputting the offset value to an exposure apparatus during exposure to compensate for the alignment deviation. In the deviation amount detecting step, of the combination of the alignment layer and the target layer,
In the exposure using the complementary division mask, the position measurement of the alignment mark of one alignment layer composed of any one block constituting the complementary division mask and the alignment mark of the target layer corresponding to the one alignment layer is performed. Using the value to calculate the amount of misalignment,
In the exposure using the combination mask, the position measurement values of the alignment mark of one alignment layer composed of any one of the masks composing the combination mask and the alignment mark of the target layer corresponding to the one alignment layer are measured. The exposure method according to claim 1, wherein the amount of misalignment is calculated by using the method. A method of performing exposure using a complementary division mask or a combination mask including a plurality of masks,
A preliminary exposure step of exposing the wafer using the complementary division mask or the combination mask,
Of the combination of one alignment layer consisting of any one block constituting the complementary division mask and a target layer corresponding to the one alignment layer,
In the exposure using the complementary division mask, the alignment layer and the target layer each composed of two or more blocks constituting the complementary division mask are grouped into a group, and each alignment mark of the group is determined using an overlay measuring device. By performing the position measurement, the amount of the alignment deviation is obtained,
In the exposure using the combination mask, the alignment layer and the target layer each including at least two or more masks constituting the combination mask are grouped into a group, and each alignment mark of the group is registered using an overlay measuring device. By performing position measurement, a deviation amount detection step of obtaining the alignment deviation amount,
An input method of calculating an offset value based on the amount of alignment deviation, and inputting the offset value to an exposure apparatus during exposure to compensate for the alignment deviation. 4. The exposure method according to claim 1, further comprising, before the inputting step, determining by simulation whether the alignment deviation amount is within an allowable deviation amount. 5. In the shift amount detecting step, the number of combinations of the alignment layer and the target layer in the group is started from 1, and the alignment layer and the target layer in the group are shifted until the alignment shift amount is within the allowable shift amount. The number of combinations is increased by one to determine the amount of alignment deviation, and the amount of alignment deviation between the minimum number of combinations of alignment layers and target layers in the group when the amount of alignment deviation is within the allowable amount of deviation And select
5. The method according to claim 4, wherein in the inputting step, an offset value is calculated based on the amount of the alignment shift, and the offset value is input to an exposure apparatus during exposure to compensate for the alignment shift. Exposure method.

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