JP2004192712A - Semiconductor storage device, and semiconductor wafer and system including the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contribute to a cost reduction by executing testing by using a general-purpose testing device which does not include a film memory therein. <P>SOLUTION: In the semiconductor storage device 101, in addition to a BIST circuit 103 for testing a memory, a RA circuit 104 is incorporated to obtain a saving solution for replacing a defective cell by a redundant circuit based on a test result (fail data) obtained by the BIST circuit 103. Thus, it is not necessary for a testing device to have a conventionally necessary fail memory for storing a test result, a general-purpose testing device is used, and this costs are reduced. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device having a redundant circuit configuration, and a semiconductor wafer and a system including the semiconductor memory device.
[0002]
[Prior art]
FIG. 6 shows a conventional semiconductor memory device 1001 and a test device 2001 dedicated to a memory device and a laser processing repair device 3001 as devices required for testing the semiconductor memory device 1001.
[0003]
The semiconductor memory device 1001 includes, in addition to the memory 1002 having a redundant circuit configuration, a built-in self-test (BIST) circuit or a test circuit 1003 incorporated as a circuit for testing the memory 1002, and a defective circuit included in the memory 1002 as a redundant circuit. And a fuse circuit 1005 for writing an address for replacement.
[0004]
The storage device dedicated test apparatus 2001 is provided exclusively for testing such a semiconductor storage device 1001, and stores a fail memory 2002 which receives and stores fail data output from the BIST circuit or the test circuit 1003, A repair analyzer (hereinafter referred to as RA) circuit 2003 for generating and outputting a given rescue solution is provided, and a data processing unit 2004 for performing data processing necessary for outputting the rescue solution to the outside as fuse cut data is provided. ing.
[0005]
The laser processing repair apparatus 3001 receives the fuse cut data output from the data processing unit 2004 and blows the fuse to write an address for replacing a defective cell with a redundant circuit in the fuse circuit 1005.
[0006]
Hereinafter, a process of performing a test on the memory 1002 of the semiconductor memory device 1001 and replacing a detected defective cell with a redundant circuit will be described with reference to FIG.
[0007]
As shown in FIG. 7A, consider a case where the memory 1002 has a memory cell array having a 9 (column) × 8 (row) bit configuration and there are 11 defective cells that are filled.
[0008]
A clock, an address, test data, and a BIST / TEST control signal required for the test are supplied from the storage device dedicated test apparatus 2001 to the BIST circuit or the test circuit 1003, and a data write / read test is performed on the memory 1002.
[0009]
As a result of the test performed by the BIST circuit or the test circuit 1003, the bit position and the number of failed cells that failed as shown in FIG. 7B are calculated, and the fail data is stored as a test result in the storage device dedicated test apparatus 2001. Output.
[0010]
The storage device dedicated test apparatus 2001 temporarily stores fail data in the fail memory 2002. Then, based on the fail data, the RA circuit 2003 obtains a remedy solution that efficiently replaces the direction in which the number of fail bits is large with a redundant circuit in that direction. As shown in FIG. 7C, the portion A is repaired in the row direction, and the portions C and D are repaired in the column direction. In the case of B in which only one fail bit exists, repair is performed in an arbitrary direction, here, in the row direction.
[0011]
Next, the number of spare columns and / or spare rows of the redundant circuit required for the obtained remedy solution is obtained. In the example shown in FIG. 7D, two spare columns and two spare rows are required. If the number of each row is within the number of each of the spare columns and spare rows included in the redundant circuit of the memory 1002, the replacement is performed by using this remedy solution. If the number of spare columns and spare rows exceeds the number of redundant circuits, fail data is again provided to the storage device dedicated test apparatus 2001 to obtain a repair solution.
[0012]
If the rescue is possible, the data processing unit 2004 performs data processing based on the remedy so that the laser processing repair apparatus 3001 can perform processing, generates fuse cut data, and stores it in an electronic medium.
[0013]
The laser processing repair device 3001 blows the fuse of the fuse circuit 1005 according to the fuse cut data, and the replacement process ends.
[0014]
[Problems to be solved by the invention]
As described above, conventionally, the test of the semiconductor memory device 1001 requires not the general-purpose test device but the test device 2001 dedicated to the storage device.
[0015]
This is because, as hardware necessary for the rescue processing, a fail memory 2002 for receiving and storing fail data of all cells of the semiconductor memory device 1001 and outputting the same to the outside, and outputting a rescue solution by receiving fail data This is because an RA circuit 2003 is required.
[0016]
However, the fail memory 2002 usually requires a capacity equivalent to that of the memory 1002 to be tested, resulting in an increase in cost.
[0017]
In view of the above circumstances, an object of the present invention is to provide a semiconductor memory device, a semiconductor wafer including the semiconductor memory device, and a system that can contribute to cost reduction by enabling a test using a general-purpose test device. And
[0018]
[Means for Solving the Problems]
The semiconductor memory device of the present invention
A memory having a redundant circuit for replacing a defective cell;
A fuse circuit for writing information for replacing a defective cell with the redundant circuit;
A test circuit that performs a test on the memory, detects a defective cell, and outputs fail data;
A repair analyzer circuit that, when the test circuit detects a defective cell, receives the fail data and generates and outputs a repair solution for replacing the defective cell with the redundant circuit;
It is characterized by having.
[0019]
The semiconductor wafer of the present invention,
A memory having a redundant circuit for replacing a defective cell;
A fuse circuit for writing information for replacing a defective cell with the redundant circuit;
A semiconductor memory device having a test circuit for performing a test on the memory, detecting a defective cell and outputting fail data,
When the test circuit detects a defective cell in an area where the semiconductor memory device is not formed, the fail data is provided, and a repair solution for replacing the defective cell with the redundant circuit is generated and output. A repair analyzer circuit is formed.
[0020]
Here, the fuse circuit may be an electrically writable memory, and may write information for replacing a defective cell with the redundant circuit according to the repair solution output from the repair analyzer circuit. .
[0021]
The system of the present invention has a self-healing function,
A memory having a redundant circuit for replacing a defective cell;
Writing information for replacing a defective cell with the redundant circuit, an electrically writable fuse circuit,
A test circuit that performs a test on the memory, detects a defective cell, and outputs fail data;
A semiconductor memory device having a repair analyzer circuit which, when the test circuit detects a defective cell, is provided with the fail data and generates and outputs a repair solution for replacing the defective cell with the redundant circuit;
When power is turned on, an initialization circuit that detects this fact and provides a control signal for causing the test circuit to start a test;
With
The test circuit executes a test of the memory when the control signal is given.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
(1) Embodiment 1
FIG. 1 shows a configuration of a semiconductor memory device 101 according to the first embodiment, and a general-purpose test device 201 and a laser processing repair device 301 necessary for testing the semiconductor memory device 101.
[0024]
The semiconductor memory device 101 includes a memory 102 to be tested, a BIST circuit 103 built in the device as a test circuit, and a fuse circuit 105 for writing an address for replacing a defective cell included in the memory 102 with a redundant circuit. ing.
[0025]
The general-purpose test apparatus 201 is a general-purpose test apparatus having no fail memory and no RA circuit, unlike the conventional dedicated test apparatus 2001 shown in FIG.
[0026]
The laser processing repair device 301 is provided with a relief solution output from a hardware circuit that performs data processing in the general-purpose test device 201 or an execution unit (hereinafter, referred to as a data processing unit) 202 that executes software for a data processing algorithm, The fuse is blown to write an address for replacement with a redundant circuit necessary for the rescue into the fuse circuit 105.
[0027]
A procedure for performing a test on the semiconductor memory device 101 according to the first embodiment will be described.
[0028]
A clock and a BIST control signal are input from the general-purpose test apparatus 201 to the BIST circuit 103, and the BIST circuit 103 tests the memory 102.
[0029]
The result of the test performed by the BIST circuit 103 is output to the RA circuit 104 in the semiconductor memory device 101 as a BIST result. Here, if there is no defective cell and the product is non-defective, there is no need to perform any further processing, so the test result is also given to the general-purpose test apparatus 201 and the processing ends.
[0030]
If there is one or more defective cells, a test result is given to the RA circuit 104, and a repair solution is calculated.
[0031]
The rescue solution is output out of the semiconductor memory device 101 and given to the data processing unit 202 in the general-purpose test device 201, where data processing is performed for the laser processing repair device 201 to generate fuse cut data. Once, or directly supplied to the laser processing repair apparatus 301 via a communication line.
[0032]
The laser processing repair device 301 performs laser processing on the fuse circuit 105 in the semiconductor memory device 101 based on the fuse cut data in order to write an address for replacing a defective cell with a redundant circuit, and the replacement process ends.
[0033]
According to the first embodiment, since the semiconductor memory device 101 incorporates not only the BIST circuit 103 but also the RA circuit 104, it is not necessary to provide a fail memory and an RA circuit, which are conventionally required, on the test apparatus side. Since the test can be performed by the general-purpose test apparatus 201 at a low cost, cost reduction is realized.
[0034]
In addition, in the semiconductor memory device 101, the output from the BIST circuit 103 operable at a high frequency is directly taken into the RA circuit 104 and processed, whereby the test time can be reduced.
[0035]
(2) Embodiment 2
FIG. 2 shows a configuration of a semiconductor wafer including a semiconductor memory device according to a second embodiment of the present invention, a general-purpose test device, and a laser processing repair device.
[0036]
In the first embodiment, the semiconductor memory device 101 includes the RA circuit 104. On the other hand, in the second embodiment, the RA circuit 114 is formed in the empty area 111a on the semiconductor wafer on which the circuit pattern of the semiconductor memory device 111 is not formed.
[0037]
At this stage, the memory 102 is tested using the general-purpose test apparatus 201. The procedure in this case is the same as that in the first embodiment, and the description is omitted.
[0038]
After the test, the empty area 111a is cut off from the area of the semiconductor memory device 111 where the circuit pattern is formed in the dicing step, so that the semiconductor memory device 111 does not include the RA circuit 114.
[0039]
According to the first embodiment, the cost can be reduced because the test can be performed by the low-cost general-purpose test apparatus 201 as in the first embodiment. In addition, the test time can be reduced by directly processing the output from the BIST circuit 103 operable at a high frequency in the same semiconductor wafer by the RA circuit 114.
[0040]
Further, according to the second embodiment, since it is not necessary to incorporate the RA circuit 114 as the semiconductor memory device 111, the chip area of the semiconductor memory device 111 can be reduced.
[0041]
(3) Embodiment 3
FIG. 3 shows a configuration of a semiconductor memory device according to a third embodiment of the present invention and a configuration of a general-purpose test device 221.
[0042]
In the third embodiment, the device required for testing the semiconductor memory device 121 is the general-purpose test device 221, and the laser processing repair device required in the first and second embodiments is unnecessary. This is because the fuse circuit 125 according to the third embodiment is configured by an electrically writable memory, for example, an EPROM, an electrically writable and erasable E ² PROM, a collectively erasable flash ROM, and the like. by.
[0043]
The semiconductor memory device 121 includes a BIST circuit 103 and an RA circuit 104 in addition to the memory 102 and the fuse circuit 125.
[0044]
Further, in the general-purpose test apparatus 201 according to the first and second embodiments, the data processing unit 202 is required to generate the fuse cut data for the laser processing repair apparatus arranged outside the semiconductor memory device. However, the general-purpose test device 221 according to the third embodiment does not need to include such a data processing unit.
[0045]
A test is performed on the semiconductor memory device 121 according to the third embodiment in the following procedure.
[0046]
A clock and a BIST control signal are input from the general-purpose test apparatus 221 to the BIST circuit 103, and the BIST circuit 103 tests the memory 102.
[0047]
The result of the test performed by the BIST circuit 103 is output to the RA circuit 104 in the semiconductor memory device 101. If there is no defective cell, the test result is given to the general-purpose test device 221 and the process ends. If there is one or more defective cells, the test result is given to the RA circuit 104, and a repair solution is calculated.
[0048]
By this remedy solution, the general-purpose test apparatus 221 is notified whether the remedy has passed or the remedy has failed. If it passes, an address for replacing a defective cell with a redundant circuit is given from the RA circuit 104 to the fuse circuit 125 based on the remedy solution, and the fuse circuit 125 electrically writes.
[0049]
According to the third embodiment, as in the first and second embodiments, since the semiconductor memory device 121 has the BIST circuit 103 and the RA circuit 104 built therein, it is possible to perform a test using the general-purpose test device 221 and to reduce cost. Is reduced. Further, in the same semiconductor memory device, the RA circuit 104 directly takes in the output from the BIST circuit 103 operable at a high frequency and processes the same, thereby shortening the test time.
[0050]
Further, unlike the first and second embodiments, a repair process using a laser processing repair device is not required, so that the time for the write process can be further reduced and the cost can be reduced.
[0051]
(4) Embodiment 4
In the fourth embodiment, the electrically writable fuse circuit 125 in the third embodiment and the RA circuit in the empty region on the semiconductor wafer where the circuit pattern of the semiconductor memory device is not formed in the second embodiment. Is equivalent to a combination of the above-described configuration.
[0052]
FIG. 4 shows a configuration of a semiconductor wafer on which a semiconductor memory device and an RA circuit are formed and a general-purpose test device according to the fourth embodiment. As described above, in the fourth embodiment, the circuit pattern of the RA circuit 114 is formed in the empty area 131a on the semiconductor wafer where the circuit pattern of the semiconductor storage device 131 is not formed.
[0053]
At this wafer stage, the memory 102 is tested using the general-purpose test device 221. The procedure in this case is the same as that in the third embodiment, and the description is omitted.
[0054]
After the test, the empty area 131a is cut off from the area of the semiconductor memory device 131 where the circuit pattern is formed in the dicing process, and the semiconductor memory device 131 does not include the RA circuit 114.
[0055]
According to the fourth embodiment, similarly to the third embodiment, the test can be performed by the low-cost general-purpose test device 221 and the laser processing repair device is not required, so that the cost can be reduced. . Further, as in the second embodiment, since it is not necessary to incorporate the RA circuit 114, the chip area of the semiconductor memory device 131 can be reduced.
[0056]
(5) Embodiment 5
According to the first to fourth embodiments, a defective cell existing at a stage before the device is shipped can be replaced with a redundant circuit to be repaired. However, if a defective cell occurs due to aging or the like while the end user is using the device after shipment, it cannot be remedied and is treated as a defective product. This is due to the fact that the rescue location cannot be changed after the product has been assembled.
[0057]
On the other hand, according to the fifth embodiment, each time the user turns on the power, the presence of a defective cell is detected, and if there is a defective cell, an address is sent to the fuse circuit in order to find a remedy solution for replacing the redundant circuit. It has a writing configuration. As a result, even when a defect occurs during use by an end user after assembling and shipping of a product, it is possible to relieve the defect.
[0058]
First, a POST (Power-On Self Test) for performing a self-test every time the power is turned on is provided by an initialization circuit 241 included in a computer or the like used by a user for initializing the system after the power is turned on. The signal and the clock are input to the BIST circuit 103, and the test of the memory 102 by the BIST circuit 103 is started.
[0059]
If there is a defective cell, the fail data generated in the BIST circuit 103 is transferred to the RA circuit 104, and a repair solution is calculated.
[0060]
Based on the remedy, an address is written in the electrically writable fuse circuit 125. In this manner, the repair process for replacing the defective cell with the redundant circuit is performed, so that the self-repair becomes possible.
[0061]
The result of the self test (POST result) is sent from the RA circuit 104 to the initialization circuit 241 to notify the user.
[0062]
According to the fifth embodiment, as in the third embodiment, the semiconductor memory device 121 includes the BIST circuit 103, the RA circuit 104, and the electrically writable fuse circuit 125, thereby providing a laser processing repair device. The test can be performed by the general-purpose test apparatus 221 without the need for the test, and the cost is reduced.
[0063]
Further, according to the fifth embodiment, after the device is shipped, each time the user turns on the power, the presence of a defective cell is detected, and if a defective cell exists, a remedy solution for replacing the cell with a redundant circuit is calculated. By performing the writing process on the fuse circuit, it is possible to relieve even when a defect occurs during use of the device. By having such a self-healing function, it is possible to improve product life and reduce costs.
[0064]
The above embodiments are merely examples, and do not limit the present invention. Various modifications can be made within the technical scope of the present invention.
[0065]
【The invention's effect】
The semiconductor memory device of the present invention, the semiconductor wafer including the semiconductor memory device, and the system include the RA circuit, so that a test can be performed using an inexpensive general-purpose test apparatus that does not include a fail memory or an RA circuit. Yes, it can contribute to cost reduction.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention, a general-purpose test device required for testing the semiconductor memory device, and a laser processing repair device.
FIG. 2 is a block diagram showing a configuration of a semiconductor wafer including a semiconductor storage device according to a second embodiment of the present invention, a general-purpose test device required for testing the semiconductor storage device, and a laser processing repair device.
FIG. 3 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention and a general-purpose test device required for testing the semiconductor memory device;
FIG. 4 is a block diagram showing a configuration of a semiconductor wafer including a semiconductor memory device according to a fourth embodiment of the present invention and a general-purpose test device required for testing the semiconductor memory device.
FIG. 5 is a block diagram showing a configuration of a system including a semiconductor memory device according to a fifth embodiment of the present invention and an initialization circuit necessary for testing the semiconductor memory device;
FIG. 6 is a block diagram showing a configuration of a conventional semiconductor memory device, a dedicated test device required for testing the semiconductor memory device, and a laser processing repair device.
FIG. 7 is an explanatory diagram showing a procedure of a process for replacing a defective cell with a redundant circuit.
[Explanation of symbols]
101, 111, 121, 131, 141 Semiconductor memory device 102 Memory 103 BIST circuit 104, 114 RA circuit 105 Fuse circuit 125 Electrically writable fuse circuit 201, 221, 241 General-purpose test device 301 Laser processing repair device

Claims (5)

A memory having a redundant circuit for replacing a defective cell;
A fuse circuit for writing information for replacing a defective cell with the redundant circuit;
A test circuit that performs a test on the memory, detects a defective cell, and outputs fail data;
A repair analyzer circuit that, when the test circuit detects a defective cell, receives the fail data and generates and outputs a repair solution for replacing the defective cell with the redundant circuit;
A semiconductor memory device comprising: The fuse circuit is an electrically writable memory, and writes information for replacing a defective cell with the redundant circuit in accordance with the repair solution output from the repair analyzer circuit. 13. The semiconductor memory device according to claim 1. A memory having a redundant circuit for replacing a defective cell;
A fuse circuit for writing information for replacing a defective cell with the redundant circuit;
A semiconductor memory device having a test circuit for performing a test on the memory, detecting a defective cell and outputting fail data,
When the test circuit detects a defective cell in an area where the semiconductor memory device is not formed, the fail data is provided, and a repair solution for replacing the defective cell with the redundant circuit is generated and output. A semiconductor wafer having a repair analyzer circuit formed thereon. 4. The fuse circuit is an electrically writable memory, and writes information for replacing a defective cell with the redundant circuit in accordance with the repair solution output from the repair analyzer circuit. A semiconductor wafer as described in the above. A memory having a redundant circuit for replacing a defective cell;
Writing information for replacing a defective cell with the redundant circuit, an electrically writable fuse circuit,
A test circuit that performs a test on the memory, detects a defective cell, and outputs fail data;
A semiconductor memory device having a repair analyzer circuit which, when the test circuit detects a defective cell, is provided with the fail data and generates and outputs a repair solution for replacing the defective cell with the redundant circuit;
When power is turned on, an initialization circuit that detects this fact and provides a control signal for causing the test circuit to start a test;
With
The self-healing system according to claim 1, wherein said test circuit executes a test of said memory when given said control signal.

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