JP2004186515A - Integrated circuit and its designing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an increase in circuit size without causing back track in design or an increase in man hours in design of an integrated circuit while a hold time constraint can be satisfied in the integrated circuit during data interchange between two or more circuit blocks. <P>SOLUTION: A circuit for forming a retard by a half period is formed in a post stage of a clock synchronization flip-flop. Half period retard generating circuits 52, 53, 60 are provided on the transmitting side of a signal between blocks 50, 51. A flip-flop carrying netlist description on the transmitting side between blocks is displaced by a half period retard cell. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit and a method of designing the same, particularly, in a semiconductor device including a plurality of circuit blocks, an integrated circuit for satisfying a hold time constraint when data is transferred between the plurality of circuit blocks, and The present invention relates to a method for designing an integrated circuit for forming the integrated circuit.
[0002]
[Prior art]
In a conventional LSI design, data transfer is performed by synchronizing functional blocks with a flip-flop (for example, Patent Document 1).
[0003]
On the other hand, in order to satisfy the restriction of the hold time, a portion where an error occurs in a real delay simulation after layout is replaced with a flip-flop having a delay element at a data input portion (for example, Patent Document 2). There is one in which a flip-flop that operates with an opposite-phase clock is inserted into a corresponding path (for example, Patent Document 3).
[0004]
Furthermore, there is a scan path configuration unit having a shift register configuration, in which a latch that operates with a clock having an opposite phase at the time of scanning is provided so as to select a half-cycle delay at the time of scanning (for example, Patent Document 4).
[0005]
[Patent Document 1]
JP-A-11-26591 (Section 5-6, FIG. 2)
[0006]
[Patent Document 2]
Japanese Patent No. 2786017 (Section 2, FIG. 1)
[0007]
[Patent Document 3]
JP-A-7-192043 (Section 8-9, FIG. 2-4)
[0008]
[Patent Document 4]
Japanese Patent Application Laid-Open No. 2000-310671 (Section 5-6, FIG. 1)
[0009]
[Problems to be solved by the invention]
When synchronizing between functional blocks with a flip-flop and exchanging data, it may be difficult to satisfy the hold time constraint due to the clock phase difference between the functional blocks.
[0010]
In the case where a flip-flop having a delay element or a flip-flop having an opposite phase is inserted into a portion where a hold constraint error has occurred in an actual delay simulation performed after layout, the flip-flop is inserted due to miniaturization and high density of an integrated circuit. There is a problem that there is no space. In addition, the wiring path is greatly changed, which has a negative effect on satisfying the delay constraints of the surrounding paths, and the time until the completion of the design is easily increased, so that a new antiphase clock needs to be supplied. There is.
[0011]
Further, in the conventional method using a flip-flop circuit configured to select that a half-cycle delay is added at the time of scanning, there is a problem that the circuit scale of all flip-flops becomes large.
[0012]
Therefore, the present invention solves such a problem, and enables an integrated circuit to satisfy a hold time constraint when exchanging data between a plurality of circuit blocks, and to design an integrated circuit. It is an object of the present invention to prevent backtracking and increase in the number of design steps, and to prevent an increase in circuit scale.
[0013]
[Means for Solving the Problems]
In order to solve these problems, the present invention is characterized by using a clock synchronous flip-flop cell having a half cycle delay so as to satisfy a hold time constraint. By using such a clock synchronous flip-flop cell having a half cycle delay for data transfer between blocks in which a clock delay difference is likely to occur, an increase in circuit scale can be prevented.
[0014]
According to the present invention, in order to generate a half-cycle delay at a stage subsequent to the clock synchronous flip-flop, a latch or flip-flop that operates with a reverse-phase clock is provided, and these are previously formed into one cell, so that they are inserted. Eliminating space, changing wiring paths, increasing the number of negative-phase clock wirings, etc. will not occur.
[0015]
According to the first method of the present invention, when a flip-flop on the transmission side between blocks described in a netlist is replaced with a half-period delay cell, before laying out a portion which is expected to hardly satisfy a hold constraint, A delay is given in advance. This makes it possible to reduce delay variation after layout. In addition, an increase in the circuit scale can be prevented by limiting all flip-flops to a block instead of a half-cycle delay.
[0016]
Furthermore, a cell name list that specifies a specific flip-flop, a block name list that specifies a block, a clock name list that specifies a clock signal, and a clock that specifies a set of one clock signal and another different clock signal A cell to be replaced with a half-period delay cell may be selected in advance using the pair list. By thus narrowing the number of cells to be replaced, the increase in the circuit scale can be further reduced.
[0017]
The second method of the present invention checks whether or not transmission and reception of signals between blocks described in a netlist is in a shift register configuration from flip-flop to flip-flop. This is replaced with a half-period delay cell, and a delay is given in advance before layout is performed on a portion expected to hardly satisfy the hold constraint. This makes it possible to reduce delay variation after layout. In addition, an increase in the circuit scale can be prevented by limiting all flip-flops to a block instead of a half-cycle delay.
[0018]
If a latch or another flip-flop that operates in the opposite phase of the clock input to the flip-flop is connected to a stage subsequent to each clock synchronous flip-flop in the netlist description, By replacing the flip-flop described above with a latch or another flip-flop in a subsequent stage by a half-cycle delay cell, the number of wirings and the number of branches of clock wirings can also be reduced.
[0019]
According to the third method of the present invention, when reading and synthesizing the RTL description, a half-period delay cell is allocated as a flip-flop on the transmission side between blocks, and it is expected that the hold constraint is hardly satisfied. A delay is given before layout is performed on a portion. This makes it possible to reduce delay variation after layout. In addition, an increase in the circuit scale can be prevented by limiting all flip-flops to a block instead of a half-cycle delay.
[0020]
Furthermore, a block name list that specifies blocks, an inter-block list that specifies between blocks, a clock name list that specifies clock signals, and a clock pair list that specifies a set of one clock signal and another clock signal different from it May be used to select a portion to be allocated to the half-period delay cell in advance. Thus, by narrowing down the number of cells to be allocated, an increase in circuit scale can be further reduced.
[0021]
According to a fourth method of the present invention, it is determined whether or not signals are transmitted and received between blocks in a shift register configuration from the first flip-flop to the second flip-flop at the time of synthesis. A half-cycle delay cell is allocated, and a delay is given in advance before layout is performed on a portion expected to hardly satisfy the hold constraint. This makes it possible to reduce delay variation after layout. In addition, an increase in the circuit scale can be prevented by limiting all flip-flops to a block instead of a half-cycle delay.
[0022]
When a latch or another flip-flop that operates in the opposite phase of the clock input to the flip-flop is connected to a stage subsequent to each clock synchronous flip-flop in the RTL description, By allocating the latches or other flip-flops at the subsequent stage to the half-cycle delay cells collectively, the number of wirings and the number of branches of the clock wiring can be reduced.
[0023]
According to the fifth method of the present invention, when a timing violation is detected by checking the synthesis result using the tentative wiring delay, a hold violation of half a cycle or more is caused in all paths from the starting flip-flop. In some cases, the flip-flop at the starting point is replaced with a half-period delay cell, and a delay is given in advance before layout is performed on a portion expected to hardly satisfy the hold constraint.
This makes it possible to reduce delay variation after layout. In addition, it is possible to prevent an increase in circuit scale by limiting all flip-flops to an error generating unit instead of having a half-cycle delay.
[0024]
If there is a path that causes a hold violation for less than half a cycle, and if the maximum delay time of all paths from the flip-flop that is the starting point is less than half a cycle, the flip-flop that is the starting point is delayed by a half cycle. Even if the cell is replaced with a cell, the delay constraint can be satisfied, so that a portion for adjusting the delay after layout can be reduced.
[0025]
According to a sixth method of the present invention, when a macro such as an SRAM requires a relatively larger hold time constraint than other cells in advance, the input hold time constraint of a cell in the synthesis library is checked and the cell is checked. A half-period delay cell is assigned as a flip-flop at the starting point of the input signal to the input terminal, and a delay is given in advance before layout is performed on a portion expected to hardly satisfy the hold constraint. This makes it possible to reduce delay variation after layout.
[0026]
Instead of looking at the input hold time constraint of the cells in the synthesis library, an attribute for instructing the synthesis library to allocate a half-cycle delay cell may be given and assigned.
[0027]
Further, a description for instructing the assignment of a half-period delay cell to the RTL description may be made, and the half-period delay cell may be assigned to a syntax to which a flip-flop having the description is to be assigned.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to FIGS.
(Embodiment 1)
FIG. 1 shows the configuration of a half-period delay cell according to the present invention.
[0029]
The half cycle delay cell 1 shown in FIG. 1 includes a clock synchronous flip-flop 2 and a half cycle delay circuit 3. The clock synchronous flip-flop 2 stores the signal of the data input 4 internally at the rising edge of the clock signal supplied from the clock input 5. The stored data is applied from the data output 6 of the clock synchronous flip-flop 2 to the data input 7 of the half-period delay circuit 3, and after being delayed by a half-period with respect to the signal from the clock input 5 by the half-period delay circuit 3, Output from the data output 8.
[0030]
FIG. 2 shows an example of the half-cycle delay circuit 3. The delay circuit 3 is a latch circuit that operates with a reverse-phase clock (corresponding to claim 3).
Data input 7 is connected to input 11 of transfer gate 10. The clock signal from the clock input 5 is input to the inverter 12 and output to the transfer gate 10, the inverter 13, and the transfer gate 15. The transfer gate 10 is turned on when the clock signal is "L", and the transfer gate 15 is turned on when the clock signal is "H". The output of the inverter 13 is input to the transfer gate 10 and the control gate of the transfer gate 15 having a polarity opposite to that of the inverter 12. The output 14 of the transfer gate 10 is wired-ORed with the output 16 of the transfer gate 15 and input to the inverter 17. The output of the inverter 17 is input to the inverter 20, and the output of the inverter 20 is output as the data output 8 outside the half-cycle delay circuit 3. The output of the inverter 17 is input to the inverter 18. The output of the inverter 18 is connected to the input 19 of the transfer gate 15.
[0031]
Next, the operation will be briefly described. While the clock input 5 is "H", the transfer gate 10 is off and the transfer gate 15 is on. Thereby, a loop of the inverter 17 and the inverter 18 is formed, and a certain value is output during the period. When the clock input 5 becomes "L", the transfer gate 10 is turned on and the transfer gate 15 is turned off. Thus, the data from the data input 7 is output from the data output 8 through the inverter 17 and the inverter 20.
[0032]
By connecting the half-period delay circuit 3 that operates as described above to the subsequent stage of the clock synchronous flip-flop 2 in FIG. 1, the data stored at the rising edge of the clock input 5 can be converted to the falling edge of the clock input 5 (“L”). From the beginning), and output from the data output 8 to function as a half cycle delay cell.
[0033]
FIG. 3 shows an example in which a clock synchronous flip-flop circuit 30 that operates with an inverted phase clock is connected as the half cycle delay circuit 3 (corresponding to claim 4).
The clock signal from the clock input 5 is inverted by the inverter 31 and input from the clock input 32 of the clock synchronous flip-flop 30. The data input 33 of the clock synchronous flip-flop 30 is connected to the data input 7 of the half-cycle delay circuit 3, and the data output 34 of the clock synchronous flip-flop 30 is connected to the data output 8.
[0034]
With this configuration, data stored in the clock synchronous flip-flop 2 at the rising edge of the clock input 5 is stored in the clock synchronous flip-flop 30 at the next falling edge of the clock input 5, and is output as the data output 8. As a result, data is output with a delay of a half cycle from the rise of the clock input 5.
[0035]
FIG. 4 shows an example in which a half-cycle delay cell is used on the transmitting side of a signal between blocks (corresponding to claim 2).
In the signal transmission / reception between the block (A) 50 and the block (B) 51, the signal line 55 among the signal lines 55 and 56 for transmitting a signal from the block (A) 50 to the block (B) 51 The output of the half-period delay cell 52 and the input of the flip-flop 58 are connected, and the signal line 56 is connected to the output of the half-period delay cell 53 and the input of the flip-flop 59. Conversely, a signal line 57 for transmitting a signal from the block (B) 51 to the block (A) 50 is connected to an output of the half-cycle delay cell 60 and an input of the flip-flop 54. The clock 61 is input to the half-cycle delay cells 52 and 53 and the flip-flop 54 through the buffer 62, and the clock 61 is input to the flip-flops 58 and 59 and the half-cycle delay cell 60 through the buffer 63.
[0036]
By adopting such a configuration, each of the flip-flops 54, 58, 59 and the half-period delay cells 52, 53, 60 for transferring data between the block (A) 50 and the block (B) 51 has a buffer. Even if there is a difference between the arrival times of the clocks supplied through the buffer 62 and the buffer 63, the transmission side has a half-cycle delay. It does not violate time constraints.
[0037]
(Embodiment 2)
FIG. 5 is a diagram showing a flow of the integrated circuit designing method of the present invention according to claim 5, wherein the logic is RTL-described in an RTL description step 100, and the RTL description is assigned to a logic circuit in a synthesis step 101, and a netlist is created. Create Next, the flip-flop on the transmitting side between the blocks is replaced with a half-cycle delay cell in the replacement step 102 with respect to the created netlist. After the replacement in the replacement step 102, a netlist in which the test circuit is inserted is created in the DFT step 103, and a layout is created in the layout step 104 based on the netlist.
[0038]
Next, the details of the replacement step 102 will be described. When replacing the flip-flop on the transmission side between blocks with a half-period delay cell, a cell name list 111 specifying a specific flip-flop, a block name list 112 specifying a block, an inter-block list 113 specifying a block, A clock name list 114 specifying a clock signal, and a clock pair list 115 specifying a set of a certain clock signal and another clock signal different from the clock name list 114 are read in a list reading step 110, and the plurality of lists are replaced with half cycle delay cells. A flip-flop on the transmission side between blocks to be selected is selected and replaced with a half-period delay cell in a cell replacement step 116.
[0039]
For example, when the cell name list 111 is read, a flip-flop on the transmission side between blocks matching the cell name is selected and replaced (corresponding to claim 6).
FIG. 6 shows this state. In the block between the block (A) 120 and the block (B) 121, a clock is supplied from the clock 131 to each flip-flop through the buffer 132 and the buffer 133, and the block is formed between the blocks. In the case where a signal is transmitted from the (A) 120 to the block (B) 121 via the signal lines 125 to 127, two flip-flops corresponding to the cell names read from the cell name list are replaced with the half-period delay cells 122, 123, and the flip-flops 124 and 128-130 not described in the list are left as they are.
[0040]
For example, when the block name list 112 is read in FIG. 5, among the flip-flops existing in the blocks in the block name list 112, the flip-flop that is the transmission side between the blocks is selected and replaced. Equivalent).
[0041]
FIG. 7 shows this state. Between the block (A) 140 and the block (B) 141, a clock is supplied from the clock 151 to the flip-flops 144 and 148-150 through the buffers 152 and 153. Between the blocks, signals are transmitted from block (A) 140 to block (B) 141 via signal lines 145 and 146, and signals are transmitted from block (B) 141 to block (A) 140 via signal line 147. In the case of the configuration, when the block (A) 140 is described in the block name list 112, the flip-flop in which the block (A) 140 is on the transmission side is replaced with half cycle delay cells 142 and 143, and the flip-flop on the reception side is replaced. And the flip-flop 148 of the block (B) not described in the list. 150 to leave the.
[0042]
Further, for example, when the inter-block list 113 is read in FIG. 5, the transmission-side flip-flop of the signal line that exchanges data between one of the blocks described in the list and a block forming a pair with the block is selected. And replace (corresponding to claim 8).
[0043]
FIG. 8 shows this state. Between the block (A) 160 and the block (B) 161 and between the block (A) 160 and the block (C) 162, each flip-flop is supplied from the clock 172 through the buffers 173 to 175. A clock is supplied to the blocks 165 and 169-171, a signal is transmitted between the blocks from the block (A) 160 to the block (B) 161 via the signal lines 166 and 167, and a block (A) 160 is transmitted between the blocks from the block (A) 160. C) In a configuration in which a signal is transmitted to the signal line 168 to the block 162, when the block (A) 160 and the block (B) 161 are described in the inter-block list 113, the block (A) 160 and the block In signal lines 166 and 167 between (B) 161, block (A) 160 is on the transmission side. The flip-flop is replaced with a half cycle delay cells 163 and 164, and the receiving side of the flip-flop 169 and 170, flip-flops 165,171 from block (A) 160 to block (C) 162 is intact.
[0044]
Next, for example, when the clock name list 114 is read, a flip-flop connected to the clock, which is a transmission side between blocks, is selected and replaced (corresponding to claim 9).
[0045]
FIG. 9 shows this state. In the block between the block (A) 180 and the block (B) 181, a clock is supplied from the clock 191 to each flip-flop through the buffer 192 and the buffer 193, and the block between the blocks is blocked. In the case where a signal is transmitted from (A) 180 to block (B) 181 via signal lines 185 and 186 and a signal is transmitted from block (B) 181 to block (A) 180 via signal line 187, When the clock 191 is described in the clock name list 114, the flip-flops on the transmitting side are replaced with the half-cycle delay cells 182, 183, and 190, and the flip-flops 184, 188, and 189 on the receiving side are left as they are.
[0046]
Further, for example, when the clock pair list 115 is read, among the flip-flops connected to one of the clocks listed in the list, the signal between the blocks is supplied to the flip-flop connected to the clock that is paired with the clock. The transmitting device is selected and replaced (corresponding to claim 10).
[0047]
FIG. 10 shows this state. Between the block (A) 200 and the block (B) 201, a clock is supplied from the clock 211 to each flip-flop of the block (A) 200 through the buffer 212, and the clock is supplied. A clock is supplied from 213 to the flip-flops 208 and 209 of the block (B) 201 through the buffer 214, and a clock is supplied from the clock 215 to the flip-flop 210 of the block (B) 201 through the buffer 216, and the block (A) is passed between the blocks. In a configuration in which a signal is transmitted from the signal 200 to the block (B) 201 via the signal lines 205 to 207, when a pair of the clock 211 and the clock 213 is described in the clock pair list 115, the clock 211 is connected to the clock 211. Flip-flop Of the flip-flops that transmit signals between the blocks to the flip-flop connected to the clock 213 that forms the pair with the clock 213, the half-cycle delay cells 202 and 203 replace the flip-flops. , The flip-flop 204 transmitting the signal and the flip-flop 208-210 on the receiving side are kept as they are.
[0048]
(Embodiment 3)
FIG. 11 shows a flow of the integrated circuit design method according to claim 11. First, the logic is RTL-described in an RTL description step 300, and the RTL description is assigned to a logic circuit in a synthesis step 301 to create a netlist. Next, in the shift register checking step 302, it is checked whether or not the transmission and reception of signals between the blocks has a shift register configuration from flip-flop to flip-flop. The transmitting flip-flop between the blocks is replaced with a half-period delay cell based on the check result of the check step 302. After the replacement in the replacement step 303, a netlist in which the test circuit is inserted is created in the DFT step 304, and a layout is created in a layout step 305 based on the netlist.
[0049]
FIG. 12 shows this state. Between the block (A) 310 and the block (B) 311, a clock is supplied from the clock 321 to each flip-flop through the buffer 322 and the buffer 323, and a block is formed between the blocks. Signals are transmitted from (A) 310 to block (B) 311 by signal lines 315 and 316, signals are transmitted from block (B) 311 to block (A) 310 by signal line 317, and signal line 316 is a block. (B) In the case of a configuration in which the signal is input to the gate 325 in the gate 311 and ORed with the signal line 324 and then input to the flip-flop 319, in the shift register checking step 302, the signal line 315 and the signal line 317 are connected. It turns out that a shift register configuration has been found between the two connected flip-flops. Then, in the replacement step 303, in response to the result, the flip-flop on the transmission side is replaced with the half-cycle delay cells 312 and 320, and the flip-flop 313 having a gate 325 in the middle, the flip-flops 314 and 318 on the reception side, 319 is left as it is.
[0050]
(Embodiment 4)
FIG. 13 shows a flow of the integrated circuit design method according to claim 12. First, the logic is RTL-described in an RTL description step 400, and the RTL description is assigned to a logic circuit in a synthesis step 401 to create a netlist. Next, in the antiphase clock connection investigating step 402, a latch or a flip-flop that operates in the reverse phase of the clock input to the flip-flop is connected to a stage subsequent to each clock synchronous flip-flop with respect to the created netlist. In the replacement step 403, the flip-flop in the netlist and the latch or flip-flop in the subsequent stage are collectively replaced with a half-period delay cell based on the result of the check in the antiphase clock connection checking step 402. . After the replacement in the replacement step 403, a netlist in which the test circuit is inserted is created in the DFT step 404, and a layout is created in the layout step 405 based on the netlist.
[0051]
FIG. 14 is a diagram showing this state. FIG. 14A shows a part of the netlist allocated to the logic circuit in the synthesis step 401. Here, the signal line 500 and the clock 501 are input to the flip-flop 502. The clock 501 is supplied to the flip-flop 505 through the inverter 503. At this time, the flip-flop 505 operates in the opposite phase of the clock with respect to the flip-flop 502. The output of the flip-flop 502 is input to the flip-flop 505 through the signal line 504. The output of the flip-flop 505 is connected to the next circuit through a signal line 506.
[0052]
(B) shows a state after the replacement processing in the replacement step 403. Here, in the anti-phase clock connection checking step 402, the flip-flop 502 and the flip-flop 505 of (a) are arranged at a stage subsequent to the clock synchronous flip-flop and operate in the opposite phase of the clock input to the flip-flop. It turns out that the loop has a certain configuration. Therefore, in the replacement step 403, the inverter 503, the flip-flop 505, and the signal line 504 are deleted, and the flip-flop 502 is replaced with the half-cycle delay cell 510.
[0053]
(Embodiment 5)
FIG. 15 shows a flow of the integrated circuit design method according to the thirteenth aspect. The logic is RTL described in an RTL description step 600, the RTL is read in a read step 601 and the read RTL description is synthesized in a synthesis step 602. Create a netlist by assigning it to a logic circuit.
[0054]
Next, the details of the combining step 602 will be described. When replacing the flip-flop on the transmission side between blocks with a half-period delay cell, a block name list 610 specifying blocks, an inter-block list 611 specifying blocks, a clock name list 612 specifying clock signals, a certain clock In the list reading step 614, a clock pair list 613 specifying a set of a signal and another clock signal different from the signal is read. Then, in the cell synthesis step 615, when performing logic synthesis, a half-period delay cell is allocated as a flip-flop having a configuration corresponding to the list, and a netlist is created.
[0055]
For example, when the block name list 610 is read, when synthesizing the logic of the blocks in the block name list 610, when allocating flip-flops, a half-period delay cell is used for a transmission side between blocks. Assigned (corresponding to claim 14).
[0056]
Next, for example, when the inter-block list 611 is read, when the logic of the first block described in the inter-block list 611 and the second block forming a pair with the first block are combined, the first block is read. When outputting a signal to the second block when allocating flip-flops, a half-cycle delay cell is allocated, and when outputting a signal to the first block when allocating flip-flops of the second block, Assigns a half-period delay cell (corresponding to claim 15).
[0057]
Further, for example, when the clock name list 612 is read, when allocating flip-flops connected to the clocks described in the clock name list 612, a half-period delay cell is used for a transmission side between blocks. Assigned (corresponding to claim 16).
[0058]
Further, for example, when the clock pair list 613 is read, the first clock described in the clock pair list 613 and the flip-flop connected to the second clock paired with the first clock are assigned to the first clock. When there is a transmission from a clock flip-flop to a flip-flop connected to a second clock between different blocks, a half-cycle delay cell is allocated as the first clock flip-flop, and conversely, a flip-flop of the second clock If there is a transmission from the flip-flop to the flip-flop connected to the first clock between different blocks, a half-cycle delay cell is allocated as the flip-flop of the second clock (corresponding to claim 17).
[0059]
(Embodiment 6)
FIG. 16 shows a flow of an integrated circuit design method according to claims 18 and 19 of the present invention. Here, the logic is described in RTL in an RTL description step 700, the RTL is read in a reading step 701, and the read RTL description is assigned to a logic circuit in a synthesis step 702 to create a netlist. In the combining step 702, for example, when an RTL description is allocated as shown in FIG. Are connected one-to-one with wiring (NETA connection description 715) in the RTL description (RTL description 710) of the upper hierarchy. If the description of the flip-flop B (REGB description 714) simply stores the signal from NETA at the rising edge of the clock (CLKB), a half-cycle delay cell is assigned to the flip-flop A. 18).
[0060]
In addition, when the RTL description 750 as shown in FIG. 18, for example, is assigned in the combining step 702, the output (OUTA) of the description of the flip-flop A (REGA description 751) in the RTL description 750 is the description of the flip-flop B. (REGB description 752) is a one-to-one connected input, and the REGB description 752 simply takes in the signal from OUTA with its clock, and the clock description of the REGA description 751 and the clock description of the REGB description 752 are opposite in phase. In the case of the relationship, the REGA description 751 and the REGB description 752 are put together, and a half-period delay cell which takes in the input (INA) and outputs (OUTB) is allocated.
[0061]
(Embodiment 7)
FIG. 19 shows a flow of an integrated circuit design method according to claims 20 and 21 of the present invention. In RTL description step 800, the logic is described in RTL, the RTL is read in reading step 801 and the read RTL description is assigned to a logic circuit in synthesis step 802 to create a netlist. The created netlist is checked in timing in step 803. The timing of the synthesis result is checked using the temporary wiring delay, and if there is no violation in the timing check step 803 in the determination step 804, the process ends as it is. If there is a violation, the process is corrected in the correction step 805 and the process ends.
[0062]
In the correction step 805, when a violation is corrected, if a hold violation of more than a half cycle has occurred in all paths from the flip-flop of the starting point, the flip-flop of the starting point is replaced with a half-cycle delay cell. 20).
[0063]
When at least one of the paths from the starting flip-flop has a hold violation of less than half a cycle, the maximum delay time of all the paths from the starting flip-flop is less than half a cycle. Even when a violation does not occur even if delayed by a half cycle, the starting flip-flop is replaced with a half-cycle delay cell (corresponding to claim 21).
[0064]
(Embodiment 8)
FIG. 20 shows the flow of the integrated circuit design method according to the present invention. Here, the logic is described in the RTL in the RTL description step 850, and the RTL is read in the reading step 851. Next, in the hold time determination step 853, referring to the cell library 852, if any of the library cells used in the read RTL is equal to or greater than the value given by the threshold value 854, the library cell An attribute is added such that the flip-flop that is the starting point of the signal line connected to the input of the cell is a half-cycle delay cell. In the synthesizing step 855, a half-period delay cell is assigned as a start-point flip-flop connected to the input of the library cell having the attribute to create a netlist (corresponding to claim 22).
[0065]
For cells in the cell library 852 that require a hold time equal to or greater than a certain threshold, an attribute is added in advance so that the flip-flop that is the starting point of the signal line connected to the input of the cell is a half-cycle delay cell. The hold time determination step 853 can be omitted (corresponding to claim 23).
[0066]
(Embodiment 9)
FIG. 21 shows a flow of the integrated circuit design method according to claim 24. In this configuration, the logic is RTL-described in an RTL description step 860, the RTL is read in a read step 861, and the read RTL description is assigned to a logic circuit in a synthesis step 862 to create a netlist. Here, the reading step 861 for reading the RTL analyzes the contents of the RTL description and checks whether or not there is a description for instructing to allocate a half-period delay cell. To this end, the reading step 861 includes a description analysis step 870 and a half-cycle delay cell assignment instruction step 871 for receiving the result and instructing to assign a half-cycle delay cell to the corresponding flip-flop. In the combining step 862, a half cycle delay cell is assigned to the flip-flop designated in the half cycle delay cell assignment instruction step 871.
[0067]
FIG. 22 shows an example of giving a description for instructing to allocate a half-period delay cell to the RTL description. A half-period delay cell allocation description 881 is described in the RTL description 880, and immediately below it. The description (REG description 882) of a certain flip-flop is specified in the half-cycle delay cell allocation instruction step 871 in FIG.
[0068]
Here, for example, when "//" is described at the head of the half-period delay cell allocation description 881, it can be neglected in the simulation (corresponding to claim 25).
[0069]
Even if there is a half-cycle delay cell allocation description 881, if there is no half-cycle delay cell as a synthesis library, it may be ignored (corresponding to claim 26).
[0070]
【The invention's effect】
According to the first aspect of the present invention, by using the half-period delay cell instead of a normal flip-flop, the hold time can be easily secured as a half cycle of the clock cycle.
[0071]
Further, by using the method for data transfer between blocks in which a clock delay difference is likely to occur, it is possible to prevent an increase in circuit scale.
Further, as a half-cycle delay cell, a latch circuit that operates with a negative-phase clock and a clock-synchronous flip-flop circuit that operates with a negative-phase clock are provided at a stage subsequent to the clock synchronous flip-flop as a circuit that generates a half-period delay. With the configuration, since these cells are previously formed into one cell, problems such as a lack of a space to be inserted, a change in a wiring path, and an increase in negative phase clock wiring do not occur. 4).
[0072]
According to the integrated circuit design method of the present invention, the hold constraint is replaced by replacing the transmission-side flip-flop between the blocks described in the netlist with a half-period delay cell before performing the layout. By providing a delay in advance to a portion expected to be hardly satisfied, it is possible to satisfy a hold time after layout and reduce delay variation after layout. In addition, an increase in the circuit scale can be prevented by limiting all flip-flops to a block instead of a half-cycle delay.
[0073]
Furthermore, a cell name list that specifies a specific flip-flop, a block name list that specifies a block, a clock name list that specifies a clock signal, and a clock that specifies a set of one clock signal and another different clock signal A cell to be replaced with a half-period delay cell may be selected in advance using the pair list. By doing so, the increase in circuit scale can be further reduced by narrowing down the number of cells to be replaced (claim 6-10).
[0074]
Further, according to the integrated circuit design method of the present invention, it is determined whether or not transmission and reception of signals between blocks described in the netlist has a shift register configuration from flip-flop to flip-flop. By replacing the flip-flop on the transmitting side with a half-period delay cell when applicable, a delay is given in advance before laying out the part that is expected to be difficult to satisfy the hold constraint, thereby reducing the hold time after layout. Satisfaction can be satisfied, and delay variation after layout can be reduced. Furthermore, the circuit scale can be prevented from increasing by limiting all flip-flops to a delay between blocks instead of having a half-cycle delay.
[0075]
If a latch or another flip-flop that operates in the opposite phase of the clock input to the flip-flop is connected to a stage subsequent to each clock synchronous flip-flop in the netlist description, The number of wirings and the number of clock wiring branches can also be reduced by replacing the flip-flop described above and a latch or another flip-flop at a stage subsequent thereto with a half-cycle delay cell (claim 12).
[0076]
Further, according to the integrated circuit design method of the present invention, when reading and synthesizing the RTL description, a half-period delay cell is allocated as a flip-flop on the transmission side between blocks to satisfy the hold constraint. If it is difficult to do so, by providing a delay to a portion expected before the layout is performed, the hold time after the layout can be satisfied, and the delay variation after the layout can be reduced. In addition, an increase in the circuit scale can be prevented by limiting all flip-flops to a block instead of a half-cycle delay.
[0077]
Furthermore, a block name list that specifies blocks, an inter-block list that specifies between blocks, a clock name list that specifies clock signals, and a clock pair list that specifies a set of one clock signal and another clock signal different from it May be used to select a portion to be allocated to the half-period delay cell in advance. By doing so, the increase in the circuit scale can be further reduced by narrowing down the number of cells to be allocated (claims 14-17).
[0078]
According to the integrated circuit design method of the present invention, it is checked whether or not transmission and reception of signals between blocks at the time of synthesis is performed in a shift register configuration from flip-flop to flip-flop. By assigning a half-period delay cell as a flip-flop and delaying the expected portion before layout if it is difficult to satisfy the hold constraint, the hold time after layout is satisfied and the delay variation after layout is reduced. It can be reduced. In addition, an increase in the circuit scale can be prevented by limiting all flip-flops to a block instead of a half-cycle delay.
[0079]
When a latch or another flip-flop that operates in the opposite phase of the clock input to the flip-flop is connected to a stage subsequent to each clock synchronous flip-flop in the RTL description, The number of wirings and the number of branches of clock wirings can be reduced by collectively allocating latches or other flip-flops in subsequent stages to half-cycle delay cells (claim 19).
[0080]
According to the integrated circuit design method of the present invention, the timing violation is detected by using the temporary wiring delay, so that the cell is replaced with a half-period delay cell. By giving a delay to a portion expected before performing the above, the hold time after layout can be satisfied, and the delay variation after layout can be reduced. In addition, it is possible to prevent an increase in circuit scale by limiting all flip-flops to an error generating unit instead of having a half-cycle delay.
[0081]
If there is a path that has a hold violation of less than half a cycle, and if the maximum delay time of all paths from the flip-flop that is the starting point is less than half a cycle, the flip-flop that is the starting point is delayed by a half cycle. Even if the cells are replaced with cells, the delay constraint can be satisfied, thereby reducing the portion for adjusting the delay after layout (claim 21).
[0082]
According to the integrated circuit design method of the present invention, when it is known that a relatively large hold time constraint is required in advance in a macro such as an SRAM, the input of a cell in the synthesis library is performed. Looking at the hold time constraint, the half-cycle delay cell is assigned as a flip-flop at the starting point of the input signal to that cell, and the synthesis is performed so that it is difficult to satisfy the hold constraint. By giving a delay in advance, it is possible to satisfy the hold time after layout and reduce the delay variation after layout.
[0083]
Also, instead of looking at the input hold time constraints of the cells in the synthesis library, an attribute for instructing the synthesis library to allocate a half-cycle delay cell may be given and assigned accordingly ( Claim 23).
[0084]
Further, a description for instructing the assignment of a half-period delay cell to the RTL description may be provided, and the half-period delay cell may be assigned to a syntax to which a flip-flop having the description is to be assigned (claim Item 24).
[0085]
It is more preferable that the description for allocating the half-period delay cell is ignored in the logic simulation.
In addition, if there is no half-cycle delay cell in the synthesis library even if there is a description for assigning a half-cycle delay cell, if an ordinary flip-flop is assigned, the RTL description can be changed to the presence or absence of the half-cycle delay cell. Can be common regardless of.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a half-cycle delay cell in an integrated circuit according to a first embodiment of the present invention;
FIG. 2 is a diagram showing an example of a half-cycle delay circuit in FIG. 1;
FIG. 3 is a diagram showing an example of a half-cycle delay circuit to which a clock synchronous flip-flop circuit is connected in the integrated circuit according to the first embodiment of the present invention;
FIG. 4 is a diagram showing an example in which a half-period delay cell is used as a signal transmitting side between blocks according to the present invention;
FIG. 5 is a diagram showing a flow of an integrated circuit design method according to a second embodiment of the present invention;
FIG. 6 is a diagram showing a state in which a cell is replaced with a half-period delay cell using the cell name list in FIG. 5;
FIG. 7 is a diagram showing a state where a block is replaced with a half-period delay cell using the block name list in FIG. 5;
FIG. 8 is a diagram showing a state in which a list is replaced with a half-period delay cell using the inter-block list in FIG. 5;
FIG. 9 is a diagram showing a state where a clock is replaced with a half-period delay cell using the clock name list in FIG. 5;
FIG. 10 is a diagram showing a state where the clock pair list in FIG. 5 is replaced with a half-period delay cell.
FIG. 11 is a diagram showing a flow of an integrated circuit design method according to a third embodiment of the present invention;
FIG. 12 is a diagram showing a state where a cell is replaced with a half-period delay cell in the flow of FIG.
FIG. 13 is a diagram showing a flow of an integrated circuit design method according to a fourth embodiment of the present invention.
FIG. 14 is a diagram showing a state where the cell is replaced with a half-period delay cell in the flow of FIG.
FIG. 15 is a diagram showing a flow of an integrated circuit design method according to a fifth embodiment of the present invention.
FIG. 16 is a diagram showing a flow of an integrated circuit design method according to a sixth embodiment of the present invention.
FIG. 17 is a diagram showing an example of an RTL description in the flow of FIG. 16;
FIG. 18 is a diagram showing another example of the RTL description in the flow of FIG.
FIG. 19 is a diagram showing a flow of an integrated circuit design method according to a seventh embodiment of the present invention.
FIG. 20 is a diagram showing a flow of an integrated circuit design method according to the eighth embodiment of the present invention;
FIG. 21 is a diagram showing a flow of an integrated circuit design method according to a ninth embodiment of the present invention;
FIG. 22 is a diagram showing an RTL description for instructing to allocate a half cycle delay cell in the flow of FIG. 21;
[Explanation of symbols]
1 half-period delay cell
2 Clock synchronous flip-flop
3 Half-cycle delay circuit
4 Data input
5 Clock input
8 Data output
50 blocks (A)
51 blocks (B)
52 half-period delay cells
53 half-period delay cell
54 flip-flops
58 flip-flops
59 flip-flops
60 half-period delay cell
61 clock
62 buffers
63 buffers

Claims (26)

An integrated circuit provided with a circuit that generates a half-cycle delay at a stage subsequent to a clock synchronous flip-flop. 2. The integrated circuit according to claim 1, wherein a half-period delay generation circuit is provided on a signal transmission side between the blocks. 2. The integrated circuit according to claim 1, wherein the circuit provided at a stage subsequent to the clock synchronous flip-flop and configured to generate a half-period delay is a latch circuit that operates with a reverse-phase clock. 2. The integrated circuit according to claim 1, wherein the circuit provided at a stage subsequent to the clock synchronous flip-flop and configured to generate a half-cycle delay is a clock synchronous flip-flop circuit that operates with a reverse-phase clock. An integrated circuit design method having a replacement step of replacing a transmission-side flip-flop between blocks described in a netlist with a half-cycle delay cell. 6. The integrated circuit design method according to claim 5, further comprising a step of reading a cell name list designating a specific flip-flop and a step of replacing a flip-flop corresponding to the list with a half-period delay cell. 6. The integrated circuit design method according to claim 5, further comprising a step of reading a block name list specifying a block, and a step of replacing a flip-flop corresponding to the list with a half-period delay cell. 6. The integrated circuit design method according to claim 5, further comprising a step of reading an inter-block list that specifies pairs of blocks, and a step of replacing a flip-flop corresponding to the list with a half-period delay cell. 6. The integrated circuit according to claim 5, further comprising a step of reading a clock name list designating a clock signal, and a step of replacing a flip-flop on a transmitting side between blocks operated by clocks corresponding to the list with a half-period delay cell. Circuit design method. A step of reading a clock pair list designating a set of a certain clock signal and another clock signal different from the clock signal, and a transmission-side flip-flop in a transmission / reception signal system between blocks operating with the set of clocks corresponding to the list. 6. The integrated circuit design method according to claim 5, further comprising a replacement step of replacing the data with a half cycle delay cell. A shift register check step for checking whether the transmission and reception of signals between blocks is a shift register configuration from flip-flop to flip-flop, and a check result of the shift register check step, the transmission-side flip-flop in the net list is 6. A method for designing an integrated circuit according to claim 5, further comprising a replacement step of replacing the cell with a half cycle delay cell. A negative-phase clock connection checking step for checking whether a latch or a flip-flop operating in the reverse phase of the clock input to the flip-flop is connected at a stage subsequent to each clock synchronous flip-flop in the netlist description; An integrated circuit design method comprising the steps of: replacing the flip-flop in the netlist and a latch or flip-flop in a stage subsequent to the flip-flop in the netlist with a half-period delay cell, . A read step for reading the RTL description; and a synthesis step for synthesizing logic from the read RTL description. In the synthesis step, a half-cycle delay cell is allocated as a flip-flop on the transmission side between blocks. Circuit design method. 14. The integrated circuit design method according to claim 13, further comprising a step of reading a block name list designating a block, wherein in the synthesizing step, a half-period delay cell is assigned as a flip-flop on the transmission side of the block corresponding to the list. 14. The integrated circuit design method according to claim 13, further comprising the step of reading an inter-block list specifying blocks, and in the synthesizing step, allocating a half-period delay cell as a transmission-side flip-flop between the blocks corresponding to the list. 14. The integrated circuit according to claim 13, further comprising a step of reading a clock name list designating a clock signal, wherein in the synthesizing step, a half-period delay cell is assigned as a flip-flop on a transmission side between blocks operating with the clock corresponding to the list. Circuit design method. A step of reading a clock pair list designating a set of a certain clock signal and another clock signal different from the clock signal. 14. The integrated circuit design method according to claim 13, wherein a half-period delay cell is assigned as a flip-flop on the transmission side. There is a reading step for reading the RTL description, and a synthesis step for synthesizing logic from the read RTL description. In this synthesis step, transmission and reception of signals between blocks are performed by the first flip-flop from the second flip-flop. 14. The integrated circuit design method according to claim 13, wherein it is determined whether or not the flip-flop has a shift register configuration, and a half-period delay cell is assigned as a corresponding transmission-side flip-flop. There is a reading step for reading the RTL description, and a synthesizing step for synthesizing logic from the read RTL description. In the synthesizing step, a signal is input to the flip-flop after the clock synchronous flip-flop. It is checked whether a latch or another flip-flop that operates in the opposite phase of the clock is connected, and the relevant flip-flop and a latch or another flip-flop at a stage subsequent thereto are collectively assigned as a half-period delay cell. Integrated circuit design method. A reading step for reading the RTL description, a synthesis step for synthesizing logic from the read RTL description, and a timing checking step for detecting a timing violation by checking the timing of the synthesis result using the temporary wiring delay And a correcting step for correcting a timing violation when it occurs. In the correcting step, when a hold violation of half a cycle or more has occurred in all the paths from the flip-flop of the starting point, An integrated circuit design method for replacing a starting flip-flop with a half-period delay cell. In the correcting step, if there is a path that causes a hold violation of less than half a cycle, and if the maximum delay time of all the paths from the flip-flop of the starting point is less than half a cycle, the flip-flop of the starting point is delayed by a half cycle. 21. The integrated circuit design method according to claim 20, wherein the integrated circuit is replaced with a cell. A reading step for reading the RTL description, a hold time determining step for determining whether the input hold time of the cell in the synthesis library is equal to or longer than a certain threshold value, and a synthesizing logic from the read RTL description. A synthesizing step, and when there is a cell equal to or larger than a threshold value in the hold time determining step, a half-period delay cell is assigned as a flip-flop at a start point of an input signal to the cell. Integrated circuit design method. It has a reading step for reading the RTL description and a synthesis step for synthesizing logic from the read RTL description. For a cell that requires an input hold time equal to or greater than a certain threshold, a half cycle delay cell is added to the synthesis library. An attribute for instructing the assignment is given, and in the synthesizing step, when the input hold time is assigned to a cell that requires a certain threshold or more, a flip-flop at the starting point of an input signal to the cell is used. An integrated circuit design method for allocating a half-period delay cell. A reading step for reading the RTL description, and a synthesizing step for synthesizing logic from the read RTL description; and a description for instructing to allocate a half-period delay cell to the RTL description in the reading step. In the integrated circuit designing method, when there is a portion having the following, in the synthesizing step, the description portion is a half-cycle delay cell. 25. The integrated circuit design method according to claim 24, wherein a description for instructing to allocate a half-period delay cell is described so as to be ignored in the RTL simulation. 25. The integrated circuit design method according to claim 24, wherein the description for instructing the assignment of the half-period delay cell is described so as to be ignored when there is no half-period delay cell in the synthesis library.

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