JP2004186494A - Manufacturing method of laminated semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated semiconductor device with higher precision by suppressing displacement amount between connection lands, among substrates, when a semiconductor package is laminated. <P>SOLUTION: A plurality of wiring boards 2 provided with a semiconductor element region Ga mounted with a semiconductor chip 10 and an interlayer connection region Gb where a connection land 4 and a through hole 7 are formed, and a plurality of intermediate substrates 13 provided with a bump 8 for aligning with an open part S in which the semiconductor chip can be inserted, are prepared between a base board 14 and a ceiling board 15. In a first process, an adhesive layer is formed on the surface of the intermediate substrate. In a second process, the alignment bump of the intermediate substrate is aligned with the through hole of the wiring board while displacing to the base board, for mutual lamination, and the ceiling board is aligned with the top part for lamination. In a third process, the laminate is thermally press-bonded to thermally cure the adhesive of the adhesive layer, forming a laminated semiconductor device. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a stacked semiconductor device formed by stacking a plurality of semiconductor packages.
[0002]
[Prior art]
2. Description of the Related Art In recent years, small memory cards equipped with flash memories have been rapidly expanding their markets for use in portable information devices such as digital still cameras and portable information terminals. In particular, in the field of digital cameras, it is already becoming mainstream, and it is trying to solidify its position as an alternative to MDs and floppy disks.
[0003]
Against this background, small memory cards are required to have higher recording capacity, smaller size, lighter weight, lower cost, and the like, and various memory IC package structures and mounting structures have been proposed.
[0004]
The memory card generally employs a method of soldering a thin mold package such as TSOP (Thin Small Outline Package) to the base substrate, or a method of directly connecting a bare chip to the base substrate by wire bonding or flip chip mounting. ing.
[0005]
However, since the capacity that can be mounted in the same area is determined by the size of the semiconductor chip (semiconductor element), in order to further increase the capacity, it is necessary to consider a mounting structure in which semiconductor chips are three-dimensionally stacked. is there.
[0006]
In such a semiconductor device, a semiconductor package in which a semiconductor chip is mounted on a thin wiring board is stacked, but the wiring boards must be separated from each other, and therefore, an intermediate board is interposed between the wiring boards. Then, by electrically connecting the wiring board and the intermediate board by soldering, electrical and structural bonding between the wiring boards can be obtained.
[0007]
Hereinafter, a method of manufacturing a conventional stacked semiconductor device will be described.
FIG. 6 is a cross-sectional view showing a state where the semiconductor device having a three-dimensional mounting structure is set on a jig to assemble the same. FIG. 7 is a cross-sectional view showing the semiconductor device having a three-dimensional mounting structure assembled on the jig. is there.
[0008]
In the figure, reference numeral 20 denotes a plurality of packaged semiconductor chips 19 having bumps 22 made of solder or the like, and a semiconductor chip 19 mounted on the surface of a wiring board 18 having a thin plate structure on which connection lands 21 are formed using a flip chip method. (Here, four) semiconductor packages 20.
[0009]
Intermediate substrates 27 are interposed between the semiconductor packages 20, and are stacked alternately and vertically. The intermediate board 27 has an opening S into which the semiconductor chip 19 mounted on the wiring board 18 is inserted.
[0010]
The connection lands 21 having the bumps 22 made of solder or the like are also formed on the intermediate substrate 27, and the wiring substrate 18 and the intermediate substrate 27 are electrically and structurally connected via the respective bumps 22.
[0011]
The lowermost one of the stacked semiconductor packages 20 is connected via the bumps 22 of the base substrate 23 and the connection lands 21, and the uppermost semiconductor package 20 is connected via the connection lands 21 formed on the ceiling substrate 28. And are electrically and structurally connected.
[0012]
The wiring board 18 has a wiring pattern 24 made of a copper thin film on the surface of an insulating substrate made of a glass epoxy resin material or the like. A semiconductor chip 19 is attached to a predetermined portion of the wiring pattern 24 using an anisotropic conductive film (ACF) 25 and is flip-chip connected via a bump 26 made of a conductive material such as a gold material.
[0013]
The gap between the semiconductor chip 19 and the wiring board 18, the intermediate board 27, the base board 23, and the ceiling board 28 and the side surfaces of the semiconductor chip 19 are sealed with a resin 29 such as epoxy.
[0014]
Alignment holes 30 are provided at predetermined positions of the semiconductor chip 19 and the wiring substrate 18, the intermediate substrate 27, the base substrate 23, and the ceiling substrate 28, and all of the alignment holes of the substrates communicate with each other.
[0015]
To further explain in terms of the lamination mounting method, four semiconductor chips 19 are mounted on the wiring board 18 by flip-chip connection to form four semiconductor packages 20.
[0016]
Then, the semiconductor package 20 and the intermediate substrate 28 are sequentially placed on the base substrate 23 while positioning the connection lands 21 on the respective substrates by inserting the positioning holes 30 into the pins 29 erected on the assembly jig Z. Mount and stack. Finally, the ceiling substrate 28 is placed.
[0017]
At this time, an epoxy resin 29 is supplied to the base substrate 26, the intermediate substrate 27, and the ceiling substrate 28. After laminating the semiconductor package 20 in four stages, the semiconductor package 20 is put into a vacuum press device, and the connection lands 21 are connected to each other.
[0018]
[Problems to be solved by the invention]
In the stacked semiconductor device having the three-dimensional mounting structure, the four-layer stacked semiconductor package 20 is connected via the bumps 22 of the connection lands 21. It is necessary to keep the amount of displacement between the connection lands 21 within a predetermined value (for example, 50 μm).
[0019]
However, in this lamination method, positioning holes 30 are provided in the wiring board 18 and the like, and the positioning holes are inserted into the pins 29 to perform positioning. A clearance is required between the peripheral surface of the positioning hole 29 and the peripheral surface of the pin 30.
[0020]
Therefore, the amount of stacking deviation between the connection lands 21 to be connected is generated by the amount of the clearance, and may exceed the predetermined value. If the semiconductor package 20 is stacked in this state to manufacture a stacked semiconductor device, there is a possibility that electrical conduction failure may occur.
[0021]
The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the amount of displacement between connection lands on each substrate when stacking semiconductor packages, thereby improving accuracy. It is an object of the present invention to provide a method of manufacturing a stacked semiconductor device which aims at the above.
[0022]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object, a method for manufacturing a stacked semiconductor device according to the present invention is directed to a method for manufacturing a stacked semiconductor device, comprising: a semiconductor element region in which a semiconductor element is mounted between a base substrate and a ceiling substrate; A plurality of wiring boards each provided with an interlayer connection region to be formed on the main surface, an opening through which a semiconductor element can be inserted, a connection land, and a plurality of hooks provided with a hook engaged with the hook. Prepare the intermediate board and each,
A first step of forming an adhesive layer on the surface of the intermediate substrate, and alternately stacking and aligning the engaging portions of the intermediate substrate and the engaging portions of the wiring substrate with respect to the base substrate while shifting the positions; A second step of aligning and laminating the ceiling substrate at the top, and thermocompression-bonding the laminated body composed of the intermediate substrate, the base substrate and the ceiling substrate to thermally cure the adhesive of the adhesive layer, thereby obtaining a laminated semiconductor device. And a third step of forming
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a vertical sectional side view illustrating the configuration of a semiconductor package.
The semiconductor package 1 includes a wiring board 2 having a thickness of about 50 μm and made of, for example, a glass epoxy resin material. On the main surface of the wiring board 2, a wiring pattern 3 made of copper or the like having a thickness of about 18 μm and a connection land 4 having a diameter of about 300 μm are formed.
[0024]
A bump 5 made of solder or the like having a thickness of about 10 μm is provided on the surface of the connection land 4 by plating. A bump 6 made of solder or the like is formed on the connection land 4 and protrudes from the back surface of the wiring board 2.
[0025]
A semiconductor chip (semiconductor element) 10 having a thickness of about 60 μm and having flexibility is mounted on a predetermined portion of the wiring pattern 3 by flip-chip bonding via a bump 11 having a height of 10 μm to 30 μm. ing.
[0026]
When the semiconductor chip 10 is flip-chip bonded, an anisotropic conductive film (ACF) 11 in which conductive particles are dispersed and arranged in a resin is interposed therebetween. Then, for example, by thermocompression bonding at a temperature of 180 ° C., electrical connection between the semiconductor chip 10 and the wiring board 2 can be performed, and resin sealing can be performed.
[0027]
For flip chip bonding, a solder connection method, a crimp connection method, or the like can be used as appropriate in addition to the thermocompression bonding described above. Alternatively, as an alternative to flip-chip bonding, a connection method such as single-point bonding may be appropriately selected to connect the wiring board 2 and the semiconductor chip 10.
[0028]
The wiring board 2 includes a semiconductor element region Ga on which the semiconductor chip 10 is mounted, and an interlayer connection region Gb in which the connection lands 4 are provided around the region or on both left and right sides.
[0029]
In particular, in the interlayer connection region Gb, a through hole 7 serving as a hook for preventing displacement between the connection lands 4 and a plurality of positioning bumps 8 are formed near the through hole. .
[0030]
The through hole 7 and the positioning bump 8 have the same diameter, or the through hole 7 is formed larger than the bump 8. As a result, when the wirings are stacked as described later, the bumps formed on the other substrate and the through holes are securely fitted to the through holes 7 and the bumps 8 of the wiring board 2. ing.
[0031]
A protrusion 9 is formed around the through hole 7 in order to securely fit the through hole 7 and the bump 8 together. The protrusion 9 is formed by applying a metal plating such as a solder having a height of about 25 μm.
[0032]
In addition to using metal plating, the protrusion 9 may be filled with a resin material such as a resist along the periphery of the through-hole 7 instead of the metal plating.
[0033]
Next, a first embodiment of a manufacturing method for obtaining a stacked semiconductor device by stacking a plurality (here, four) of the semiconductor packages 1 configured as described above will be described.
FIG. 2 is a cross-sectional view of the semiconductor device before lamination (before assembly), and FIG. 3 is a cross-sectional view of the stacked semiconductor device in a completed state after assembly.
[0034]
Four semiconductor packages 1 integrally formed as described above with reference to FIG. 1 are prepared with the semiconductor chip 10 facing the lower surface and the wiring board 2 facing the upper surface.
[0035]
Intermediate substrates 13 are interposed between the semiconductor packages, and these are alternately stacked. The intermediate substrate 13 is provided with an opening S for accommodating the semiconductor chip 10, and is designed so as not to contact the semiconductor chip in a stacked state.
[0036]
A plurality of connection lands 4 are provided at predetermined positions on the intermediate substrate 13, and bumps 5 made of solder or the like having a thickness of about 10 μm are provided on this surface by plating. The connection lands 4 are formed with bumps 6 made of solder or the like protruding on the back surface side of the intermediate substrate 13.
[0037]
In addition, positioning bumps 6 as hook portions are formed at predetermined portions of the intermediate substrate 13. The positioning bumps 8 are located at positions correctly facing the through holes 7 provided in the wiring board 2 with the intermediate substrate 13 interposed between the semiconductor packages 1.
[0038]
Further, a through hole 7 serving as a hook is provided in a portion of the intermediate substrate 13 near the connection land 4. Along the periphery of the through hole 7, a protrusion 9 made of metal plating such as solder having a height of about 25 μm is provided.
[0039]
The through holes 7 of the intermediate substrate 13 are also located at positions facing the positioning bumps 8 provided on the wiring substrate 2 with the intermediate substrate 13 interposed between the semiconductor packages 1. The relationship between the diameters of the through holes 7 and the positioning bumps 8 in the intermediate substrate 13 is the same as the relationship between the diameters of the through holes 7 and the bumps 8 in the wiring board.
[0040]
On both surfaces of each intermediate substrate 13, an adhesive layer 16 that covers the adhesive with a predetermined thickness is formed. The adhesive layer 16 covers the connection lands 4 and covers the bumps 5 with substantially the same thickness. Then, the tips of the bumps 6 and 8 slightly protrude, and fill the through holes 7 to completely close them.
[0041]
Along with the lamination of the semiconductor package 1 and the intermediate substrate 13 described above, a base substrate 14 is superimposed on the lowermost portion, and a ceiling substrate 15 is superimposed on the uppermost portion. Note that a dummy semiconductor package 18 is interposed between the lowermost intermediate substrate 13 and the base substrate 14.
[0042]
This dummy semiconductor package 18 does not require a wiring pattern and prepares a substrate 19 having no semiconductor chip. The connection lands 4 and the bumps 6 and 8 having exactly the same structure are formed at the same position as the wiring substrate 2. A through hole 7 is provided. Both surfaces are covered with an adhesive layer 16 and the through holes 7 are closed with an adhesive.
[0043]
The wiring substrate 2 and the intermediate substrate 13, the ceiling substrate 15 and the wiring substrate 2, the intermediate substrate 13 and the substrate 19 of the dummy semiconductor package 18 and the base substrate 14, which constitute the semiconductor package 1, are superimposed on a flat jig Za. Is done.
[0044]
The connection lands 4 formed on the respective substrates 2, 13,... Are electrically connected to each other by the bumps 6, and are bonded and sealed by the adhesive layer 16 to obtain a stacked semiconductor device.
[0045]
Next, a method of manufacturing a stacked semiconductor device formed by stacking the four semiconductor packages 1 described above will be described. FIG. 4 is a flowchart of a method for manufacturing a stacked semiconductor device.
[0046]
In step S1, the wiring board 2 having the configuration before packaging the semiconductor chip 10 shown in FIG. 1, the intermediate substrate 13 having the structure before forming the adhesive layer 16 shown in FIG. Then, the base substrate 14 and the ceiling substrate 15 are respectively manufactured.
[0047]
In step S2, an adhesive is applied to both surfaces of the intermediate substrate 13, the dummy semiconductor package 18, and one surface of each of the base substrate 14 and the ceiling substrate 15 to form an adhesive layer 16. (First step)
In step S3, the semiconductor chip 10 is packaged on each wiring board 2 as described with reference to FIG. Here, four semiconductor packages 1 are obtained.
[0048]
In step S4, the dummy semiconductor package 18 is overlaid on the base substrate 14, and the intermediate substrate 13 and the semiconductor package 1 are alternately stacked on the dummy semiconductor package 18. At this time, the alignment bumps 8 and the through holes 7 of the semiconductor package 1 and the intermediate substrate 13 are aligned by visual recognition and arranged.
[0049]
For example, in the case where the positions are shifted and superimposed, the intermediate substrate 13 is aligned until a feeling of engagement is obtained. When the positions are aligned, the alignment bumps 8 and the through holes 7 are engaged and cannot be shifted, so that the alignment is completed there.
[0050]
Due to the positions of the through holes 7 and the positioning bumps 8 and the setting conditions, there is no room for relative displacement between the connection lands 4. Finally, the ceiling substrate 15 is positioned and arranged at the top of the stacked body of the semiconductor package 1 and the intermediate substrate 13. (Second step)
In step S5, the semiconductor packages 1 and the like in a stacked state are put into a vacuum press. As the pressing conditions, for example, a pressure of about 3.0 MPa is applied under a pressure of about 3.0 MPa at a degree of vacuum of 4.0 kPa or less and a temperature of 180 ° C. for 60 minutes to perform thermocompression bonding. Therefore, a stacked semiconductor device is completed. (Third step)
By adopting the above-described manufacturing method, when the semiconductor package 1, the intermediate substrate 13, the base substrate 14, the ceiling substrate 15 and the like are stacked and connected, the alignment by recognition is possible, and the alignment is performed as in the conventional concept. Precise positioning, which has been difficult with the pin 29, can be performed.
[0051]
Further, at the time of interlayer bonding, misalignment that is likely to occur due to the flow of the adhesive or thermal stress is reliably suppressed, and a stacked semiconductor device that meets predetermined specifications can be efficiently produced.
[0052]
FIG. 5 is a diagram illustrating a second embodiment of the method of manufacturing the stacked semiconductor device.
The semiconductor package 1A in which the semiconductor chip 10 is mounted on the wiring substrate 2A, the intermediate substrate 13A, the base substrate 14A, the ceiling substrate 15A, and the dummy semiconductor package 18A are basically shown in FIGS. The same components as those described above are denoted by the same reference numerals, and a new description will be omitted.
[0053]
The difference is that at least the left and right sides of each of the substrates 2A, 13A,... Extend outward. These extending amounts are the same for each substrate, and a positioning hole a is provided in the extending portion. Naturally, the positions of the positioning holes a are accurately set, and are located at positions facing each other in a state where the substrates are stacked.
[0054]
On the other hand, the positioning jig Z as described above with reference to FIGS. 6 and 7 is prepared, and the respective substrates 2A, 13A,... Are stacked in the order described with reference to FIGS. That is, the positioning holes a of the substrates 2A, 13A,... May be inserted into the pins 29 of the positioning jig Z.
[0055]
That is, the positioning of the through holes 7 and the positioning bumps 8 provided in the respective substrates 2A, 13A,... Is not limited to visual recognition, and the positioning using the pins 17 is also used as in the conventional concept. It is possible.
At this time, it is needless to say that the respective substrates are shifted by 2A, 13A,... Within the range of the clearance with the pins 17 until the feeling of engagement is obtained.
[0056]
【The invention's effect】
As described above, according to the present invention, it is possible to manufacture a stacked semiconductor device that can be stacked with a simple method with high production efficiency and that is free from a connection failure due to a displacement in a connection land.
[Brief description of the drawings]
FIG. 1 is a cross-sectional side view of a semiconductor package according to an embodiment of the present invention.
FIG. 2 is a sectional view of the stacked semiconductor device according to the embodiment before being assembled;
FIG. 3 is an exemplary sectional view of the stacked semiconductor device according to the embodiment after assembly;
FIG. 4 is a flowchart of the method for manufacturing the stacked semiconductor device according to the embodiment.
FIG. 5 is a cross-sectional view of a stacked semiconductor device according to another embodiment.
FIG. 6 is a cross-sectional view before assembling a conventional stacked semiconductor device. FIG. 7 is a cross-sectional view after assembling a conventional stacked semiconductor device.
DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip (semiconductor element), Ga ... Semiconductor element area, 4 ... Connection land, 7 ... Through hole (hook part), Gb ... Interlayer connection area, 2 ... Wiring board, S ... Opening, 8 ... Positioning Bumps (hook portions), 13: intermediate substrate, 14: base substrate, 15: ceiling substrate, 16: adhesive layer, 10: semiconductor package.

Claims (1)

A plurality of wiring boards each having, on a main surface thereof, a semiconductor element region in which a semiconductor element is mounted, an interlayer connection region in which a connection land and a hook portion are formed, between a base substrate and a ceiling substrate, An opening that can be inserted, a connection land, and a plurality of intermediate substrates each having a hooking portion that engages with the hooking portion are prepared,
A first step of forming an adhesive layer on the surface of the intermediate substrate;
With respect to the base substrate, the engaging portion of the intermediate substrate and the engaging portion of the wiring substrate are alternately stacked while being shifted, and the ceiling substrate is aligned and stacked on the top of the stacked body. Two steps,
A third step of thermocompression-bonding the laminated body including the intermediate substrate, the base substrate, and the ceiling substrate to thermally cure the adhesive of the adhesive layer to form a laminated semiconductor device. Of manufacturing a semiconductor device.

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