JP2004184362A - Semiconductor integrated circuit and electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of easily grasping an access state. <P>SOLUTION: As initialization, observation address data and observation bit data are output from a CPU and individually stored into an observation addressing register 311 and an observation bit specifying register 312. When the observation address data matches data on an address bus, data on a data bus is stored by a register 35. Then, from an output bit selecting part 36 based on the observation bit data, the bit data of data output from the register 35 is output as a signal Dn. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and an electronic circuit.
[0002]
[Prior art]
When an ASIC (Application Specific Integrated Circuit) is mounted on a real machine (for example, a copying machine) to check the operation, the normal operation is performed on the entire real machine instead of operating only the ASIC, and the operation of the ASIC is checked. Had gone. When a failure occurs during the operation of the actual device, a signal on the board is detected by an oscilloscope, a logic analyzer, or the like, and the ASIC causing the failure is identified. Alternatively, a defect is detected by causing a CPU (Central Processing Unit: Central Processing Unit) to execute a debugging program or the like to cause the actual machine to perform various operations (for example, see Patent Document 1; Corresponding to the claims). Alternatively, a technique for setting a predetermined data to be input to an internal circuit by using a boundary scan test circuit mounted on an ASIC and reading data from a ROM or a RAM to grasp the state of the internal circuit. Is known (for example, refer to Patent Document 2; corresponds to Claim 3).
[0003]
[Patent Document 1]
JP-A-6-174802 (pages 6-16, FIG. 1)
[Patent Document 2]
JP-A-2000-131389 (pages 2 to 4, FIG. 1)
[0004]
[Problems to be solved by the invention]
However, labor and time are required to confirm a defective portion using an oscilloscope or a logic analyzer. Further, as described in Patent Document 1, a debug program is executed by a CPU, or as described in Patent Document 2, input data is set using a boundary scan test circuit to operate an internal circuit. In such a case, there is a possibility that the operation timing of the ASIC changes as compared with the normal operation. For this reason, there has been a phenomenon that a defect that does not occur during the operation verification of the ASIC occurs in the normal operation. Further, when the operation timing of the ASIC changes, the timing of a signal output from the ASIC to a peripheral device also changes, which makes it difficult to determine the cause of the problem.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit or the like capable of easily grasping an access state.
[0006]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit configured to input observation address data and observation bit data, and to be connected to an address bus and a data bus. And
An observation address designation register for latching the observation address data;
An observation bit designation register for latching the observation bit data,
A comparison unit that compares the data on the address bus with the data stored in the observation address designation register, and outputs a comparison signal when they are the same,
When the comparison signal is output from the comparison unit, data of a bit corresponding to data stored in the observation bit designation register is output as bit data among a plurality of bits constituting data on the data bus. An output bit selection unit,
It is characterized by having.
[0007]
According to the first aspect of the present invention, it is possible to output bit data on the data bus when the address data on the address bus becomes predetermined address data. Therefore, the bit data on the data bus can be easily grasped. Furthermore, if the observation address data and the observation bit data are set at the initial setting stage, the bit data on the data bus can be grasped without interrupting the normal operation for the above setting.
[0008]
According to a second aspect of the present invention, there is provided the semiconductor integrated circuit according to the first aspect,
A first register unit connected to the data bus and storing data on the data bus;
A second register unit connected to an output stage of the first register unit and storing data output by the first register unit;
A change detection unit that detects whether the data stored in the first register unit and the data stored in the second register unit are the same and outputs a detection signal,
Is further provided.
[0009]
According to the second aspect of the present invention, for example, when data on the data bus when data on the address bus becomes a desired address is stored in the first register as needed, The stored data is stored in the second register unit as needed. Then, data stored in each register unit can be compared. That is, for example, it is possible to easily grasp whether or not the data read / written with respect to a predetermined address changes at intervals of time.
[0010]
Further, the invention according to claim 3 is the semiconductor integrated circuit according to claim 1,
A boundary scan test circuit including a plurality of boundary scan register cells having a first latch circuit and a second latch circuit connected in series;
Whether the first data composed of the data stored in the first latch circuit group of each of the boundary scan register cells is the same as the second data composed of the data stored in the second latch circuit group A change detection unit that detects the change and outputs a detection signal;
The first latch circuit group outputs the stored data and stores the data on the data bus when the comparison signal is output from the comparison unit; Is stored in the second latch circuit group.
[0011]
According to the third aspect of the present invention, for example, when the data on the data bus when the data on the address bus becomes a desired address is stored in the first latch circuit group as needed, the first latch circuit The data stored in the group is stored in the second latch circuit group as needed. Then, it is possible to compare the data stored in each register unit constituted by the latch circuit. That is, for example, it is possible to easily grasp whether or not the data read / written with respect to a predetermined address changes at intervals of time. Further, since data can be grasped by using an existing boundary scan test circuit in the semiconductor integrated circuit, the circuit area can be reduced.
[0012]
The invention according to claim 4 is the semiconductor integrated circuit according to claim 2 or 3,
It is characterized by further comprising a selection unit that selects and outputs one of the bit data and the detection signal based on the data stored in the observation bit designation register.
[0013]
According to the fourth aspect of the present invention, by changing the data stored in the observation bit designation register, the observer can select and output either bit data or a detection signal according to the situation. .
[0014]
Next, an invention according to claim 5 is the semiconductor integrated circuit according to any one of claims 1 to 4,
An external output unit that externally outputs data stored in the observation address designation register and the observation bit designation register is further provided.
[0015]
According to the fifth aspect of the present invention, since the data stored in the observation address designation register and the observation bit designation register can be output from the external output unit, it is determined whether the observation address data and the observation bit data are correctly set. Can be confirmed.
[0016]
An electronic circuit according to a sixth aspect of the present invention includes a semiconductor integrated circuit according to any one of the first to fifth aspects,
A processor connected to the address bus and the data bus;
It is characterized by having.
[0017]
According to the sixth aspect of the present invention, the observation address data and the observation bit data are output to the semiconductor integrated circuit according to any one of the first to fifth aspects at the stage of initializing the processor, and the normal operation is performed thereafter Can be performed. Therefore, there is no need to execute a debugging program or the like for setting the observation address data and the observation bit data, and the operation verification of the electronic circuit can be performed while the processor operates normally.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor integrated circuit and an electronic circuit to which the present invention is applied will be described in detail with reference to FIGS.
[0019]
[First Embodiment]
The first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of an electronic circuit for the CPU 1 to control the ASIC 2 via the address bus ADRB and the data bus DATB. The CPU 1 outputs signals such as a write enable signal WE, a read enable signal OE, and a chip select signal CS to the ASIC 2 in accordance with instructions such as a program stored in a ROM or the like (not shown). Further, the CPU 1 outputs necessary data to the address bus ADRB and the data bus DATB, and controls the operation of each circuit constituting the electronic circuit. The write enable signal WE and the read enable signal OE are signals for setting the ASIC 2 to the write mode or the read mode, and the chip select signal CS is a signal for starting the operation of the ASIC 2.
[0020]
The ASIC 2 receives a write enable signal WE, a read enable signal OE, and a chip select signal CS from the CPU 1. As a result, the internal circuit of the ASIC 2 operates, and various signals (not shown) are output from the ASIC 2 to peripheral devices and the like. The ASIC 2 includes an access analysis unit 3 and a CPU-I / F circuit 4. The data on the data bus DATB is input to the access analysis unit 3 when the address data on the address bus ADRB matches the address data set in advance. Then, the bit data of the data is output from the access analysis unit 3 to the output terminal TEST. The output terminal TEST is an external output unit that outputs data to the outside of the ASIC 2.
[0021]
FIG. 2 is a block diagram showing an internal configuration of the access analysis unit 3 and the CPU-I / F circuit 4. The access analysis unit 3 includes a comparison unit 32, logics 33 and 34, an output bit selection unit 36, and a register unit 35. The CPU-I / F circuit 4 is an interface circuit accessible from the CPU 1 and includes an observation address designation register 311 and an observation bit designation register 312.
[0022]
The observation address designation register 311 is configured by a flip-flop (hereinafter, referred to as “F / F”) corresponding to the effective address bus width of the address bus ADRB. Then, the observation address data output from the CPU 1 is stored.
[0023]
The observation bit designation register 312 is configured by an F / F for an effective data bus width of the data bus DATB. Then, the observation bit data output from the CPU 1 is stored.
[0024]
Specifically, for example, when the effective address bus width of the address bus ADRB is 8 bits and the effective data bus width of the data bus DATB is 8 bits (D0 to D7), as an example, “FF” is stored in the observation address designation register 311. "Address" is stored, and any one of "0" to "7" is stored in the observation bit data.
[0025]
The comparison unit 32 compares the data on the address bus ADRB with the observation address data stored in the observation address designation register 311. If it is determined that the values are the same, the signal S1 is output. For example, when the address “FF” is stored in the observation address designation register 311 and the data on the address bus ADRB becomes the address “FF”, the comparison unit 32 outputs the signal S1.
[0026]
The logic 33 receives the write enable signal WE and the chip select signal CS. Then, when both signals are active, the signal S2 is output. Note that the timing may be adjusted in the ASIC 2 for the write enable signal WE and the chip select signal CS, and the signals after the timing adjustment may be input to the logic 33 to output the signal S2. Logic 34 receives signals S1 and S2. Then, when both signals are active, the signal S3 is output.
[0027]
The register section 35 is configured by an F / F or the like for the width of the data bus DATB. Data is input to each input terminal of each F / F from each data line of the data bus DATB. The signal S3 is input to the clock terminal CK of each F / F. When the signal S3 becomes active, data on the data bus DATB is input to each F / F, and the data is stored. For example, when the data on the data bus DATB is “FF”, “1” is stored in each F / F configuring the register unit 35.
[0028]
Note that the signal S3 may be used as an enable signal for each F / F configuring the register unit 35, and a clock signal used for the operation of the ASIC 2 may be input to the clock terminal CK. In this case, when the signal S3 becomes active, data on the data bus DATB is input to and stored in each F / F at the rising or falling edge of the clock signal.
[0029]
The output bit selection unit 36 receives the observation bit data stored in the observation bit designation register 312 and the data output from the register unit 35. Then, the bit data selected based on the observed bit data from the data input from the register unit 35 is output from the output bit selection unit 36 to the output terminal TEST as a signal Dn.
[0030]
More specifically, for example, when “0” is stored in the observation bit designation register 312, the output bit selection unit 36 outputs the first bit (D0) bit data of the data input from the register unit 35. Is output as a signal Dn.
[0031]
Next, the circuit operation will be described. First, observation address data and observation bit data are output from the CPU 1 as initial settings before normal operation. The observation address data is stored in the observation address specification register 311, and the observation bit data is stored in the observation bit specification register 312.
[0032]
Thereafter, the CPU 1 performs a normal operation. During the normal operation of the CPU 1, the comparison unit 32 compares the observation address data stored in the observation address designation register 311 with the data on the address bus ADRB. When the data matches, the comparison unit 32 outputs a signal S1. When the write enable signal WE and the chip select signal CS are active, the logic 33 outputs a signal S2. When the signals S1 and S2 become active, the logic 34 outputs a signal S3. Then, the data on the data bus DATB is latched by the register unit 35.
[0033]
The output bit selection unit 36 selects bit data from the data output from the register unit 35 based on the observation bit data stored in the observation bit designation register 312, and outputs the selected bit data to the output terminal TEST as a signal Dn.
[0034]
As described above, the observation address data and the observation bit data can be set before the CPU 1 starts the normal operation. Therefore, the data on the data bus DATB when the data on the address bus ADRB reaches the set address can be grasped without interrupting the normal operation of the CPU 1.
[0035]
In other words, the operation timing of the ASIC or the like is shifted between the normal operation and the operation by the execution of the debugging program. Can be reduced.
[0036]
The semiconductor integrated circuit and the electronic circuit according to the present invention are not limited to the above-described contents, and various changes can be made without departing from the spirit of the present invention.
[0037]
For example, in order to grasp the data stored in the observation address designation register 311, the observation bit designation register 312, and the register unit 35, an output unit for outputting these data to an output terminal may be provided. Thereby, the observation address data and the observation bit data stored in the observation address designation register 311 and the observation bit designation register 312 can be confirmed. Further, data stored in the register unit 35 can be grasped.
[0038]
Next, examples of the present invention will be described. FIG. 3 is a block diagram showing a circuit configuration of the ASIC 200 corresponding to the boundary scan test. The boundary scan test circuit mainly includes a boundary scan register 101, a bypass register 102, an instruction register 103, an option register 104, and a TAP (Test Access Port) controller 105, and has a TDI terminal (test data input terminal) as an input / output terminal. ) 106, a TCK (test clock) terminal 107, a TMS (test mode selector) terminal 108, a TRST (test reset) terminal 109, and a TDO (test data) output terminal 110.
[0039]
The boundary scan register 101 includes boundary scan register cells (hereinafter, referred to as “BSR”) 20a, 20b,... Disposed between the internal circuit and each of the input / output terminals 114 (hereinafter, collectively referred to as “BSR20”). ) Are connected in series, and the event occurring at the input / output terminal 114 can be observed or controlled by the BSR 20. That is, the BSR 20 functions equivalently to the conventional signal detection test probe.
[0040]
The bypass register 102 provides a path for bypassing the signal input from the TDI terminal 106 to the TDO terminal 110 via the shortest path. The instruction register 103 is a circuit that reads and decodes instruction bits and causes the device to execute various functions according to the result. The option register 104 is a circuit in which information for identifying a device and a manufacturer is set. The TAP controller 105 is a sequential circuit that controls the boundary scan register 101 according to signals input from the TCK terminal 107 and the TMS terminal 108.
[0041]
The ASIC 200 further includes an access analysis control unit 40 and a CPU-I / F circuit 4. FIG. 4 is a block diagram showing the configuration of the boundary scan register 101, the access analysis control unit 40, and the CPU-I / F circuit 4.
[0042]
The access analysis control unit 40 includes a comparison unit 32, logics 33 and 34, an output bit selection unit 36, and a clock selection unit 45. Hereinafter, the same components are denoted by the same reference numerals, and description thereof will be omitted.
[0043]
The signal S3 output from the logic 34 and the signals S4 and S5 output from the TAP controller 105 are input to the clock selection unit 45. When the ASIC 200 is in normal operation, the clock selection unit 45 outputs the signals A and B in synchronization with the signal S3. When the boundary scan test operation is being performed, the signals A and B are output in synchronization with the signals S4 and S5.
[0044]
The BSR 20 configuring the boundary scan register 101 latches data on the data bus DATB based on the signal A input from the clock selection unit 45. The latched data is output to the output bit selection unit 36. That is, the BSR 20 is used as a circuit having the same function as the register unit 35 included in the access control unit 3 described in FIG.
[0045]
FIG. 5 is a diagram showing a circuit configuration of the BSR 20a. The BSR 20a includes multiplexers 201 and 204 and latch circuits 202 and 203, and operates according to signals A and B output from the clock selection unit 45 and signals C and D output from the TAP controller 105.
[0046]
First, when the ASIC 200 is operating normally, the signals A and B are output from the clock selector 45 in synchronization with the signal S3. The signal A is input to the clock terminal CK2 of the latch circuit 202, and the signal B is input to the clock terminal CK3 of the latch circuit 203. The I1 terminals of the multiplexers 201 and 204 are connected to one data line of the data bus DATB. Then, according to the signals C and D output from the TAP controller 105, the multiplexers 201 and 204 are set to output the signal input to the I1 terminal.
[0047]
When the signal A is input to the latch circuit 202, the latch circuit 202 latches the data output from the multiplexer 201. Then, the latched data is output to the output bit selection unit 36. That is, the data output from all the BSRs latching the data on the data bus DATB is input to the output bit selection unit 36. The output bit selection unit 36 outputs, from the input data, data selected based on the observation bit data stored in the observation bit designation register 312 to the output terminal as a signal Dn.
[0048]
On the other hand, during the boundary scan test operation, the clock selection unit 45 outputs the signals A and B based on the signals S4 and S5 output from the TAP controller 105. The BSR 20 operates as an original boundary scan register. That is, based on the signal C, the multiplexer 201 outputs data (data input to the I2 terminal) shifted and output from the latch circuit of the preceding BSR. Then, the latch circuit 202 latches data output from the multiplexer 201 in synchronization with the signal A. The latched data is output to the latch circuit 203 and is shifted and output to the subsequent BSR. As described above, by the shift operation by the latch circuit of the BSR 20, the serial signal for circuit test input from the TDI terminal 106 is transmitted to each BSR 20. Then, based on the signal B, the latch circuit 203 latches the data output from the latch circuit 202. The latched data is output to the multiplexer 204. From the multiplexer 204, data input to the I2 terminal according to the signal D is output to the internal circuit. Thus, the internal circuit starts operation by inputting circuit test data.
[0049]
As described above, in the case of the ASIC 200 including the boundary scan test circuit, the data on the data bus DATB can be fetched by using the boundary scan register 101 and desired bit data can be output from the output terminal. Thus, there is no need to newly install a register unit, and the circuit area can be reduced.
[0050]
[Second embodiment]
A second embodiment will be described with reference to FIGS. In the first embodiment, the bit data on the data bus DATB is output to the output terminal TEST according to the observation bit data stored in the observation bit designation register 312. In the present embodiment, however, the output of the register unit 35 is provided. An ASIC that latches data in another register unit, determines whether data output from the two register units have the same value, and outputs the determination result will be described.
[0051]
In the configuration of the electronic circuit according to the second embodiment, the access analyzer 3 of the ASIC 2 of the electronic circuit of FIG. 1 according to the first embodiment is replaced with the access analyzer 5 shown in FIG. The configuration is the same. Therefore, hereinafter, the same components will be denoted by the same reference numerals, and description thereof will be omitted.
[0052]
The register section 37 has the same configuration as the register section 35, and data output from each F / F of the register section 35 is input to an input terminal of each F / F. Specifically, when the signal S3 becomes active, data output from the register unit 35 is input to and stored in each F / F of the register unit 37. Therefore, the register section 35 and the register section 37 are shift registers.
[0053]
Data output from the register units 35 and 37 is input to the change detection unit 38. Then, the respective data are compared with each other, and the result of determining whether or not the data is the same is output as a signal S6.
[0054]
Specifically, for example, the bit data of each of the register unit 35 and the register unit 37 is input to the two-input Exclusive-OR, the output signals of all the two-input Exclusive-OR are input to the OR circuit, and the output of the OR circuit is output. Is signal S6. In this case, if the data output from the register unit 35 and the register unit 37 are of the same value, the signal S6 is “0”, and if the data is of a different value, the signal S6 is “1”.
[0055]
The selection unit 39 receives the signal Dn and the signal S6, and selects one of them based on the observation bit data. Then, the selected signal is output to the output terminal TEST. Specifically, for example, when the data stored in the observation bit designation register 312 is “0” to “7”, the selection unit 39 selects and outputs the signal Dn. On the other hand, when the observation bit data is other than “0” to “7”, the selection unit 39 selects and outputs the signal S6.
[0056]
Next, the circuit operation will be described. First, the CPU 1 outputs observation address data and observation bit data as initial settings before normal operation. Then, the observation address data is stored in the observation address specification register 311, and the observation bit data is stored in the observation bit specification register 312.
[0057]
Thereafter, the CPU 1 performs a normal operation. During the normal operation of the CPU 1, the comparison unit 32 compares the observation address data stored in the observation address designation register 311 with the data on the address bus ADRB. When the data matches, a signal S1 is output. Logic 33 outputs signal S2 when write enable signal WE and chip select signal CS are active. When the signals S1 and S2 become active, the logic 34 outputs the signal S3. Then, the register unit 35 latches the data on the data bus DATB. Then, the stored data is output from the register unit 35. At the same time, the register unit 37 latches the data output by the register unit 35.
[0058]
Then, from the output bit selection unit 36, of the data output from the register unit 35, bit data selected based on the observation bit data stored in the observation bit designation register 312 is output as a signal Dn. On the other hand, the change detection unit 38 compares the data stored in the register unit 35 with the data stored in the register unit 37, and outputs a signal S6 as a comparison result. Then, based on the observation bit data stored in the observation bit designation register 312 by the selection unit 39, either the signal S6 or the signal Dn is selected and output to the output terminal TEST.
[0059]
As described above, the observation address data and the observation bit data can be set as the initial settings before the normal operation of the CPU 1 starts. Thereby, the data on the data bus DATB when the data on the address bus ADRB reaches the set address can be grasped without interrupting the normal operation of the CPU 1.
[0060]
Therefore, the operation timing of the ASIC or the like is shifted between the normal operation and the operation by the execution of the debug program, so that a failure is overlooked, or a wasteful time is increased due to an increase in verification time due to the occurrence of an unnecessary failure. Can be reduced.
[0061]
Next, a case where a boundary scan test circuit built in an ASIC is used as an embodiment of the present invention will be described. Note that the internal configuration of the ASIC described here is the same as the configuration in which the access analysis control unit 40 configuring the ASIC 200 in FIG. 3 is replaced with the access analysis control unit 50 illustrated in FIG.
[0062]
The access analysis control unit 50 includes a comparison unit 32, logics 33 and 34, an output bit selection unit 36, a clock selection unit 45, a change detection unit 38, and a selection unit 39. 7, the BSR 20 configuring the boundary scan register 101 latches data on the data bus DATB based on signals A and B input from the clock selection unit 45. The latched data is output to the output bit selection unit 36 and the change detection unit 38. That is, the BSR 20 is used as a circuit having the same function as the register units 35 and 37 included in the access control unit 5 described above.
[0063]
FIG. 8 is a diagram showing a circuit configuration of the BSR 20a. In FIG. 8, when the ASIC 200 is operating normally, the clock selection unit 45 outputs signals A and B in synchronization with the signal S3. The signal A is input to the clock terminal CK2 of the latch circuit 202, and the signal B is input to the clock terminal CK3 of the latch circuit 203. The multiplexers 201 and 204 are set so as to output the signal input to the I1 terminal by the signals C and D output from the TAP controller 105. The signals input to the I1 terminals of the multiplexers 201 and 204 are bit data on the data bus DATB.
[0064]
Latch circuit 202 latches data output from multiplexer 201 according to signal A. Then, the data stored by the latch circuit 202 is output to the latch circuit 203, the output bit selection unit 36, and the change detection unit 38. Data output from all the BSRs (BSRs 20a, 20b,...) That latch data on the data bus DATB are input to the output bit selection unit 36 and the change detection unit 38.
[0065]
Latch circuit 203 latches data output from latch circuit 202 according to signal B. Then, the data stored by the latch circuit 203 is output to the change detection unit 38. Data output from all the BSRs latching data on the data bus DATB is input to the output bit selection unit 36 and the change detection unit 38.
[0066]
Then, the change detection unit 38 detects the data input from the first-stage latch circuit (the latch circuit 202 of each BSR; the first latch circuit group) constituting the BSR and the data of the second-stage latch circuit (the latch circuit 203 of each BSR; the second latch circuit). And the data input from the latch circuit group). Then, the signal S6 is output from the change detection unit 38 to the selection unit 39 as a comparison result. On the other hand, from the output bit selection unit 36, among the data output from the BSR 20, bit data selected based on the observation bit data stored in the observation bit designation register 312 is output to the selection unit 39 as a signal Dn. . Then, based on the observation bit data stored in the observation bit designation register 312 by the selection unit 39, either the signal S6 or the signal Dn is selected and output to the output terminal.
[0067]
As described above, in the case of the ASIC 200 including the boundary scan test circuit, the data on the data bus DATB can be fetched by using the boundary scan register 101, and the desired bit data can be output from the output terminal. There is no need to install, and the circuit area can be reduced.
[0068]
【The invention's effect】
According to the first aspect of the present invention, it is possible to output bit data on the data bus when the address data on the address bus becomes predetermined address data. Therefore, the bit data on the data bus can be easily grasped. Further, if the observation address data and the observation bit data are set as the initial settings, the bit data on the data bus can be grasped without interrupting the normal operation for the above setting.
[0069]
According to the invention described in claim 2, for example, when data on the data bus when data on the address bus becomes a desired address is stored in the first register as needed, the data is stored in the first register. The obtained data is stored in the second register unit as needed. Then, data stored in each register unit can be compared. That is, for example, it is possible to easily grasp whether or not the data read / written with respect to a predetermined address changes at intervals of time.
[0070]
According to the third aspect of the present invention, for example, when the data on the data bus when the data on the address bus becomes a desired address is stored in the first latch circuit group as needed, the first latch circuit group Is stored in the second latch circuit group at any time. Then, data stored in each register unit can be compared. That is, for example, it is possible to easily grasp whether or not the data read / written with respect to a predetermined address changes at intervals of time. Further, since data can be grasped by using an existing boundary scan test circuit in the semiconductor integrated circuit, the circuit area can be reduced.
[0071]
According to the fourth aspect of the invention, by changing the data stored in the observation bit designation register, the observer can select and output either bit data or a detection signal according to the situation.
[0072]
According to the fifth aspect of the present invention, since the data stored in the observation address designation register and the observation bit designation register can be output from the external output unit, whether or not the observation address data and the observation bit data are set correctly is determined. You can check.
[0073]
According to the sixth aspect of the present invention, the observation address data and the observation bit data are output to the semiconductor integrated circuit according to any one of the first to fifth aspects at the stage of initial setting of the processor, and thereafter the normal operation is executed. can do. Therefore, there is no need to execute a debugging program or the like for setting the observation address data and the observation bit data, and the operation verification of the electronic circuit can be performed while the processor operates normally.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an electronic circuit for a CPU to control an ASIC via an address bus and a data bus.
FIG. 2 is a block diagram showing an internal configuration of an access analyzer and a CPU-I / F circuit according to the first embodiment.
FIG. 3 is a block diagram showing a circuit configuration of an ASIC corresponding to a boundary scan test.
FIG. 4 is a block diagram showing a configuration of a boundary scan register, an access analysis control unit, and a CPU-I / F circuit according to the first embodiment.
FIG. 5 is a diagram illustrating a circuit configuration of an access analysis control unit according to the first embodiment.
FIG. 6 is a block diagram showing an internal configuration of an access analyzer and a CPU-I / F circuit according to the second embodiment.
FIG. 7 is a block diagram showing a configuration of a boundary scan register, an access analysis control unit, and a CPU-I / F circuit according to the second embodiment.
FIG. 8 is a diagram illustrating a circuit configuration of an access analysis control unit according to the second embodiment.
[Explanation of symbols]
1 CPU
2,200 ASIC
3 Access analysis section
32 Comparison section
33, 34 logic
36 Output bit selector
35, 37 Register section
38 Change detector
39 Selector
4 CPU-I / F circuit
311 Observation address specification register
312 Observation bit designation register
101 Boundary scan register
20a, 20b Boundary scan register cell
40, 50 access analysis control unit
45 Clock selector

Claims (6)

A semiconductor integrated circuit configured to be able to input observation address data and observation bit data, and connected to an address bus and a data bus,
An observation address designation register for latching the observation address data;
An observation bit designation register for latching the observation bit data,
A comparison unit that compares the data on the address bus with the data stored in the observation address designation register, and outputs a comparison signal when they are the same,
When the comparison signal is output from the comparison unit, data of a bit corresponding to data stored in the observation bit designation register is output as bit data among a plurality of bits constituting data on the data bus. An output bit selection unit,
A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to claim 1,
A first register unit connected to the data bus and storing data on the data bus;
A second register unit connected to an output stage of the first register unit and storing data output by the first register unit;
A change detection unit that detects whether the data stored in the first register unit and the data stored in the second register unit are the same and outputs a detection signal,
A semiconductor integrated circuit, further comprising: The semiconductor integrated circuit according to claim 1,
A boundary scan test circuit including a plurality of boundary scan register cells having a first latch circuit and a second latch circuit connected in series;
Whether the first data composed of the data stored in the first latch circuit group of each of the boundary scan register cells is the same as the second data composed of the data stored in the second latch circuit group A change detection unit that detects the change and outputs a detection signal;
The first latch circuit group outputs the stored data and stores the data on the data bus when the comparison signal is output from the comparison unit; Wherein the data output by the second latch circuit group is stored in the second latch circuit group. The semiconductor integrated circuit according to claim 2, wherein:
A semiconductor integrated circuit, further comprising: a selection unit that selects and outputs one of the bit data and the detection signal based on data stored in the observation bit designation register. The semiconductor integrated circuit according to claim 1, wherein:
A semiconductor integrated circuit further comprising an external output unit that externally outputs data stored in the observation address designation register and the observation bit designation register. A semiconductor integrated circuit according to any one of claims 1 to 5,
A processor connected to the address bus and the data bus;
An electronic circuit, comprising:

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