JP2004180403A - Rush current control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem with a conventional rush current control circuit that an external connection device ceases to operate due to the working of a protective function provided in the main device by lessening a power ON current which flows when the external connection device is connected while the main device is operating. <P>SOLUTION: A rush current control circuit 30, which operates, being supplied with power for operation from the main device through a connection cord including a power supply line and being connected to the device body, is provided with a current control resistor R<SB>1</SB>which controls the current flowing to the smoothing capacitor C<SB>1</SB>arranged between power supply lines 31 and 32 when the above connection cord 23 is connected to the above device 10, and an FET transistor 33 which short-circuits the line so that the above current control resistor R<SB>1</SB>may be nonresistant to the above smoothing capacitor C<SB>1</SB>after elaping of a specified period of time since connection of the above connection cord 23 to the above device body 10. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inrush current suppression circuit, and is particularly suitable for use in an external connection device in which a connection means including a power supply line is connected to an apparatus main body and operation power is supplied from the apparatus main body to operate. .
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in an electronic apparatus, generally, an external connection device is connected to a main body device and these are integrally operated. It is also common practice to supply operating power for an external connection device connected to the main unit from the main unit.
[0003]
For example, if an external connection device is connected to a portable notebook personal computer via a USB (Universal Serial Bus), the power of the external connection device may be supplied from the portable notebook personal computer. (Maximum current is about 500 mA when default: 100 mA is set).
[0004]
In order to prepare for such applications, general-purpose equipment is provided with a power supply for an external connection device. In addition, in a general-purpose device, a power supply for supplying power to the outside often has a protection function incorporated therein in preparation for an abnormal operation of the external connection device, a connection error or a failure.
[0005]
For example, from a USB of a portable notebook personal computer, a current of 100 mA is supplied in a standard setting, but in this setting, if an external connection device tries to supply a larger current, a protection circuit operates and power supply is stopped. I am trying to do it. Therefore, if the external connection device consumes an extremely large current even momentarily, the operation of the portable notebook personal computer supplying the operating power may be inconvenient.
[0006]
On the other hand, the external connection device configured to receive operating power from the device main body is configured to operate with a small operating current on average, but instantaneously outputs a large current. It often has a built-in circuit. However, by providing a smoothing capacitor in the power supply line, the large current flowing instantaneously is supplied to the circuit from the smoothing capacitor, and the operating current supplied from the outside is set to a stable small value. Is widely practiced. This is generally known in logic circuits.
[0007]
FIG. 7 shows a specific example. In this example, the device main body 70 and the external connection device 73 are connected via a connection cable 75. The device main body 70 is provided with a power supply circuit 71 and a communication interface 72, and the external connection device 73 is provided with an internal circuit 74.
[0008]
The power supply circuit 71 and the internal circuit 74 are connected via a potential supply line Vdd and a reference potential line GND. In the example of FIG. 7, a coil L1 is provided on the potential supply line Vdd, and a capacitor C1 is connected between the potential supply line Vdd and the reference potential line GND.
[0009]
The communication interface 72 and the internal circuit 74 are connected via communication cables Tx and Rx. Then, transmission and reception between the device main body 70 and the external connection device 73 are performed via the communication cables Tx and Rx, and the power supply circuit 71 connects to the external connection device 73 via the potential supply line Vdd and the reference potential line GND. The operating power is supplied.
[0010]
[Problems to be solved by the invention]
By the way, when the external connection device 73 is connected to the USB of the device main body 70 (for example, a portable notebook personal computer) and the device main body 70 is operating, the power supply lines Vdd and GND of the external connection device 73 are connected. A large current for charging flows instantaneously through the smoothing capacitor C1 connected to.
[0011]
When the instantaneous large current flowing is detected on the device main body 70 side, the protection function provided in the device main body 70 operates to stop the power supply to the external connection device 73, and as a result, the external connection There is a problem that the device 73 does not operate.
[0012]
For example, as a characteristic of a portable notebook personal computer (external connection device 73), the characteristic of detecting a large current flowing instantaneously differs greatly depending on the concept of each notebook personal computer maker. In other words, some manufacturers increase the detection capability for safety, and others are commercially available that allow a period during which the applied current generated when the external connection device 73 is connected flows.
[0013]
For this reason, when the external connection device 73 is developed so as to correspond to the USB provided in a general-purpose notebook personal computer, it is possible to individually evaluate each portable notebook personal computer in each forest. Was needed.
[0014]
However, since the USB has been generalized, it is hardly possible to evaluate all devices. In addition, since the specifications may be changed even for devices of the same model, it is impossible to completely eliminate the problem that normal operation is not performed despite the recommended model for operation confirmation.
[0015]
In view of the above problems, the present invention reduces the power-on current that flows when an external connection device is connected while the main unit is operating, and the protection function provided in the main unit operates to operate the external device. An object of the present invention is to solve a problem that a connection device does not operate.
[0016]
[Means for Solving the Problems]
An inrush current suppression circuit according to the present invention is a rush current suppression circuit provided in an external connection device that has connection means for connecting to an apparatus main body and operates by receiving power supply from the apparatus main body via the connection means. And a rush current suppressing resistor for suppressing a current flowing through a smoothing capacitor provided on a power supply line when the connecting means is connected to the device main body via the connecting means. And a semiconductor switching element for short-circuiting the inrush current suppressing resistor so as to have no resistance with respect to the smoothing capacitor after a predetermined time has elapsed from connection to the main body.
According to another feature of the present invention, the semiconductor switching element is an FET transistor connected in parallel with the inrush current suppressing resistor, and the semiconductor switching element is connected to the device main body at a predetermined time after being connected to the device main body. Until the time elapses, a timer circuit for suppressing the gate electrode of the FET transistor from reaching the operating voltage is provided.
Another feature of the present invention is that the timer circuit includes a series circuit of a timer resistor and a timer capacitor, and one end of the series circuit is connected to one of the power supply lines. The other end of the series circuit is connected to the other supply line of the power supply line, and a connection point between the timer resistor and the timer capacitor is connected to a gate electrode of the FET transistor. It is characterized by:
Another feature of the present invention is that a discharge path for discharging the electric charge accumulated in the timer capacitor is provided when the connection means is detached from the apparatus main body. I have.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a first embodiment of the inrush current suppression circuit of the present invention will be described with reference to the accompanying drawings.
As shown in FIG. 1, a rush current suppressing circuit 30 (see FIG. 2) according to the present embodiment connects a connector 21 to a USB terminal 11 of a portable notebook personal computer (apparatus main body) 10 and a connection cord. It is arranged inside an external connection device 20 that operates by being supplied with operating power from the portable notebook personal computer 10 via 23.
[0018]
FIG. 2 is a diagram showing a main configuration of the rush current suppressing circuit 30 of the present embodiment provided inside the connection device main body 22 constituting the external connection device 20.
As shown in FIG. 2, the rush current suppressing circuit 30 of the present embodiment is disposed between the reference potential line 31 and the potential supply line 32, and the portable notebook personal computer 10 is operating. when inserting the connector 21 to the USB terminal 11 in the state, suppressing the rush current flowing to the smoothing capacitor C _1.
[0019]
In the present embodiment, the potential supply line 32 is connected to the positive potential Vdd side, and a P-channel FET transistor 33 is interposed there. Then, together with the FET transistor 33 and the current suppressing resistor R ₁ in parallel is arranged, the timer capacitor C ₂ and the timer resistor between the reference potential line 31 and the potential supply line 32 R ₂ Is provided in series.
[0020]
Further, a gate electrode G of the timer capacitor C ₂ and the connection point of the timer resistor R ₂ and the FET transistor 33 is connected, the gate electrode G voltage of the connection point as the gate voltage V _G Given to.
[0021]
With the configuration described above, when inserting the connector 21 in a state where the portable notebook computer 10 is operating in the USB terminal 11, the current I _P supplied portable or laptop 10, resistors for current suppression charging the smoothing capacitor _{C 1} through the vessel R1. Thus, as indicated by reference numeral A in FIG. 3 (a), the current IP gradually decreases in accordance with the charging of the smoothing capacitor C _1.
[0022]
Further, since the current I _P also flows through the capacitor C ₂ and the circuit of the timer resistor R ₂ timer, as shown in FIG. 3 (b), "C2 × R2" gate electrode G in response to the time constant of descends gate voltage V _G applied to. This state is indicated by reference numeral D in FIG.
[0023]
Then, when a predetermined time has elapsed, the FET transistor 33 is turned on as shown in FIG. Accordingly, the conduction between the source electrode S and the drain electrode D of the FET transistor 33, so that current flows I _P through the source electrode S~ drain electrode D. This timing is indicated by reference numeral B in FIG. Thus, in the steady state, a prescribed output voltage V _OUT is output to the internal circuit 24 as shown in FIG.
[0024]
Then, as shown in FIG. 3 (d), by connecting the connector 21 when the connection is disconnected from the USB terminal 11 is canceled, the charge accumulated in the timer capacitor C ₂ is discharged, code E gate voltage V _G is instantaneously in the minus as indicated by. Thus, by the charge accumulated in the timer capacitor C ₂ is discharged, since the connector 21 to the next is FET transistor 33 is turned off when connected to the USB terminal 11, the FET transistor 33 disadvantage that the source electrode S~ drain electrode smoothing capacitor C ₁ and a current I _P flows through D are rapidly charged does not occur.
[0025]
Further, immediately after that disconnect the connector 21 from the USB terminal 11, in a state in which the FET transistor 33 is on, when the connector 21 is reconnected to the USB terminal 11, the smoothing capacitor _{C 1} is still Since the battery is sufficiently charged, no rush current flows in this case.
[0026]
In the above-described embodiment, an example having the connection cord 23 has been described. However, the present invention can be similarly applied to a case where the connection connector 21 is directly connected to the connection device main body 22.
[0027]
(Second embodiment)
FIG. 4 shows a second embodiment of the inrush current suppression circuit according to the present invention.
In this second embodiment of the inrush current suppression circuit 40, thereby connecting the potential supply line 32 to the -V _SS potential, shows an example of using the N-channel FET transistor 41 as a semiconductor switching element. The other parts are the same as those in the circuit of FIG. 2 described above, and thus detailed description will be omitted.
[0028]
(Third embodiment)
Next, a second embodiment of the inrush current suppressing circuit of the present invention will be described with reference to FIGS.
The case of the third embodiment of the inrush current limit circuit 50, the smoothing capacitor C ₁ in series, connecting the FET transistor 51 as a semiconductor switching element. Then, connect the current suppressing resistor R ₁ in parallel with the FET transistor 51. Further, a series circuit between the smoothing capacitor C ₁ and a timer capacitor C ₂ and the timer resistor R ₂ in parallel with the FET transistor 51 is provided.
[0029]
The diode D between the connection point and the potential supply line 32 of the series circuit of the capacitor C ₂ and the timer resistor R ₂ for the timer is connected. The diode D, when the connector 21 is connected unplugged from the USB terminal 11 is released, and constitutes a discharge path for charge stored in the capacitor C ₂ for the timer.
[0030]
With the above configuration, when the connector 21 is inserted into the USB terminal 11, a potential of V _dd is applied between the potential supply line 32 and the reference potential line 31, as shown in FIG. . Thus, the smoothing capacitor C ₁ as shown in FIG. (B), charging current flows ic. The charging current ic, as indicated by symbol G in FIG. 6 (b), will converge towards zero with a time constant of the resistor R ₁ and the smoothing capacitor C ₁ for current suppression.
[0031]
The gate voltage VG of the FET transistor 51, as shown in FIG. 6 (c), rises towards the potential of V _dd at a time constant determined by a timer resistor R ₂ and a timer capacitor C _2. Then, in the process, when the FET transistor 51 is turned on, the charging current ic converges to ic = 0 as shown by a symbol H in FIG.
[0032]
Even in this example, connector 21 becomes disconnected unplugged from the USB terminal 11, the charge accumulated in the smoothing capacitor C ₁ is discharged to flow to the internal circuit 24. This state is indicated by reference symbol J in FIG. The charge accumulated in the timer capacitor C ₂ is because it is discharged through the timer resistor R ₂ and diode D, does not occur inconvenience even if reconnection takes place.
[0033]
Since the present invention is configured as described above, when the connector 21 is connected to the USB terminal 11 and the power used in the connection device main body 22 is supplied from the portable notebook personal computer 10, the portable type personal computer 10 is used. Even if the connector 21 is connected while the notebook computer 10 is operating, a large inrush current can be reliably prevented from flowing.
[0034]
Accordingly, by providing the inrush current suppression circuit of the present embodiment, I can use a large smoothing capacitor C ₁ to the power supply line of the connecting device main body 22, it is possible to stabilize the operation of the internal circuit 24. In addition, even if there is some variation in the standard of the overcurrent suppressing mechanism on the side of the device main body 10 that is operated by connecting the connection device main body 22, the device can be operated without any inconvenience, and the range of selection of externally connectable devices is reduced. Can be spread.
[0035]
【The invention's effect】
As described above, according to the present invention, since a large capacitor can be used for the power supply line, the operation of the external connection device can be stabilized. This makes it possible to dispose a large capacitor on the power supply line, so that the operation of the external connection device can be stabilized. Further, it is possible to widen a range of selection of devices on the device main body side that can be operated by connecting the external connection device.
In addition, it is possible to remove and connect an external connection device that receives power supply from the device main body during the operation of the device main body, thereby improving usability when connecting the external connection device to the device main body and performing a predetermined operation. It can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a view showing an embodiment of the present invention and showing a state in which an external connection device is connected to a portable notebook personal computer as a device main body.
FIG. 2 is a circuit diagram showing the first embodiment and showing a schematic configuration of an inrush current suppression circuit.
FIG. 3 is an operation waveform diagram for explaining an operation of the inrush current suppression circuit according to the first embodiment.
FIG. 4 is a circuit diagram showing a second embodiment and showing a schematic configuration of an inrush current suppression circuit.
FIG. 5 is a circuit diagram showing a third embodiment and showing a schematic configuration of an inrush current suppressing circuit.
FIG. 6 is an operation waveform diagram for explaining an operation of the inrush current suppression circuit according to the third embodiment.
FIG. 7 is a diagram showing a conventional example of a power supply circuit of an external connection device that operates by being supplied with operation power from the device main body.
[Explanation of symbols]
REFERENCE SIGNS LIST 10 portable notebook computer 11 USB terminal 20 external connection device 21 connection connector 22 connection device main body 23 connection cord 24 internal circuit 30 inrush current suppression circuit 31 reference potential line 32 potential supply line 33 FET transistor C1 smoothing capacitor R1 current suppression resistance C2 Timer capacitor R2 Timer resistor

Claims (4)

An inrush current suppression circuit provided in an external connection device that has a connection unit connected to the device main body and operates by receiving power supply from the device main body through the connection unit,
A rush current suppressing resistor for suppressing a current flowing through a smoothing capacitor provided on a power supply line when connected to the device main body through the connection means, and the connection means is connected to the device main body. A rush current suppressing circuit, comprising: a semiconductor switching element for short-circuiting the rush current suppressing resistor so as to have no resistance with respect to the smoothing capacitor after a predetermined time has elapsed after connection. The semiconductor switching element is an FET transistor connected in parallel with the inrush current suppressing resistor, and the gate of the FET transistor is connected until a predetermined time elapses after the connection means is connected to the device main body. The inrush current suppression circuit according to claim 1, further comprising a timer circuit for suppressing the electrode from reaching an operation voltage. The timer circuit includes a series circuit of a timer resistor and a timer capacitor, one end of the series circuit is connected to one of the power supply lines, and the other end of the series circuit is the power supply line. 3. The inrush current according to claim 2, wherein a connection point between the timer resistor and the timer capacitor is connected to a gate electrode of the FET transistor. Suppression circuit. 4. The rush current suppression circuit according to claim 3, wherein a discharge path is provided for discharging the electric charge stored in the timer capacitor when the connection means is detached from the apparatus main body.

Images