JP2004179503A - Semiconductor device, its manufacturing method, semiconductor package, and its manufacturing method - Google Patents

Semiconductor device, its manufacturing method, semiconductor package, and its manufacturing method Download PDF

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JP2004179503A
JP2004179503A JP2002345824A JP2002345824A JP2004179503A JP 2004179503 A JP2004179503 A JP 2004179503A JP 2002345824 A JP2002345824 A JP 2002345824A JP 2002345824 A JP2002345824 A JP 2002345824A JP 2004179503 A JP2004179503 A JP 2004179503A
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wiring pattern
semiconductor element
electrode
semiconductor device
semiconductor
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Koji Yamaguchi
浩司 山口
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be improved in heat dissipating properties by providing a metal layer on a semiconductor element and reduced in size, to provide its manufacturing method, a semiconductor package, and its manufacturing method. <P>SOLUTION: The figure indicates the semiconductor package containing the semiconductor device 50 related to a first one of the embodiments. As shown in the figure, the semiconductor device 50 related to one of the embodiments is equipped with a relay board 30 containing a first wiring pattern, and the first semiconductor element 10 containing an electrode 12 electrically connected to the first wiring pattern. Furthermore, the semiconductor device 50 may be equipped with external terminals 16 which are electrically connected to the first wiring pattern protruding from the surface of the relay board 30. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に関し、特に、中継基板を利用した構造の半導体装置並びにその製造方法及び半導体パッケージ並びにその製造方法に属する。
【０００２】
【従来の技術】
半導体装置の動作時の発熱が、半導体装置内に蓄積されると、半導体装置の特性等が変化等して、信頼性が低下する虞がある。このため、従来は、半導体素子の表面等にヒートスラグや放熱フィンを設けることにより、半導体装置の放熱効果を高めていた。
【０００３】
【特許文献１】
特開平１１−４０７２４号公報
【０００４】
【発明が解決しようとする課題】
しかしながら、従来技術には以下に掲げる問題点があった。
【０００５】
半導体装置の動作時における発熱量が大きい場合、中継基板にヒートスラグを用いた構造では放熱が不十分であり、また、放熱フィンを用いた構造では半導体装置の小型化が図れないという問題点があった。
【０００６】
本発明は斯かる問題点を鑑みてなされたものであり、その目的とするところは、半導体素子に金属層を設けることで放熱効果を高くすることができ、かつ、小型化が可能な半導体装置並びにその製造方法及び半導体パッケージ並びにその製造方法を提供する点にある。
【０００７】
【課題を解決するための手段】
本発明の半導体装置は、第１の配線パターンを有する中継基板と、前記第１の配線パターンと電気的に接続された第１の電極を表面に含み、前記第１の電極を含む面が前記中継基板の表面と対向するように前記中継基板に搭載された第１の半導体素子と、を備え、前記第１の半導体素子は、前記第１の電極を含む面の裏面に金属層を有することを特徴とする。
前記中継基板は、前記第１の配線パターンと電気的に接続する外部端子を有してもよい。
また、本発明の半導体パッケージは、上記中継基板に外部端子を有する半導体装置と、前記外部端子と電気的に接続する第２の配線パターンを有し、前記半導体装置が搭載された回路基板と、を備え、前記第１の半導体装置の前記金属層は、前記回路基板の前記第２の配線パターンを有する表面に接続していることを特徴とする。
また、本発明の半導体装置の製造方法は、第１の電極を有する半導体素子の、前記第１の電極を有する面の裏面に金属層を設ける工程と、第１の配線パターンを有する中継基板に、前記第１の電極を有する面を前記中継基板の表面に対向させて、前記半導体素子を搭載し、前記第１の配線パターンと前記第１の電極とを電気的に接続する工程と、を備えることを特徴とする。
さらにまた、本発明の半導体パッケージの製造方法は、第１の配線パターンを有する中継基板に、第１の電極と前記第１の電極を有する面の裏面に設けられた金属層とを有する半導体素子を、前記第１の電極が形成された面が前記中継基板に対向するように搭載し、前記第１の配線パターンと前記第１の電極とを電気的に接続する工程と、前記中継基板に、前記中継基板の表面から突出し、前記第１の配線パターンに電気的に接続する外部端子を形成する工程と、第２の配線パターンを有する回路基板に、前記中継基板を搭載し、前記外部端子と前記第２の配線パターンとを電気的に接続し、前記金属層を前記回路基板の表面に接続する工程と、を備えることを特徴とする。
【０００８】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて詳細に説明する。
【０００９】
（第１の実施の形態）
図１は、本実施の第１の実施の形態に係る半導体装置５０を含む半導体パッケージを示す図である。図１に示すように、本実施の一の実施の形態に係る半導体装置５０は、第１の配線パターンを含む中継基板３０と、第１の配線パターンに電気的に接続する電極１２を含む第１の半導体素子１０と、を備える。さらに、第１の配線パターンと電気的に接続し、中継基板３０の表面から突出する外部端子１６を備えてもよい。
【００１０】
中継基板３０は、絶縁基材と絶縁基材上に設けられた第１の配線パターンを少なくとも有する。中継基板３０は、中継基板３０の表面の少なくとも一部に第１の配線パターンが設けられている。中継基板３０は、中継基板３０の表面のみに、第１の配線パターンが設けられた片面配線基板であってもよいし、中継基板３０の内部にも第１の配線パターンに電気的に接続する他の配線パターンを有する多層配線基板であってもよいし、中継基板の第１の配線パターンが形成された面の裏面にも第１の配線パターンに電気的に接続する他の配線パターンを有する両面配線基板であってもよい。絶縁基材は、ポリイミドやポリエチレンテレフタラート等の可撓性材料からなるものであってもよいし、ガラスエポキシ材料等のリジットな材料からなるものであってもよい。中継基板３０は、半導体素子１０が搭載された面の裏面３０ｆ２に、放熱のためのヒートスラグ層３０ｓを有してもよい。これによれば、さらに、半導体装置５０の放熱性を向上することができる。中継基板３０は、略板状に形成されていてもよい。これによれば、半導体素子１０の裏面の金属層１０ｍを回路基板４０等の被接続物に接続する際に、精度良く半導体素子１０を被接続物に対して配置することができ、半導体素子１０にダメージが生じるのを防ぐことができる。中継基板３０には、開口部が形成されていてもよい。第１の半導体素子１０の少なくとも一部が開口部内に配置されていてもよい。
【００１１】
外部端子１６は、中継基板３０の第１の配線パターンが形成された表面から突出して形成されてもよい。外部端子１６は、導電材料からなり、第１の配線パターンと電気的に接続する。外部端子１６は、半田ボール等の突起電極であってもよいし、導電ピンからなるものであってもよい。外部端子１６が半田からなる場合には、回路基板４０等の被接続物と接続する際に、外部端子１６の高さを調節できるため、半導体素子１０にダメージが生じにくい。外部端子１６と第１の配線パターンとは、ワイヤで電気的に接続されていてもよいし、中継基板３０の表面３０ｆ１に引き回された第１の配線パターンに接合されて、電気的に接続されたものであってもよい。第１の配線パターンに接合される場合、外部端子１６は、第１の配線パターンと半田や合金等で金属接合されていてもよいし、導電性のペースト等で接着剤接合されていてもよい。
【００１２】
第１の半導体素子１０は、電極１２を有する面１０ｆ３が、中継基板３０の第１の配線パターンが形成された面３０ｆ１に対向するように配置される。第１の半導体素子１０は、内部に集積回路を含む。電極１２は、集積回路に電気的に接続して設けられている。第１の半導体素子１０の電極１２は、中継基板３０の第１の配線パターンと電気的に接続している。電極１２は、半導体素子１０の表面１０ｆ３に設けられた電極パットのみからなるものであってもよいし、図１から３に示すように、電極パッドと電極パッド上に突出して設けられた突起電極を含むものであってもよい。図２に示すように、第１の半導体素子１０は、第１の半導体素子１０の電極１２が形成された面１０ｆ３の裏面１０ｆ４に放熱層１０ｍを有する。放熱層１０ｍは、半導体素子１０のうち、放熱層１０ｍと電極１２とを除く半導体本体の放熱性よりも高い放熱性を有する材料からなる。例えば、放熱層１０ｍは金属層である。これによれば、半導体装置５０を回路基板４０等の被接続物に接続する場合に、半導体素子１０からの発熱を効果的に放熱することができる。金属層は、金属、金属化合物及び合金の少なくともいずれかを含む層である。放熱層１０ｍは、半導体素子１０の裏面１０ｆ４の全面に形成されているものであってもよいし、一部に形成されているものであってもよい。放熱層１０ｍの厚みは、半導体素子１０のうち、放熱層１０ｍと電極１２とを除く半導体本体の厚みよりも小さくてもよい。
【００１３】
外部端子１６の厚みは、半導体素子１０の厚み以上の大きさであってもよい。これによれば、半導体装置５０を回路基板４０等の被接続物に接続する際に、半導体素子１０にダメージが生じにくい。
【００１４】
次に、本発明の第１の実施の形態にかかる半導体装置の製造方法について説明する。
まず、第１の半導体素子１０を用意する。第１の半導体素子１０は、例えば、図２に示すような形態であってもよい。まず、切断ラインを介して電極１２を有する複数の半導体素子１０が隣接して設けられた半導体ウエハを用意する。半導体ウエハの電極１２が設けられた面の裏面に放熱層１０ｍを設ける。放熱層１０ｍは、半導体ウエハの電極１２が設けられた面の裏面の全面に形成してもよいし、一部に形成してもよい。半導体ウエハに放熱層１０ｍを形成した後に、放熱層１０ｍを有する半導体ウエハを切断ラインに沿って切断し、複数の半導体素子１０に個片化する。これにより、電極１２を有する面１０ｆ３の裏面１０ｆ４に放熱層１０ｍを有する半導体素子１０を用意する。また、第１の半導体素子１０を用意する工程は、半導体ウエハを切断して個片化した後に、個片化された半導体チップの裏面１０ｆ４に、放熱層１０ｍを設けることにより行ってもよい。また、半導体ウエハ又は半導体素子１０への放熱層１０ｍの形成は、シールの貼付け、印刷、コーティング、スパッタリング、ＣＶＤ、蒸着などで行ってもよい。シールの貼付けを用いれば、半導体ウエハの切断工程後の放熱層１０ｍの形成を容易に行うことができる。
【００１５】
次に、第１の配線パターンを有する中継基板３０に、電極１２を有する第１の半導体素子１０を搭載し、第１の配線パターンと電極１２とを電気的に接続する。この際、半導体素子１０と中継基板３０とを、第１の半導体素子１０の電極１２を有する面が中継基板３０の表面に対向するように配置して、第１の配線パターンと電極１２とを電気的に接続する。第１の配線パターンと電極１２とは、異方性導電接着剤や絶縁性接着剤を用いて接着剤接合をしてもよいし、半田等のろう材や第１の配線パターンと電極１２との合金や金属間拡散を用いて金属接合してもよい。
【００１６】
次に、中継基板３０の第１の配線パターンが形成された表面３０ｆ１に、中継基板３０の表面から突出するように外部端子１６を設ける。第１の配線パターンに、外部端子１６が接合するように設けられてもよい。また、外部端子１６と第１の配線パターンとは、第１の配線パターンに接続されたワイヤを介して電気的に接続されてもよい。
これによって、本実施の形態にかかる半導体装置を製造することができる。本実施の形態では、外部端子１６を設ける工程を、半導体素子１０の中継基板３０への搭載工程の後に行う例について説明したが、外部端子１６を設ける工程は、半導体素子１０を中継基板３０に搭載する前に行ってもよい。
【００１７】
（第２の実施の形態）
図３は、本発明の第２の実施の形態に係る半導体装置を含む半導体パッケージの構成を示す図である。本発明の第２の実施の形態に係る説明において、本発明の第第１の実施の形態にかかる説明と同一の構成に関する説明は省略する。なお、図１〜２と図３において、同一の構成に関しては、同一符号を付している。図３に示すように、本発明の第２の実施の形態に係る半導体装置は、さらに、第１の半導体素子１０及び中継基板３０の間に配置された第２の半導体素子２０とを備える。第２の半導体素子２０は、電極１８を有し、電極１８と中継基板３０の第１の配線パターンとは電気的に接続している。また、第１の半導体素子１０の電極１２は、第２の半導体素子２０を介して、中継基板３０の第１の配線パターンに電気的に接続している。さらに、第１の半導体素子１０と中継基板３０との間に、他の半導体素子が設けられていてもよい。
【００１８】
中継基板３０は、図３に示すように、少なくとも第２の半導体素子２０の一部を収容する開口部を備えてもよい。これによれば、半導体装置５０の厚みを低減でき、小型化を実現することができる。開口部の深さと外部端子１６の厚みとの合計は、第１の半導体素子１０と第２の半導体素子２０との合計の厚み以上の大きさであってもよい。これによれば、半導体装置５０を回路基板４０等の被接続物に接続する際に、半導体素子１０にダメージが生じにくい。
【００１９】
第１の半導体素子１０と第２の半導体素子２０とは、積層されて配置されている。第１の半導体素子１０と第２の半導体素子２０とは、電極１２を介して接続している。第１の半導体素子１０と第２の半導体素子２０とは、接着剤等で固着されていてもよい。
次に、本発明の第２の実施の形態にかかる半導体装置の製造方法について説明する。本発明の第２の実施の形態の半導体装置の製造方法は、第１の実施の形態の半導体装置の製造方法と、半導体素子の中継基板３０への搭載工程のみが異なるため、半導体素子の中継基板３０への搭載工程についてのみ説明し、第１の実施の形態にかかる説明と同一の構成に関する説明は省略する。
【００２０】
本発明の第２の実施の形態にかかる半導体装置の製造方法における、半導体素子の中継基板３０への搭載工程を説明する。まず、第１の半導体素子１０と第２の半導体素子２０とが固着された状態で、中継基板３０に搭載し、第２の半導体素子２０を中継基板３０に固着する。この際、半導体素子１０と中継基板３０とを、第１の半導体素子１０の電極１２を有する面が中継基板３０の表面に対向するように配置する。第２の半導体素子２０の電極１８と中継基板３０の第１の配線パターンとは、第２の半導体素子２０が中継基板３０に固着される際に電気的に接続されてもよいし、第２の半導体素子２０が中継基板３０に固着された後に電気的に接続されてもよい。第２の半導体素子２０の電極１８と中継基板３０の第１の配線パターンとは、ワイヤを用いて電気的に接続されてもよい。
【００２１】
次に、本発明の実施の形態にかかる半導体装置５０を実装した半導体パッケージについて説明する。半導体装置５０を含む半導体パッケージは、第１及び２の実施の形態において説明した半導体装置５０と、半導体装置５０が搭載され、半導体装置５０の外部端子１６と電気的に接続する第２の配線パターンを有する回路基板４０と、を備える。
【００２２】
回路基板４０は、絶縁基材と絶縁基材上に設けられた第２の配線パターンを有する。絶縁基材は、ポリイミドやポリエチレンテレフタラート等の可撓性材料からなるものであってもよいし、ガラスエポキシ材料等のリジットな材料からなるものであってもよい。絶縁基材は、塑性変形する材料からなるものでもよい。これによれば、半導体装置５０が回路基板４０に接続する際に、回路基板４０が塑性変形できるため、半導体素子１０に回路基板４０と中継基板３０とからのダメージが生じにくい。回路基板４０は、回路基板４０の表面のみに、第２の配線パターンが設けられた片面配線基板であってもよいし、回路基板４０の内部にも第２の配線パターンに電気的に接続する他の配線パターンを有する多層配線基板であってもよいし、回路基板の第２の配線パターンが形成された面の裏面にも第２の配線パターンに電気的に接続する他の配線パターンを有する両面配線基板であってもよい。
【００２３】
第１の半導体素子１０の放熱層１０ｍが設けられた裏面１０ｆ４は、回路基板４０に接続されている。これによれば、第１の半導体素子１０から、効果的に放熱を行うことができ、半導体パッケージの小型化を図ることができる。裏面１０ｆ４は、導電部材を用いて回路基板４０に接続されていてもよい。これによれば、導電部材を介して、半導体素子１０からの発熱を、回路基板４０を介して放熱することができる。導電部材は、半田等のろう材や導電ペーストからなるものであってもよい。導電部材が、導電ペースト等のペーストからなる場合には、放熱層１０ｍを回路基板４０ｍに接続する際に、半導体素子１０にダメージが生じにくい。放熱層１０ｍが金属層である場合、放熱層１０ｍを回路基板４０の第２の配線パターンに導電部材を用いて電気的に接続してもよい。これによれば、放熱性が向上するだけでなく、半導体素子１０の裏面からグランド電位を供給することができる。
【００２４】
次に、本発明の実施の形態にかかる半導体装置を実装した半導体パッケージの製造方法について説明する。
まず、本発明の実施の形態にかかる半導体装置５０の半導体素子１０の裏面１０ｆ４又は回路基板４０の半導体素子１０の搭載領域に導電部材を形成する。導電部材は導電ペーストであってもよいし、半田等のろう材であってもよい。
【００２５】
半導体装置５０の外部端子１６が形成された側を、回路基板４０に向けて配置し、回路基板４０に半導体装置５０を搭載する。そして、回路基板４０の第２の配線パターンと外部端子１６とを電気的に接続する。回路基板４０の第２の配線パターンと外部端子１６とは、接着剤接合や金属接合を用いて接合されていてもよい。例えば、半田等のろう材を用いて接合されてもよい。この際、半導体素子１０の裏面１０ｆ４は、導電部材を介して、回路基板４０に接続される。導電部材は、回路基板４０の第２の配線パターンに電気的に接続するように配置されてもよい。例えば、導電部材と外部端子１６とを構成する材料が、それぞれ、半田等のろう材で形成されている場合、半導体装置５０を搭載してから加熱することにより、第２の配線パターン及び外部端子１６の電気的接続と、第１の配線パターン及び電極１２の接続とを同一工程で行うことができる。
【００２６】
これによって、本実施の形態にかかる半導体パッケージを製造することができる。本実施の形態では、導電部材を設ける工程を含む場合について説明したが、導電部材を設ける工程は省略してもよい。この場合、放熱層１０ｍと回路基板４０との表面とが、直接接続又は近接するように形成される。
【００２７】
【発明の効果】
本発明は以上のように構成されているので、以下に掲げる効果を奏する。
【００２８】
半導体素子の表面に放熱層を設けることによって、半導体素子の放熱効果を高めることができる。このため、放熱性を向上しつつ、半導体装置及びパッケージの小型化を図ることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係る半導体パッケージの構成を示す図である。
【図２】本発明の半導体装置又は半導体パッケージにおける半導体素子の一例を示す図である。
【図３】本発明の実施の形態２に係る半導体パッケージの概略構成を示す図である。
【符号の説明】
１０ 第１の半導体素子、
１０ｍ 放熱層、
１２ 電極、
１４ 配線、
１６ 外部端子、
２０ 第２の半導体素子、
３０ 中継基板、
３０ｓ ヒートスラグ、
４０ 搭載基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a structure using a relay board, a method of manufacturing the same, a semiconductor package, and a method of manufacturing the same.
[0002]
[Prior art]
If heat generated during operation of the semiconductor device is accumulated in the semiconductor device, the characteristics and the like of the semiconductor device may change, and the reliability may be reduced. For this reason, conventionally, the heat dissipation effect of the semiconductor device has been enhanced by providing a heat slug or a radiation fin on the surface or the like of the semiconductor element.
[0003]
[Patent Document 1]
JP-A-11-40724
[Problems to be solved by the invention]
However, the prior art has the following problems.
[0005]
When the amount of heat generated during operation of the semiconductor device is large, heat dissipation is insufficient with a structure using a heat slug as a relay board, and the structure using a heat radiation fin cannot reduce the size of the semiconductor device. there were.
[0006]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor device in which a metal layer is provided on a semiconductor element, whereby a heat radiation effect can be enhanced and the size can be reduced. And a method for manufacturing the same, a semiconductor package, and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
The semiconductor device of the present invention includes, on a surface thereof, a relay substrate having a first wiring pattern, and a first electrode electrically connected to the first wiring pattern, and the surface including the first electrode has a surface A first semiconductor element mounted on the relay substrate so as to face a surface of the relay substrate, wherein the first semiconductor element has a metal layer on a back surface of a surface including the first electrode. It is characterized by.
The relay board may have an external terminal electrically connected to the first wiring pattern.
Further, the semiconductor package of the present invention has a semiconductor device having an external terminal on the relay board, a second wiring pattern electrically connected to the external terminal, a circuit board on which the semiconductor device is mounted, Wherein the metal layer of the first semiconductor device is connected to a surface of the circuit board having the second wiring pattern.
Further, according to the method for manufacturing a semiconductor device of the present invention, a step of providing a metal layer on a back surface of a surface having the first electrode of a semiconductor element having a first electrode; Mounting the semiconductor element with the surface having the first electrode facing the surface of the relay board, and electrically connecting the first wiring pattern and the first electrode. It is characterized by having.
Still further, a method of manufacturing a semiconductor package according to the present invention is directed to a semiconductor element having a relay substrate having a first wiring pattern, the semiconductor element having a first electrode and a metal layer provided on the back surface of the surface having the first electrode. Is mounted so that the surface on which the first electrode is formed is opposed to the relay substrate, and the first wiring pattern and the first electrode are electrically connected. Forming an external terminal projecting from a surface of the relay board and electrically connecting to the first wiring pattern; mounting the relay board on a circuit board having a second wiring pattern; Electrically connecting the metal layer to the second wiring pattern, and connecting the metal layer to a surface of the circuit board.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0009]
(First Embodiment)
FIG. 1 is a diagram illustrating a semiconductor package including a semiconductor device 50 according to the first embodiment. As shown in FIG. 1, a semiconductor device 50 according to one embodiment of the present invention includes a relay substrate 30 including a first wiring pattern and a relay substrate 30 including an electrode 12 electrically connected to the first wiring pattern. And one semiconductor element 10. Further, an external terminal 16 electrically connected to the first wiring pattern and protruding from the surface of the relay board 30 may be provided.
[0010]
The relay substrate 30 has at least an insulating base material and a first wiring pattern provided on the insulating base material. The relay substrate 30 has a first wiring pattern provided on at least a part of the surface of the relay substrate 30. The relay board 30 may be a single-sided wiring board provided with the first wiring pattern only on the surface of the relay board 30, or may be electrically connected to the first wiring pattern inside the relay board 30. It may be a multilayer wiring board having another wiring pattern, or may have another wiring pattern electrically connected to the first wiring pattern on the back surface of the surface of the relay substrate on which the first wiring pattern is formed. It may be a double-sided wiring board. The insulating base material may be made of a flexible material such as polyimide or polyethylene terephthalate, or may be made of a rigid material such as a glass epoxy material. The relay substrate 30 may have a heat slug layer 30s for heat dissipation on the back surface 30f2 of the surface on which the semiconductor element 10 is mounted. According to this, the heat dissipation of the semiconductor device 50 can be further improved. The relay board 30 may be formed in a substantially plate shape. According to this, when connecting the metal layer 10m on the back surface of the semiconductor element 10 to an object to be connected such as the circuit board 40, the semiconductor element 10 can be accurately arranged with respect to the object to be connected. Can be prevented from being damaged. An opening may be formed in the relay board 30. At least a part of the first semiconductor element 10 may be arranged in the opening.
[0011]
The external terminals 16 may be formed so as to protrude from the surface of the relay board 30 on which the first wiring pattern is formed. The external terminal 16 is made of a conductive material, and is electrically connected to the first wiring pattern. The external terminal 16 may be a protruding electrode such as a solder ball or a conductive pin. When the external terminal 16 is made of solder, the height of the external terminal 16 can be adjusted when connecting to the object to be connected such as the circuit board 40, so that the semiconductor element 10 is hardly damaged. The external terminals 16 and the first wiring pattern may be electrically connected by wires, or may be joined to the first wiring pattern routed to the surface 30f1 of the relay board 30 to be electrically connected. May be done. When the external terminals 16 are joined to the first wiring pattern, the external terminals 16 may be metal-joined to the first wiring pattern with solder, an alloy, or the like, or may be joined to the first wiring pattern with a conductive paste or the like. .
[0012]
The first semiconductor element 10 is arranged such that the surface 10f3 having the electrode 12 faces the surface 30f1 of the relay substrate 30 on which the first wiring pattern is formed. The first semiconductor element 10 includes an integrated circuit inside. The electrode 12 is provided so as to be electrically connected to the integrated circuit. The electrode 12 of the first semiconductor element 10 is electrically connected to the first wiring pattern of the relay board 30. The electrode 12 may be composed of only an electrode pad provided on the surface 10f3 of the semiconductor element 10, or as shown in FIGS. 1 to 3, an electrode pad and a protruding electrode provided on the electrode pad. May be included. As shown in FIG. 2, the first semiconductor element 10 has a heat radiation layer 10m on the back surface 10f4 of the surface 10f3 on which the electrode 12 of the first semiconductor element 10 is formed. The heat radiating layer 10m is made of a material having a higher heat radiating property than the semiconductor body of the semiconductor element 10 excluding the heat radiating layer 10m and the electrode 12. For example, the heat radiation layer 10m is a metal layer. According to this, when the semiconductor device 50 is connected to a connected object such as the circuit board 40, heat generated from the semiconductor element 10 can be effectively radiated. The metal layer is a layer containing at least one of a metal, a metal compound, and an alloy. The heat radiation layer 10m may be formed on the entire back surface 10f4 of the semiconductor element 10, or may be formed on a part thereof. The thickness of the heat radiation layer 10m may be smaller than the thickness of the semiconductor body of the semiconductor element 10 excluding the heat radiation layer 10m and the electrode 12.
[0013]
The thickness of the external terminal 16 may be larger than the thickness of the semiconductor element 10. According to this, when the semiconductor device 50 is connected to the connection target such as the circuit board 40, the semiconductor element 10 is hardly damaged.
[0014]
Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described.
First, the first semiconductor element 10 is prepared. The first semiconductor element 10 may have, for example, a form as shown in FIG. First, a semiconductor wafer provided with a plurality of semiconductor elements 10 having electrodes 12 adjacent to each other via a cutting line is prepared. A heat radiation layer 10m is provided on the back surface of the semiconductor wafer on which the electrode 12 is provided. The heat radiation layer 10m may be formed on the entire back surface of the surface of the semiconductor wafer on which the electrodes 12 are provided, or may be formed partially. After the heat dissipation layer 10m is formed on the semiconductor wafer, the semiconductor wafer having the heat dissipation layer 10m is cut along a cutting line to be divided into a plurality of semiconductor elements 10. Thereby, the semiconductor element 10 having the heat radiation layer 10m on the back surface 10f4 of the surface 10f3 having the electrode 12 is prepared. Alternatively, the step of preparing the first semiconductor element 10 may be performed by cutting the semiconductor wafer into individual pieces and then providing a heat radiation layer 10m on the back surface 10f4 of the individualized semiconductor chips. Further, the formation of the heat radiation layer 10m on the semiconductor wafer or the semiconductor element 10 may be performed by sticking a sticker, printing, coating, sputtering, CVD, vapor deposition, or the like. By using the sticking of the seal, it is possible to easily form the heat radiation layer 10m after the step of cutting the semiconductor wafer.
[0015]
Next, the first semiconductor element 10 having the electrode 12 is mounted on the relay substrate 30 having the first wiring pattern, and the first wiring pattern and the electrode 12 are electrically connected. At this time, the semiconductor element 10 and the relay substrate 30 are arranged such that the surface of the first semiconductor element 10 having the electrode 12 faces the surface of the relay substrate 30, and the first wiring pattern and the electrode 12 are Make an electrical connection. The first wiring pattern and the electrode 12 may be bonded to each other using an anisotropic conductive adhesive or an insulating adhesive, or may be a brazing material such as solder or the first wiring pattern and the electrode 12. May be joined using an alloy or diffusion between metals.
[0016]
Next, the external terminals 16 are provided on the surface 30f1 of the relay substrate 30 on which the first wiring pattern is formed so as to protrude from the surface of the relay substrate 30. The external terminals 16 may be provided so as to be joined to the first wiring pattern. Further, the external terminal 16 and the first wiring pattern may be electrically connected via a wire connected to the first wiring pattern.
Thereby, the semiconductor device according to the present embodiment can be manufactured. In the present embodiment, the example in which the step of providing the external terminals 16 is performed after the step of mounting the semiconductor element 10 on the relay board 30 has been described. It may be performed before mounting.
[0017]
(Second embodiment)
FIG. 3 is a diagram illustrating a configuration of a semiconductor package including a semiconductor device according to a second embodiment of the present invention. In the description according to the second embodiment of the present invention, the description of the same configuration as the description according to the first embodiment of the present invention will be omitted. In FIGS. 1 and 2 and FIG. 3, the same components are denoted by the same reference numerals. As shown in FIG. 3, the semiconductor device according to the second embodiment of the present invention further includes a second semiconductor element 20 disposed between the first semiconductor element 10 and the relay substrate 30. The second semiconductor element 20 has the electrode 18, and the electrode 18 is electrically connected to the first wiring pattern of the relay board 30. Further, the electrode 12 of the first semiconductor element 10 is electrically connected to the first wiring pattern of the relay board 30 via the second semiconductor element 20. Further, another semiconductor element may be provided between the first semiconductor element 10 and the relay board 30.
[0018]
As shown in FIG. 3, the relay board 30 may include an opening that accommodates at least a part of the second semiconductor element 20. According to this, the thickness of the semiconductor device 50 can be reduced, and downsizing can be realized. The sum of the depth of the opening and the thickness of the external terminal 16 may be larger than the total thickness of the first semiconductor element 10 and the second semiconductor element 20. According to this, when the semiconductor device 50 is connected to the connection target such as the circuit board 40, the semiconductor element 10 is hardly damaged.
[0019]
The first semiconductor element 10 and the second semiconductor element 20 are stacked and arranged. The first semiconductor element 10 and the second semiconductor element 20 are connected via the electrode 12. The first semiconductor element 10 and the second semiconductor element 20 may be fixed with an adhesive or the like.
Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described. The method for manufacturing a semiconductor device according to the second embodiment of the present invention differs from the method for manufacturing a semiconductor device according to the first embodiment only in the step of mounting the semiconductor element on the relay board 30. Only the mounting process on the substrate 30 will be described, and the description of the same configuration as that of the first embodiment will be omitted.
[0020]
A step of mounting a semiconductor element on the relay board 30 in the method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described. First, in a state where the first semiconductor element 10 and the second semiconductor element 20 are fixed, they are mounted on the relay board 30, and the second semiconductor element 20 is fixed to the relay board 30. At this time, the semiconductor element 10 and the relay substrate 30 are arranged such that the surface of the first semiconductor element 10 having the electrode 12 faces the surface of the relay substrate 30. The electrode 18 of the second semiconductor element 20 and the first wiring pattern of the relay board 30 may be electrically connected when the second semiconductor element 20 is fixed to the relay board 30, The semiconductor element 20 may be electrically connected after being fixed to the relay substrate 30. The electrode 18 of the second semiconductor element 20 and the first wiring pattern of the relay board 30 may be electrically connected using a wire.
[0021]
Next, a semiconductor package on which the semiconductor device 50 according to the embodiment of the present invention is mounted will be described. The semiconductor package including the semiconductor device 50 includes a semiconductor device 50 described in the first and second embodiments, and a second wiring pattern on which the semiconductor device 50 is mounted and which is electrically connected to the external terminal 16 of the semiconductor device 50. And a circuit board 40 having
[0022]
The circuit board 40 has an insulating base and a second wiring pattern provided on the insulating base. The insulating base material may be made of a flexible material such as polyimide or polyethylene terephthalate, or may be made of a rigid material such as a glass epoxy material. The insulating base may be made of a plastically deformable material. According to this, when the semiconductor device 50 is connected to the circuit board 40, the circuit board 40 can be plastically deformed, so that the semiconductor element 10 is less likely to be damaged by the circuit board 40 and the relay board 30. The circuit board 40 may be a single-sided wiring board provided with the second wiring pattern only on the surface of the circuit board 40, or may be electrically connected to the second wiring pattern inside the circuit board 40. It may be a multilayer wiring board having another wiring pattern, and also has another wiring pattern electrically connected to the second wiring pattern on the back surface of the surface of the circuit board on which the second wiring pattern is formed. It may be a double-sided wiring board.
[0023]
The back surface 10f4 of the first semiconductor element 10 on which the heat dissipation layer 10m is provided is connected to the circuit board 40. According to this, heat can be effectively radiated from the first semiconductor element 10, and the size of the semiconductor package can be reduced. The back surface 10f4 may be connected to the circuit board 40 using a conductive member. According to this, heat generated from the semiconductor element 10 can be radiated through the circuit board 40 via the conductive member. The conductive member may be made of a brazing material such as solder or a conductive paste. When the conductive member is made of a paste such as a conductive paste, the semiconductor element 10 is hardly damaged when the heat radiation layer 10m is connected to the circuit board 40m. When the heat radiation layer 10m is a metal layer, the heat radiation layer 10m may be electrically connected to the second wiring pattern of the circuit board 40 using a conductive member. According to this, not only the heat radiation property is improved, but also the ground potential can be supplied from the back surface of the semiconductor element 10.
[0024]
Next, a method for manufacturing a semiconductor package on which the semiconductor device according to the embodiment of the present invention is mounted will be described.
First, a conductive member is formed on the back surface 10f4 of the semiconductor element 10 of the semiconductor device 50 according to the embodiment of the present invention or on the mounting area of the semiconductor element 10 on the circuit board 40. The conductive member may be a conductive paste or a brazing material such as solder.
[0025]
The side on which the external terminals 16 of the semiconductor device 50 are formed is arranged facing the circuit board 40, and the semiconductor device 50 is mounted on the circuit board 40. Then, the second wiring pattern of the circuit board 40 and the external terminals 16 are electrically connected. The second wiring pattern of the circuit board 40 and the external terminals 16 may be joined using an adhesive or a metal. For example, they may be joined using a brazing material such as solder. At this time, the back surface 10f4 of the semiconductor element 10 is connected to the circuit board 40 via a conductive member. The conductive member may be arranged so as to be electrically connected to the second wiring pattern of the circuit board 40. For example, when the materials forming the conductive member and the external terminals 16 are each formed of a brazing material such as solder, the semiconductor device 50 is mounted and then heated to form the second wiring pattern and the external terminals. The 16 electrical connections and the connection of the first wiring pattern and the electrode 12 can be performed in the same step.
[0026]
Thereby, the semiconductor package according to the present embodiment can be manufactured. In this embodiment, the case where the step of providing the conductive member is included has been described, but the step of providing the conductive member may be omitted. In this case, the heat radiation layer 10m and the surface of the circuit board 40 are formed so as to be directly connected or close to each other.
[0027]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0028]
By providing the heat dissipation layer on the surface of the semiconductor element, the heat dissipation effect of the semiconductor element can be enhanced. Therefore, it is possible to reduce the size of the semiconductor device and the package while improving heat dissipation.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a semiconductor package according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a semiconductor element in a semiconductor device or a semiconductor package of the present invention.
FIG. 3 is a diagram illustrating a schematic configuration of a semiconductor package according to a second embodiment of the present invention;
[Explanation of symbols]
10 first semiconductor elements,
10m heat dissipation layer,
12 electrodes,
14 wiring,
16 external terminals,
20 second semiconductor element,
30 relay board,
30s heat slag,
40 Mounting board

Claims (10)

第１の配線パターンを有する中継基板と、
前記第１の配線パターンと電気的に接続された第１の電極を表面に含み、前記第１の電極を含む面が前記中継基板の表面と対向するように前記中継基板に搭載された第１の半導体素子と、を備え、
前記第１の半導体素子は、前記第１の電極を含む面の裏面に金属層を有する
ことを特徴とする半導体装置。A relay board having a first wiring pattern;
A first electrode mounted on the relay board such that a surface including a first electrode electrically connected to the first wiring pattern is provided, and a surface including the first electrode is opposed to a surface of the relay board. And a semiconductor element of
The semiconductor device according to claim 1, wherein the first semiconductor element has a metal layer on a back surface of a surface including the first electrode. 前記中継基板は開口部を有し、
前記第１の半導体素子の少なくとも一部は、前記開口部内に配置される
ことを特徴とする請求項１に記載の半導体装置。The relay board has an opening,
The semiconductor device according to claim 1, wherein at least a part of the first semiconductor element is disposed in the opening. 前記第１の半導体素子と前記中継基板との間に配置され、前記第１の配線パターンに接続する第２の電極を有する第２の半導体素子を、さらに備えることを特徴とする請求項１又は２に記載の半導体装置。The semiconductor device according to claim 1, further comprising a second semiconductor element disposed between the first semiconductor element and the relay substrate, the second semiconductor element having a second electrode connected to the first wiring pattern. 3. The semiconductor device according to 2. 前記中継基板は開口部を有し、
前記第２の半導体素子の少なくとも一部は、前記開口部内に配置される
ことを特徴とする請求項３に記載の半導体装置。The relay board has an opening,
4. The semiconductor device according to claim 3, wherein at least a part of the second semiconductor element is disposed in the opening. 前記中継基板は、前記第１の半導体素子が搭載された前記表面の裏面に、ヒートスラグ層を有することを特徴とする請求項１から４のいずれかに記載の半導体装置。5. The semiconductor device according to claim 1, wherein the relay substrate has a heat slug layer on a back surface of the front surface on which the first semiconductor element is mounted. 6. 前記中継基板は、前記第１の配線パターンと電気的に接続する外部端子を有することを特徴とする請求項１から５のいずれかに記載の半導体装置。6. The semiconductor device according to claim 1, wherein the relay board has an external terminal electrically connected to the first wiring pattern. 7. 請求項５に記載の半導体装置と、
前記外部端子と電気的に接続する第２の配線パターンを有し、前記半導体装置が搭載された回路基板と、を備え、
前記第１の半導体装置の前記金属層は、前記回路基板の前記第２の配線パターンを有する表面に接続している
ことを特徴とする半導体パッケージ。A semiconductor device according to claim 5,
A circuit board having a second wiring pattern electrically connected to the external terminal, the circuit board having the semiconductor device mounted thereon,
The semiconductor package according to claim 1, wherein the metal layer of the first semiconductor device is connected to a surface of the circuit board having the second wiring pattern. 請求項７記載の半導体パッケージを備えることを特徴とする電子機器。An electronic apparatus comprising the semiconductor package according to claim 7. 第１の電極を有する半導体素子の、前記第１の電極を有する面の裏面に金属層を設ける工程と、
第１の配線パターンを有する中継基板に、前記第１の電極を有する面を前記中継基板の表面に対向させて、前記半導体素子を搭載し、前記第１の配線パターンと前記第１の電極とを電気的に接続する工程と、
を備えることを特徴とする半導体装置の製造方法。Providing a metal layer on the back surface of the surface of the semiconductor device having the first electrode, the surface having the first electrode;
On a relay substrate having a first wiring pattern, the semiconductor element is mounted with the surface having the first electrode facing the surface of the relay substrate, and the first wiring pattern, the first electrode, Electrically connecting the
A method for manufacturing a semiconductor device, comprising: 第１の配線パターンを有する中継基板に、第１の電極と前記第１の電極を有する面の裏面に設けられた金属層とを有する半導体素子を、前記第１の電極が形成された面が前記中継基板に対向するように搭載し、前記第１の配線パターンと前記第１の電極とを電気的に接続する工程と、
前記中継基板に、前記中継基板の表面から突出し、前記第１の配線パターンに電気的に接続する外部端子を形成する工程と、
第２の配線パターンを有する回路基板に、前記中継基板を搭載し、前記外部端子と前記第２の配線パターンとを電気的に接続し、前記金属層を前記回路基板の表面に接続する工程と、
を備えることを特徴とする半導体パッケージの製造方法。On a relay substrate having a first wiring pattern, a semiconductor element having a first electrode and a metal layer provided on the back surface of the surface having the first electrode is formed by using a semiconductor element having a surface on which the first electrode is formed. Mounting to face the relay substrate, and electrically connecting the first wiring pattern and the first electrode;
Forming, on the relay board, external terminals that protrude from the surface of the relay board and are electrically connected to the first wiring pattern;
Mounting the relay board on a circuit board having a second wiring pattern, electrically connecting the external terminals and the second wiring pattern, and connecting the metal layer to a surface of the circuit board; ,
A method of manufacturing a semiconductor package, comprising:
JP2002345824A 2002-11-28 2002-11-28 Semiconductor device, its manufacturing method, semiconductor package, and its manufacturing method Withdrawn JP2004179503A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210777A (en) * 2005-01-31 2006-08-10 Nec Electronics Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210777A (en) * 2005-01-31 2006-08-10 Nec Electronics Corp Semiconductor device

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