JP2004179409A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a diode satisfying both of an enhancement of a switching speed and a suppression of a leakage current. <P>SOLUTION: A p-type impurity is diffused through an opening of an insulated film 4 to form a p-type semiconductor region 6 in an n-type silicon semiconductor substrate 1, and simultaneously a silicon oxide film 7 is formed in the opening. A micro-opening 8 for introducing a heavy metal as a life time killer is formed in a silicon oxide film 7. A golden film 10 is formed and a golden silicon alloy layer 10a is formed. The golden film 10 is removed, and the golden silicon alloy layer 10a and the semiconductor substrate 1 are heated in accordance with a lamp anneal process, so that a gold of the golden silicon alloy layer 10a is diffused to a desired region of the semiconductor substrate 1. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor element such as a diode, a transistor, or a thyristor, which can selectively diffuse a heavy metal as a lifetime killer into a desired region of a semiconductor substrate.
[0002]
[Prior art]
In a semiconductor device having a PN junction, a heavy metal impurity such as gold or platinum, that is, a lifetime killer is diffused into a semiconductor substrate in order to improve a switching speed of an element. Is known, for example, from Patent Document 1 mentioned above. The heavy metal impurities diffused in the semiconductor substrate constitute a trapping order for carriers. As a result, carriers are recombined via the trap, and the carrier life, that is, the lifetime is shortened, and the switching speed is improved. As a result, a semiconductor device with a high operating frequency can be obtained.
[0003]
However, when a heavy metal as a lifetime killer is diffused into the semiconductor substrate, the effect of shortening the carrier lifetime and improving the switching speed is obtained, but there is a problem that the leakage current increases.
[0004]
[Problems to be solved by the invention]
In order to solve the above problems, it is conceivable to selectively diffuse heavy metals into a semiconductor substrate using a silicon oxide film as a mask.
However, even if the heavy metal is simply diffused through the opening formed in the silicon oxide film as a mask, the diffusion coefficient of the heavy metal is 5 to 7 orders of magnitude larger than other impurities (for example, impurities for determining the conductivity type). For this reason, the heavy metal diffuses almost entirely in the thickness direction of the element, and it is difficult to distribute the heavy metal only in a selected desired region.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of favorably achieving selective diffusion of a heavy metal into a desired region of a semiconductor substrate.
[0006]
[Means for Solving the Problems]
The present invention for solving the above problems and achieving the above object has a first semiconductor region and a conductivity type opposite to the first semiconductor region, and selectively removes a conductivity type determining impurity from one main surface. Preparing a semiconductor substrate having a second semiconductor region formed by diffusion into the semiconductor substrate; and forming the second semiconductor region in a direction perpendicular to a main surface of the semiconductor substrate. Forming a heavy metal selective diffusion mask having a heavy metal non-blocking portion disposed inside and having a smaller area than the second semiconductor region on one main surface or the other main surface of the semiconductor substrate; Placing a heavy metal or a substance containing the same on at least the heavy metal non-blocking portion of the mask, and subjecting the heavy metal or the substance containing the same to heat treatment by light or electromagnetic waves to convert the heavy metal to the semiconductor substrate. Those involved in the method of manufacturing a semiconductor device and a step of selectively diffused in.
[0007]
In addition, as shown in claim 2, the step of disposing a heavy metal or a substance containing the same on at least the heavy metal non-blocking portion of the mask, forming a heavy metal film on the mask and on the heavy metal non-blocking portion, Preferably, a step of forming an alloy layer of a heavy metal and a semiconductor in the heavy metal non-blocking portion and then removing the heavy metal film on the mask is performed.
The mask may include an oxide film of a semiconductor substrate formed on a surface of the semiconductor substrate, the heavy metal non-blocking portion may be an opening formed in the oxide film, and Alternatively, the substance containing the same is desirably an alloy of a heavy metal and a semiconductor.
Preferably, the mask comprises an oxide film of the semiconductor substrate formed on the surface of the semiconductor substrate, and the heavy metal non-blocking portion comprises a portion in which a crack is formed in the oxide film. .
[0008]
【The invention's effect】
According to the invention of each claim, the heavy metal is limited and satisfactorily limited to a desired region of the semiconductor substrate by a combination of the heavy metal non-blocking portion having an area smaller than that of the second semiconductor region and heating by light or electromagnetic waves which is easily controlled. It will be possible to introduce. Therefore, it is possible to suppress the leakage current and improve the switching speed.
According to the second to fourth aspects of the present invention, the limited introduction of heavy metals can be easily and satisfactorily achieved.
[0009]
[First Embodiment]
Next, a method of manufacturing a diode as a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
[0010]
First, an N-type silicon semiconductor substrate 1 is prepared as shown in FIG. This semiconductor substrate 1 has flat first and second main surfaces 1a and 1b facing each other.
[0011]
Next, as shown in FIG. 1B, an N-type impurity (for example, phosphorus) is diffused from the lower surface of the semiconductor substrate 1, that is, the entire second main surface 1b, so that the N ⁺ -type semiconductor having a relatively high impurity concentration is diffused. Region 2 is formed. Thus, an N-type semiconductor region 3 having a low impurity concentration and functioning as the first semiconductor region of the present invention and an N ⁺ -type semiconductor region 2 having a higher impurity concentration than the region 3 are formed on the semiconductor substrate 1. You.
[0012]
Next, as shown in FIG. 1C, an insulating film 4 made of a silicon oxide film or the like is formed on the upper surface of the semiconductor substrate 1, that is, the first main surface 1a, and as shown in FIG. An opening 5 is formed in a portion corresponding to a region where a P-type semiconductor region functioning as a region is to be formed. Thereby, the insulating film 4 functions as a diffusion mask for forming a P-type semiconductor region.
[0013]
Next, a P-type impurity (for example, polon) is selectively diffused into the N-type semiconductor region 3 through the opening 5 of the insulating film 4 as a diffusion mask. Thereby, as shown in FIG. 1D, a P-type semiconductor region 6 as a second semiconductor region in the present invention is formed in the N-type semiconductor region 3. At this time, a thin silicon oxide film 7 is formed on first main surface 1a of semiconductor substrate 1 exposed in opening 5 by heat treatment for diffusion of P-type impurities. This silicon oxide film 7 is used as a heavy metal selective diffusion mask.
[0014]
Next, as shown in FIGS. 2 and 3, a minute opening 8 is formed in the thin silicon oxide film 7. Thereby, the heavy metal diffusion mask 9 is obtained. The opening 8 serving as the heavy metal non-blocking portion is formed in a plan view, that is, in a direction perpendicular to the first main surface 1a, and the insulating film 4 serving as a diffusion mask for forming the P-type semiconductor region 6 and the P-type semiconductor region. And has a sufficiently smaller area than the P-type semiconductor region 6 and the P-type impurity diffusion opening 5. The ratio S2 / S1 of the area S1 of the P-type semiconductor region 6 or the P-type impurity diffusion opening 5 to the area S2 of the heavy metal diffusion opening 8 is preferably 1/100 to 1/5, more preferably 1/50 to 1 / 10.
In FIGS. 2 and 3, the P-type semiconductor region 6 and the two openings 5 and 8 are formed in a substantially square shape in plan view, but may be circular or rectangular.
[0015]
Next, as shown in FIG. 4A, for example, a gold (Au) film 10 is formed as a heavy metal film on the heavy metal diffusion mask 9 composed of the insulating film 4 and the silicon oxide film 7 and in the opening 8 by vacuum evaporation. I do. By heating the semiconductor substrate 1 during or after this vacuum deposition, gold as a heavy metal and silicon of the semiconductor substrate 1 are alloyed, and a gold-silicon alloy layer 10 a is formed in the opening 8.
[0016]
Next, as shown in FIG. 4B, the gold film 10 is removed while leaving the gold-silicon alloy layer 10a.
[0017]
Next, as shown in FIG. 4B, a well-known infrared lamp 11 for lamp annealing is disposed above the center of the first main surface 1a of the semiconductor substrate 1, and the semiconductor substrate 1 having the gold silicon alloy layer 10a is formed. Heat is applied to the gold-silicon alloy layer 10a and the semiconductor substrate 1 by restrictively projecting the infrared rays 12 to the central portion, and gold as a lifetime killer is diffused from the gold-silicon alloy layer 10a to the semiconductor substrate 1. At this time, the heating time and the heating temperature are adjusted by the control means 13 connected to the infrared lamp 11. According to the lamp annealing, the semiconductor substrate 1 can be limitedly heated so that the temperature profile, that is, the temperature distribution becomes steep, and the heating time and the heating temperature are adjusted by the control means 13 so that the accuracy of the temperature profile and the heavy metal Can easily be improved in the accuracy of the distribution. In accordance with the present invention, a lifetime killer made of gold is limited by placing gold as a heavy metal in the micro-apertures 8 and being limitedly heated by infrared rays 12 as shown by the crosses in FIG. As described in the above, the semiconductor layer can be diffused into the N-type semiconductor region 3 and the N ⁺ -type semiconductor region 2 so as to be included in the P-type semiconductor region 6 and at a position slightly apart from the PN junction 14 in the cross section. Further, the lifetime killer can be distributed at a high concentration in a desired area.
[0018]
Next, the silicon oxide film 7 serving as the heavy metal diffusion mask 9 is removed to expose the P-type semiconductor region 6 on the first main surface 1a of the semiconductor substrate 1, and the first semiconductor region 6 is exposed as shown in FIG. An anode electrode 15 as an electrode and a cathode electrode 16 as a second electrode are formed. The anode electrode 15 is electrically connected to the P-type semiconductor region 6 on the first main surface 1a of the semiconductor substrate 1, and the cathode electrode 16 is electrically connected to the N ⁺ -type semiconductor region 2 on the second main surface 1b. Have been.
The insulating film 4 shown in FIG. 4B remains in FIG. 4C, and the anode electrode 15 is connected to the P-type semiconductor region 6 through the opening 5. Can be newly formed, or the insulating film 4 shown in FIG. 4B can be removed to form a new insulating film, and an opening for the anode electrode 15 can be formed here. If the gold-silicon alloy layer 10a shown in FIG. 4B remains after the lamp annealing, a step of removing the same can be provided.
FIG. 4 (C) showing the completed diode does not show a lifetime killer with a cross, but the lifetime killer is distributed similarly to FIG. 4 (B).
[0019]
This embodiment has the following effects.
(1) When viewed in a plan view, an opening 8 having an area sufficiently smaller than the area of the P-type semiconductor region 6 is provided, gold as a heavy metal is disposed therein, a gold-silicon alloy layer 10a is formed, and infrared rays 12 Since gold is locally diffused into the semiconductor substrate 1 by heating, the amount of doping of gold introduced between the semiconductor elements can be controlled relatively well, and a desired region of the semiconductor substrate 1, that is, a small distance from the PN junction 14, can be controlled. The gold as a lifetime killer can be accurately and densely distributed to the N-type semiconductor region 3 and the N ⁺ -type semiconductor region 2. Therefore, the switching speed can be improved by suppressing the leakage current.
(2) Since the silicon oxide film 7 formed when forming the P-type semiconductor region 6 is used as the silicon oxide film 7 for forming the heavy metal diffusion mask 9, the heavy metal diffusion mask 9 can be easily formed.
(3) Since the gold-silicon alloy layer 10a is arranged in the opening 8 and gold is used as a supply source to diffuse gold as a lifetime killer, it is possible to accurately and easily supply gold to a specific region.
[0020]
[Second embodiment]
Next, a method of manufacturing the diode according to the second embodiment of the present invention will be described with reference to FIGS. However, in FIGS. 5 to 7, substantially the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted. In the second embodiment, the description of the substantially same steps as those in the first embodiment will be omitted.
[0021]
FIGS. 5A to 5D show the same ones as FIGS. 1A to 1D. In the second embodiment, as in the first embodiment, the semiconductor substrate 1 shown in FIG. 5A is prepared, and after the steps of FIGS. 5B and 5C, the semiconductor substrate 1 is provided with an N ⁺ type semiconductor. The region 2, the N-type semiconductor region 3, and the P-type semiconductor region 6 are also formed.
[0022]
Next, as shown in FIG. 6A, cracks, that is, fine gaps or cracks are selectively formed in the silicon oxide film 7 by a well-known sandblast method in which fine particles 21 made of an abrasive are sprayed as shown by arrows. A heavy metal non-blocking portion 22 is obtained. The size and position of the heavy metal non-blocking portion 22 are the same or substantially the same as those of the gold introduction opening 8 in FIGS. Many cracks in the heavy metal non-blocking portion 22 include both those that penetrate the silicon oxide film 7 as a mask from the upper surface to the lower surface and those that do not.
[0023]
Next, as shown in FIG. 6B, a gold film 10 as a heavy metal film is formed on the upper surfaces of the silicon oxide film 7 as a heavy metal diffusion mask and the insulating film 4 by a vacuum evaporation method.
[0024]
Next, as shown in FIG. 6 (C), infrared rays 12 are projected by a known lamp annealing method to heat the gold film 10 and the central portion corresponding to the heavy metal non-blocking portion 22 of the semiconductor substrate 1 so as to heat the gold film 10. Gold is introduced into the semiconductor substrate 1 through the cracks in the heavy metal non-blocking portion 22, and gold as a lifetime killer is diffused into a region indicated by a cross in FIG. 6C, that is, a region similar to FIG. 4B. .
[0025]
Next, as shown in FIG. 7, an anode electrode 15 and a cathode electrode 16 are formed in the same manner as in FIG. 4C to complete a diode.
[0026]
The second embodiment has the following effects.
(1) Gold as a heavy metal can be accurately distributed in a desired region of the semiconductor substrate 1 by a combination of the limited heavy metal non-blocking portion 22 and the lamp annealing. Therefore, the switching speed can be improved by limiting the leakage current.
(2) Since the silicon oxide film 7 generated when the P-type semiconductor region 6 is formed is used as a mask for gold diffusion, a gold diffusion mask can be easily formed.
(3) Since the heavy metal non-blocking portion 22 is formed by sandblasting, a heavy metal selective diffusion mask can be easily obtained.
[0027]
[Third Embodiment]
Next, a diode manufacturing method according to the third embodiment will be described with reference to FIG. However, in FIG. 8, substantially the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted.
[0028]
Also in the third embodiment, the one shown in FIG. 1D is prepared as in the first embodiment. Next, as shown in FIG. 8, a silicon oxide film 7a for a heavy metal diffusion mask is formed on the second main surface 1b of the semiconductor substrate 1. Next, an opening 8 is formed at the center of the silicon oxide film 7a in FIG. 8 so as to coincide with the opening 8 in the silicon oxide film 7 in FIG. Next, a gold film as a heavy metal film is formed on the silicon oxide film 7a and in the opening 8, a gold-silicon mixed layer 10a is formed, and unnecessary gold films are removed as in FIGS. 4A and 4B. . Next, as in the first embodiment, the gold of the gold-silicon mixed layer 16a is diffused into a desired region of the semiconductor substrate 1 as a lifetime killer by a lamp annealing method. Gold is distributed in the N ⁺ -type semiconductor region 2 and the N-type semiconductor region 3 slightly apart from the PN junction as shown by the mark x in FIG. Next, the silicon oxide films 7 and 7a are removed, and the same thing as the anode electrode 15 and the cathode electrode 16 of FIG. 4C is formed to complete the diode.
[0029]
According to the third embodiment, since gold as a heavy metal is not diffused to the PN junction, an increase in leakage current can be prevented more effectively.
[0030]
[Modification]
The present invention is not limited to the above embodiment, and for example, the following modifications are possible.
(1) The present invention can be applied to other semiconductor elements such as transistors, thyristors, and ICs. In the case of a transistor, the P-type semiconductor region 6 is used as a base region, an emitter region is formed therein, and the N ⁺ type and N-type semiconductor regions 2 and 3 are used as collector regions.
(2) Instead of infrared rays 12, heating can be performed by light or electromagnetic waves that can be heated.
(3) Platinum other than gold or a mixture of gold and platinum can be used as a heavy metal as a lifetime killer.
(4) Even when the sand blast method of the second embodiment is used, a silicon oxide film 7a is formed on the second main surface 1b of the substrate 1 as in FIG. 8, and a heavy metal non-blocking portion having a crack is provided here. be able to.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a diode according to a first embodiment of the present invention in the order of manufacturing steps.
FIG. 2 is a sectional view showing the diode of the first embodiment in a step following FIG. 1;
FIG. 3 is a plan view of the diode of FIG. 2;
FIG. 4 is a cross-sectional view showing the diode of the first embodiment in a step following FIG. 2;
FIG. 5 is a cross-sectional view illustrating a diode according to a second embodiment of the present invention in the order of manufacturing steps.
FIG. 6 is a cross-sectional view showing the diode of the second embodiment in a step following FIG. 5;
FIG. 7 is a cross-sectional view showing the diode of the second embodiment in a step following FIG. 6;
FIG. 8 is a sectional view showing a diode according to a third embodiment of the present invention in a state similar to FIG. 4B.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor substrate 2 N ⁺ type semiconductor region 3 N type semiconductor region 4 insulating film 5 opening 6 P type semiconductor region 7 silicon oxide film 8 opening 9 heavy metal selective diffusion mask 10 gold film 10 a gold silicon alloy layer 11 lamp 12 infrared ray 14 PN Junction 15 Anode electrode 16 Cathode electrode

Claims (4)

It has a first semiconductor region and a second semiconductor region having a conductivity type opposite to that of the first semiconductor region and formed by selectively diffusing a conductivity type determining impurity from one main surface. Preparing a semiconductor substrate,
Heavy metal selective diffusion having a heavy metal non-blocking portion disposed inside the second semiconductor region and formed in an area smaller than the second semiconductor region when viewed from a direction perpendicular to the main surface of the semiconductor substrate; Forming a mask for one main surface or the other main surface of the semiconductor substrate,
Disposing a heavy metal or a substance containing the same on at least the heavy metal non-blocking portion of the mask;
Subjecting the heavy metal or a substance containing the same to heat treatment with light or electromagnetic waves to selectively diffuse the heavy metal into the semiconductor substrate. A step of disposing a heavy metal or a substance containing the same on at least the heavy metal non-blocking portion of the mask includes forming a heavy metal film on the mask and on the heavy metal non-blocking portion, and forming a heavy metal and a semiconductor on the heavy metal non-blocking portion. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming an alloy layer with the metal alloy and removing the heavy metal film on the mask. The mask comprises an oxide film of a semiconductor substrate formed on a surface of the semiconductor substrate,
The heavy metal non-blocking portion is an opening formed in the oxide film,
2. The method according to claim 1, wherein the heavy metal or a substance containing the heavy metal is an alloy of a heavy metal and a semiconductor. 2. The semiconductor device according to claim 1, wherein the mask comprises an oxide film of the semiconductor substrate formed on the surface of the semiconductor substrate, and the heavy metal non-blocking portion comprises a portion formed with cracks in the oxide film. Production method.

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