JP2004178789A - Reproducing method of recording medium, reproducing control circuit, and reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure stable reproducing performance and to reduce omission of data caused by out of synchronism even when the quality of a reproduced signal is deteriorated by the defect of a recording medium or the like. <P>SOLUTION: This method is a reproducing method of a recording medium in which data is recorded with a block unit having a plurality of frames of the prescribed length and position information of the block is recorded. The method comprises a step in which the data and the position information of the block are obtained from the recording medium, a step in which a recording position for each frame in the block is predicted from the position information of the obtained block, a step in which synchronism is obtained with the frame unit from the obtained data, a step in which a storing place for a memory of the data obtained based on the predicted recording position is decided, and a step in which the obtained data is stored in the storing place of the decided memory. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a method and apparatus for reproducing information recorded on a recording medium for digitizing and recording information, and more particularly, to a recording medium in which positional information is recorded in advance, and a plurality of predetermined frame units associated with the positional information and having a predetermined frame unit. The present invention relates to a method and apparatus for reproducing data recorded in units of blocks. In addition, the present invention relates to a reproduction method, a reproduction control circuit, and a reproduction apparatus for reproducing data from a recording medium on which data such as a magnetic recording medium or an optical disk is error-correction-coded and further divided into a plurality of frames and recorded.

  With the progress of the information-oriented society, information transmission has been steadily increasing in speed and capacity, and a recording medium for recording and storing the information is also required to be faster and larger in capacity.

Generally, in a recording medium for digitizing and recording information, recording / reproduction / management of the data is performed in block units each having a predetermined byte length. The recorded data includes
1) user data obtained by digitizing information to be recorded such as audio / video / computer data;
2) an error correction code (parity code) for detecting or correcting a data error at the time of reading,
3) Redundant data such as a data ID for identifying a data recording position is included. These data are converted into modulation codes suitable for the recording / reproducing signal characteristics of the recording medium, and then recorded as a code sequence. In many cases, recording is performed in such a manner that a synchronization signal is encoded and inserted at each predetermined cycle of a code sequence converted into a modulation code.

  The synchronization signal plays a role of properly synchronizing data when reading data. The reproducing apparatus reads the data ID with frame synchronization, identifies the recording position of the data, and then demodulates and corrects the necessary recording data to obtain the original user data.

  As a method of arranging a coded synchronization signal, a method of arranging a specific pattern at the beginning of a frame of a predetermined byte length is known. As the specific pattern, a pattern that does not exist in the modulation code sequence is used. In addition, by setting the synchronization signal as a combination of (specific pattern + type identifier) and decoding the type identifier in the synchronization signal of one frame or the synchronization signal of several consecutive frames, the frame position in the block can be specified.

  A physical format of a DVD (= Digital Versatile Discs), which is a versatile optical disc, among recording media recently put to practical use will be described as an example. The modulation code sequence uses a run length limited code in which the mark length and the space length are limited from 3T to 11T (T is a channel bit period), and the synchronization signal at the beginning of the frame is a specific pattern using 14T which does not exist in the modulation code sequence. Included as One sector is composed of 26 consecutive frames including 2048 bytes of user data, and a data ID for identifying data is assigned to each sector. Furthermore, one block is composed of 16 consecutive sectors, and encoding / decoding of the error correction code is performed in units of one block. Note that the synchronization signal at the beginning of the frame is configured such that one of the eight types of identifiers is arranged before the specific pattern 14T. These eight types of synchronization signals are called SY0, SY1, SY2, SY3, SY4, SY5, SY6, and SY7. The first frame of each sector includes a data ID in which the SY0 synchronization signal is arranged, and one of SY1 to SY7 is arranged in the subsequent 25 frames.

  As a result, in the apparatus for reproducing the optical disk as described above, if SY0 can be read, it can be specified as the first frame of the sector, and if the data ID is read, the data recording position can be identified and the search operation can be performed. If the type identifiers of three consecutive frames other than SY0 can be correctly read, the frame position in the sector can be specified.

  In a recording medium (recordable optical disk or the like) on which a user can write information, the track on which the data is recorded has a format (change in groove shape) different from that of the recording data (phase change of the recording film, etc.). Etc.), unique address information is recorded in advance. Generally, the recording position of the address information and the relative position of the recording data are determined in advance in association with the pre-recorded address information. In an apparatus for writing information on such a recording medium, data is recorded with reference to the unique address information.

  By the way, conventionally, in an optical disk such as a DVD, an error correction code such as a Reed-Solomon code is used to correct an error caused by a defect of a medium or dust or a scratch attached on a disk surface.

In an error correction code, when the minimum distance of the code is d, the number of corrections t is generally
d ≧ 2 × t + 1
Is established.

  Furthermore, when performing the correction process, if the error position is known in advance, so-called known error position information, that is, erasure correction using the erasure pointer is possible, and the number of corrections can be increased up to twice by performing erasure correction. Can be enhanced.

Assuming that the number of erasure corrections is e,
d ≧ 2 × t + e + 1
Holds, for example, a code having a minimum distance d = 33 has a correction capability (t = 0, e = 32) of a maximum of 32 corrections when all erasure corrections are performed.

  In order to perform the above erasure correction, an error position must be specified in advance, and various methods for specifying the error position have been proposed.

  For example, like an optical disk, coded data obtained by performing error correction coding on data is divided into a plurality of frame data having a predetermined length, and a predetermined synchronization signal is added to the beginning of the modulated frame data obtained by modulating the frame data. In a recording medium having a frame structure in which a frame obtained by recording a frame is recorded on a recording medium, the occurrence of a bit slip is detected from the detection result of the synchronization signal, and the error occurrence position is specified, thereby improving the correction capability (for example, Patent Document 2).

  Further, there is an example in which not only the detection result of the synchronization signal but also a code having a higher correction capability for detecting a burst error and a code having a lower correction capability but a lower redundancy are combined (for example, Non-Patent Documents 1 and 2). And Patent Document 3). As a result, two codes are formed between the synchronization signals, and the erasure position for erasure correction of a code having a low correction capability is specified by using a combination of a correction result of a code having a high correction capability and a detection result of a synchronization signal.

  As described above, conventionally, there has been proposed a method of improving a correction capability by using a detection result of a synchronization signal to specify an error position in erasure error correction, that is, to generate an erasure pointer.

JP-A-11-176081 JP-A-63-157372 (page 3, FIG. 3) Japanese Unexamined Patent Publication No. 2001-515542 (pages 10-11, FIG. 2) Tatsuya Narahara, 7 others, "Optical Disc System for Digital Video Recording", SPIE, Optical Memory and Optical Data Storage International Symposium 1999 (Part of the Joint International Symposium on) Optical Memory and Optical Data Storage 1999), July 1999, Volume 3864, p.50 Tatsuya Narahara and 2 others, “Error Modeling and Performance Analysis of Error-Correcting Codes for the Digital Video Recording System”, SPIE, Part of the Joint International Symposium on Optical Memory and Optical Data Storage 1999, July 1999, Volume 3864, p.340

  However, the method described in the conventional example has some problems.

  First, as a first problem, synchronization at the time of data reproduction is performed by a specific pattern included in a synchronization signal recorded together with data, and a search operation is performed by reading a data ID. For example, if the synchronization signal (SY0 synchronization signal in the case of DVD) in the head frame of a certain sector cannot be identified, the data ID cannot be read, and the data search operation cannot be performed stably.

  Also, by reading the synchronization signal of a plurality of consecutive frames other than the head of the sector, the position of the frame in the sector can be specified, but if the data quality is not good, it takes time to determine the synchronization or the synchronization is determined. In some cases, an impossible task may occur.

  In addition, when the data is retrieved, the recorded data at the required location is read and demodulation and error correction are performed. become. If the out-of-synchronization state continues for several frames, it becomes impossible to identify even if a frame slip has occurred. Even after returning from such a state and the synchronization signal can be read, it is necessary to read the synchronization signal of more than one frame in order to specify the position of the frame, which may increase data errors There was sex.

  On the other hand, in order to use the detection result of the synchronization signal as described above to generate the lost pointer at the time of the lost error correction, there are the following problems.

  The first problem is that since a circuit block for detecting the synchronization signal and a circuit block for performing error correction using the detection result are different, the detection result of the synchronization signal is synchronized with the demodulated demodulated data. The point is that it must be sent to a circuit block for error correction.

  The second problem is that since the timing at which the detection result of the synchronization signal is generated is different from the timing at which the error correction is performed, the detection result of the synchronization signal must be stored until the error correction is performed. It is. In detecting the synchronization signal, a detection operation is performed before execution of the demodulation operation in order to obtain frame synchronization before demodulating the reproduction signal. On the other hand, the error correction is often performed after the demodulated data is once stored in a memory such as a DRAM and all the frames constituting the error correction code are stored. Therefore, the timing at which the detection result of the synchronization signal is generated is different from the timing at which the error correction is performed, and it becomes necessary to store the detection result of the synchronization signal until the error correction is performed.

  Therefore, a first object of the present invention is to secure stable reproduction performance even when the quality of a reproduction signal is deteriorated due to a defect of a recording medium or the like, and to reduce data loss due to loss of synchronization.

  A second object of the present invention is to make it possible to use demodulated data and a corresponding synchronous detection result at the time of error correction.

A method for reproducing a recording medium according to the present invention is a method for reproducing a recording medium in which data is recorded in units of blocks having a plurality of frames of a predetermined length and positional information of the blocks is recorded,
Obtaining the data and the position information of the block from the recording medium;
Estimating a recording position for each frame in the block from the acquired position information of the block,
Obtaining synchronization on a frame basis from the acquired data;
Determining the storage location in the memory of the data obtained based on the predicted recording position,
Storing the acquired data in the determined storage location of the memory.

A step of determining whether or not the data is synchronized in the frame unit;
Detecting that the synchronization in the frame unit is restored again when the synchronization in the frame unit is not obtained,
When it is detected that the synchronization in the frame unit has been restored, the storage location of the data in the memory is determined based on the predicted recording position of the frame.

Further, the reproduction control circuit for a recording medium according to the present invention is a reproduction control circuit for a recording medium in which data is recorded in units of blocks each having a plurality of frames of a predetermined length and position information of the blocks is recorded. hand,
Signal reading means for obtaining the data and the position information of the block from the recording medium,
Recording position prediction means for predicting a recording position in frame units in the block from the acquired position information of the block,
Synchronization means for obtaining synchronization on a frame basis from the acquired data;
A memory for storing the data;
And control means for determining a storage location of the data in the memory based on the predicted recording position.

It is to be noted that the synchronization detecting means for detecting whether or not the synchronization of the data in the frame unit is obtained, and detecting that the synchronization in the frame unit is restored again when the synchronization in the frame unit is not obtained. Further preferably,
The control unit stores the acquired data in the memory based on the recording position predicted by the recording position prediction unit when the synchronization detection unit detects that the synchronization in frame units has been restored. Determine the location.

  Further, a playback device according to the present invention includes the playback control circuit.

In the method for reproducing a recording medium according to the present invention, encoded data obtained by performing error correction encoding on data is divided into a plurality of frame data having a predetermined length, and modulated frame data is added to the beginning of the modulated frame data. A reproduction method for reproducing the data from a recording medium on which a predetermined synchronization signal is recorded,
A signal acquisition step of acquiring a signal from the recording medium,
A synchronization signal detection step of obtaining a synchronization signal detection result by detecting a synchronization signal of each of the frames from the acquired signal;
A frame synchronization step of correcting synchronization of the frame based on the obtained synchronization signal detection result;
A synchronization signal detection result information generating step of generating synchronization signal detection result information obtained by coding each of the synchronization signal detection results according to a predetermined rule,
Demodulating the modulated frame data of each frame to generate demodulated frame data,
A synchronization signal detection result adding step of adding the synchronization signal detection result information of the frame in association with each of the demodulated frame data.

For each of the demodulated frame data, a lost pointer generating step of generating a lost pointer for erasure correction using the corresponding synchronization signal detection result information,
It is preferable that the method further includes the step of performing erasure correction of an error correction code composed of the plurality of demodulated frame data using the erasure pointer corresponding to the demodulated frame data.

  Further, the method may further include a memory storing step of storing the synchronization signal detection result information and the corresponding demodulated frame data in different areas of a memory in association with each other.

  Further, the synchronization signal detection result information is obtained from “normal detection” when the synchronization signal is normally detected, “undetected” not detecting the synchronization signal, and the timing of the detection result of the synchronization signal detected immediately before. At least three types of detection results of "out-of-synchronization detection" when a new synchronization signal is detected at a timing that deviates from the predicted timing may be coded so as to be distinguished.

Further, in the frame synchronization step, the synchronization delay in which a new synchronization signal is detected earlier than the timing predicted from the timing of the detection result of the synchronization signal detected immediately before is corrected, and the synchronization delay is If less than one frame,
In the memory storing step, the frame data immediately after the synchronization delay correction may be stored in the memory after correcting the storage position in the memory to a position skipped by the amount equivalent to the synchronization delay correction.

Further, in the frame synchronization step, the synchronization delay in which a new synchronization signal is detected earlier than the timing predicted from the timing of the detection result of the synchronization signal detected immediately before is corrected, and the synchronization delay is 1 If the synchronization delay is longer than a frame,
The memory storage step corrects the synchronization signal detection result information and the frame data immediately after the synchronization delay correction, and corrects the storage position in the memory to a position skipped by the amount corresponding to the synchronization delay correction, and stores the same in the memory. To store,
In the lost pointer generation step, the lost pointer may be generated by regarding the synchronization signal detection result information that has been skipped and not stored in the memory as being undetected.

The reproduction control circuit for a recording medium according to the present invention is configured such that encoded data obtained by performing error correction encoding on data is divided into a plurality of frame data of a predetermined length, and modulated frame data is added to the head of the modulated frame data. A reproduction control circuit for reproducing the data from a recording medium on which the predetermined synchronization signal is recorded,
Frame synchronization means for correcting the synchronization of the frame, based on a synchronization signal detection result obtained by detecting the synchronization signal of each frame from the reproduction signal obtained from the recording medium,
Synchronization signal detection result information generating means for generating synchronization signal detection result information obtained by coding each of the synchronization signal detection results according to a predetermined rule,
Demodulation means for demodulating the modulated frame data of each frame to generate demodulated frame data,
Synchronization signal detection result adding means for adding the synchronization signal detection result information of the frame to the head of each demodulated frame data,
A memory for storing the synchronization signal detection result information and the respective demodulated frame data,
And a memory storage unit for storing the synchronization signal detection result information and the respective demodulated frame data in the memory.

Furthermore, an erasure pointer generating means for generating an erasure pointer for erasure correction using the synchronization signal detection result information, Means,
It is preferable to further include

  The synchronization signal detection result information includes “normal detection” when the synchronization signal is normally detected, “undetected” when the synchronization signal is not detected, and the timing of the detection result of the synchronization signal detected immediately before. At least three types of detection results, "out-of-synchronization detection" when a new synchronization signal is detected at a timing that deviates from the predicted timing, may be encoded.

Further, in the case where the frame synchronization means corrects a synchronization delay in which a new synchronization signal is detected earlier than the timing predicted from the synchronization signal detected immediately before, and the synchronization delay is less than one frame. Is
The memory storage unit may correct the storage position of the frame data in the memory immediately after the synchronization delay correction to a position skipped by the amount equivalent to the synchronization delay correction, and store the frame data in the memory. Good.

Further, the frame synchronization means corrects a synchronization delay at which a new synchronization signal is detected earlier than the timing predicted from the synchronization signal detected immediately before, and the synchronization delay is one frame or more. In Case of,
The memory storage means corrects the storage position of the synchronization signal detection result information and the frame data in the memory immediately after the synchronization delay correction to a storage position skipped by an amount equivalent to the correction of the synchronization delay, and corrects the frame data. Is stored in the memory,
The lost pointer generating means may generate the lost pointer by regarding the synchronization signal detection result information corresponding to the frame that has been skipped and not stored in the memory as “not detected”.

  Further, a playback device for a recording medium according to the present invention includes the playback control circuit.

  As described above in detail in the embodiments, the reproduction method, the reproduction control circuit, and the reproduction apparatus of the present invention include a unit for predicting the position of the recording data from the position information recorded in advance. Synchronization can be kept more stable. Even if the quality of the recording data temporarily deteriorates due to scratches, dust, etc., it is possible to quickly resynchronize the frames. In addition, since the reproduction method and the reproduction apparatus of the present invention store the demodulated data in the buffer memory on a frame basis, it is possible to quickly correct the data storage position after restoration from the loss of synchronization. . Therefore, even if the quality of the recorded data is deteriorated due to scratches, dust, repetitive recording, etc. of the recording medium, it is possible to minimize the loss of demodulated data and maximize the effect of the error correction code. Become. Therefore, the reproducing apparatus and the reproducing method of the present invention exert a very large effect when applied to, for example, a large-capacity video disk recorder.

  Further, according to the present invention, for reproduction of recorded data recorded in a frame structure, synchronization signal detection result information of a synchronization signal at the head of each frame is sent to an error correction circuit block together with demodulated frame data, and this is transmitted to a memory. It is stored and stored in different areas, and it is possible to perform erasure correction using a detection result of a synchronization signal transmitted at the time of performing error correction. As a result, it is possible to improve the error correction capability and realize highly reliable data reproduction.

  An embodiment of the present invention will be described below with reference to the drawings, taking an optical disk medium as an example of a recording medium according to the present invention.

(Embodiment 1)
A method for reproducing a recording medium, a reproduction control circuit, and a reproducing apparatus according to Embodiment 1 of the present invention will be described below. FIG. 1 is a schematic diagram of an optical disk medium 11. As shown in FIG. 1, guide grooves (hereinafter referred to as grooves) are formed in a spiral shape on the recording surface of the optical disc medium 11. The information track 12 is constituted by the groove. The recording data is recorded in the information track 12 in units of a recording block 13 composed of a plurality of frames of a predetermined length. In the information track 12, the position information of the recording block 13 is recorded in advance by a change in the shape of a groove such as a wobbled groove. Although not shown, a phase change recording film is formed on the recording surface of the recording medium 11, and the recording device narrows the beam spot of the laser beam and irradiates the recording film with the laser beam to locally increase the temperature. As a result, a phase change between crystalline and amorphous occurs, and information can be recorded.

  The position information includes information for specifying the position of the recording block 13 which is a unit for recording data. In the apparatus for reproducing the optical disk medium, the information block 12 is reproduced and the position information is read, whereby the recording block 13 is read. Can be specified.

  Further, the recording data is recorded on a groove formed in advance with the recording block 13 as a unit. The recording block 13 is composed of a plurality of frames 14 of a predetermined length, and a synchronization signal 15 is arranged at the head of each frame 14.

  FIG. 8 shows an example of a recording data structure of one sector after modulation. One sector is composed of 26 consecutive frames, and the number of data bytes per frame is 91 bytes, and the total number of bytes is 2366 bytes. This includes redundant data such as a data ID and a parity byte of an error correction code in addition to 2048 bytes of user data. By the modulation, the binary 8 bits are converted into 16 channel bits, and as a result, the 91-byte binary data becomes a modulation code sequence of 1456 channel bits. Furthermore, a synchronization signal having a 32-channel bit length is added to the head, and becomes recording data of one frame. That is, one frame has a length of 1488 channel bits.

  As shown in FIG. 8, the synchronization signal is divided into eight types according to the position of each frame in the sector. A specific pattern consisting of a mark / space of (14T + 4T) and a pattern immediately before the specific pattern are respectively assigned for type identification. The synchronizing signal of the first frame corresponding to the first in each sector is called SY0, the synchronizing signal of the second frame is SY5, and the third to 26th frames are based on their order and whether they are odd or even. Separate patterns from SY1 to SY7 are arranged. Thus, for example, when the synchronization signals of three consecutive frames are read as {SY5, SY1, SY5}, the synchronization signals of three consecutive frames are {SY5, SY1, SY6} after the lapse of the fourth frame from the head of the sector. In the case of reading, it can be identified that it is after 12 frames from the head of the sector.

  FIG. 9 shows an example of a method for recording position information. The groove, which is a guide groove formed in advance, is meandered (wobbled) at a predetermined spatial frequency (here, 186 channel bit period), and a predetermined period unit (here, land) is provided between the grooves 41. Position information is recorded depending on whether or not pits are arranged every eight wobbles (ie, one frame). The pits recorded on this land are called land pre-pits 43. Position information recorded in advance using the land pre-pits 43 is called a pre-pit address. As shown in FIG. 1 as the information track 12 and the recording block 13, the correspondence between the pre-pit address and the recording block 13 is defined in advance. That the correspondence is defined in advance means that a predetermined number of pre-pit addresses and the recording blocks 13 correspond one-to-one while maintaining a predetermined relative positional relationship. In the case of this example, two pre-pit addresses are included in one recording block 13, which is a unit in which data is recorded, and each pre-pit address and each recording block are a set of two consecutive bits. It corresponds to one to one.

  Next, a brief description will be given of a positional relationship between positional information previously formed by land pre-pits and data to be phase-change recorded. In the recording apparatus, when recording data, the beginning of the information unit of the land pre-pit and the recording position of the synchronization signal, which is the beginning of the frame of the recording data, are made to substantially match, or a predetermined relative positional relationship is maintained. To By doing so, the data recording position can be predicted by reading the position information even when the data is reproduced in the reproducing device.

  Hereinafter, a method of predicting a data recording position while reading position information will be specifically described. As described above, the interval at which a meaningful value is obtained as position information, that is, the interval at which the pre-pit address is updated, is only twice per ECC block (recording block). Therefore, it is not possible to predict a data recording position in a fine unit such as a sector unit or a frame unit only by reading the position information.

  Therefore, a prediction counter is used to precisely predict the data recording position. The prediction counter includes a counter FLCNT for measuring one frame length, a counter FRCNT for counting the number of frames, and a counter SCNT for counting the number of sectors. In order to reduce the error of the prediction counter, it is preferable that the counter FLCNT that measures at least one frame length uses a channel clock extracted from the wobble.

  The counter FLCNT is a loop counter that increments from 0 to 1931 with 11 bits and returns to 0. The counter FRCNT is a loop counter that increments from 0 to 25 with 5 bits and returns to 0. The counter SCNT is a loop counter that increments from 0 to 15 with 4 bits and returns to 0. Further, each counter can preset each count value at the timing when the position information of the land pre-pit is read. This makes it possible to match the count value corresponding to the predicted position of the recording data at the time when the position information of the land pre-pit has been read, while taking into account the processing delay of the reading circuit. The predicted position of the recording data in this example refers to a relative position starting from the beginning of one ECC block expressed as {sector number / frame number / channel bit number}.

  As described above, once the prediction counter is preset in accordance with the reading of the position information, the recording data position can be predicted by the loop counting operation of each counter. The prediction of the recording data position can be accurately performed as long as the tracking of the light beam is not lost or the phase synchronization between the channel clock extracted from the wobble and the wobble is not completely lost.

  Next, an advantage of predicting a recording data position from position information recorded in advance by a groove shape will be described. The period of the wobble groove, which is the carrier of the positional information, is generally at least about 10 times the average T (average mark space length) of the modulation code sequence and at least twice the maximum T (longest mark space length). . This is to prevent the recorded data and the wobble from interfering in frequency and deteriorating the quality of the reproduced signal. As described above, since the frequency of the wobble is lower than the frequency band of the recording data, the amount of information lost when the recording surface of the medium is damaged is smaller for the wobble than for the recording data. Therefore, it can be said that the PLL that performs the phase comparison at the edge of the wobble is more resistant to defects, scratches, dust, and the like of the medium than the PLL that performs the phase comparison at the edge of the recording data. In other words, it can be said that the clock signal obtained from the wobble signal is much more stable than the clock signal obtained from the recording data.

  FIG. 2 is a block diagram showing a configuration of the playback device according to the first embodiment. The operation of the playback device will be described. First, the signal reading means 21 irradiates the recording medium 11 with a light beam and reads a signal from the reflected light. In order to read the wobble and land pre-pit signals, a signal RF1 is obtained by reproducing a signal in the tracking direction based on a known push-pull method. Further, in order to read recorded data, a signal RF2 reproduced by using a change in reflectance as a signal is obtained.

  The signal RF1 is sent to the position information reproducing means 22, where a wobble signal component is extracted and a channel clock is obtained using a technique such as a phase locked loop (PLL). Further, the position information reproducing means 22 extracts the signal component of the land pre-pit from RF1, reproduces the position information from the land pre-pit signal, and decodes it. After a phase-locked channel clock is obtained from a built-in wobble signal PLL (not shown) and the position information is correctly decoded from the land pre-pit signal, a prediction counter (not shown) starts operating to predict the recording data. Outputs a count value representing the position. As the count value, it is preferable to always output the sector count result SP, the frame count result FP, and the channel count result CP.

  On the other hand, the signal RF2 is sent to the synchronization means 23, and the signal component of the recording data is extracted to obtain a channel clock and channel data by using a technique such as a phase locked loop (PLL). Further, a specific pattern (14T + 4T) in the synchronization signal is detected from the channel data, and a synchronization signal (synchronization signal) SY is output. The synchronization signal SY may be output after being detected for several consecutive frames as necessary, taking into account the reliability of detection of the specific pattern. Further, it is preferable that the synchronization unit 23 incorporates a unit for measuring a detection interval of the synchronization signal, a unit for generating a detection prediction window of the synchronization signal, and the like as necessary. Thus, it is possible to prevent the pseudo synchronizing signal SY from being output at an erroneous detection interval, and to interpolate and output the synchronizing signal SY internally from the previous detection result when the synchronizing signal is not detected.

  As an interpolation output method of the synchronization signal SY when the synchronization signal is not detected, an interpolation method based on a synchronization clock of the reproduction PLL can be considered. For example, a counter is provided which counts the number of channel clocks (1488 channel bits in this example) corresponding to one frame length starting from the time of detection of the synchronization signal detected immediately before, and interpolating output using the output of the counter. It can be performed. The counter can be used as a means for measuring the detection interval of the synchronization signal and a means for generating a detection prediction window.

  Further, the synchronization means 23 identifies not only the specific pattern in the synchronization signal but also the type, and outputs a sync type detection signal SYID. For example, in the case of the recording data format shown in FIG. 8, since there are eight types of synchronization signals, SY0 to SY7, any one of SYID = 0 to 7 is output according to the detection of SY0 to SY7, and the synchronization signal is output. When a reproduction error occurs in the signal and the type cannot be identified, SYID = 8.

  Further, the synchronization means 23 outputs a synchronization state signal LOCK according to the detection state of the frame synchronization. For example, when the frame synchronization is normal, the synchronization state signal LOCK = 1 is set. When the frame synchronization is abnormal, that is, when the frame is out of frame synchronization, LOCK = 0 is set. More specifically, when the synchronization signal is not detected continuously for a predetermined number of frames, LOCK = 0 is notified to indicate that the synchronization is lost.

  The synchronization signal SY is sent to the demodulation means 24, and is used as a timing for starting demodulation from channel data to binary data. As a result of the demodulation, the demodulation means 24 sends the demodulated data DEMDT and the data strobe signal DTEN to the memory control means 25. The data strobe signal DTEN is used as an update timing of the demodulated data DEMDT.

  The memory control means 25 plays a role in correctly storing the demodulated data DEMDT in the buffer memory 26. The synchronization signal 23 is sent from the synchronization means 23 to the memory control means 25, the sync type detection signal SYID, and the synchronization state signal LOCK are sent to the memory control means 25, and the recording data prediction positions SP and FP are sent from the position information reproduction means 22. The storage position of the demodulated data DEMDT is controlled using these signals.

  The buffer memory 26 can specify the data storage location (byte position for writing or reading) by the memory address MADR, and the memory control means 25 controls the memory address MADR of the buffer memory 26 to obtain the demodulated data DEMDT. Control the storage location of

  FIG. 3 is a block diagram showing an example of the internal configuration of the memory control means 25. The frame number identification means 31 is means for identifying the frame number from the head of the sector using the synchronization signal SY and the sync type detection signal SYID from the synchronization means 23. Specifically, the sync type detection signal SYID is taken in at the timing of the synchronization signal SY, and the frame number FRNUM specified based on the sync type SYID over the past several frames is output. For example, according to the recording data format shown in FIG. 8, when the sync type detection signals SYID of the past three frames are {SY5, SY1, SY5}, FRNUM = 3, {SY5, SY1, SY6}. In such a case, FRNUM = 0 to 25 may be set in accordance with the number of frames from the head of the sector, such as FRNUM = 11. If the sync type detection signal SYID = 8 (unknown type) or does not apply to any of the predetermined combinations, FRNUM = 26 (frame number unknown) may be set.

  The byte number counter 32 is a counter that counts the number of bytes for each frame, and clears the count value BC = 0 with the synchronization signal SY from the synchronization means 23, and every time the data strobe signal DTEN = 1 from the demodulation means 24. When the count value BC is incremented by one and reaches BC = 91, the count operation is held until BC = 0 is cleared by the next synchronization signal SY.

  The frame number counter 33 is a counter for counting the number of frames in one sector. When the head of the sector is detected by the frame number FRNUM = 0 from the frame number identification means 31, the count value is cleared as FC = 0, The count value FC is incremented by one with the synchronization signal SY from the synchronization means 23, and when FC = 25, FC = 0 is cleared by the next synchronization signal SY. In addition, the count value can be corrected to a predetermined value based on the control of the frame slip detection unit 35. The count value FC is counted by a clock based on the synchronization signal SY detected immediately before, and FC is incremented by detecting the next synchronization signal SY. On the other hand, even when the next synchronizing signal SY is not detected, the count is continued with the original clock and FC is incremented.

  The sector number counter 34 is a counter for counting the number of sectors in one ECC block. The sector number counter SC is cleared to 0 at the head of the ECC block, and the frame number counter 33 returns the count value FC from 25 to 0. At the same time, the count value SC is incremented by one, and when SC = 15 and FC = 25, SC = 0 is cleared by the next synchronization signal SY. In addition, the count value can be corrected to a predetermined value based on the control of the frame slip detection unit 35. The count value SC is counted by a clock based on the synchronization signal SY detected immediately before, and the SC is incremented by detecting a predetermined number of synchronization signals SY. On the other hand, even when the synchronization signal SY is not detected, the counting is continued by the original clock, and the SC is incremented at a predetermined time.

  The frame slip detecting means 35 detects the return from the out-of-synchronization by seeing the change of the synchronization state signal LOCK, and also detects the predicted recording data positions SP, FP, the sector count SC, and the frame count FC. By comparison, the presence or absence of a frame slip is detected.

  Even when a synchronization signal is not detected, the synchronization signal SY is interpolated and output based on the channel clock synchronized with the reproduction PLL as described above, so that the byte number counter 32, the frame number counter 33, and the sector number counter are The operation is as described above regardless of whether the synchronization signal is detected or not.

  The address conversion means 36 converts the data into a memory address MADR designating a storage location of the buffer memory 26 using the byte count value BC, the frame count value FC, the sector count count SC, and the like, and outputs the converted address.

  The FIFO 37 is a first-in first-out (FirstInFirstOut) memory that holds and outputs the demodulated data DEMDT for a predetermined time. The address conversion means 36 delays the demodulated data DEMDT by a predetermined time in consideration of the processing delay required until the output of the memory address MADR, and then outputs the data as memory storage data DATA. By doing so, the memory address MADR and the memory storage data DATA are output to the buffer memory 26 at the same time, and the demodulated data can be stored in the correct storage location.

  FIG. 4 shows an example of a storage map of the buffer memory 26 according to the present embodiment. One horizontal line is the number of bytes that can store the amount of data recorded in one frame, and is expressed as m bytes in the figure. The vertical is the number of rows corresponding to the number of frames of one ECC block, and is expressed as n frames in the figure. In the case of the recording data format described with reference to FIG. 8, it is sufficient that m = 91 and n = 416. By managing the buffer memory 26 with the storage map as described above, it is possible to store data of one ECC block in a frame unit in the demodulated order.

  Normally, when the demodulated data in the target ECC block is to be stored in the buffer memory 26, the target ECC block is searched by decoding the data ID in the recording data, and is sequentially stored in the buffer memory 26 from the beginning. Store. The head of the ECC block is found from the type identification result of the synchronization signal and the decoding result of the data ID, and the storage of the head of the demodulated data of each frame is controlled by the synchronization signal SY.

  Now, consider the case where the quality of the reproduced signal of the recorded data is temporarily degraded, and the detection of the synchronization signal and the decoding of the data ID cannot be performed over several frames or one sector. In such a case, there is a possibility that the reproduction PLL built in the synchronization means 23 is out of synchronization. Since the recording data includes signals of different mark / space lengths in the modulation code sequence, if the synchronization signal cannot be detected continuously, it cannot be easily determined whether or not the PLL itself has lost synchronization.

  On the other hand, as described above, the period of the wobble signal obtained from RF1 is sufficiently longer than the period of the recording signal obtained from RF2, so that the wobble signal PLL built in the position information reproducing means 22 has a smaller damage to the medium than the reproduced PLL. It is stable against signal degradation due to dust and dust. Therefore, it is unlikely that the synchronization is lost even in the above case. If the wobble signal itself is obtained as a signal close to a single cycle having a predetermined frequency as a carrier even if the out-of-synchronization occurs, it is determined whether the wobble signal PLL is out-of-synchronism with the wobble signal. The determination can be easily made only by comparing the phases of the PLL clocks.

  Therefore, even if the detection of the synchronization signal is disabled due to the deterioration of the quality of the recording data, as long as the wobble signal PLL, which is more stable than the reproduction PLL, is phase locked, the reproducing apparatus can determine the number of frames in the ECC block. Whether the eyes are to be demodulated can be determined by the predicted position of the recorded data by the position information reproducing means 22.

For example, when the demodulated data in a certain ECC block is to be stored in the buffer memory 26, as described above, the position information reproducing unit 22 sets the predicted recording data position to the predicted sector position SP _x (SP _x is 0 or more and 15 or less). ), And the frame prediction position FP _x (FP _x is an integer of 0 or more and 25 or less), the _nxth line ( _nx is 0 or more, 415) of the storage location of the buffer memory where the data is to be stored Integer below)
n _x = SP _x × FP _x
Can be sought.

  As described above, by using the position information reproduction result and the synchronous clock of the wobble signal PLL, it is possible to always predict the position of the recording data in the ECC block in real time. Further, by using the predicted position of the recording data, the storage position of the demodulated data in the buffer memory can be controlled in frame units. Therefore, even if the synchronization signal in the recording data is continuously undetected, the demodulated data can be appropriately stored in the buffer memory.

  Next, a specific description will be given of the buffer memory storage control when a frame is lost due to the deterioration of the quality of recording data.

  First, an example is given in which the reproduction PLL loses synchronization in the direction of decreasing the frequency, the non-detection state of the seven-frame synchronization signal continues in time, and as a result, one frame slip (loss) occurs.

  FIG. 5 shows a timing chart of one frame missing. When the reproduction PLL goes out of synchronization, pattern detection is not performed at the point where the synchronization signal should be originally detected as shown in the figure, and the interpolation function based on the synchronization clock of the PLL operates to interpolate in a time-slower direction. A synchronization signal SY is output. At this time, the sync type detection signal SYID = 8 (type unknown) and the frame number FRNUM = 26 (frame number unknown).

  In the example shown in the figure, when the synchronization state signal LOCK = 1 (normal synchronization state), when the undetected state of the synchronization signal continues for four or more frames, it is determined that loss of synchronization has occurred, and LOCK = 0 (out of synchronization state). I have. Further, when the synchronization state signal LOCK = 0 (out of synchronization state), LOCK = 1 (normal synchronization state) when the synchronization signal is detected for two consecutive frames.

  Further, when the synchronization status signal LOCK changes from 0 to 1 (that is, when the synchronization status signal LOCK returns from the out-of-synchronization), the recording position prediction signals SP and FP are compared with the sector number count value SC and the frame number count value FC. If (SP = SC and FP = FC) are not satisfied, it is considered that a frame slip has occurred, and the storage position of the frame data in the buffer memory 26 is moved in frame units.

  More specifically, in the case of this example, when LOCK = 0 changes to 1, SP = 2, FP = 5, SC = 2, FC = 4, and the value of the frame number count value FC is The value is smaller than the recording position prediction signal FP by one, and it can be determined that one frame is lost during the period of the loss of synchronization. Therefore, the frame number count value FC is corrected from the current 4 to 5. As a result, the output memory address MADR of the address conversion means 36 can be automatically changed to indicate the correct storage location. Therefore, data can be recorded at the correct storage location in the memory immediately after recovery from the loss of synchronization.

  In the present example, the recording position prediction signal and the count value indicating the storage position of the buffer memory are compared in units of frames, but may be compared in units of bytes more finely. However, since the relative relationship between the two slightly fluctuates due to the fluctuation of the recording position in the recording device and the PLL jitter in the reproducing device, the unit of comparison should not be an error as a unit of comparison in consideration of the amount of fluctuation in advance. It is desirable to do.

  Next, an example is described in which the reproduction PLL loses synchronization in the direction in which the frequency increases, and the non-detection state of the 10-frame synchronization signal continues over time, resulting in a 2-frame slip (erroneous insertion).

  FIG. 6 shows a timing chart of inserting two frames. As shown in the figure, when the reproduction PLL loses synchronization, pattern detection is not performed at the time when a synchronization signal should be originally detected, and an interpolation function based on a synchronization clock of the PLL operates to increase in time. An interpolation synchronization signal SY is output.

  Also in this example, the transition condition of the synchronization state signal LOCK is the same as the example of FIG. At the time when the synchronization status signal LOCK = 0, which is the time of recovery from the loss of synchronization, changes from 0 to 1, the recording position prediction signal is SP = 3, FP = 7, the sector count SC = 3, the frame count at this time Since FC = 9, it can be determined that erroneous data was inserted during the period of out-of-synchronization, and two extra frames were stored in the buffer memory. Therefore, the frame number count value FC is corrected from 9 at present to 7. As a result, the output memory address MADR of the address conversion means 36 can be automatically changed to indicate the correct storage location. Therefore, data can be recorded at the correct storage location in the memory immediately after recovery from the loss of synchronization.

  FIG. 7 is a flowchart showing the flow of the processing shown in the timing charts with reference to FIGS. 5 and 6 from the viewpoint of the storage control of the buffer memory by the memory control unit 25. Hereinafter, the flowchart of FIG. 7 will be described.

(A) The data reproduction process of the target ECC block is started. First, a synchronization state signal LOCK indicating presence / absence of loss of synchronization is set normally (LOCK = 1).
(B) Obtain data and block position information (S01).
(C) It is determined whether or not the synchronization signal SY has been detected (S02). If the synchronization signal SY is not detected, the process returns to step S01 for acquiring data for the next frame. When the synchronization signal SY is not detected, it is determined that the state is out of synchronization, and LOCK = 0 is set. In this case, the synchronization signal SY is interpolated and output based on the synchronization signal detected immediately before as described above. On the other hand, when the synchronization signal SY is detected, it is determined that the state is the normal synchronization, and LOCK = 1 is set.

(D) The sector number counter SP for predicting the recording position of each sector in the block from the position information and the frame number counter FP for predicting the recording position of each frame in the sector are updated. Further, the sector number counter SC and the frame number counter FC are updated based on the detected or interpolated synchronization signal SY (S03).

(E) It is determined whether or not frame synchronization has been restored, that is, whether or not there has been a change from the synchronization state signal LOCK = 0 to 1 (S04). Therefore, when there is a change from the out-of-synchronization state (LOCK = 0) to the normal synchronization state (LOCK = 1), the process branches to YES as the synchronization recovery. On the other hand, if the normal synchronization is maintained (LOCK = 1), the process branches to NO.
(F) The recording position prediction signals SP and FP are compared with the sector number count value SC and the frame number count value FC (S05). If they match, it is determined that no frame slip has occurred, and the flow branches to YES.
(G) On the other hand, if there is a mismatch between the two, it is considered that a frame slip has occurred, and the value of the sector position prediction signal SP is substituted for the sector count value SC. Further, the value of the frame position prediction signal FP is substituted for the frame number count value FC (S06).
(H) Data is recorded in the storage location of the memory corresponding to the SC value and the FC value (S07).

(I) Thereafter, an end determination is made (S08), and if it is to be continued, the process proceeds to a data and position information acquisition step (S01). If it is to be terminated, a termination process is performed thereafter.

  By performing the processing according to the flow described in the above flowchart, in the case of occurrence of a frame slip, the storage position of the buffer memory can be promptly corrected at the time of returning from the frame slip.

  In particular, by predicting the recording position using information from a system (wobble groove and land pre-pit) different from the information read from the recording data and performing frame slip determination and correction processing, only the information read from the recording data is obtained. It is possible to perform the recording position correction process faster and more reliably as compared with the method performed in the above. Further, since the storage unit of the buffer memory can be corrected on a frame basis, it is possible to minimize the data loss due to the frame slip without complicating the management of the buffer memory.

  As described above, with the method and apparatus described in the present embodiment, it is possible to always predict the position of recording data from wobble groups and land pre-pits that are formed in a groove shape in advance. If a frame slip occurs due to the loss of synchronization, it is possible to determine whether the frame slip has occurred by comparing the predicted position of the recording data and the storage position of the demodulated data in the buffer memory at the time of recovery from the loss of synchronization. In addition, when the storage location of the buffer memory is shifted due to the occurrence of a frame slip, it is possible to control the subsequent demodulated data to be stored in the correct location by using the predicted position of the recording data. It has been shown.

  In the present embodiment, the detection of frame slip and the correction of the storage location in the buffer memory are all performed by the recording position prediction signal. However, the detection is performed based on the data ID of the recording data and the synchronization signal type (alignment coincidence). The method can be used in combination. For example, before and after the occurrence of a frame slip, the wobble signal PLL is also out of synchronization, or in a situation where the quality of the land pre-pits is poor and it is difficult to predict the recording data position, the data ID of the recording data and the type of the synchronization signal Is effective.

  Further, in the present embodiment, the optical disk medium has been described as an example of the recording medium, but the present invention is not limited to this. Like the wobble groove and the land pre-pit shown in the present embodiment, there is a separate channel from the channel on which user data is recorded on one recording medium, and both channels are read almost simultaneously by the reproducing apparatus. It is possible to predict the information storage position of the user data recording channel based on the read information from the separate channel because the information from the separate channel and the recording position of the user data are associated with each other. Reached. Furthermore, it is even better if the separate channel is more robust than the user data recording channel (if the medium has an error resistance to defects, scratches and dust).

  Further, in the present embodiment, the storage map of the buffer memory is a simple frame unit, but is not limited to this. Actually, the arrangement may be appropriate for the encoding / decoding processing in the device according to the configuration of the error correction code (product code, interleave method, etc.). For example, the efficiency of the correction process can be improved by setting the memory byte space and the parity byte equivalent area of the error correction code to be separate areas. In addition, the processing can be speeded up by deinterleaving at the same time as storing the demodulated data in the buffer memory. In any case, this can be dealt with by changing the internal configuration of the memory address conversion means applied to the buffer memory, and such differences regarding the details of the storage map of the buffer memory do not directly affect the essence of the present invention. .

(Embodiment 2)
A reproducing method according to Embodiment 2 of the present invention will be described below. FIGS. 10A to 10C are schematic diagrams showing the structure of frame data according to the second embodiment. FIG. 10A shows the configuration of an error correction code of a sector. Each error correction code 101 has a parity 102 of 16 bytes added to data 102 of 128 bytes. Further, a sector is composed of eight error correction codes 101. The coding direction of each error correction code 101 is coded in the column direction, and by recording this in the row direction, interleaving is performed to improve the correction capability for burst errors.

  Each error correction code 101 is encoded by a known Reed-Solomon code, and has an error correction capability of up to 8 bytes by a 16-byte parity 103. Further, by performing erasure correction, error correction of up to 16 bytes can be performed. A sector of 1 Kbyte is formed by the eight error correction codes 101, and recording or reproduction is performed with one sector as a minimum unit.

  FIG. 10B shows the structure of frame data obtained by dividing the above error correction code for each row. The eight error correction codes 101 constituting the sector are interleaved and One frame is divided into frame data 104 composed of 8 bytes.

  FIG. 10C shows a frame structure. Each frame data 104 is modulated to become modulated frame data 105. Further, a synchronization signal 106 is added to the head of each modulated frame data 105. Here, the modulation method is an example of (8, 16) modulation used in DVDs and the like, in which 8 bits are converted into 16 bits, and the frame data 104 of 8 bytes is modulated by 8 × 16 = 128 bits. It is converted into frame data 105. The synchronization signal 106 is composed of a predetermined specific pattern that does not appear in (8, 16) modulation and a frame number, and has a 32-bit length. One frame is composed of 32 + 128 = 160 bits, and one sector is composed of a total of 144 frames. Note that the configuration of the synchronization signal is not necessarily the above-described configuration.For example, by using a plurality of specific patterns, changing the synchronization signal of each frame, and detecting the arrangement of the specific pattern of the synchronization signal of the plurality of frames, A configuration for specifying a frame number may be used.

  Optical discs generally use the above-described frame structure. When bit slips or the like occur due to scratches or defects in the medium, the synchronization signal at the beginning of each frame is detected and resynchronization is performed. Is performed to perform synchronization correction.

  FIG. 11 is a schematic diagram showing the configuration of the optical disk, and shows a state in which the sectors shown in FIG. In FIG. 11, a sector 202, which is the minimum unit of recording and reproduction, is divided into 144 frames and recorded on the optical disk 201. Each frame is composed of a 32-bit synchronization signal 204 and a 128-bit modulated frame data 203. Be composed.

  FIG. 12 is a flowchart illustrating a reproducing method according to the second embodiment, in which the optical disk shown in FIGS. 10 and 11 is reproduced. Hereinafter, this flowchart will be described.

(A) First, frame synchronization is performed for each frame by detecting a synchronization signal from a reproduction signal from a disk. This step is a frame synchronization step 301. Since the synchronization signal is recorded in a predetermined pattern, the detection of the synchronization signal is performed by detecting the coincidence with the reproduction signal. Here, the frame synchronization means that the number of each frame and the head of each frame are specified from the reproduction signal, and further the head of each modulated frame data is specified.

(B) For each modulated frame data, the synchronization signal detection result information 311 coded with respect to the synchronization signal detection result is created. This step is a synchronization signal detection result information generation step 302. As the synchronization signal detection result, three types of synchronization signal detection results of normal detection, out-of-synchronization detection, and non-detection are set. The information 311 is generated.
i) Normal detection When detecting the synchronization signal, the number of bits from the detection of the synchronization signal of the previous frame is also counted. Here, since one frame is 160 bits, if the synchronization signal of the next frame is detected exactly 160 bits later, an error such as loss of synchronization occurs between the previous frame and the frame. No, the synchronization signal detection result 309 is a normal detection.
ii) Out-of-synchronization detection If the out-of-synchronization is detected from the timing of 160 bits from the head of the previous frame, synchronization correction for re-establishing frame synchronization based on the newly detected synchronization signal is performed. As a result of the frame synchronization, the demodulation processing described below is performed on the 128-bit modulated frame data 308 based on the specified start position. In this case, the synchronization signal detection result 309 is an out-of-synchronization detection. The out-of-synchronization includes a synchronization delay and a synchronization advance.
iii) Undetected If no synchronization signal is detected, the current synchronization is continued, and the synchronization signal detection result 309 is not detected.

As will be described later, the synchronization signal detection result information 311 is composed of 8 bits = 1 byte, and the remaining 6 bits can be used to roughly specify the frame number. Further, the number of bits of the synchronization signal detection result information 311 and the method of encoding are not limited to the above, and a configuration in which a frame number can be completely specified by increasing the number of bits, for example, may be used.
(C) A demodulation process is performed on the 128-bit modulated frame data 308 based on the head position specified as a result of the frame synchronization. This step is a demodulation step 303, in which each modulated frame data is demodulated to generate demodulated frame data 310.
(D) The synchronization signal detection result information 311 is added to the head of each demodulated frame data demodulated and transmitted to the error correction circuit block. This step is a synchronization signal detection result adding step 304.
(E) Store the transferred demodulated frame data and synchronization signal detection result information 311 in separate areas of a memory such as a DRAM. This step is a memory storage step 305.
(F) From the respective synchronization signal detection result information 311 stored in the memory, at the time of erasure correction, an erasure pointer for specifying an error position is generated. Here, the erasure pointer is generated only from each synchronization signal detection result information 311, but may be combined with other means that can estimate the error position. This step is a lost pointer generation step 306.
(G) Perform erasure correction using the erasure pointer. This step is an error correction step 307. By performing erasure correction, it is possible to obtain a maximum of twice the correction capability.

  After that, the demodulated frame data stored in the memory can be read and reproduced. Since error correction is performed as described above, correct data can be reproduced.

  Hereinafter, each step from the frame synchronization step 301 to the memory storage step 305 will be described in detail with reference to FIGS.

(Example 1)
FIG. 13 and FIG. 14 are diagrams illustrating the first embodiment in which the synchronization signal detection result indicates a normal detection. FIG. 13A is a schematic diagram showing the data structure of a reproduced signal input to the frame synchronization step 301, and FIG. 13B is a diagram showing the transmission of the synchronization signal detection result from the addition step 304 to the memory storage step 305. FIG. 6 is a schematic diagram showing a data structure of demodulated frame data and synchronization signal detection result information.

  FIG. 13 shows an example in which the synchronization signal 402 of the (m + 1) th frame is detected at a timing of exactly 128 + 32 bits from the detection timing of the mth synchronization signal 401. That is, this is an example in which the synchronization timing of the (m + 1) th frame estimated from the detection timing of the synchronization signal 401 of the mth frame by counting the clocks and the timing of actually detecting the synchronization signal 402 match.

  In this case, the synchronization signal detection result in the frame synchronization step 301 is normal detection 00, and the lower two bits of the synchronization signal detection result information 406 of the (m + 1) th frame generated in the synchronization signal detection result information generation step 302 are 00. . The synchronization signal detection result information is composed of 1 byte = 8 bits. Although not shown, upper bits (6 bits) and lower 6 bits of the frame number are stored. For example, in the synchronization signal detection result information 406, the lower 6 bits of m + 1 are stored.

  Further, based on the frame synchronization in the frame synchronization step 301, the modulated frame data 404 is demodulated in the demodulation step 303 to generate demodulated frame data 408. Since (8, 16) modulation is used in the second embodiment, 128-bit modulated frame data is converted into 8-byte demodulated frame data.

  Each synchronization signal detection result information is added to the head of each demodulated frame data in a synchronization signal detection result adding step 304 and sent to a memory storage step 305 of the error correction circuit block. As described above, since the corresponding synchronization signal detection result information is added to each demodulated frame data, it is possible to easily associate each demodulated frame data with the synchronization signal detection result.

  FIG. 14 shows a state in which the transmission data in which each synchronization signal detection result information is added to the head of each demodulated frame data of FIG. 13 is stored in the memory. In FIG. 14, the synchronization signal detection result information and the demodulated frame data are stored in different areas of the memory. For storage in different areas, only a single memory may have different storage areas, or different memories may be used to set respective storage areas.

  In each area, synchronization signal detection result information and demodulated frame data are stored at a predetermined address according to each frame number. For example, in the synchronization signal detection result information 502 of the (m + 1) th frame, the lower 2 bits are 00 and stored at a predetermined m + 1 position. Similarly, the demodulated frame data 503 of the (m + 1) th frame is stored at a predetermined (m + 1) position. The demodulated frame data and the corresponding synchronization signal detection result information are stored in correspondence with each other.

(Example 2)
15 and 16 are diagrams illustrating a second embodiment in which the synchronization signal detection result is “not detected”. FIG. 15A is a schematic diagram showing the data structure of a reproduced signal input to the frame synchronization step 301, and FIG. FIG. 6 is a schematic diagram showing a data structure of demodulated frame data and synchronization signal detection result information to be transmitted.

  FIG. 15 shows an example in which the synchronization signal 602 of the (m + 1) th frame is not detected due to a scratch on the medium or the like. At this time, the synchronization signal detection result in the frame synchronization step 301 is not detected, and the lower two bits of the synchronization signal detection result information 606 of the (m + 1) th frame generated in the synchronization signal detection result information generation step 302 become 01. The synchronization signal detection result information is composed of 1 byte = 8 bits. Although not shown, upper bits and lower 6 bits of a frame number are stored. For example, in the synchronization signal detection result information 606, the lower 6 bits of m + 1 are stored.

  In the frame synchronization step 301, since the synchronization signal 602 has not been detected, the timing estimated from the detection timing of the synchronization signal 601 of the m-th frame by counting the clock is used as the synchronization timing. However, the reliability in this case is low.

  Next, based on the frame synchronization in the frame synchronization step 301, the modulated frame data 604 is demodulated in the demodulation step 303 to generate demodulated frame data 608. Since (8, 16) modulation is used in the second embodiment, 128-bit modulated frame data is converted into 8-byte demodulated frame data.

  Each synchronization signal detection result information is added to the beginning of each demodulated frame data in a synchronization signal detection result adding step 304 and sent to a memory storage step 305 in the error correction circuit block. As described above, since the corresponding synchronization signal detection result information is added to each demodulated frame data, it is possible to easily associate each demodulated frame data with the synchronization signal detection result. This makes it possible to easily specify demodulated frame data for which no synchronization signal detection result information has been detected.

  FIG. 16 shows a state in which the transmission data in which each synchronization signal detection result information is added to the head of each demodulated frame data of FIG. 15 is stored in the memory. In FIG. 16, the synchronization signal detection result information and the demodulated frame data are stored in different areas of the memory.

  In each area, synchronization signal detection result information and demodulated frame data are stored at a predetermined address according to each frame number. For example, in the synchronization signal detection result information 702 of the (m + 1) th frame, the lower two bits are 01 and stored at a predetermined m + 1 position. Similarly, the demodulated frame data 703 of the (m + 1) th frame is stored at a predetermined (m + 1) th position. The demodulated frame data and the corresponding synchronization signal detection result information are stored in correspondence with each other.

(Example 3)
FIGS. 17 and 18 show a case where a new synchronization signal is detected at a timing that deviates from the timing predicted from the timing of the detection result of the synchronization signal detected immediately before, and a case where the synchronization signal detection result is out-of-synchronization detection. This is a third embodiment of the present invention. In this case, synchronization correction is required. FIG. 17A is a schematic diagram showing the data structure of a reproduced signal input to the frame synchronization step 301, and FIG. 17B is a diagram showing the transmission of the synchronization signal detection result from the addition step 304 to the memory storage step 305. FIG. 6 is a schematic diagram showing a data structure of demodulated frame data and synchronization signal detection result information to be transmitted.

  In FIG. 17, the synchronization signal 802 of the (m + 1) -th frame should be originally detected at the timing of 32 + 128 bits from the detection timing of the m-th synchronization signal 801. This is an example of a case where the bit timing, that is, the synchronization delay is longer than the original timing.

  At this time, the synchronization signal detection result in the frame synchronization step 301 is a synchronization correction, and the lower two bits of the synchronization signal detection result information 806 of the (m + 1) th frame generated in the synchronization signal detection result information generation step 302 become 10.

  In the frame synchronization step 301, since the synchronization signal 802 is detected at a timing deviating from the timing predicted by the clock, the synchronization is corrected to the timing of the newly detected synchronization signal 802.

  Next, based on the frame synchronization in the frame synchronization step 301, the modulated frame data 804 is demodulated in the demodulation step 303 to generate demodulated frame data 808. Since (8, 16) modulation is used in the second embodiment, 128-bit modulated frame data is converted into 8-byte demodulated frame data. On the other hand, the demodulated frame data 807 of the frame m has 7 bits here because the number of bits is insufficient.

  Each synchronization signal detection result information is added to the head of each demodulated frame data in a synchronization signal detection result adding step 304 and sent to a memory storage step 305 of the error correction circuit block. As described above, since the corresponding synchronization signal detection result information is added to each demodulated frame data, it is possible to easily associate each demodulated frame data with the synchronization signal detection result. Thereby, the synchronization signal detection result information can easily specify the demodulated frame data of the synchronization correction.

  FIG. 18 shows a state in which the transmission data in which each synchronization signal detection result information is added to the head of each demodulated frame data of FIG. 17 is stored in the memory. In FIG. 18, the synchronization signal detection result information and the demodulated frame data are stored in different areas of the memory. The demodulated frame data and the corresponding synchronization signal detection result information are stored in correspondence with each other.

  In each area, synchronization signal detection result information and demodulated frame data are stored at a predetermined address according to each frame number. For example, the synchronization signal detection result information 902 of the (m + 1) -th frame is stored at a predetermined m + 1 position where the lower 2 bits are 10. Similarly, the demodulated frame data 903 of the (m + 1) th frame is stored at a predetermined (m + 1) position. The demodulated frame data and the corresponding synchronization signal detection result information are stored in correspondence with each other.

  Also, the demodulated frame data 903 of the m-th frame is stored in only 7 bytes, and the (m + 1) -th demodulated frame data 904 is stored skipping one byte. Such a skip is performed, for example, when transferring from the synchronization signal detection result adding step 304 to the memory storage step 305, together with the transfer data, distinguishes whether the data being transferred is synchronization signal detection result information or demodulated frame data. It is apparent that the control signal can be easily realized by separately providing a control signal.

  The first example of the above-described out-of-synchronization detection is an example in which the synchronization correction is a synchronization delay equivalent to one byte.

(Example 4)
FIGS. 19 and 20 show the case where a new synchronization signal is detected at a timing that deviates from the timing predicted from the timing of the detection result of the synchronization signal detected immediately before, as described above. FIG. 14 is a diagram illustrating a fourth example of the second example in which out-of-synchronization is detected; The fourth embodiment is an example in which the synchronization advance of less than one frame is corrected, contrary to the case of the first example.

  FIG. 19A is a schematic diagram showing the data structure of the reproduced signal input to the frame synchronization step 301, and FIG. 19B is a diagram showing the transmission from the synchronization signal detection result adding step 304 to the memory storage step 305. FIG. 6 is a schematic diagram showing a data structure of demodulated frame data and synchronization signal detection result information to be transmitted. In FIG. 19, the synchronization signal 802 of the (m + 1) -th frame should be originally detected at the timing of 32 + 128 bits from the detection timing of the m-th synchronization signal 801. This is an example of a case where the synchronization has advanced from the bit timing, that is, the original timing.

  In this case, the result of the synchronization signal detection by the frame synchronization step 301 is out-of-synchronization detection 10. Therefore, in the synchronization signal detection result information generation step 302, the lower two bits of the synchronization signal detection result information 1006 of the (m + 1) th frame become 10.

  In the frame synchronization step 301, since the synchronization signal 1002 is detected at a timing deviating from the timing predicted from the clock, the synchronization is corrected to the timing of the newly detected synchronization signal 1002.

  Next, based on the frame synchronization in the frame synchronization step 301, the modulated frame data 1004 is demodulated in a demodulation step 303 to generate demodulated frame data 1008. On the other hand, the demodulated frame data 807 of the frame m has an extra bit number, but since only one demodulated frame data originally has a maximum of 8 bytes, only the first 8 bytes are transferred.

  Each synchronization signal detection result information is added to the head of each demodulated frame data in a synchronization signal detection result adding step 304 and sent to a memory storage step 305 of the error correction circuit block. As described above, since the corresponding synchronization signal detection result information is added to each demodulated frame data, it is possible to easily associate each demodulated frame data with the synchronization signal detection result. Thereby, the synchronization signal detection result information can specify the demodulated frame data corresponding to the synchronization correction.

  FIG. 20 shows a state in which the transmission data shown in FIG. 19, in which each synchronization signal detection result information is added to the head of each demodulated frame data, is stored in the memory. In FIG. 20, the synchronization signal detection result information and the demodulated frame data are stored in different areas of the memory. The demodulated frame data and the corresponding synchronization signal detection result information are stored in correspondence with each other.

  In each area, synchronization signal detection result information and demodulated frame data are stored at a predetermined address according to each frame number. For example, the synchronization signal detection result information 1102 of the (m + 1) -th frame is stored at a predetermined m + 1 position where the lower 2 bits are 10. The demodulated frame data 1103 of the (m + 1) -th frame is stored at a predetermined (m + 1) position.

(Example 5)
FIGS. 21 and 22 show the case where the synchronization signal detection result is a synchronization signal detected at a timing that deviates from the timing predicted by the clock based on the synchronization signal detected last time. It is a figure showing Example 5 of the 3rd example. The fifth embodiment is an example in which the synchronization delay of one or more frames is corrected, which is different from the first and second examples.

  FIG. 21A is a schematic diagram showing the data structure of a reproduction signal input to the frame synchronization step 301, and FIG. 21B is a diagram showing the transmission of the synchronization signal detection result from the addition step 304 to the memory storage step 305. FIG. 6 is a schematic diagram showing a data structure of demodulated frame data and synchronization signal detection result information. FIG. 21 shows an example in which the (m + 3) th synchronization signal 1202 is detected after the detection of the m-th synchronization signal 801. This is an example of a case where the (m + 1) th synchronization signal should be originally detected, but the frequency of the clock suddenly rises due to the departure of the PLL and the synchronization is delayed by one frame or more from the original timing.

  In this case, the result of the synchronization signal detection by the frame synchronization step 301 is out-of-synchronization detection 10. Therefore, in the synchronization signal detection result information generation step 302, the lower two bits of the synchronization signal detection result information 1206 of the (m + 3) th frame become 10.

  In the frame synchronization step 301, since the synchronization signal is detected at a timing that deviates from the timing at which the synchronization signal 1202 is predicted from the clock, the synchronization is corrected to the timing of the newly detected synchronization signal 1202.

  Next, based on the frame synchronization in the frame synchronization step 301, the modulated frame data 1204 is demodulated in the demodulation step 303 to generate demodulated frame data 1208.

  Each synchronization signal detection result information is added to the head of each demodulated frame data in a synchronization signal detection result adding step 304 and sent to a memory storage step 305 of the error correction circuit block. As described above, since the corresponding synchronization signal detection result information is added to each demodulated frame data, it is possible to easily associate each demodulated frame data with the synchronization signal detection result. Thereby, the synchronization signal detection result information can easily specify the demodulated frame data of the synchronization correction.

  FIG. 22 shows a state in which the transmission data shown in FIG. 21 in which each synchronization signal detection result information is added to the head of each demodulated frame data is stored in the memory. In FIG. 22, the synchronization signal detection result information and the demodulated frame data are stored in different areas of the memory. The demodulated frame data and the corresponding synchronization signal detection result information are stored in correspondence with each other.

  In each area, synchronization signal detection result information and demodulated frame data are stored at a predetermined address according to each frame number. For example, in the synchronization detection result information 1302 of the (m + 3) th frame, the lower 2 bits are 10 and are stored at a predetermined m + 3 position. Similarly, demodulated frame data 1303 of the (m + 3) th frame is stored at a predetermined m + 3 position.

  Also, the synchronization signal detection result information and demodulated frame data of the (m + 1) th and (m + 2) th frames are skipped and not stored because they were not transferred. Such a skip can be easily realized by referring to the frame number stored in the upper bits of the synchronization signal detection result information.

  As a more desirable embodiment, when such a skip is detected, it is preferable to store the code 01 in the case where the synchronization signal is not detected in the skipped synchronization signal detection result information. Here, the code 01 is stored in the (m + 1) th and (m + 2) th synchronization signal detection result information. By storing the code 01, an erasure pointer can be generated for the demodulated frame data skipped as described later.

  Here, an example in which a synchronization delay of one or more frames has occurred immediately after a frame of normal detection has been described. For example, after a synchronization signal has not been detected over a plurality of frames, a frame in which a synchronization signal is last detected The same processing can be performed when, for example, the clock signal counted from is shifted by one frame or more from the newly detected synchronization signal.

(Example 6)
FIGS. 23 and 24 are diagrams illustrating a sixth example of the fourth example in which the synchronization signal is detected at a timing deviating from the timing predicted from the clock as in the case described above, and synchronization correction is required. . The sixth embodiment is an example in which the synchronization advance of one or more frames is corrected, contrary to the fifth embodiment. FIG. 23A is a schematic diagram showing the data structure of a reproduction signal input to the frame synchronization step 301, and FIG. FIG. 3 is a schematic diagram illustrating a data structure of demodulated frame data and synchronization signal detection result information.

  FIG. 23 shows an example in which the m-th synchronization signal 1402 is detected again after the detection of the m-th synchronization signal 1401. Although the (m + 1) th synchronization signal should be detected originally, the synchronization signal is finally detected after the first m-th synchronization signal 1401 is falsely detected or after the synchronization signal is not detected over a plurality of frames. The same processing can be performed when the clock count is counted from the frame in which the signal is detected and the newly detected synchronization signal is shifted by one or more frames.

  At this time, the result of the synchronization signal detection in the frame synchronization step 301 is out-of-synchronization detection 10. Therefore, in the synchronization signal detection result information generation step 302, the lower 2 bits of the synchronization signal detection result information 1406 of the m-th frame become 10.

  In the frame synchronization step 301, since the synchronization signal 1402 is detected at a timing that deviates from the timing predicted by the clock, the synchronization is corrected to the timing of the newly detected synchronization signal 1402.

  Next, based on the frame synchronization in the frame synchronization step 301, the modulated frame data 1404 is demodulated in the demodulation step 303 to generate demodulated frame data 1408.

  Each synchronization signal detection result information is added to the head of each demodulated frame data in a synchronization signal detection result adding step 304 and sent to a memory storage step 305 of the error correction circuit block. As described above, since the corresponding synchronization signal detection result information is added to each demodulated frame data, it is possible to easily associate each demodulated frame data with the synchronization signal detection result. This makes it possible to easily specify demodulated frame data in which the synchronization signal detection result information indicates that synchronization has been lost. In the fifth embodiment, the data of the m-th frame is transmitted twice.

  FIG. 24 is a schematic diagram showing a state in which the transmission data shown in FIG. 23 in which each synchronization signal detection result information is added to the head of each demodulated frame data is stored in the memory. In FIG. 24, the synchronization signal detection result information and the demodulated frame data are stored in different areas of the memory. The demodulated frame data and the corresponding synchronization signal detection result information are stored in correspondence with each other.

  In each area, synchronization signal detection result information and demodulated frame data are stored at a predetermined address according to each frame number. For example, in the synchronization signal detection result information 1502 of the m-th frame, the lower two bits are 10 and are stored at a predetermined m position. Similarly, the demodulated frame data 1503 of the m-th frame is stored at a predetermined m position.

  The synchronization signal detection result information and demodulated frame data of the m-th frame are transferred twice in total, but the one transferred earlier is overwritten by the one transferred later. Note that, like the skip, such an overwriting operation can be easily realized by referring to the frame number stored in the upper bit of the synchronization signal detection result information.

  The detection of the synchronization signal and the synchronization correction have been described in detail with reference to FIGS. 13 to 24. However, as a more preferable embodiment, a window for limiting the detection range of the synchronization signal is provided. Is changed depending on the undetected continuation of the synchronization signal, the continuation of the detection, and the like, so that a stronger resistance to false detection of the synchronization signal can be realized.

  Next, the lost pointer generation step 306 will be described in detail with reference to FIG. FIG. 25 illustrates generation of a lost pointer for demodulated frame data stored in a different area from the synchronization detection result information stored in the memory. 25A shows synchronization signal detection result information, and FIG. 25B shows demodulated frame data constituting an error correction code of a sector. Codes in the column direction are formed so as to have the same structure as FIG. It is composed of eight 128 + 16 byte codes. The lost pointer is generated in units of frame data in the row direction, that is, in FIG. 25, in units of 8 bytes of one row.

As described above, there are three types of synchronization signal detection result information: normal detection 00, undetected 01, and out-of-sync detection 10.
(A) In the case of normal detection 00, no lost pointer is generated for the corresponding demodulated frame data.
(B) In the case of undetected 01 (1606), the demodulated frame data 1608 of the corresponding frame is determined to have low reliability because only the synchronization processing of the clock has been performed from the detection result of the previous synchronization signal, and An erasure pointer 1604 is generated for the demodulated frame data 1608.
(C) In the case of out-of-synchronization detection 10 (1607), it is determined that the reliability of the demodulated frame data 1609 immediately before the corresponding frame is low because the synchronization is corrected at the time of detecting the synchronization of the corresponding frame. Then, an erasure pointer 1605 is generated for the demodulated frame data 1609 immediately before the corresponding frame.

  The erasure correction is performed by setting these erasure pointers to the error position of the code in the column direction. By performing erasure correction, the number of corrections per code is improved up to twice. The generation of the lost pointer can be realized by storing the row number or the like where the demodulated frame data is stored in a register or the like that can be referred to by the error correction circuit at the time of the lost error correction.

  As described above, in the reproduction method according to the second embodiment of the present invention, the synchronization signal detection result information is sent to the error correction circuit block together with the demodulated frame data, and the erasure pointer is generated by using the information. Allow corrections to be made. As a result, highly reliable data reproduction can be realized.

(Embodiment 3)
The third embodiment is an example of the playback control circuit of the present invention, and is an example of a circuit configuration of the playback method of the second embodiment. FIG. 26 is a configuration diagram of the reproduction control circuit according to the third embodiment, and includes a demodulation circuit block 1701 and an error correction circuit block 1702. The demodulation circuit block 1701 includes a frame synchronization circuit 1703, a synchronization detection result information generation circuit 1705, a demodulation circuit 1704, and a synchronization signal detection result addition circuit 1706. The error correction circuit block 1702 includes an error correction circuit 1710, an erasure pointer generation circuit 1709, and the like, and executes error correction using an external memory 1708.

The operation of the reproduction control circuit will be described below.
(A) A reproduction signal 1713 reproduced from an optical disk is input to a frame synchronization circuit 1703.
(B) The frame synchronization circuit 1703 detects the synchronization signal at the head of each frame and performs frame synchronization. As a result of the frame synchronization, a synchronization signal detection result 1715 is sent to the synchronization signal detection result information generation circuit 1705. Also, the modulated frame data 1714 is sent to the demodulation circuit 1704. This frame synchronization circuit 1703 can be easily constituted by a pattern comparison circuit, a counter, and the like.

(C) The demodulation circuit 1704 demodulates the modulated frame data 1714 and sends out the demodulated frame data 1716. Here, a demodulation circuit of a known (8, 16) modulation method can be used.

(D) The synchronization signal detection result information generation circuit 1705 codes the synchronization signal detection result 1715 according to a predetermined rule. Here, the normal detection is 00, the non-detection is 01, and the out-of-sync detection is 10. Furthermore, the synchronization signal detection result information generation circuit 1705 generates 1-byte synchronization signal detection result information 1717 together with the lower 6 bits of the frame number. The synchronization signal detection result information generation circuit 1705 can be easily constituted by a logic circuit or the like.

(E) The synchronization signal detection result adding circuit 1706 adds the synchronization signal detection result information 1717 to the head of the demodulated frame data 1716 of each frame, and sends it to the error correction circuit block 1702. Further, the synchronization signal detection result adding circuit 1706 sends out together with the transmission data 1719, a control signal 1721 for distinguishing the synchronization signal detection result information from the demodulated frame data. The synchronization signal detection result adding circuit 1706 can be constituted by a selector or the like.

(F) The transmitted synchronization signal detection result information and demodulated frame data are separated by the separation circuit 1707. At the time of separation, a control signal 1721 for distinguishing each is used. The separated synchronization signal detection result information and demodulated frame data are stored in different areas of the memory 1708 via the bus control circuit 1711. The separation circuit 1707 can be easily constituted by two independent address generation circuits and the like. The details are omitted.

(G) The lost pointer generation circuit 1709 generates a lost pointer from the synchronization detection result information stored in the memory 1708 and stores the lost pointer in a register that the error correction circuit 1710 can refer to. The lost pointer generation circuit 1709 can be constituted by a microprocessor or the like.

(H) The error correction circuit 1710 performs erasure correction using an erasure pointer on an error correction code composed of demodulated frame data stored in the memory. The error correction circuit 1710 can be configured by a known Reed-Solomon code correction circuit.

(I) The I / F control circuit 1712 sends out the reproduced data 1720 stored in the memory 1708 in which the error correction has been executed to, for example, an MPEG decoding circuit. The I / F control circuit may be an interface circuit with an ATAPI or SCSI protocol control circuit.

(J) The bus control circuit 1711 controls the internal bus 1718 and performs recording / reproduction on the memory 1808.

  As described above, in the reproduction control circuit according to the third embodiment of the present invention, the synchronization signal detection result information is transmitted to the error correction circuit block together with the demodulated frame data, and the erasure pointer is generated by using the information. Enables erasure correction to be performed. As a result, highly reliable data reproduction can be realized. Note that details of frame synchronization, synchronization signal detection result information, generation of a lost pointer, and the like are the same as in the second embodiment, and a description thereof will not be repeated.

(Embodiment 4)
The fourth embodiment is an example of the playback apparatus of the present invention, and is an example of the configuration of an optical disc playback apparatus including the playback control circuit 1814 of the third embodiment. FIG. 27 is a block diagram showing a configuration of an optical disc reproducing apparatus that reproduces compressed image data from an optical disc 1801 on which the data is recorded. This reproducing apparatus includes, in addition to the reproduction control circuit 1814 of the third embodiment, an optical head 1802 composed of a semiconductor laser and an optical element, a reproduction circuit 1803 for binarizing an analog reproduction signal and generating a digital reproduction signal, It comprises an MPEG decoding circuit 1807 for expanding MPEG compressed data, a DA conversion circuit 1808, and a control CPU 1809 for controlling the entire playback device. Note that the reproduction control circuit 1814 includes a demodulation circuit block 1804, an error correction circuit block 1805, and a memory 1806.

The operation of the optical disk reproducing device configured as described above will be described below.
The laser beam emitted from the semiconductor laser of the optical head 1802 becomes reflected light modulated by pits or dark and light dots formed on the recording surface of the optical disk 1801, and returns to the optical head 1802. The modulated reflected light is converted into an electric signal by the photoelectric element, and is input to the reproduction circuit 1803 as an analog reproduction signal 1810. The reproduction circuit 1803 performs conversion from analog to digital, converts it into a digital reproduction signal, and sends it to the reproduction control circuit 1814.

  As described in the third embodiment, the reproduction control circuit 1814 performs frame synchronization, demodulation, and erasure correction using the erasure pointer generated from the synchronization detection result information. The detailed operation is the same as that of the third embodiment, and will not be described.

  The reproduced data 1811 having been subjected to the error correction and subjected to the error correction is MPEG-decoded by the MPEG decoding circuit 1807. The expanded reproduction data 1812 is converted into an analog signal by a DA conversion circuit 1808, and is sent to a TV monitor or the like as a sound or image signal 1813.

  Control of the entire optical disc reproducing apparatus is performed by a control CPU 1809. Note that, in this configuration diagram, a control signal, a servo circuit for focusing, tracking, and the like are omitted.

  In the optical disk reproducing apparatus according to the fourth embodiment configured as described above, the synchronization signal detection result information is added to the corresponding demodulated frame data and transmitted to the error correction circuit block, and the erasure pointer is used by using this. By the generation, the corresponding demodulated frame data can be specified, and the erasure correction can be performed on the corresponding demodulated frame data. As a result, highly reliable data reproduction can be realized.

  Note that the exemplification of any specific configuration and specific numerical values described in the present embodiment does not limit the definition of the present invention. However, the invention is defined only by the claims.

FIG. 2 is a schematic diagram illustrating a structural example of a recording medium according to Embodiment 1 of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a playback device according to Embodiment 1. FIG. 3 is a block diagram illustrating an example of an internal configuration of a memory control unit 205. FIG. 3 is a schematic diagram illustrating an example of a storage map of a buffer memory 206 according to the first embodiment. 5 is a timing chart showing an example of an internal signal change when a frame is lost according to Embodiment 1 of the present invention. 5 is a timing chart showing an example of an internal signal change when a frame is inserted according to Embodiment 1 of the present invention. 5 is a flowchart illustrating a flow of buffer memory storage control when a frame slip occurs in Embodiment 1 of the present invention. FIG. 3 is a diagram illustrating an example of a recording data format structure of a recording medium according to the first embodiment of the present invention. FIG. 3 is a schematic diagram illustrating a structure example of position information of a recording medium according to the first embodiment. FIG. 13 is a schematic diagram showing a frame data structure according to Embodiment 2 of the present invention. FIG. 9 is a schematic diagram illustrating a configuration of an optical disc according to Embodiment 2 of the present invention. 13 is a flowchart illustrating a reproduction method according to Embodiment 2. FIG. 19 is a schematic diagram showing a data structure in Example 1 when a synchronization signal detection result is a normal detection in the reproduction method in Embodiment 2; FIG. 14 is a diagram illustrating a state in which synchronization signal detection result information and demodulated frame data in FIG. 13 are stored. FIG. 19 is a schematic diagram showing a data structure in Example 2 when a synchronization signal detection result is not detected in the reproduction method according to Embodiment 2. FIG. 16 is a diagram illustrating a state in which synchronization signal detection result information and demodulated frame data in FIG. 15 are stored. FIG. 21 is a schematic diagram showing a data structure in Example 3 of the first example in a case where a synchronization signal detection result is out-of-synchronization detection in the reproduction method according to Embodiment 2; FIG. 18 is a diagram illustrating a state in which synchronization signal detection result information and demodulated frame data in FIG. 17 are stored. FIG. 19 is a schematic diagram showing a data structure in Example 4 of the second example in a case where the synchronization signal detection result is out-of-synchronization detection in the reproduction method according to Embodiment 2. FIG. 20 is a diagram illustrating a state in which synchronization signal detection result information and demodulated frame data in FIG. 19 are stored. FIG. 21 is a schematic diagram showing a data structure in a fifth example of the third example when a synchronization signal detection result is out-of-synchronization detection in the reproduction method according to the second embodiment. FIG. 22 is a diagram illustrating a state in which synchronization signal detection result information and demodulated frame data in FIG. 21 are stored. FIG. 19 is a schematic diagram showing a data structure in Example 6 of the fourth example when the synchronization signal detection result is out-of-synchronization detection in the reproducing method according to Embodiment 2. FIG. 24 is a diagram illustrating a state in which synchronization signal detection result information and demodulated frame data in FIG. 23 are stored. FIG. 19 is a schematic diagram illustrating generation of a lost pointer in the reproduction method according to the second embodiment. FIG. 13 is a block diagram illustrating a configuration of a reproduction control circuit according to Embodiment 3. FIG. 14 is a block diagram illustrating a configuration of an optical disc reproducing device according to a fourth embodiment.

Explanation of reference numerals

Reference Signs List 11 optical disk medium, 12 information tracks, 13 recording blocks, 14 frames, 15 synchronization signals, 21 signal reading means, 22 position information reproducing means, 23 synchronization means, 24 demodulation means, 25 memory control means, 26 buffer memory, 31 frame number Identification means, 32 byte number counter, 33 frame number counter, 34 sector number counter, 35 frame slip detection means, 36 address conversion means, 37 FIF0, 41 wobble grooves, 42 recording data, 43 land pre-pits, 105, 203, 308, 403, 404, 603, 604, 803, 804, 1003, 1004, 1203, 1204, 1403, 1404, 1714 Modulated frame data, 106, 204, 401, 402, 601, 602, 801, 802 1001, 1002, 1201, 1202, 1401, 1402 Synchronization signal, 301 frame synchronization step, 302 synchronization signal detection result information generation step, 303 demodulation step, 304 synchronization signal detection result addition step, 305 memory storage step, 306 erasure pointer generation step , 307 error correction step, 309, 1715 synchronization signal detection result, 311,405,406,501,502,605,606,701,702,805,806,901,902,1005,1006,1101,1102,1205 1206, 1301, 1302, 1405, 1406, 1501, 1502, 1717 Synchronization signal detection result information, 310, 407, 408, 503, 504, 607, 608, 703, 704, 807 , 808, 903, 904, 1007, 1008, 1103, 1104, 1207, 1208, 1303, 1304, 1407, 1408, 1503, 1504, 1716 Demodulated frame data, 1701, 1804 Demodulated circuit block, 1702, 1805 Error correction circuit block , 1703 frame synchronization circuit, 1704 demodulation circuit, 1705 synchronization signal detection result information generation circuit, 1706 synchronization signal detection result addition circuit, 1707 separation circuit, 1708, 1806 memory, 1709 erasure pointer generation circuit, 1710 error correction circuit, 1711 bus control Circuit, 1712 I / F control circuit, 1713 reproduction signal, 1718 internal bus, 1719 transmission data, 1720, 1811 reproduction data, 1721 control signal, 1801 optical disk, 1802 Optical head, 1803 playback circuit, 1807 MPEG decoding circuit, 1808 DA conversion circuit, 1809 control CPU, 1810 playback signal, 1814 playback control circuit, 1812 expanded playback data, 1813 audio / image signal

Claims (23)

A method for reproducing a recording medium on which data is recorded in units of blocks each having a plurality of frames of a predetermined length and positional information of the blocks is recorded,
Obtaining the data and the position information of the block from the recording medium;
Estimating a recording position for each frame in the block from the acquired position information of the block,
Obtaining synchronization on a frame basis from the acquired data;
Determining the storage location in the memory of the data obtained based on the predicted recording position,
Storing the acquired data in the determined storage location of the memory. Judging whether or not the synchronization of the data in the frame unit has been obtained;
Detecting that the synchronization in the frame unit is restored again when the synchronization in the frame unit is not obtained,
2. The recording apparatus according to claim 1, wherein when it is detected that the synchronization in the frame unit has been restored, a storage location of the data in the memory is determined based on a predicted recording position of the frame. Media playback method.   2. The method according to claim 1, wherein a storage location of the data in the memory is determined using the frame as a minimum unit.   2. The reproducing method according to claim 1, wherein the position information of the block is recorded in a different form from the data on the recording medium. A synchronization signal detection result information generating step of generating synchronization signal detection result information obtained by coding the detection result of the synchronization signal in frame units according to a predetermined rule;
A demodulation step of demodulating the data of each frame to generate demodulated frame data;
2. The reproduction method according to claim 1, further comprising a synchronization signal detection result adding step of adding the synchronization signal detection result information of the frame to each of the demodulated frame data and adding the information.   2. The method according to claim 1, further comprising obtaining synchronization on a frame basis from the acquired position information. Data is recorded in units of blocks each having a plurality of frames of a predetermined length, and a reproduction control circuit of a recording medium in which positional information of the blocks is recorded,
Signal reading means for obtaining the data and the position information of the block from the recording medium,
Recording position prediction means for predicting a recording position in frame units in the block from the acquired position information of the block,
Synchronization means for obtaining synchronization on a frame basis from the acquired data;
A memory for storing the data;
A control unit for determining a storage location of the data in the memory based on the predicted recording position. A synchronization detecting unit configured to detect whether the synchronization of the data in the frame unit is obtained, and to detect that the synchronization in the frame unit is restored again when the synchronization in the frame unit is not obtained. ,
The control unit stores the acquired data in the memory based on the recording position predicted by the recording position prediction unit when the synchronization detection unit detects that the synchronization in frame units has been restored. The reproduction control circuit according to claim 7, wherein a place is determined.   8. The reproduction control circuit according to claim 7, wherein a storage location of the data in the buffer memory is determined using the frame as a minimum unit.   A reproduction apparatus comprising the reproduction control circuit according to claim 7. A recording medium in which encoded data obtained by performing error correction encoding on data is divided into a plurality of frame data of a predetermined length, and modulated modulation frame data and a predetermined synchronization signal added to the head of the modulation frame data are recorded. A playback method for playing back the data from
A signal acquisition step of acquiring a signal from the recording medium,
A synchronization signal detection step of obtaining a synchronization signal detection result by detecting a synchronization signal of each of the frames from the acquired signal;
A frame synchronization step of correcting synchronization of the frame based on the obtained synchronization signal detection result;
A synchronization signal detection result information generating step of generating synchronization signal detection result information obtained by coding each of the synchronization signal detection results according to a predetermined rule;
Demodulating the modulated frame data of each frame to generate demodulated frame data,
A synchronization signal detection result adding step of adding the synchronization signal detection result information of the frame to each of the demodulated frame data in association with the demodulated frame data. For each demodulated frame data, a lost pointer generation step of generating a lost pointer for erasure correction using the corresponding synchronization signal detection result information,
The error correction method according to claim 11, further comprising: performing an erasure correction of an error correction code composed of the plurality of demodulated frame data using the erasure pointer corresponding to the demodulated frame data. Playback method.   12. The reproducing method according to claim 11, further comprising a memory storing step of storing the synchronization signal detection result information and the corresponding demodulated frame data in different areas of a memory in association with each other.   The synchronization signal detection result information is predicted from “normal detection” when the synchronization signal is normally detected, “undetected” not detecting the synchronization signal, and the timing of the detection result of the synchronization signal detected immediately before. 14. A method according to claim 11, wherein at least three kinds of detection results of "out-of-synchronization detection" when a new synchronization signal is detected at a timing out of the timing are distinguished and coded. The reproduction method described in the section. In the frame synchronization step, the synchronization delay in which a new synchronization signal is detected earlier than the timing predicted from the timing of the detection result of the synchronization signal detected immediately before is corrected, and the synchronization delay is one frame. If less than
12. The method according to claim 11, wherein in the memory storing step, the frame data immediately after the synchronization delay correction is stored in the memory after correcting the storage position in the memory to a position skipped by the amount corresponding to the synchronization delay correction. 15. The reproducing method according to any one of items 1 to 14. In the frame synchronization step, the synchronization delay in which a new synchronization signal is detected earlier than the timing predicted from the timing of the detection result of the synchronization signal detected immediately before is corrected, and the synchronization delay is one frame or more. In the case of a synchronization delay of
In the memory storing step, the synchronization signal detection result information immediately after the synchronization delay correction and the frame data are respectively stored in the memory by correcting the storage position in the memory to a position skipped by the amount corresponding to the synchronization delay correction. Along with
16. The reproducing method according to claim 15, wherein in the lost pointer generating step, the lost pointer is generated by regarding the synchronization signal detection result information skipped and not stored in the memory as being undetected. . A recording medium in which encoded data obtained by performing error correction encoding on data is divided into a plurality of frame data of a predetermined length, and modulated modulation frame data and a predetermined synchronization signal added to the head of the modulation frame data are recorded. A reproduction control circuit for reproducing the data from
Frame synchronization means for correcting the synchronization of the frame, based on a synchronization signal detection result obtained by detecting the synchronization signal of each frame from the reproduction signal obtained from the recording medium,
Synchronization signal detection result information generating means for generating synchronization signal detection result information obtained by coding each of the synchronization signal detection results according to a predetermined rule,
Demodulation means for demodulating the modulated frame data of each frame to generate demodulated frame data,
Synchronization signal detection result adding means for adding the synchronization signal detection result information of the frame to the head of each demodulated frame data,
A memory for storing the synchronization signal detection result information and the respective demodulated frame data,
A reproduction control circuit comprising: a memory storage unit that stores the synchronization signal detection result information and the respective demodulated frame data in the memory. An erasure pointer generating means for generating an erasure pointer for erasure correction using the synchronization signal detection result information; and ,
The reproduction control circuit according to claim 17, further comprising:   19. The reproduction control circuit according to claim 17, wherein the memory storage means stores the synchronization signal detection result information and the demodulated frame data in different areas of a memory.   The synchronization signal detection result information is predicted from the “normal detection” when the synchronization signal is normally detected, “undetected” not detecting the synchronization signal, and the timing of the detection result of the synchronization signal detected immediately before. 20. The coding method according to claim 17, wherein at least three types of detection results of "out-of-synchronization detection" when a new synchronization signal is detected at a timing deviating from the timing are coded. The reproduction control circuit according to the paragraph. In the case where the frame synchronization unit corrects a synchronization delay in which a new synchronization signal is detected earlier than the timing predicted from the synchronization signal detected immediately before, and when the synchronization delay is less than one frame,
The memory storage unit corrects a storage position of the frame data in the memory immediately after the synchronization delay correction to a position skipped by an amount equivalent to the synchronization delay correction, and stores the frame data in the memory. The reproduction control circuit according to any one of claims 17 to 20, wherein The frame synchronization means corrects a synchronization delay in which a new synchronization signal is detected earlier than the timing predicted from the synchronization signal detected immediately before, and the synchronization delay is a synchronization delay of one frame or more. To
The memory storage means corrects the storage position of the synchronization signal detection result information and the frame data in the memory immediately after the synchronization delay correction to a storage position skipped by an amount equivalent to the correction of the synchronization delay, and corrects the frame data. Is stored in the memory,
22. The erasure pointer according to claim 21, wherein the erasure pointer generation unit generates the erasure pointer by regarding the synchronization signal detection result information corresponding to the frame that has been skipped and not stored in the memory as "undetected". Reproduction control circuit.   A playback device comprising the playback control circuit according to claim 17.

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