JP2004178267A - Memory circuit creation method and device, memory circuit, circuit model verification method and device, and circuit model creation method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and efficiently construct a memory circuit to be modeled on a logical emulator. <P>SOLUTION: The desired memory operation of a target memory is realized by a memory circuit constituted of a memory 16 preliminarily mounted on an emulator main body 10 and a wrapper circuit 500 integrated in an FPGA 12 being a rewritable logical device. Countermeasures to the change of a memory peripheral circuit are taken by the wrapper circuit 500 integrated into the emulator device. Actually, the hardware change of the memory peripheral circuit is made unnecessary. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory circuit used for a verification system (emulator system) for performing logic verification of a semiconductor device, for example, and a method and an apparatus for generating the memory circuit. The present invention also relates to a method and an apparatus for verifying an individual circuit modeled on a verification system including a memory circuit, and a method and an apparatus for generating a circuit model.
[0002]
[Prior art]
2. Description of the Related Art With the advance of semiconductor technology, the degree of integration of logic ICs has been further improved, and a large-scale system can be integrated on one chip. Also, one-chip or a plurality of LSIs (Large Scale Integrated Circuits) are used for electronic devices. It is becoming possible to build systems such as equipment.
[0003]
When developing a semiconductor device such as a one-chip LSI or an ASIC (Application Specific Integrated Circuit), the logic operation of a logic circuit inside the semiconductor device (target circuit) is generally verified (debugged). Later, actual devices (chips) are manufactured.
[0004]
As a method of this logic verification, for example, there is a logic simulation (software simulation). In this method, an operation of a logic circuit to be subjected to logic verification is realized by an electronic computer (for example, a computer such as a workstation), and an output corresponding to a predetermined input pattern is predicted and analyzed (waveform analysis is performed by software). It is a mechanism.
[0005]
However, in this logic simulation, the operation speed is slower than that of an actual logic circuit, and the number of steps becomes very large when the scale of the logic circuit becomes large, and the logic verification time is lengthened. However, there is a problem that it is not always equivalent to the operation of a real circuit, and it is difficult to simulate the entire system faithfully. For this reason, it is practically impossible to verify the logic circuit of the entire system only by logic simulation.
[0006]
As another method of logic verification, there is a method of performing verification using a prototype LSI or a prototype using a substrate as a hardware element corresponding to a target circuit. In this method, for example, patterning of a prototype LSI is required, so that it takes several weeks to obtain a prototype. Therefore, it is difficult to repeatedly produce and verify a prototype.
[0007]
As a solution to the above-mentioned problem of the verification method, logic verification by logic emulation (hardware emulation / logic emulation) has attracted attention today (for example, see Patent Document 1).
[0008]
[Patent Document 1]
JP-A-2002-229813
[0009]
This logic emulation verifies the logic operation of a target circuit using a different kind of hardware element from the target circuit. For example, an operation equivalent to a logic circuit such as an LSI or a computer is performed on a printed circuit board. This is realized by a plurality of electronic components (a different kind of hardware element corresponding to the target circuit) mounted on the device, and the logic circuit is verified by operating the circuit at an operation speed close to the actual logic circuit.
[0010]
For example, it is realized by an emulator constituted by a programmable integrated semiconductor circuit (FPGA; Field Programmable Gate Array) which reads LSI design data and performs an operation equivalent to the LSI, and is realized by a CPU (Central Processing Unit). A general-purpose component such as a central processing unit) or a memory is mounted on an external printed circuit board, the emulator and the printed circuit board are connected, and the circuit is operated at an operation speed close to the actual logic circuit to verify the logic circuit.
[0011]
According to this logic emulation method, a system of several million gates can be constructed, verification of the system as a whole at an operating speed close to the actual speed is possible, and it is several thousand times more than software simulation using a computer. The verification result can be obtained in about one-half time. In addition, since the circuit configuration of the FPGA is variable, the circuit configuration of the FPGA is changed during verification to confirm the function, and the final circuit is determined. Then, the logic circuit verification (evaluation) of the entire system is performed in an operation close to the actual circuit. It can also be done at speed. At this time, by performing the logic circuit verification while changing the circuit configuration using the FPGA, it is also possible to determine a logic circuit of a specific function to be newly designed or a logic circuit for each user. This also allows the application specific integrated circuit ASIC to be provided in a relatively short period of time.
[0012]
[Problems to be solved by the invention]
On the other hand, in recent semiconductor devices, circuits have become complicated, a processor and a memory can be built in, and the system has become large-scale. Functions such as a CPU, a logic circuit, and a storage device (memory) are each provided independently. In addition to these, there is an increasing trend toward SOC (System On Chip), which realizes a desired system by mounting them on a single chip.
[0013]
Therefore, when the system-on-chip SOC is to be verified, the number of verification items is rapidly increasing. In this case, naturally, some items cannot be verified in the software simulation because the verification time is long. Therefore, it is necessary to perform system verification using a prototype board on which a prototype chip or the like is mounted, and more preferably, to perform system verification based on an actual device that performs system verification using logic emulation.
[0014]
In actual system-based system verification using prototype boards and logic emulation, functions are realized by mounting processors and memory circuits on rewritable devices and memory cells such as FPGAs that constitute the prototype boards and the verification system itself. However, it is difficult to accommodate the latest processor, high-performance memory, or large-scale memory in the verification system main unit, and a dedicated processor chip or external memory ( A circuit composed of these may be implemented by mounting an external circuit). In this way, even for a large-scale circuit, the designed logic circuit is mounted on a rewritable device such as an FPGA, a dedicated processor chip or an external memory, and an operation functionally equivalent to the actual chip is performed. You can check by emulation.
[0015]
For example, in an actual system-based system verification using logic emulation, a memory other than a logic circuit such as an SRAM (Static Random Access Memory) or an SDRAM (Synchronous Dynamic Random Access Memory) is mounted on a memory cell inside the emulator or an external board. A memory circuit is realized in combination with an external circuit (Wrapper circuit; wrapper circuit) that controls the memory so as to operate equivalently to the memory inside the system-on-chip SOC using an external memory such as an SRAM. Conventionally, when verifying the operation of this model, the operation of the model is often verified by confirming that the operation is the same as the specification of the memory.
[0016]
However, in recent system-on-chip SOC designs, a C language such as SystemC (trademark), SpecC, or CoWareC (trademark) is used without using an RTL (register transfer level) function description language (HDL) such as Verilog-HDL or VHDL. Designing with basic system-level languages is also increasing. In this case, detailed operation specifications of the memory alone often do not exist except for the simulation result. In addition, since many of these simulation results have different file formats, it is difficult or practically impossible to compare them with the results of logic simulation and logic emulation as they are.
[0017]
For this reason, it is often the case that a circuit is implemented in a logic emulator and verification is performed without sufficient verification of the operation. It has become to.
[0018]
A memory circuit using a memory such as an SDRAM or an SRAM is not limited to a memory circuit modeled by logic emulation, but is frequently used for temporarily storing data in an electric circuit. However, it is often difficult to study circuits because it is difficult to procure memories to be used. In such a case, the study must be delayed until the memory is obtained, or the study must be performed using a substitute memory.
[0019]
However, the method of delaying the examination causes a problem that the examination period is lengthened. In addition, when using alternative memory, the operation of the alternative memory and the original memory (target memory) do not always match, so it is necessary to change the circuits around the memory (wrapper circuit) so that the alternative memory operates. Problem may occur.
[0020]
Also, in this case, even when the memory peripheral circuit is changed and the entire memory circuit is constructed using the substitute memory, as described above, the problem is how to construct the memory model of the circuit and verify the operation. It becomes. If the memory circuit composed of the substitute memory and the wrapper circuit does not perform the same operation as the original target memory, the logic verification (logic emulation) using the assumed target memory model will fail. It is. Conventionally, it has been difficult to perform appropriate verification because a verification mechanism for such a case has not been established.
[0021]
As described above, when handling a memory circuit, it is required to shorten the design period. In this regard, it is a major problem in various aspects that it is difficult to procure a memory to be used.
[0022]
As a technique relating to a test method of a memory circuit, a technique for specifying a defective memory or a defective bit has been proposed (for example, see Patent Document 2).
[0023]
[Patent Document 2]
JP 2000-331499 A
[0024]
According to the method disclosed in Patent Document 2, provision of a circuit for holding a mismatch signal for each bit facilitates identification of defective bits, simultaneously tests memories having the same address configuration, and outputs the result once. The purpose of this is to reduce the memory test time by observing whether or not the scan is correct.
[0025]
However, as described above, the method of Patent Document 2 relates to the reduction of the memory failure and the test time, and the construction of a memory circuit using a substitute and whether the memory model performs the same operation as the original memory. It is difficult to use for verification.
[0026]
In addition, in the logic emulation, not only the memory circuit but also the modeled individual circuit is an equivalent circuit using a substitute, and the logic verification using the memory circuit composed of the substitute memory and the wrapper circuit is performed. The same problem occurs.
[0027]
The present invention has been made in view of the above circumstances, and has a method and apparatus for generating a memory circuit capable of efficiently or easily generating a memory circuit that operates in the same manner as a target memory. It is an object of the present invention to provide a memory circuit.
[0028]
Another object of the present invention is to provide a method and an apparatus for generating a circuit model that can reliably and easily constitute an individual circuit such as a memory circuit modeled on a logic emulation system as a substitute.
[0029]
Further, the present invention provides a verification method and apparatus capable of reliably and easily verifying a model of such an individual circuit when configuring an individual circuit such as a memory circuit modeled on a logic emulation system with a substitute. The purpose is to provide.
[0030]
[Means for Solving the Problems]
That is, the method of generating a memory circuit according to the present invention is a method of generating a model of a memory circuit that performs substantially the same operation as a target memory using a substitute memory, and is connected to the substitute memory. In addition, a wrapper circuit that causes the memory circuit to operate substantially equivalent to the target memory by cooperating with the substitute memory is incorporated in the rewritable logic device. As a substitute memory, a memory cell provided outside the logic device may be used instead of a memory built in the logic device.
[0031]
Here, when the capacity of the target memory is smaller than the capacity of the alternative memory, it is preferable to construct the wrapper circuit so that the capacity of the target memory is handled by the capacity of the single alternative memory.
[0032]
When the capacity of the target memory is larger than the capacity of the alternative memory, it is preferable to construct the wrapper circuit so that the capacity of the target memory is assigned in combination with the capacity of a plurality of alternative memories.
[0033]
An apparatus for generating a memory circuit according to the present invention is an apparatus for generating a model of a memory circuit that performs substantially the same operation as a target memory using a substitute memory, wherein a memory type related to a type of the target memory memory is provided. A type information obtaining unit for obtaining information; a specification information obtaining unit for obtaining memory specification information on the performance of the target memory; a memory type information obtained by the type information obtaining unit; and a memory specification information obtained by the specification information obtaining unit. And a wrapper circuit generating unit that generates a model of a wrapper circuit that is connected to the substitute memory and that causes the memory circuit to operate substantially equivalent to the target memory by cooperating with the substitute memory. did.
[0034]
The memory circuit according to the present invention is generated by using the method and apparatus for generating a memory circuit according to the present invention, and is connected to a substitute memory and incorporated in a rewritable logic device. The circuit shall be included. Here, the wrapper circuit includes a functional part that causes the memory circuit to operate substantially equivalent to the target memory by cooperating with the substitute memory.
[0035]
In addition, the wrapper circuit may be configured to control the spare memory so that the capacity of the target memory is handled by the capacity of the single spare memory, or to handle the capacity of the target memory by the capacity of a plurality of spare memories. It is desirable to include a functional part for controlling the use of a plurality of alternative memories while controlling the use of the individual alternative memories.
[0036]
A circuit model verification method according to the present invention is a method for verifying an operation of an individual circuit modeled on a logic verification system for verifying a logic operation of a target circuit, and includes an emulation result and a logic which are verification results by the logic verification system. By comparing the second verification result, which is a verification result obtained by a verification method different from the verification method by the verification system, the individual circuit modeled on the logic verification system becomes an original circuit (target circuit) corresponding to the individual circuit. It is determined whether or not the same operation is performed.
[0037]
A typical example of the individual circuit is a memory circuit that performs substantially the same operation as the target memory by using a substitute memory. Of course, the present invention is not limited to such a memory circuit, and may be another equivalent circuit using a substitute.
[0038]
Here, the second verification result includes a system-level simulation result (system-level verification result) of an individual circuit modeled on a target circuit designed in a system-level language, and a target circuit created in a function description language. It is preferable that the result is at least one of the simulation results (function description language level verification results) at the function description language level of the individual circuit modeled above. It is more preferable to compare both the system level verification result and the function description language level verification result with the emulation result.
[0039]
If the format of the output file indicating the second verification result is different from the file format that can be handled by the verification by the logical verification system, the format of the output file indicating the second verification result is verified by the logical verification system. It is recommended to convert to a file format that can be handled by and then compare with the emulation result.
[0040]
A circuit model verification device according to the present invention is a device that performs a circuit model verification method according to the invention, and a logic verification unit that acquires an emulation result that is a verification result by a logic verification system, and a verification method that is performed by the logic verification system. A second verification unit that obtains a second verification result that is a verification result by a different verification method, and compares an emulation result obtained by the logic verification unit with a second verification result obtained by the second verification unit. Thus, the individual circuit modeled on the logic verification system includes a verification result comparison unit that determines whether or not the individual circuit performs the same operation as the corresponding original circuit (target circuit).
[0041]
Here, the second verification unit is configured to generate a system-level simulation result of an individual circuit modeled on a target circuit designed in a system-level language, and an individual circuit modeled on a target circuit created in a function description language. Preferably, at least one of the simulation results at the function description language level is obtained as a second verification result.
[0042]
In addition, the circuit model verification device according to the present invention includes a file conversion unit that converts a format of the output file indicating the second verification result into a file format that can be handled by verification by the logic verification system, It is preferable that the verification result comparison unit compares the verification result indicated by the output file converted by the file conversion unit with the emulation result.
[0043]
The circuit model generation method according to the present invention is an individual circuit that is modeled on a logic verification system that verifies the logic operation of a target circuit by using the circuit model verification method according to the present invention. This is a method for generating a model of an individual circuit configured to perform substantially the same operation as the target circuit by using the emulation result, which is the verification result by the logic verification system, and the verification method different from the verification method by the logic verification system. A first step of comparing the result with a second verification result, and an individual circuit modeled on the logic verification system based on the comparison of the verification result is the same as the original circuit (target circuit) corresponding to this individual circuit. And a second step of determining whether or not to perform an operation.
[0044]
If the same operation as that of the original circuit is not performed, the model of the individual circuit modeled on the logic verification system is corrected with reference to the comparison result of the first step. And the second step are repeated to determine the model of the individual circuit.
[0045]
A typical example of the individual circuit is a memory circuit that performs substantially the same operation as the target memory by using a substitute memory. Of course, the present invention is not limited to such a memory circuit, and may be another equivalent circuit using a substitute.
[0046]
Here, the first step includes a system-level simulation result of an individual circuit modeled on a target circuit designed in a system level language and a function of the individual circuit modeled on a target circuit created in a function description language. It is preferable that at least one of the simulation results at the description language level is acquired as a second verification result, and the second verification result is compared with the emulation result.
[0047]
Further, the circuit model generation method according to the present invention includes a third step of converting the format of the output file indicating the second verification result into a file format that can be handled by the verification by the logic verification system. Preferably, the first step is to compare the verification result indicated by the output file converted by the third step with the emulation result.
[0048]
A circuit model generation device according to the present invention is a device that performs the circuit model generation method according to the present invention, and includes a logic verification unit that acquires an emulation result that is a verification result by a logic verification system, and a verification method that is performed by the logic verification system. A second verification unit that obtains a second verification result that is a verification result obtained by a verification method different from that of the first verification unit, and compares an emulation result obtained by the logic verification unit with a second verification result obtained by the second verification unit. And a verification result comparison unit for performing a first step of determining whether the individual circuit modeled on the logic verification system performs the same operation as the original circuit corresponding to the individual circuit. It was prepared.
[0049]
Further, on the condition that the judgment result in the second step in the verification result comparing section indicates that the circuit does not perform the same operation as the original circuit, the logic is performed by referring to the comparison result in the first step in the verification result comparing section. A control unit is provided for correcting the model of the individual circuit modeled on the verification system and controlling the corrected model to repeat the first step and the second step.
[0050]
Here, as a first step, the verification result comparison unit performs a system level simulation result of an individual circuit modeled on a target circuit designed in a system level language and a modeling on a target circuit created in a function description language. It is preferable that at least one of the simulation results at the function description language level of the individual circuit to be performed is compared with the emulation result as a second verification result.
[0051]
In addition, the circuit model generation device according to the present invention includes a file conversion unit that converts the format of the output file indicating the second verification result into a file format that can be handled by verification by the logic verification system, It is preferable that the verification result comparison unit compares the verification result indicated by the output file converted by the file conversion unit with the emulation result as a first step.
[0052]
In addition, a program suitable for realizing the above-described various methods and apparatuses by software using an electronic computer (computer) or a computer-readable storage medium storing the program may be extracted as an invention. The program may be provided by being stored in a computer-readable storage medium, or may be distributed via a wired or wireless communication unit.
[0053]
[Action]
In the memory circuit generation method and apparatus having the above configuration, a memory circuit that operates substantially equivalent to a target memory is constructed using a memory and a rewritable logic device such as an FPGA. Then, a wrapper circuit connected to the memory is mounted in the logical device.
[0054]
Further, in the circuit model verification method and apparatus having the above configuration, whether or not a circuit modeled (implemented) on a logic emulator performs the same operation as the original circuit (target circuit) is determined by comparing the verification result by the logic emulation with another Confirm by comparing with the verification result by the verification method.
[0055]
Further, in the circuit model generation method and apparatus having the above configuration, the method of the circuit model verification method and apparatus described above is used, and if the comparison result does not match, the circuit model is corrected with reference to the comparison result, and again, Compare the verification result by logic emulation with the verification result by other verification methods. By repeating this process until the comparison result matches, an individual circuit equivalent to the target circuit is created using the substitute.
[0056]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0057]
FIG. 1 is a diagram showing a schematic configuration of a verification system (logic emulation system) for performing logic emulation.
[0058]
The verification system 1 includes an emulator main body 10, a CPU board 20 having a CPU and a test chip 22 built in the SOC, and an external memory board 30 having a large-scale memory and a high-performance memory 32 built in the SOC.
[0059]
The emulator main body (verification system main body) 10 includes a logic circuit 14, a memory 16, and a test bench circuit configured by a programmable programmable FPGA (Field Programmable Gate Array) 12 that reads LSI design data and performs an operation equivalent to the LSI. 18 and the like.
[0060]
As the memory 16, for example, a memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) that performs a memory holding operation that can be written and read at any time, such as an SRAM (Static Random Access Memory), may be used. Note that the FPGA 12 and the memory 16 may be one if the system scale of the target circuit to be verified is small, but a plurality of each is used if the system scale is large.
[0061]
A plurality of CPU boards 20 and external memory boards 30 are prepared as needed. The emulator main body 10 is connected to the CPU board 20 and the external memory board 30 by an external board connection I / F section 92 constituting an interface (I / F) section 90.
[0062]
The verification system 1 also includes a controller PC for loading (supplying) the logic function definition data for determining the logic function of the FPGA 12 to the FPGA 12 or monitoring or controlling the entire verification system around the emulator main body 10. (PC; Personal Computer) 80, a workstation 82 for generating logical design data, and loading test data (input data) for verification into the emulator main body 10 and reading and holding data (output data) of verification results PCs 84 and 86 for data input and output, and a logic analyzer (hereinafter referred to as a logic analyzer) 88 for monitoring logic data under verification.
[0063]
Note that test data (input data) for verification may be the same as that used in software simulation. The test data for verification is supplied to the FPGA 12 via the test bench circuit 18 of the emulator main body 10, so that a software simulation verification environment is realized by a system verification apparatus using logic emulation (that is, the verification system 1). Become like
[0064]
The data (output data) of the verification result is output to the data input / output PCs 84 and 86 via the test bench circuit 18 and stored in a predetermined storage medium (for example, a hard disk device). In this case, the test data for verification (input data) and the data of the verification result (output data) are collectively referred to as “software simulation input / output data”.
[0065]
The controller PC 80 is a dedicated cable in the controller I / F unit 94, and the data input / output PCs 84, 86 are a PCI (Peripheral Component Interconnect) bus or an ISA (Industry Standard Architecture) bus in the data I / F units 96a, 96b. The logic analyzer 88 is a dedicated probe in the logic analyzer I / F section 98, and is connected to the emulator body 10 respectively.
[0066]
By providing a common interface mechanism such as a PCI bus or an ISA bus as the data I / F sections 96a and 96b which interface the verification data to the emulator main body 10, a plurality of different data can be input / output on the same interface. It becomes possible.
[0067]
As the data I / F units 96a and 96b, a parallel standard interface other than the PCI bus and the ISA bus may be used. The invention is not limited to the parallel bus interface, but may be an example of the Institute of Electrical and Electronics Engineers, Inc. (IEEE) 1394 standard, the USB (Universal Serial Bus) 1.0 / 2.0 standard, or the PCI standard. A serial interface such as “PCIExpress (trademark)” (PCI Express) may be used.
[0068]
Standard interfaces such as a parallel bus interface such as a PCI bus and an ISA bus are legal (legal) laws recognized by non-commercial organizations such as IEEE and JIS (Japanese Industrial Standards) or governmental organizations (public standard bodies). It may be a public interface used to establish uniformity in the area of hardware or software development according to the technical guidelines (above).
[0069]
Further, the interface is not limited to such a public interface, and may be a private standard interface compiled by a private organization or a single company, that is, a so-called industry standard interface (industrial standard interface). In any case, the standard interface may be any connection interface that satisfies a certain standard.
[0070]
For example, the hardware development or development that occurs when a product or philosophy is developed by a company and deviations from the standard through success and imitation cause compatibility issues or become widely used to limit marketability. De facto technical guidelines for software development (informal standards) may be employed as the standard interface in the present embodiment.
[0071]
The controller PC 80 and the workstation 82 are connected by a network LAN (Local Area Network). The workstation 82 generates logical design data which is logically described in a format called, for example, RTL (Register Transfer Level) or HDL (Hardware Description Language). In addition, the workstation 82 transfers the description data of the circuit portion corresponding to the logical design data or the data obtained by converting the description data into a predetermined data format to the controller PC 80. The controller PC 80 decodes this data, generates logic function definition data necessary for setting a logic function in the FPGA 12, and loads the logic function definition data into the FPGA 12, thereby implementing a target circuit corresponding to an ASIC, SOC, or the like. (Implement).
[0072]
Further, the workstation 82 transfers the load module generated for the target circuit evaluation to the controller PC 80. The load module is supplied to the emulator main body 10 having the FPGA 12, the CPU board 20 connected to the emulator main body 10, and the like. The in-circuit emulation converts the FPGA 12 to an actual logic circuit (target circuit) on a target circuit to be developed. By operating at an operation speed close to an ASIC or SOC corresponding to the target circuit), it is used for performing verification or testing such as system debugging or software debugging.
[0073]
As a peripheral system of the verification system 1, a target circuit using an internal memory LPM (Local Place Memory) or a memory 16 (SRAM in this example) or a memory 32 on an external memory board 30 built in the FPGA 12 is used. A memory circuit construction system 7 for generating a wrapper circuit for performing an operation substantially equivalent to a memory (for example, a DRAM; hereinafter also referred to as a target memory) inside the system-on-chip SOC is prepared. The memory circuit construction system 7 includes a memory circuit generation device 400 and a workstation 82, each connected by a network LAN. The workstation 82 notifies the memory circuit generation device 400 of information (memory type, capacity, etc.) on the target memory.
[0074]
In addition, as a peripheral system of the verification system 1, the operation of the wrapper circuit generated by the memory circuit generation device 400 of the memory circuit construction system 7, or the operation of a memory circuit configured using this wrapper circuit or a substitute such as the memory 16 A circuit model verification system 9 for verifying is provided. The circuit model verification system 9 includes a circuit model verification device 450 and a workstation 82 connected to each other via a network LAN, a data input / output PC 86, a logic analyzer 88, and the like. The circuit model verification device 450 has the function of the circuit model generation device according to the present invention.
[0075]
The circuit model verification device 450 is notified of information (memory type, capacity, and the like) on the target memory from the workstation 82, and the circuit information of the generated wrapper circuit is notified from the memory circuit generation device 400. The verification result of the logic emulation using the logic emulator device 5 including the emulator body 10 and the external board 11 is also notified from the data input / output PC 86 and the logic analyzer 88.
[0076]
The circuit information of the wrapper circuit generated by the memory circuit generation device 400 is input to the circuit model verification device 450, and the memory circuit using the memory of the substitute product including the generated wrapper circuit is converted into an actual memory (target memory). It is verified whether the same operation is performed. If there is no problem in this verification, the generated circuit information of the wrapper circuit is notified to the workstation 82, and is written to the FPGA 12 via the controller PC 80 and to the memory circuit generation device 400 in the same manner as when writing normal circuit information to the FPGA 12. The generated wrapper circuit is incorporated. If a problem is found in the verification by the circuit model verification device 450, it goes without saying that necessary measures are taken.
[0077]
<< A memory circuit construction method using a substitute memory >>
FIG. 2 is a schematic diagram focusing on a memory circuit used in the verification system 1 shown in FIG. 1 and a construction method of the memory circuit.
[0078]
As shown in the figure, the emulator main body 10 includes a logic circuit 14 composed of an FPGA 12 (only one is shown in the figure, but a plurality of FPGAs) and a memory unit 17 composed of four SRAMs, on an emulator substrate 10a. A connector 46 which is a part of an external board connection I / F unit 92 (see FIG. 1) which can be connected to another board such as the external board 11 (see FIG. 1) such as the CPU board 20 or the external memory board 30; A connector 48 which is a part of a controller I / F unit 94 for loading circuit data into the FPGA 12 is mounted.
[0079]
As shown in FIG. 1, the emulator main body 10 is connected via a connector 48 to a controller PC 80 having software for generating circuit data and a mechanism for loading a circuit.
[0080]
In the FPGA 12 mounted on the emulator substrate 10a, an internal memory LPM (Local Place Memory), a memory 16 (SRAM in this example) built in the FPGA 12, or an external memory board 30 connected by a connector 46 is provided. Using an external memory (not shown), a wrapper circuit for performing an operation substantially equivalent to a memory (for example, a DRAM) inside a system-on-chip SOC as a target circuit is incorporated. As described in FIG. 1, the wrapper circuit is generated by the memory circuit generation device 400.
[0081]
FIG. 3 shows a configuration of a memory circuit when the external memory board 30 is used. In this case, the wrapper circuit is mounted in the FPGA 12 of the emulator body 10.
[0082]
FIG. 4 is an example of a functional block diagram of the memory circuit generation device 400. As shown in the figure, the memory circuit generation device 400 includes a type information acquisition unit 412 that acquires memory type information J12 relating to the type of target memory (for example, SDRAM or SRAM) used for the system-on-chip SOC. A specification information acquisition unit 414 is provided to acquire memory specification information J14 regarding the performance of a target memory used for the system-on-chip SOC, such as depth (word; Word) or memory capacity (memory size).
[0083]
Further, the memory circuit generation device 400 uses the information J12 and J14 acquired by the information acquisition units 412 and 414 (collectively, the memory information acquisition unit 410) to generate a wrapper circuit. 420 is provided. The wrapper circuit generation unit 420 sends the data to the internal memory LPM, the memory 16 or the connector 46 built in the FPGA 12 mounted on the emulator substrate 10a based on the information J12 and J14 acquired by the memory information acquisition unit 410. For operating substantially equivalent to a target memory such as a DRAM or an SDRAM using a memory 32 (collectively referred to as a substitute memory hereinafter) on an external memory board 30 connected to the external memory board 30. Generate a wrapper circuit.
[0084]
In the above configuration, the memory circuit generation device 400 may be configured by, for example, a dedicated hardware circuit having a function of generating a wrapper circuit, or may be configured by using a general-purpose computer such as a personal computer or a workstation. Is also good. That is, the series of processes for generating the wrapper circuit can be executed by hardware, but can also be executed by using software. For example, the workstation 82 and the controller PC 80 shown in FIG. 1 may have the function of the memory circuit generation device 400.
[0085]
When the wrapper circuit generation processing is executed by software, an OS (operating system) which is software for controlling the entire operation and an application program which is software for performing the wrapper circuit generation function are provided by dedicated hardware. The computer is installed (embedded) from a recording medium into a computer incorporated in the computer or a general-purpose personal computer that can execute various functions by installing various programs. As a result, the memory circuit generation device according to the present invention is realized as software based on a program.
[0086]
The recording medium is a magnetic disk (including a flexible disk) on which the program is recorded, an optical disk (CD-ROM (Compact Disc-Read Only Memory)), which is distributed separately from the computer to provide the program to the user, Not only a DVD (including a Digital Versatile Disc), a magneto-optical disk (including an MD (Mini Disc)), or a package medium (portable storage medium) such as a semiconductor memory but also pre-installed in a computer The program may be provided to the user in a locked state, or may be configured by a ROM or a hard disk in which the program is recorded. Alternatively, a program constituting software may be distributed via a wired or wireless communication unit.
[0087]
For example, a storage medium storing a program code of software for realizing a wrapper circuit generation function is supplied to a system or apparatus, and a computer (or CPU or MPU) of the system or apparatus reads out the program code stored in the storage medium. The effect of the wrapper circuit generation processing is also achieved by executing. In this case, the program code itself read from the storage medium implements the wrapper circuit generation function.
[0088]
When the computer executes the readout program code, not only the wrapper circuit generation function is realized, but also the operating system OS running on the computer performs actual processing based on the instruction of the program code. A case where a part or the whole is performed and the wrapper circuit generation function is realized by the processing may be performed.
[0089]
Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. The CPU or the like provided in the card or the function expansion unit may perform part or all of the actual processing, and the processing may realize the wrapper circuit generation function.
[0090]
FIG. 5 is a flowchart illustrating an example of a processing procedure for generating a wrapper circuit in the memory circuit generation device 400.
[0091]
First, the type information acquisition unit 412 acquires memory type information J12 indicating whether the type of memory desired to be used in the system-on-chip SOC is SDRAM or SRAM (S100). The acquisition of the memory type information J12 may be via an input by a user. Alternatively, a mechanism for decoding the design specification of the system-on-chip SOC and automatically acquiring the design specification may be provided.
[0092]
When the SRAM is selected (S100-SRAM), the specification information obtaining unit 414 first obtains information indicating the number of data bits as an example of the memory specification information J14 (S110). The specification information acquisition unit 414 acquires information indicating the memory depth as another example of the memory specification information J14 (S112). The acquisition of the memory specification information J14 may be performed through an input by the user. Alternatively, a mechanism for decoding the design specification of the system-on-chip SOC and automatically acquiring the design specification may be provided.
[0093]
Next, the wrapper circuit generation unit 420 determines the memory type indicated by the memory type information J12 acquired by the type information acquisition unit 412 and the number of bits and the memory depth indicated by the memory specification information J14 acquired by the specification information acquisition unit 414. Based on each value, the number of replacement memories (the number of memories) required to configure the target memory using the replacement memory such as the internal memory LPM or the memory 16 (SRAM in this example) in the FPGA 12 Is determined (S114).
[0094]
For example, when the determined number of memories is "1" (S116-YES), the wrapper circuit generation unit 420 outputs the wrapper circuit immediately (S120) because a circuit that controls only that memory is sufficient. On the other hand, when the number of memories is plural (S116-NO), the interface between the memories must be considered, so the wrapper circuit generator 420 first generates an interface circuit for that (S118). Thereafter, the wrapper circuit generation unit 420 outputs the wrapper circuit as a wrapper circuit to which an interface circuit has been added (S120).
[0095]
On the other hand, when the SDRAM is selected (S100-SDRAM), the basic processing procedure is the same as that when the SRAM is selected, but the specification information acquisition unit 414 acquires information on the memory depth (S112). In that information about the memory capacity, which is an example of the memory specification information J14, is obtained (S132).
[0096]
FIG. 6 is an example of an operation specification of the memory 16 alone mounted on the emulator board 10a. FIG. 7 is a table showing a detailed description of each signal of the memory 16 alone.
[0097]
The size (memory capacity) of each memory 16 (SRAM in this example) is 32 bits × 128 kilobytes, and four of these are mounted on the emulator board 10a, and have a total size of 128 bits × 128 kilobytes. The operation of another memory (the target memory used in the system-on-chip SOC in this example) is realized by using the single memory (SRAM) and the wrapper circuit.
[0098]
In the signal shown in FIG. 7, "ADVLn" is fixed to "0 (L; low)" because it is unique to the chip and is not used in the present embodiment. “CE1n ＠” (＠ is 1 to 4) controls the use of the four memories 16 and is set to “0” or “1 (H; high)” in consideration of the target memory. .
[0099]
FIG. 8 is a diagram illustrating an example of an SRAM memory model (timing chart of memory operation) as an example of a target memory. The SRAM model of the example shown in FIG. 8 is a model of 8 bits × 36720 words.
[0100]
FIG. 9 is a diagram showing an example of a memory circuit model (hereinafter also referred to as a memory model) generated to realize the operation of the SRAM model shown in FIG. 8 by a substitute memory such as the memory 16 or a wrapper circuit. It is. In FIG. 9, four SRAMs are mounted as the memory 16 in the memory unit 17. Note that “1′b0” set in ADVLDn, CENn, and MODE of the memory unit 17 indicates that 1-bit binary “0” is set in each terminal.
[0101]
The wrapper circuit 500 around the memory unit 17 is generated by the memory circuit generation device 400 according to the above-described steps S100 to S120. When performing the logic emulation, the wrapper circuit 500 is preferably Implemented (implemented) in the FPGA 12.
[0102]
As shown in FIG. 9, the wrapper circuit 500 includes a replacement memory (in this example, shown in FIG. 6) which is mounted to perform the operation of the memory model shown in FIG. The wrapper circuit 500 is configured based on a comparison with the timing of an SRAM (SRAM as the memory 16).
[0103]
For example, in the wrapper circuit 500, the flip-flop (FF) 510 for adjusting the phase between the data, the control signal and the address, and adjusting the timing at which the internal memory LPM of the FPGA 12 takes in the data, receives the data input (I [7: 0]). Are added one by one.
[0104]
Further, the wrapper circuit 500 selects one of a read (Read) output (data Out [7: 0]) and a hold (Hold) output of the memory 16 for the data output (A [7: 0]). An output selection circuit (SEL) 514 is also added. Furthermore, since the number of bits of the input address (IA [15: 0]) is one bit less than the input (A [16: 0]) of the wrapper circuit 500, as shown by the mark A in the figure, the most significant bit of the input address “0” is added to the bit MSB side.
[0105]
As described above, as the memory unit 17, four SRAMs as the memory 16 are mounted on the emulator substrate 10a. To realize the operation of the SRAM model shown in FIG. Since only one SRAM may be used, only the first SRAM (shown by (1) in the figure) is used. Therefore, as shown in the table of FIG. 7, only the chip enable CE1n1 corresponding to the first SRAM is set to “0”, and the remaining chip enable CEs (shown by (2) to (4) in the figure) are enabled. CE1n2 to CE1n4 are fixed to “1”.
[0106]
The inverter 512 provided in the output enable OEn is provided to match the active polarity when the write enable WEn is also used for the output enable OEn. The output of the inverter 512 is input to the switching input terminal of the selection circuit 514, and is used as a selection switching signal of the selection circuit 514.
[0107]
FIGS. 10 and 11 are diagrams showing an example of a memory model (timing chart of memory operation) of an SDRAM as an example of a target memory. Here, FIG. 10 is a timing chart at the time of a write (Write) operation, and FIG. 11 is a timing chart at the time of a read (Read) operation. The SDRAM model of the example shown in FIGS. 10 and 11 has a storage capacity of 4M (mega).
[0108]
FIG. 12 is a diagram showing an example of a memory circuit generated to realize the operation of the 4MS DRAM model shown in FIGS. 10 and 11 by a substitute memory such as the memory 16 or a wrapper circuit. FIG. 13 is a table showing the relationship between the state of each signal of the memory circuit and the state.
[0109]
The wrapper circuit 520 around the memory unit 17 is generated by the memory circuit generation device 400 according to the above-described steps S100 to S340. When performing logic emulation, the wrapper circuit 520 is preferably Implemented (implemented) in the FPGA 12.
[0110]
As shown in FIG. 12, the wrapper circuit 520 includes an operation of the memory model shown in FIGS. 10 and 11, which is a target memory, and a substitute memory (in this example, FIG. The wrapper circuit 520 is configured based on a comparison with the timing of the SRAM 16 as the memory 16 shown in FIG.
[0111]
For example, a comparison between FIG. 6 and FIG. 10 reveals that the write data timing is delayed by 1T (one clock) from the actual memory model. In addition, a comparison between FIG. 6 and FIG. 11 shows that the output timing of the read data is earlier than the actual memory model by 2T (two clocks). The memory circuit generation device 400 configures the wrapper circuit 520 in consideration of these delay amounts (clock differences).
[0112]
For example, as a circuit element corresponding to the 1T delay of the write data, a flip-flop 532 that delays the write enable signal DQM in units of 16 bits of data for controlling the lower 16 bits of the data by 1T, and the input data D by 2T Flip-flops 534 and 536 for delay are provided so that the output of the subsequent stage is input to the data input (data In [31: 0]). In addition, a flip-flop 538 that delays the data output (data Out [31: 0]) of the memory unit 17 by 1T is provided as a circuit element corresponding to the 2T delay of the read data.
[0113]
As described above, as the memory unit 17, four SRAMs as the memory 16 are mounted on the emulator substrate 10a. However, in order to realize the operation of the SDRAM model shown in FIGS. Uses only one SRAM, so only the first SRAM (shown by (1) in the figure) is used. Therefore, as shown in the table of FIG. 7, only the chip enable CE1n1 corresponding to the first SRAM is used, and the remaining chip enable CE1n2 (shown by (2) to (4) in the drawing) are used. CE1n4 is fixed to “1”.
[0114]
The wrapper circuit 520 causes each of the write (write) and read (read) operations (collectively, Write / Read) to be performed in units of four in the burst period, similarly to the operation of the 4MS DRAM as the target memory. For this purpose, a write enable signal generation circuit 530 for generating a write enable pulse Wenn having a width of 4T from the write enable XWE (reference X means original input; the same applies hereinafter) is added. This write enable pulse Wenn is used as the write enable WEn of the memory unit 17.
[0115]
Further, the wrapper circuit 520 also controls the chip enable CE1n ＠ (＠ is only 1 in this example) at the time of the Read / Write operation in units of four, so that the 4T-wide output enable OEn and the chip enable CE1n1 are output from the chip select XCS. A circuit element for generating is added.
[0116]
The wrapper circuit 560 is a circuit for controlling the output using the most significant bit MSB of the incremented read address, as in the case of writing, for the processing at the time of reading. First, the chip enable CE1n1 and CE1n3 and the ADVLDn signal A command decoder 540, a state machine 542, and an ADVL signal generation circuit 544 are added as circuit elements for controlling the output enable signal OEn, and an output enable signal generation circuit 546 and a flip-flop 548 are added as circuit elements for controlling the output enable signal OEn. I have.
[0117]
The address bus input (A [16: 0]) of the wrapper circuit 520 according to the present embodiment includes a circuit element for incrementing the address Addr for a burst operation (operation in units of four) at the time of a read / write operation. An address signal generation circuit (make address) 550 for associating the X-direction address input AX and the Y-direction address input AY with the address Addr of the memory 16, and an address addition circuit for controlling the address in units of four at the time of the Read / Write operation (Addr1 = Addr1 + 1) 552 is added.
[0118]
The address addition circuit 552 executes “Addr1 = Addr1 + 1” three times in order based on the address Addr generated by the address signal generation circuit 550, and stores a total of four addresses (Addr, Addr + 1, Addr + 2, Addr + 3) in the memory unit 17. Address input (A [16: 0]).
[0119]
For example, the command decoder (Command Decoder) 540, the state machine 542, and the ADVL signal generation circuit 544 added to the chip enable CE1n1 and ADVLn corresponding to the first SRAM change the chip enable CE1n1 of 4T width from the chip select XCS. It is for generating. The output enable signal generation circuit (OEn_Gen) 546 and the flip-flop 548 added to the output enable OEn are for generating a 4T width output enable signal OEn from the chip select XCS.
[0120]
Here, the command decoder 540 includes a chip select XCS, a write enable XWE, a row address strobe XRAS (Row Address Strobe), a column address strobe XCAS (Column Address Strobe), a refresh XRFSH (Refresh), and a refresh XRFSH. And the command to be output is determined based on each original signal of the precharge XPRE (Precharge), and each command (Command) shown in FIG. 13 is output at the timing shown in FIG. 10 or FIG.
[0121]
The state machine 536 outputs, based on the command output from the command decoder 530, state information indicating an operation state of the entire memory circuit during operation. That is, as shown in FIG. 13, the state information is determined by a combination of the states of the chip select XCS, the write enable XWE, the row address strobe XRAS, the column address strobe XCAS, the refresh XRFSH, and the precharge XPRE.
The state machine 542 determines the state using the command output from the command decoder 540. The ADVL signal generation circuit 544 generates the chip enable CE1n1 signal and the ADVLDn signal using the state output here and the most significant bit of the address generated by the address addition circuit 552.
[0123]
The ADVL signal generation circuit 544 sets the chip enable signal CE1n1 corresponding to the first SRAM to “0” in 4T units only during the active period based on the state information output from the state machine 536. The ADVL signal generation circuit 544 sets the ADVLDn signal to “0” in 4T units at the time of writing and reading, and to “1” in other states.
[0124]
The output enable signal generation circuit 546 outputs an output enable signal OEn having a pulse width of 4 clocks using the command output from the command decoder 540. The write enable signal generation circuit 530 generates a write enable signal WEn having a width of 4T from a write enable signal XWE having only a width of 1T (1clk).
[0125]
At the time of writing, in the timing chart of FIG. 10, AX at the next ACT timing after the issuance of the DESL command is captured as an address in the X direction, and AY at a timing delayed by one clock is captured as an address in the Y direction. Then, a WRITE command is fetched after ACT, and the write operation starts from the next cycle. In this case, the address is taken in the section from Addr to Addr + 3 in the timing chart of FIG. 10, and the data actually written is from Data1 to Data4. Then, when PALL (PRECHARGE ALL) is read, the write operation ends. When writing to another address, the process starting from the ACT command is repeated.
[0126]
At the time of reading, in the timing chart of FIG. 11, after the DESL command is issued, AX is taken in by the next issued ACT command, and AY is taken in by the next clock. Then, the value Data1 stored at the address ADDR read at the next timing after the next READ command is fetched is read. The same read operation is performed up to ADDR + 3. Then, when PALL (PRECHARGE ALL) is read, the read operation ends. To read another address, the process starting with the ACT command is repeated.
[0127]
FIG. 14 is a diagram showing another example of a memory circuit generated to realize the operation of the memory model by a substitute memory such as the memory 16 or a wrapper circuit. The wrapper circuit 520 shown in FIG. 12 uses only one of the four SRAMs as the memory 16 mounted on the emulator substrate 10a and uses the 4MS DRAM model shown in FIGS. 10 and 11 as a target memory. This is a wrapper circuit for configuring a memory circuit that operates equivalent to. On the other hand, the wrapper circuit 560 shown in FIG. 14 is a wrapper circuit for configuring a memory circuit that operates equivalently to the target memory model by using a plurality of memories. Here, a case where an 8M SDRAM is designed as a target memory model will be described.
[0128]
The basic operation of the 8MS DRAM is the same as that of the 4MS DRAM, but one memory 16 (SRAM) mounted on the emulator board 10a cannot store all data. To this end, a feature is that a processing circuit is provided in which the mounted memory to be accessed changes according to the address. In the present embodiment, a first SRAM (shown by (1) in the figure) and a third SRAM (shown by (3) in the figure) are used. This will be specifically described below.
[0129]
The wrapper circuit 560 of the present embodiment determines a data storage destination by looking at the most significant bit side MSB of the counter output of the address addition circuit 552 that increments the address Addr for a burst operation (operation in units of four). It has a configuration. Specifically, the difference from the configuration shown in FIG. 12 is that the most significant bit output Addr1 [17] of the address addition circuit 552 is input to the ADVL signal generation circuit 544. The ADVL signal generation circuit 544 corresponds not only to the chip enable CE1n1 corresponding to the first (shown by (1) in the figure) SRAM but also to the third (shown by (3) in the figure) SRAM. The difference from the configuration shown in FIG. 12 is that the chip enable CE1n3 is also controlled.
[0130]
The ADVL signal generation circuit 544 selects the memory 16 as the data storage destination by switching the chip enable CE1n1 and CE1n3 according to the address (Addr1 [17]) input from the address addition circuit 552. For example, when the address Addr1 [17] = 0, only the chip enable CE1n1 is set to active “0” to use the first SRAM, and when the address Addr1 [17] = 1, only the chip enable CE1n3 is active. By setting to “0”, the third SRAM is used.
[0131]
With such a configuration, the most significant bit (Addr1 [17]) of the incremented read address can be used at the time of reading as well as at the time of writing. By switching and using the SRAM, it is possible to adopt a capacity of 8M.
[0132]
As described above, three cases (SRAM compatible as target memory and SDRAM compatible) of realizing the same operation as the target memory by using the substitute memory and the wrapper circuit have been described. Or SDRAM.
[0133]
Further, as for the memory size (memory capacity) of the target memory, the case of 4M or 8M has been described in the above embodiment, but another memory capacity may be used. For example, in order to support 16M, a configuration is used in which four SRAMs mounted on the emulator substrate 10a are switched and used according to the value (00, 01, 10, 11) of the two most significant bits of the address. By doing so, it is possible to take measures.
[0134]
Further, in the above embodiment, the example in which the memory 16 on the emulator board 10a is used has been described, but it goes without saying that the memory 32 mounted on the external memory board 30 may be used. In particular, when the total capacity of the memory 16 mounted on the emulator substrate 10a cannot be covered by the total capacity of the target memory, it is essential to use the memory 32 on the external memory board 30.
[0135]
As described above, according to the configuration of the above-described embodiment, even if the memory to be used (that is, the target memory) is not obtained, as long as the operation specifications are known, the memory (the actual In the embodiment, the memory 16 and the memory 32) and a wrapper circuit for causing the memory to perform an operation equivalent to the operation of the target memory can be considered, so that a memory peripheral circuit can be studied. In addition, the wrapper circuit can be conveniently incorporated in a rewritable logic device (the FPGA 12 in the embodiment) used in the emulator device.
[0136]
That is, since a mechanism for replacing the memory to be used is prepared in the emulator device, the memory can be replaced when the real memory is obtained, and the examination work can proceed smoothly. Further, even after the product is commercialized, it can be easily used for a study work when replacing the memory with another memory due to a discontinuation of production, etc., which can contribute to shortening the study period and cost reduction.
[0137]
<< Method of verifying and generating wrapper circuit and memory circuit >>
Next, a method of verifying the wrapper circuit generated by the memory circuit generation device 400, a method of verifying the memory circuit including the wrapper circuit, and a method of generating a model of the memory circuit will be described.
[0138]
FIG. 15 is a schematic diagram focusing on the circuit model verification system 9 shown in FIG. An FPGA 12 which is a rewritable device is mounted on an emulator main body 10 for performing logic emulation. The emulator body 10 is connected to an external memory board 30 which is a board on which the external memory 32 is mounted, via an external board connection I / F unit 92. The emulator main body 10 also includes a memory 16 in addition to the FPGA 12.
[0139]
Circuit data to be mounted on the FPGA 12 is transmitted from a controller PC 490 such as a controller PC 80 or a workstation 82 connected to the emulator main body 10 via a cable. The emulation test vector (verification data) is sent from the data input / output PC 86 connected to the emulator body 10 via a cable. Similarly, the verification result (emulation result) of the logic emulation is sent to the data input / output PC 86 via the cable. The digital pattern observation result at the time of logic emulation is acquired by the logic analyzer 88.
[0140]
The circuit model verification device 450 of this embodiment refers to the verification result of the logic emulation when verifying the wrapper circuit and the memory circuit. For this reason, the circuit model verification device 450 and the control computer 490 are connected by a cable, and are configured to be able to instruct the control computer 490 to execute logic emulation when necessary. The control computer 490 controls the data input / output PC 86 to send a test vector (verification data) of the logic emulation to the emulator main body 10 when the logic emulation is executed. The verification result (emulation result) of the logic emulation is sent to a circuit model verification device 450 connected to the data input / output PC 86 and the logic analyzer 88 via a cable.
[0141]
The circuit model verification device 450 may also be used as the data input / output PC 86 or the control computer 490. That is, one computer may be used.
[0142]
FIG. 16 is an example of a functional block diagram of the circuit model verification device 450. As shown in FIG. 16A, a circuit model verification device 450 includes a type information acquisition unit 462 that acquires memory type information J12 relating to the type of memory (for example, SDRAM or SRAM) used for the system-on-chip SOC, for example, A specification information acquisition unit 464 is provided to acquire memory specification information J14 relating to the performance of a memory (target memory) used for the system-on-chip SOC, such as the number of bits, memory depth (word; Word) or memory capacity (memory size). .
[0143]
Further, the circuit model verification device 450 is generated by the memory circuit generation device 400 using the information J12 and J14 acquired by the information acquisition units 462 and 464 (collectively, the memory information acquisition unit 460). An operation verification unit 470 that verifies whether the wrapper circuit performs the same operation as the target memory.
[0144]
Furthermore, the circuit model verification device 450 performs the same operation as that of the original circuit (the target circuit such as the target memory) based on the determination result in the operation verification unit 470 so as to perform the function of the circuit model generation device that generates the model of the individual circuit. A control unit 488 that corrects the circuit model modeled on the logic verification system with reference to the comparison result on the condition that the circuit model is not to be performed, and repeats the same processing for the model after the correction. .
[0145]
As shown in FIG. 16B, the operation verifying unit 470 extracts a system level design model 602 and a test vector for verification 604 from each piece of information J12, J14, and uses the extracted models 602, 604 to perform system level design. Has a system level verification unit 472 that is an example of a second verification unit that performs the simulation of.
[0146]
The operation verification unit 470 extracts the memory circuit model 612 based on the function description language model of the target memory from the information J12 and J14, and the extracted memory circuit model 612 and the test vector for verification acquired by the system level verification unit 472. And a function description level verification unit 474 that is another example of the second verification unit that performs a function description level simulation by using the function description level simulation unit 614.
[0147]
Further, the operation verification unit 470 performs an operation check using the verification test vector 624 obtained by the system level verification unit 472 and the information 624 of the emulation modeling circuit designed by the memory circuit generation device 400 to perform emulation. It has a logic verification unit (emulation unit) 476 for acquiring the result.
[0148]
Note that the circuit model verification device 450 of the present embodiment refers to the verification result of the logic emulation by the logic emulator device 5 when verifying the wrapper circuit and the memory circuit. For this reason, the logic verification unit 476 does not need to actually perform the logic emulation, but may perform the instruction and obtain the verification result.
[0149]
The operation verification unit 470 compares the verification results obtained by the system level verification unit 472, the function description level verification unit 474, and the operation verification unit 476, and generates a wrapper generated by the memory circuit generation device 400. A verification result comparison unit 478 for determining whether the circuit performs the same operation as the target memory is provided.
[0150]
Note that the verification result comparison unit 478 includes a file conversion unit 480 that converts a different file format to a specific file format because the file output of each verification result cannot be compared unless the file format is the same.
[0151]
In this embodiment, the output pattern file output from the system level verification unit 472 is different from the format of the output file output from the other function description level verification unit 474 and the logic verification unit 476. For this reason, the file conversion unit 480 of the present embodiment executes a file conversion process so that the output pattern file obtained as a result of the verification by the system level verification unit 472 matches the format of the output file of the remaining verification units 474 and 476. .
[0152]
In the above configuration, the circuit model verification device 450 may be configured by a dedicated hardware circuit that performs a verification function of a wrapper circuit or a memory circuit, or may be configured by using a general-purpose computer such as a personal computer or a workstation. You may. That is, a series of processes for verifying the wrapper circuit and the memory circuit can be executed by hardware, but can also be executed by using software. For example, the workstation 82 and the controller PC 80 shown in FIG. 1 may have the function of the circuit model verification device 450. Further, the memory circuit generation device 400 and the circuit model verification device 450 may be integrally configured.
[0153]
When the verification process of the memory circuit or the like is executed by software, an OS (operating system) that is software for controlling the entire operation and an application program that is software for performing a verification function of the above-described memory circuit or the like include: It is installed (incorporated) from a recording medium into a computer incorporated in dedicated hardware or a general-purpose personal computer that can execute various functions by installing various programs. As a result, the circuit model verification device according to the present invention is realized as software based on a program.
[0154]
The recording medium is a magnetic disk (including a flexible disk) on which the program is recorded, an optical disk (CD-ROM (Compact Disc-Read Only Memory)), which is distributed separately from the computer to provide the program to the user, Not only a DVD (including a Digital Versatile Disc), a magneto-optical disk (including an MD (Mini Disc)), or a package medium (portable storage medium) such as a semiconductor memory but also pre-installed in a computer The program may be provided to the user in a locked state, or may be configured by a ROM or a hard disk in which the program is recorded. Alternatively, a program constituting software may be distributed via a wired or wireless communication unit.
[0155]
For example, a storage medium storing a program code of software for realizing a verification function such as a memory circuit is supplied to a system or apparatus, and a computer (or CPU or MPU) of the system or apparatus stores the program code stored in the storage medium. The effect of the verification process for the memory circuit and the like can be achieved by reading and executing. In this case, the program code itself read from the storage medium implements the verification processing function.
[0156]
When the computer executes the readout program code, not only the wrapper circuit generation function is realized, but also the operating system OS running on the computer performs actual processing based on the instruction of the program code. A case where a part or the whole is performed and the wrapper circuit generation function is realized by the processing may be performed.
[0157]
Further, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. The CPU or the like provided in the card or the function expansion unit may perform part or all of the actual processing, and the processing may realize the wrapper circuit generation function.
[0158]
FIG. 17 is a diagram illustrating the processing function of the file conversion unit 480. Here, FIG. 17A is a functional block diagram illustrating a detailed example of the file conversion unit 480. FIG. 17B is a flowchart illustrating an example of a file conversion processing procedure in the file conversion unit 480.
[0159]
FIG. 18 shows an example of the combined file generated by the file conversion unit 480. FIG. 18A shows the combined file of FIG. 18A, and the combined file of FIG. 18A shows the function description level verification unit 474 and the logic verification unit 476. FIG. 18B illustrates an example of a file that has been converted to match the format of the output file.
[0160]
As shown in FIG. 17A, the file conversion unit 480 includes a system level output file acquisition unit 482 for acquiring an output pattern file obtained as a result of verification by the system level verification unit 472, and a system level output file acquisition unit 482. The file combining unit 484 for combining various files included in the obtained output pattern file and the file format of the combined file combined by the file combining unit 484 are changed to the output file format of the remaining verification units 474 and 476. And a conversion execution unit 486 that executes a file conversion process so as to match and outputs the file as a simulation result file.
[0161]
As shown in FIG. 17B, the system level output file acquisition unit 482 first acquires an output pattern file obtained as a verification result from the system level verification unit 472 (S300). The output pattern file of the system-level simulator by the system-level verification unit 472 includes three types: a basic information file, a signal information file, and a signal file. The basic information file includes information such as creation date and time and time scale. In the signal information file, the name of a signal obtained by probing the simulation result is described. The signal file contains signal operation information for each time.
[0162]
Here, the file formats that can be handled by the function description level verification unit 474 and the logic verification unit 476 of the present embodiment are, as in the case of the file shown in FIG. On the other hand, it must be in a cohesive format. Therefore, even if the three types of files, that is, the basic information file, the signal information file, and the signal file, are directly input as verification test vectors of the function description level verification unit 474 and the logic verification unit 476, appropriate comparison verification cannot be performed.
[0163]
Therefore, first, the file combining unit 484 combines these three types of files and outputs a combined file (see FIG. 18A) (S310). Although the time information is added to all the signal changes in this combined file, it still matches the file format that can be handled by the remaining verification units 474 and 476 (see FIG. 18B). Therefore, the function description level verification unit 474 and the logic verification unit 476 cannot perform appropriate comparison verification. In other words, it is still impossible to input to the function description level verification unit 474 and the logic verification unit 476 with the combined file as it is.
[0164]
For example, in the combined file shown in FIG. 18A, the file is output in a format in which time information (the numerical value after # is time; unit picosecond) and data are arranged in pairs one by one and sequentially arranged. Unlike the file shown in (B), the data at the same time is not in a format that is integrated with the time information at that time. In the comparison verification performed by the function description level verification unit 474 and the logic verification unit 476 according to the present embodiment, the file format of the circuit model is the same as the file shown in FIG. If not, appropriate comparative verification cannot be performed.
[0165]
Therefore, the conversion execution unit 486 converts the file format of the combined file output from the file combining unit 484 into a format in which data having the same time information is combined so that the remaining verification units 474 and 476 can handle the combined file. (S320). After that, the conversion execution unit 486 inputs the simulation result file after the file conversion to the function description level verification unit 474 as the test vector 614 for verification for the function description level simulator, and also as the test vector 624 for verification for the emulator. The data is input to the logic verification unit 476 (S322).
[0166]
FIG. 19 is a flowchart illustrating an example of a verification procedure and a generation procedure of a memory circuit including the wrapper circuit generated by the memory circuit generation apparatus 400 and the memory circuit including the wrapper circuit in the circuit model verification apparatus 450.
[0167]
First, the system level verification unit 472 converts a system level design model (system language circuit model) 602 and a test vector for verification 604 designed in a system level language based on the C language such as SystemC (trademark), SpecC or CoWareC. Then, a system level simulation is performed (S400). Then, the output pattern file obtained by this simulation is used as a test vector for verification for a functional description level simulator and an emulator.
[0168]
As described with reference to FIG. 17, since the file output of each verification result cannot be compared unless it is in the same file format, the output pattern file of the verification result of the system-level simulation having a file format different from the others is stored in a file. After the file is converted by the conversion unit 480, it is input to the function description level verification unit 474 as the test vector 614 for verification for the function description level simulator, and is input to the logic verification unit 476 as the test vector 624 for verification for the emulator. (S402).
[0169]
Next, the function description level verification unit 474 is a function description language designed in RTL (register transfer level) function description language (HDL) such as Verilog-HDL or VHDL and mounted on an actual system-on-chip SOC. A logic simulation (functional description level simulation) is performed using the memory circuit model (functional description language circuit model) 612 and the test vector for verification 614 based on the model (S410).
[0170]
Next, the logic verification unit 476 performs an operation check using the verification test vector 624 and the emulation modeling circuit (circuit model for emulator) 622 designed by the memory circuit generation device 400 (S420). However, in practice, the logic verification unit 476 may instruct the logic emulator device 5 to perform emulation processing and obtain the verification result.
[0171]
Next, the verification result comparing unit 578 compares the verification result (emulation result) 626 obtained by this emulator with the verification result (an example of the second verification result) 606 of the system level simulation and the logic simulation (function description level simulation). And (430) are compared with the verification result (another example of the second verification result) 616.
[0172]
If the comparison result output by the verification result comparison unit 578 is the same (S432-YES), the control unit 488 determines that the model generated by the memory circuit generation device 400 performs the same operation as the original memory (target memory). The judgment is made, and the verification processing and the circuit model generation processing are terminated. When the result is different (S432-NO), the control unit 488 notifies the memory circuit generation device 400 of the comparison result and instructs the reconfiguration of the circuit model.
[0173]
The memory circuit generation device 400 corrects the model of the wrapper circuit with reference to the comparison result notified from the circuit model verification device 450. In response to this, the circuit model verification device 450 checks the operation again. Each functional element of the circuit model verification system 9 performs such processing until the output results match.
[0174]
In the above embodiment, the verification result of the system level simulation and the logic simulation is compared with the verification result using the logic emulator device 5, and the same operation as the target memory is generated by the memory circuit generation device 400. Although it has been determined whether or not the circuit is to be executed, the determination method is not limited to this.
[0175]
For example, a circuit generated by the memory circuit generation device 400 by comparing and evaluating only one of the verification results of the system level simulation and the logic simulation with the verification result using the logic emulator device 5 and performing the same operation as that of the target memory. It may be determined whether or not to execute. However, it should be noted that the determination accuracy, that is, the quality of the circuit model of the wrapper circuit or the memory circuit generated by the memory circuit generation device 400 is reduced.
[0176]
Also, by comparing the results of logic emulation with those of other verification methods, it is possible to check whether the circuit modeled on the logic emulator operates the same as the target circuit. Not only that, a plurality of verification results can be matched, and the reliability of the quality of the generated circuit model can be improved.
[0177]
Further, in the above embodiment, as an individual circuit modeled in the logic emulator device, a memory circuit that performs an operation substantially equivalent to a target memory by using a substitute memory is targeted, and a model of the memory circuit is verified. And the generation of the circuit model have been described, but the individual circuit is not limited to such a memory circuit. The individual circuit is not limited to the memory circuit configured by the alternative memory and the wrapper circuit, and the same effects as described above can be obtained by applying the embodiment to other equivalent circuits using the alternative. be able to.
[0178]
Further, in the above embodiment, the file conversion by the file conversion unit 480 is performed on the output file from the system level verification unit 472, but the file conversion is performed by the output from the system level verification unit 472. It is not limited to files. This is because the file format that can be handled by each verification unit depends on each verification system.
[0179]
In any case, when the file formats that can be handled by the respective verification units are different, by performing a file conversion process on any (or all) output files so as to obtain a unified file format, What is necessary is just to make the whole a unified (common) file format.
[0180]
As described above, according to the configuration of the above embodiment, the result of the system level simulation and the logic simulation using the common test pattern and the logic emulator device 5 of the wrapper circuit generated by the memory circuit generation device 400 are used. By matching with the verification result, the reliability of the quality of the wrapper circuit generated by the memory circuit generation device 400 and the circuit model of the memory circuit including the wrapper circuit is improved.
[0181]
If a problem is found in the verification result, a corrected model reflecting the result can be reconfigured and verified again by an emulator device incorporated in the verification system. Here, since the wrapper circuit generated by the memory circuit generation device 400 is incorporated in the FPGA 12 in which the circuit configuration of the logic emulator device 5 is variable, the circuit configuration of the FPGA 12 is changed during verification to check the function. Is repeated to determine the final wrapper circuit and memory circuit. As a result, the wrapper circuit and the memory circuit can be determined in a relatively short time.
[0182]
In addition, the logic circuit verification (evaluation) of the entire system (system-on-chip SOC in the above embodiment) can be performed at an operation speed close to the actual circuit, in addition to the repeated verification of the wrapper circuit and the memory circuit.
[0183]
When the output file format of each verification result is different, the results of different verification means are converted to a common data format and handled as test patterns, so that test patterns can be created at once. The design time can be shortened.
[0184]
As described above, the present invention has been described using the embodiment. However, the technical scope of the present invention is not limited to the scope described in the embodiment. Various changes or improvements can be made to the above-described embodiment without departing from the spirit of the invention, and embodiments with such changes or improvements are also included in the technical scope of the present invention.
[0185]
Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of the features described in the embodiments are not necessarily essential to the means for solving the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. Even if some components are deleted from all the components shown in the embodiment, as long as the effect is obtained, a configuration from which some components are deleted can be extracted as an invention.
[0186]
For example, in the above-described embodiment, a description has been given of a generation method and a verification method of a memory circuit incorporated in a logic emulator device. However, the application range of the above-described embodiment is not limited to the memory circuit on the logic emulator device, and data may be stored in an electric circuit. The present invention is applicable to any memory circuit used for temporary storage and the like.
[0187]
【The invention's effect】
As described above, according to the present invention, a desired memory operation of a target memory is incorporated into a memory mounted on a board constituting a logic emulator apparatus or a logic device (for example, an FPGA) that can be rewritten with an external memory. Since it is realized with a wrapper circuit, changes in the memory peripheral circuit can be handled by the wrapper circuit built into the emulator device, virtually eliminating the need for hardware changes in the memory peripheral circuit. can do.
[0188]
In addition, since a mechanism to replace the memory to be used is built into the emulator device, it is easy to perform a study when replacing the real memory or when replacing the memory with another memory due to discontinuation of production after commercialization. Yes, it can contribute to shortening the study period and cost.
[0189]
In addition, when verifying the operation of the generated wrapper circuit and the memory circuit including the wrapper circuit, the verification result by the logic emulator device is compared with the verification result by a method other than the verification method using the logic emulator device. Since it is determined whether or not the memory model on the logic emulator performs the same operation as the original memory (target memory), it is possible to match a plurality of verification results and improve the quality of the generated memory model. You can now increase the reliability.
[0190]
Also, by comparing the results of logic emulation with those of other verification methods, it is possible to check whether the circuit modeled on the logic emulator operates the same as the target circuit. Not only that, a plurality of verification results can be matched, and the reliability of the quality of the generated circuit model can be improved.
[0191]
In addition, if the comparison results do not match, the circuit model is corrected by referring to the comparison result, and the verification result by the logic emulation and the verification result by another verification method are used again. By comparing with a verification result, a model of an individual circuit using a substitute equivalent to the target circuit can be easily and reliably generated. Thereby, the accuracy of the logic emulation is also improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a logic emulation system.
FIG. 2 is a schematic diagram focusing on a memory circuit used in the verification system shown in FIG. 1 and a method of constructing the memory circuit.
FIG. 3 shows a configuration of a memory circuit when an external memory board is used.
FIG. 4 is an example of a functional block diagram of a memory circuit generation device.
FIG. 5 is a flowchart illustrating an example of a processing procedure for generating a wrapper circuit in the memory circuit generation device.
FIG. 6 is an example of operation specifications of a single memory mounted on an emulator substrate.
FIG. 7 is a table showing a detailed description of each signal of a single memory.
FIG. 8 is a diagram showing an example of a memory model (timing chart of memory operation) of an SRAM as an example of a target memory.
FIG. 9 is a diagram illustrating an example of a memory circuit generated to implement the operation of the SRAM model illustrated in FIG. 8 with a substitute memory or a wrapper circuit.
FIG. 10 is a diagram illustrating an example of a memory model during a write operation of an SDRAM as an example of a target memory.
FIG. 11 is a diagram illustrating an example of a memory model at the time of a read operation of an SDRAM as an example of a target memory.
FIG. 12 is a diagram showing an example of a memory circuit generated to implement the operation of the 4MS DRAM model shown in FIGS. 10 and 11 with a substitute memory or a wrapper circuit.
FIG. 13 is a table showing a relationship between states of respective signals of the memory circuit of FIG. 12;
FIG. 14 is a diagram showing an example of a memory circuit generated to realize the operation of the 8MS DRAM model by a substitute memory or a wrapper circuit.
FIG. 15 is a schematic diagram focusing on the circuit model verification system shown in FIG. 1;
FIG. 16 is an example of a functional block diagram of a circuit model verification device.
FIG. 17 is a diagram illustrating a processing function of a file conversion unit.
18A is a diagram illustrating an example of a combined file, and FIG. 18B is a diagram illustrating an example of a file obtained by converting the combined file of FIG.
FIG. 19 is a flowchart illustrating an example of a verification procedure for a wrapper circuit and a memory circuit including the wrapper circuit and a generation procedure of the memory circuit in the circuit model verification apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Verification system, 5 ... Logic emulator device, 7 ... Memory circuit construction system, 9 ... Circuit model verification system, 10 ... Emulator main body, 11 ... External board, 12 ... FPGA, 14 ... Logic circuit, 16 ... Memory, 18 ... Test bench circuit, 20 CPU board, 22 CPU, 30 external memory board, 32 memory 32, 80 controller PC, 82 workstation, 84 PC for data input / output, 86 PC for data input / output, Reference numeral 88: logic analyzer, 90: interface section, 92: external board connection I / F section, 94: controller I / F section, 96a, 96b: data I / F section, 98: logic analyzer I / F section, 400 .., A memory circuit generation device, 410, a memory information acquisition unit, 412, a type information acquisition unit, 414, a specification information acquisition unit, 420, Upper circuit generation unit, 450: circuit model verification device (circuit model generation device), 462: type information acquisition unit, 462: specification information acquisition unit, 470: operation verification unit, 472: system level verification unit, 474: function description level Verification unit, 476: Logical verification unit, 478: Verification result comparison unit, 480: File conversion unit, 482: System level output file acquisition unit, 484: File combination unit, 486: Conversion execution unit, 488: Control unit, 500: Wrapper circuit, 514 selection circuit, 520 wrapper circuit, 530 write enable signal generation circuit, 560 wrapper circuit, 578 verification result comparison unit, J12 memory type information, J14 memory specification information

Claims (22)

A memory circuit generation method for generating a model of a memory circuit that performs substantially the same operation as a target memory using a substitute memory,
A wrapper circuit, which is connected to the substitute memory and cooperates with the substitute memory to cause the memory circuit to operate substantially equivalent to the target memory, is incorporated in a rewritable logic device. Memory circuit generation method. 2. The method according to claim 1, wherein the wrapper circuit is constructed such that the capacity of the target memory is controlled by the capacity of the single substitute memory. 2. The memory circuit generation method according to claim 1, wherein the wrapper circuit is constructed so that the capacity of the target memory is assigned in combination with the capacity of the plurality of alternative memories. The method according to claim 1, wherein a memory cell provided outside the logic device is used as the substitute memory. A memory circuit generation device that generates a model of a memory circuit that performs substantially the same operation as a target memory using a substitute memory,
A type information acquisition unit that acquires memory type information regarding the type of the target memory memory;
A specification information acquisition unit that acquires memory specification information regarding the performance of the target memory memory;
Based on the memory type information obtained by the type information obtaining unit and the memory specification information obtained by the specification information obtaining unit, connected to the alternative memory and cooperating with the alternative memory. And a wrapper circuit generation unit for generating a model of a wrapper circuit that causes the memory circuit to operate substantially equivalent to the target memory. A memory circuit that performs substantially the same operation as the target memory using the substitute memory,
A wrapper circuit connected to the replacement memory and incorporated in the rewritable logic device;
The memory circuit according to claim 1, wherein the wrapper circuit includes a functional part that causes the memory circuit to operate substantially equivalent to the target memory by cooperating with the substitute memory. 7. The memory circuit according to claim 6, wherein the wrapper circuit includes a functional part for controlling the replacement memory so that the capacity of the target memory is taken up by a single capacity of the replacement memory. . The wrapper circuit includes a functional part that controls the replacement memory while switching the use of the plurality of replacement memories so that the capacity of the target memory is handled by the capacity of the plurality of replacement memories. The memory circuit according to claim 6, wherein A circuit model verification method for verifying the operation of an individual circuit modeled on a logic verification system for verifying a logical operation of a target circuit,
The emulation result, which is a verification result by the logic verification system, and a second verification result, which is a verification result by a verification method different from the verification method by the logic verification system, are modeled on the logic verification system. A method of verifying a circuit model, comprising determining whether the individual circuit performs the same operation as an original circuit corresponding to the individual circuit. A system-level simulation result of the individual circuit modeled on the target circuit designed in a system level language as the second verification result, and a modeled on the target circuit created in a function description language 10. The circuit model verification method according to claim 9, wherein the comparison is performed with at least one of simulation results of a function description language level of the individual circuit. If the format of the output file indicating the second verification result is different from the file format that can be handled by the verification by the logical verification system,
Converting the format of the output file indicating the second verification result to a file format that can be handled by verification by the logical verification system,
The circuit model verification method according to claim 9, wherein the verification result indicated by the converted output file is compared with the emulation result. 12. The circuit model verification method according to claim 11, wherein the individual circuit is a memory circuit that operates substantially equivalent to a target memory by using a substitute memory. A circuit model verification device that verifies the operation of an individual circuit modeled on a logic verification system that verifies a logical operation of a target circuit,
A logic verification unit that acquires an emulation result that is a verification result by the logic verification system;
A second verification unit that obtains a second verification result that is a verification result by a verification method different from the verification method by the logical verification system;
By comparing the emulation result obtained by the logic verification unit with the second verification result obtained by the second verification unit, the individual circuit modeled on the logic verification system corresponds to the individual circuit. A circuit model verification device comprising: a verification result comparison unit that determines whether the same operation as an original circuit to be performed is performed. The second verification unit is configured to perform a system level simulation result of the individual circuit modeled on the target circuit designed in a system level language, and to model the result on the target circuit created in a function description language. 14. The circuit model verification device according to claim 13, wherein at least one of the simulation results at the function description language level of the individual circuit is obtained as the second verification result. A file conversion unit that converts a format of an output file indicating the second verification result into a file format that can be handled by verification by the logical verification system;
14. The circuit model verification device according to claim 13, wherein the verification result comparison unit compares a verification result indicated by an output file converted by the file conversion unit with the emulation result. A circuit model generation method for generating a model of an individual circuit modeled on a logic verification system for verifying a logic operation of a target circuit,
The individual circuit is configured to operate substantially equivalent to the target circuit using a substitute,
A first step of comparing an emulation result that is a verification result by the logic verification system with a second verification result that is a verification result by a verification method different from the verification method by the logic verification system;
A second step of determining whether or not the individual circuit modeled on the logic verification system performs the same operation as the original circuit corresponding to the individual circuit based on the comparison of the verification results,
When the same operation as the original circuit is not performed, the model of the individual circuit modeled on the logic verification system is corrected with reference to the comparison result of the first step, and the corrected model is A circuit model generating method, wherein a model of the individual circuit is determined by repeating a first step and a second step. The first step includes, as the second verification result, a system-level simulation result of the individual circuit modeled on the target circuit designed in a system-level language and the target created in a function description language. 17. The circuit model generating method according to claim 16, wherein at least one of simulation results at a function description language level of the individual circuit modeled on the circuit is compared with the emulation result. A third step of converting the format of the output file indicating the second verification result into a file format that can be handled by the verification by the logical verification system;
17. The method according to claim 16, wherein the first step compares a verification result indicated by an output file converted by the third step with the emulation result. 17. The circuit model generation method according to claim 16, wherein the individual circuit is a memory circuit that performs substantially the same operation as a target memory by using a substitute memory. An individual circuit modeled on a logic verification system for verifying a logical operation of a target circuit, the circuit generating a model of the individual circuit configured to operate substantially equivalent to the target circuit using a substitute. A model generation device,
A logic verification unit that acquires an emulation result that is a verification result by the logic verification system;
A second verification unit that obtains a second verification result that is a verification result by a verification method different from the verification method by the logical verification system;
A first step of comparing the emulation result obtained by the logic verification unit with the second verification result obtained by the second verification unit; and A verification result comparison unit that performs a second step of determining whether or not the circuit performs the same operation as the corresponding original circuit;
Refer to the comparison result of the verification result comparison unit in the first step, on condition that the judgment result in the second step in the verification result comparison unit indicates that the same operation as in the original circuit is not performed. And a control unit that corrects the model of the individual circuit modeled on the logic verification system and controls the corrected model to repeat the first step and the second step. A circuit model generation device characterized by the above-mentioned. The verification result comparison unit may include, as the first step, a system level simulation result and a function description of the individual circuit modeled on the target circuit designed in a system level language, as the second verification result 21. The circuit according to claim 20, wherein the emulation result is compared with at least one of simulation results of a function description language level of the individual circuit modeled on the target circuit created in a language. Model generator. A file conversion unit that converts a format of an output file indicating the second verification result into a file format that can be handled by verification by the logical verification system;
21. The circuit model according to claim 20, wherein the verification result comparison unit compares, as the first step, a verification result indicated by an output file converted by the file conversion unit with the emulation result. Generator.

Images