JP2004172417A - Manufacturing method for semiconductor device and polishing tool - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device and a polishing method wherein a device formation region on a semiconductor substrate in which region any transistor is formed prevents any scratch or any damage from occurring therein or thereon. <P>SOLUTION: In a process of previously protecting the device formation region with a thin protective film 10 upon forming a shallow trench portion 20 serving as a device isolation region in the semiconductor substrate 1, the protective film 10 comprises a harder material than a nitrided film (Si<SB>3</SB>N<SB>4</SB>). Besides the nitrided film, there may be effective TiAlN, TiC, TiCN, DLC(diamond like carbon), and BN. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a material of a protective film used in an STI forming step is improved and a polishing method used in an STI forming step.
[0002]
[Prior art]
In recent years, as the degree of integration of semiconductor devices has increased, circuit wiring has become finer, and the distance between wirings has become smaller. In particular, in the case of optical lithography having a line width of 0.5 μm or less, the depth of focus becomes shallow, so that the imaging surface of the stepper needs to be flat. As one means for flattening the surface of such a semiconductor wafer, a polishing apparatus that performs chemical mechanical polishing (CMP) is known.
[0003]
This type of chemical mechanical polishing (CMP) apparatus includes a polishing table having a polishing pad on an upper surface and a top ring. Then, an object to be polished is interposed between the polishing table and the top ring, and while the polishing liquid (slurry) is supplied to the surface of the polishing pad, the object to be polished is pressed by the top ring to the polishing table, and The surface of the object is polished flat and mirror-like.
[0004]
Such a CMP apparatus is used, for example, in an STI (Shallow Trench Isolation) forming process for forming a transistor circuit in the lowermost layer of a semiconductor device. 5A to 5F are schematic cross-sectional views showing an example of the STI forming step and the transistor forming step. A nitride film 110 (generally a silicon nitride film Si) is formed in an element formation region on the silicon substrate 100.₃N₄(See FIG. 5A), and the silicon substrate 100 is dry-etched (Reactive Ion Etching (RIE)) using the nitride film 110 as a mask to form a shallow trench (shallow groove) 120, that is, an element isolation region. (See FIG. 5B). The Si exposed in the trench is thermally oxidized to form SiO₂Form a thin film. Next, a silicon oxide film 130 as an insulating material is embedded in the trench 120 by CVD (FIG. 5C).
[0005]
When the silicon oxide film 130 is buried in the trench 120, as shown in FIG. 5C, an extra silicon oxide film 130 remains on the outer peripheral surface of the trench, and this extra silicon oxide film 130 is polished by polishing. Then, the surface of the nitride film 110 is exposed (see FIG. 5D). Next, the nitride film 110 is removed by wet etching to form a groove 130a of a silicon oxide film (see FIG. 5E), and a transistor 140 is formed in the element formation region through the groove 130a of the silicon oxide film. (See FIG. 5F).
[0006]
In such an STI forming step, the purpose of the polishing step using CMP is to completely remove an excess silicon oxide film formed on the nitride film as described above. Incomplete removal of the silicon oxide film hinders subsequent etching of the nitride film.
[0007]
Conventionally, in the above-mentioned polishing in the STI forming step, a polyurethane-based polishing pad and a slurry in which silica abrasive grains are dispersed are used as polishing members, and the semiconductor wafer is moved while the polishing pad and the semiconductor wafer are relatively moved. A method has been employed in which a polishing pad is pressed to a predetermined thickness while supplying a slurry to the polishing pad. However, this method has the following problems.
(1) Since the nitride film is less polished than the silicon oxide film, as shown in FIG. 6, the silicon oxide film 130 is polished too much compared to the nitride film 110, and dishing occurs. That is, it is difficult to control the remaining thickness of the silicon oxide film.
(2) Unevenness occurs in polishing of the nitride film, and it is not possible to obtain sufficient in-plane uniformity on the nitride film. That is, it is difficult to control the remaining film thickness of the nitride film.
[0008]
[Problems to be solved by the invention]
As a countermeasure against the above-mentioned problem, a polyurethane polishing pad is used as a polishing tool, and ceria abrasive (CeO) is used as a polishing liquid.₂) Is used, and a method of polishing the above-mentioned semiconductor wafer while using a slurry in which a high concentration of a surfactant is added in a very small amount is used. The polishing principle of this method is described below.
a) Anionic surfactant adheres to the ceria abrasive grain surface (the ceria abrasive grain surface has a positive charge) and also adheres to the nitride film surface (the nitride film surface also has a positive charge).
b) Both the ceria abrasive and the nitride film are covered with an anionic surfactant. Since both surfaces have the same charge and repel each other, the ceria abrasive grains are difficult to approach the nitride film surface. Therefore, the polishing rate of the nitride film becomes extremely low.
c) Since the nitride film acts as a stopper, the unevenness of the oxide film is corrected, and the in-plane uniformity of the entire semiconductor wafer is uniformed.
d) Since the polishing of the nitride film does not proceed, the polishing rate of the oxide film in the trench portion also decreases. Therefore, dishing is suppressed.
[0009]
By applying this method, the problems of dishing and the remaining film thickness have been improved as compared to the past (500 ° for silica slurry, 200 to 300 ° for ceria slurry). However, the dishing level was not satisfactory because a polishing pad was used as a polishing tool. In addition, the problem of scratching has newly emerged.
[0010]
To improve dishing, it is necessary to harden the pad. As a method therefor, application of a fixed abrasive pad (or fixed abrasive) has been attempted. The fixed abrasive pad is a pad in which fine abrasive grains are held by a resin and hardened into a pad shape. Since this pad is harder than a generally used polyurethane polishing pad, it is excellent in step characteristics. Ceria (CeO)₂When the wafer on which the STI was formed was polished while adding an anionic surfactant to the fixed abrasive pad on which the abrasive grains were fixed, dishing (see FIG. 6) performance and residual film variation were remarkable as shown below. To be improved. It can fully cope with the specification that the technical node is required to be 100 nm or less.
・ Dishing amount: 100kg or less
・ Nitride film variation: 50mm or less
[0011]
However, the problem that scratches occur also occurs here, and some of the scratches are quite deep. Generation of scratches is considered to be mainly caused by generation of coarse particles due to dressing of the surface of the fixed abrasive (or the fixed abrasive pad). Further, it is considered that the deep scratch occurs because the pad is hard.
[0012]
Deep scratches generated in a polishing process using fixed abrasive grains (or fixed abrasive pads) often occur on a nitride film (that is, an element formation region), and some scratches penetrate the nitride film. The polishing process in the STI forming process is a pre-process for forming a transistor on a semiconductor substrate. Scratch generated in an element formation region where a transistor is formed affects the yield of a device. In particular, if the underlying silicon substrate is damaged by penetrating the nitride film, a transistor circuit can no longer be formed in that region. Therefore, the scratch on the nitride film (that is, the element formation region) must be so shallow that it does not penetrate the nitride film even if it occurs.
[0013]
The present invention has been made in view of such problems of the related art, and provides a manufacturing method and a polishing method of a semiconductor device which does not cause scratching or damage in an element forming region for forming a transistor of a semiconductor substrate. Aim.
[0014]
[Means for Solving the Problems]
In the step of removing the excess silicon oxide film by the above-described CMP and exposing the surface of the nitride film which is the protective film, in order to suppress the generation of the scratch of the protective film, the present inventors considered the cause of the generation of the scratch, As a result of diligent research into such reduction measures, the present invention has been made. This will be described below.
(1) Cause of scratch occurrence
The cause of scratch generation is mainly due to coarse particles contained in the slurry (polishing liquid). The coarse particles are originally contained in the slurry, or are fine abrasive particles that are aggregated and coarsened by physical or chemical action.
Ceria slurry generally has a particle size of about 0.2 μm, which is slightly larger than silica slurry. Ceria abrasive grains are produced by repeatedly refining and classifying a raw material containing a large amount of impurities. However, due to the problem of classification accuracy, there is a high probability that minute amounts of coarse particles are included even in the final stage of production. In addition, at the use stage, since a high concentration of a surfactant is added, the abrasive grains are likely to aggregate. When these coarse particles enter the polishing interface, the wafer surface is surely scratched.
[0015]
Ceria abrasive grains are contained in the fixed abrasive grains for STI polishing, but since the surfactant used is at a low concentration, the aggregation phenomenon such as ceria slurry hardly occurs. It is considered that the generation of scratches when using fixed abrasive grains is mainly caused by the generation of coarse particles due to dressing of the surface of the fixed abrasive grains. Further, it is considered that a deep scratch occurs because the pad (the fixed abrasive grains itself) is hard.
[0016]
Deep scratches generated in the polishing process using fixed abrasive grains are often generated mainly on the nitride film (that is, the element formation region), and some of the scratches penetrate the nitride film. The polishing process in the STI forming process is a pre-process for forming a transistor on a semiconductor substrate. Scratch generated in an element formation region where a transistor is formed affects the yield of a device. In particular, if the underlying silicon substrate is damaged by penetrating the nitride film, a transistor circuit can no longer be formed in that region. Therefore, the scratch on the nitride film (that is, the element formation region) must be so shallow that it does not penetrate the nitride film even if it occurs.
[0017]
(2) Measures to reduce scratches
The three performances required for the CMP used in the STI forming step are: a) less dishing, b) less variation in remaining film thickness, and c) less scratching. If a polishing process using fixed abrasives is applied, the performances of a) and b) can be reliably cleared. As measures to clear c), “improvement of fixed abrasive grains” and “nitride film (Si₃N₄Application of hard material instead of)).
[0018]
(1) Improvement of fixed abrasive
Improvement of fixed abrasive mainly means improvement of constituent materials. In general, fixed abrasives require dressing of the surface of the fixed abrasive, which is called dressing, in order to ensure a stable polishing rate. For dressing, a so-called dresser in which a large number of diamond particles having a size of about 100 μm are electrodeposited on a plate surface is usually used. When dressing is performed, fine abrasive grains are released from the surface of the fixed abrasive grains, but coarse particles are also released at the same time. These coarse particles are considered to be the main cause of scratch generation.
[0019]
In order to suppress the generation of coarse particles, it is necessary to stably secure the polishing rate without dressing with a diamond dresser. The reason why the polishing rate cannot be secured without dressing is that the abrasive grains are firmly held by the resin inside the fixed abrasive grains. In other words, if the resin holding force is weakened, there is a possibility that the polishing rate can be stably secured without dressing.
[0020]
As the composition of the fixed abrasive having such characteristics, those having a low binder ratio (40 vol% or less), those having a high porosity (30 vol% or more), and those having a high abrasive ratio (30 vol% or more) are used. desirable. As the resin material, a resin material having extremely low abrasive grain holding power is suitable, and for example, PVA, polyester, urethane, or the like is preferable. Such a fixed abrasive can ensure a stable polishing rate without dressing with a diamond dresser.
[0021]
In addition, a fixed abrasive containing a resin whose binding force is weakened by a chemical solution such as an alkali solution, a photosensitizer resin such as benzophenone having an action of weakening the binding force of the resin by light irradiation of a specific wavelength such as UV light. Including fixed abrasive grains, fixed abrasive grains containing a photo-degradable resin whose bonding force weakens when irradiated with light of a specific wavelength such as UV light, or a so-called photocatalytic action that develops oxidizing power or reducing power when irradiated with light of a specific wavelength It is considered that a fixed abrasive containing the material having the above is effective. These can also ensure a stable polishing rate without dressing with a diamond dresser.
[0022]
(2) Nitride film (Si₃N₄Application of hard material instead of)
Generation of scratches in the polishing process using fixed abrasive grains is considered to be mainly caused by the generation of coarse particles due to dressing of the surface of the fixed abrasive grains. Further, it is considered that a deep scratch occurs due to the hard pad.
Deep scratches generated in the polishing process using fixed abrasive grains are often generated mainly on the nitride film (that is, the element formation region), and some of the scratches penetrate the nitride film. The polishing process in the STI forming process is a pre-process for forming a transistor on a semiconductor substrate. Scratch generated in an element formation region where a transistor is formed affects the yield of a device. In particular, if the underlying silicon substrate is damaged by penetrating the nitride film, a transistor circuit can no longer be formed in that region. Therefore, the scratch on the nitride film (that is, the element formation region) must be so shallow that it does not penetrate the nitride film even if it occurs.
As described in (1), in order to suppress the occurrence of scratches, it is necessary to realize fixed abrasive grains that do not require a diamond dresser, but there are many technical issues to be solved, At present, there is a limit to the reduction of scratches from the surface.₃N₄) Was studied for the application of a hard material instead.
[0023]
In the STI forming step, a nitride film (Si) is formed as a thin film formed on the surface of the element forming region.₃N₄) Is used. Nitride film (Si₃N₄) Is a material that has been used for a long time as a device constituent material, but is mainly used in the STI forming process for the following three reasons.
i) It functions as a mask material when dry etching (RIE) the silicon substrate.
ii) It functions as a stopper material for CMP polishing.
iii) The surface on which the transistor is formed is protected from scratches generated by CMP.
Among them, the most important function is iii), that is, the main purpose of the nitride film is to protect the element formation region.
[0024]
The present inventor paid attention to the purpose of protecting the element formation region, and further improved the protection function by using a harder material than the nitride film for the material for protecting the element formation region, thereby suppressing the number of scratches generated in this region. The present inventors have found that there is a possibility that the depth of the scratch can be reduced, and have invented the present invention.
[0025]
In one embodiment of the method for manufacturing a semiconductor device of the present invention, in forming a shallow groove serving as an element isolation region in a semiconductor substrate, the element formation region is protected by a thin protective film in advance. (Si₃N₄) Is made of a material that is harder than
As a material harder than the nitride film, a SiC thin film is effective. In addition, TiAlN, TiC, TiCN, DLC (diamond-like carbon), BN and the like are also effective.
[0026]
The hardness (micro Vickers hardness HV) of each of the above materials is shown below.
・ Si₃N₄(Nitride film): hardness 1800 to 2000 (kg / mm²)
-SiC: 3000-3500 (kg / mm²)
・ TiAlN: 3500 to 4000 (kg / mm²)
・ TiC: 3000 to 3200 (kg / mm²)
-TiCN: 3000 to 3200 (kg / mm²)
-DLC (diamond-like carbon): 2000-4000 (kg / mm²)
Among the above materials, SiC is expected to be used as a hard mask material for covering and protecting a so-called Low-k material used as an insulating film for forming a Cu wiring. It is thought that the frequency of use as a device constituent material will increase in the future, and versatility will increase.
[0027]
Another aspect of the method for manufacturing a semiconductor device according to the present invention is a method of forming a shallow groove serving as an element isolation region in a semiconductor substrate, wherein the element formation region is protected by a thin protective film in advance. Film (Si₃N₄) And a thin film made of a material harder than the nitride film.
In the two-layer structure in the above embodiment, the nitride film (Si₃N₄) Is preferably disposed in the lower layer as any of hard materials such as SiC, TiAlN, TiC, TiCN, DLC (diamond-like carbon), and BN.
[0028]
In the method of polishing a semiconductor wafer according to the present invention, when forming a shallow groove serving as an element isolation region in a semiconductor substrate, an STI forming step of protecting an element formation region with a protective film in advance and embedding an oxide film in the formed shallow groove is provided. Wherein the protective film is made of a material harder than a nitride film, and an excess oxide film formed on the protective film is polished and removed with fixed abrasive grains.
The polishing tool for a semiconductor wafer of the present invention is a polishing tool used for the method for polishing a semiconductor wafer, wherein the fixed abrasive grains are composed of abrasive grains and a binder for fixing the abrasive grains, and the abrasive grains are formed of a protective film. Also, it is characterized by being made of a soft material.
[0029]
As described above, the nitride film has a feature that functions as a stopper material when polishing by CMP. This function is exhibited by the effect of adsorbing the surfactant to the surface of the nitride film. Although it is expressed even in the above-mentioned hard materials, the nitride film appears more remarkably. As a method of protecting the Si substrate while utilizing the characteristics of the nitride film, a two-layer structure can be considered. For example, the configuration is such that a nitride film is disposed as an upper layer, and a hard material (such as SiC, TiAlN, TiC, TiCN, DLC (diamond-like carbon), or BN) is disposed as a lower layer. In order to make use of the stopper function of the nitride film, it is desirable to arrange the nitride film in an upper layer. The film thickness is desirably “nitride film (upper layer)> hard material (lower layer)”. A material harder than a nitride film is not easily removed by polishing or etching. Therefore, it is desirable that the protection film in the element formation region is mainly formed of a nitride film, and the lower hard film is as thin as possible. For example, the thickness of the hard film is preferably 50 nm or less.
[0030]
CMP is used to remove an excess oxide film after the trench is filled with an oxide film. As a removing method, a fixed abrasive pad (fixed abrasive) having excellent dishing characteristics and remaining film range characteristics is preferable. . Further, the abrasive used for the fixed abrasive pad is preferably made of a material softer than the protective film. For example, CeO₂, SiO₂, BaCO₃, CaCO₃, ZrO₂And so on. Comparing with 10-step Mohs hardness, SiO₂= 7, CeO₂= 6 and SiC = 9, so those having a Mohs' hardness of 7 or less are preferable. By the way, when compared with Vickers hardness, materials having a Mohs 'hardness of 6 to 7 are about 500 to 800, and materials having a Mohs' hardness of 9 are about 1500 to 6000. SiC is SiO₂And CeO₂About four times harder.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
1A to 1F are schematic cross-sectional views showing an example of an STI formation and transistor manufacturing process using the semiconductor device manufacturing method according to the present invention. A protection film 10 made of silicon carbide (SiC) is formed in an element formation region on the silicon substrate 1 by using a CVD (Chemical Vapor Deposition) method (see FIG. 1A), and the protection film 10 made of the silicon carbide is formed. Is used as a mask to dry-etch (Reactive Ion Etching (RIE)) the silicon substrate 1 to form a shallow trench (shallow groove) 20, that is, an element isolation region (see FIG. 1B). The Si exposed in the trench is thermally oxidized to form SiO₂Form a thin film. Next, a silicon oxide film 30 as an insulating material is buried in the trench 20 by a CVD method (FIG. 1C).
[0032]
When the silicon oxide film 30 is buried in the trench 20, as shown in FIG. 1C, an extra silicon oxide film 30 remains on the outer peripheral surface of the trench, and this extra silicon oxide film 30 is polished by polishing. After removal, the surface of the protective film 10 made of silicon carbide is exposed (see FIG. 1D). Next, the protective film 10 made of silicon carbide is removed by wet etching or the like to form a groove 30a of a silicon oxide film (see FIG. 1E), and an element is formed through the groove 30a of the silicon oxide film. The transistor 40 is formed in the region (see FIG. 1F). As the protective film 10, a nitride film (Si₃N₄Any material may be used as long as it is harder than silicon carbide, and TiAlN, TiC, TiCN, DLC (diamond-like carbon), BN, or the like may be used instead of silicon carbide.
[0033]
In such an STI forming step, the purpose of the polishing step using CMP is to completely remove an excess silicon oxide film formed on the protective film made of silicon carbide. If the removal of the silicon oxide film is incomplete, the subsequent etching of the protective film made of silicon carbide or the like is hindered.
[0034]
Next, a polishing apparatus used in the polishing step by CMP of the present invention will be described with reference to FIG. FIG. 2A is a schematic elevation view of the polishing apparatus, and FIG. 2B is a plan view showing a main part of the polishing apparatus. As shown in FIGS. 2A and 2B, the polishing apparatus includes a polishing table 50 and a semiconductor wafer having a protective film 10 formed on a silicon substrate 1 and a silicon oxide film 30 formed on the protective film 10. The polishing apparatus includes a top ring 51 for holding the wafer W and polishing the semiconductor wafer W while pressing the semiconductor wafer W against a polishing surface on an upper surface of the polishing table 50, and a polishing liquid supply nozzle 52 for supplying a polishing liquid to the polishing table 50. . The polishing apparatus also includes an atomizer 53 having a plurality of injection nozzles (not shown) connected to a nitrogen gas supply source and a liquid supply source, and a dresser 54 for dressing the polishing table 50. .
[0035]
As shown in FIG. 2A, the top ring 51 is suspended from a top ring head 56 by a rotatable top ring drive shaft 55. The top ring head 56 is supported by a swinging shaft 57 that can be positioned, and the swinging shaft 57 causes the top ring 51 to move between a polishing position on the polishing table 50 and a transfer position for transferring a semiconductor wafer. It is possible. The dresser 54 is suspended from a dresser head 66 by a rotatable dresser drive shaft 65. The dresser head 66 is supported by a swing shaft 67 that can be positioned, and the swing shaft 67 allows the dresser 54 to move between a dresser position on the polishing table 50 and a standby position.
[0036]
The upper surface of the polishing table 50 is constituted by fixed abrasive grains (or fixed abrasive pad) 50a in which abrasive grains and pores or pore agents are combined by a binder (resin). A polished surface for polishing the semiconductor wafer W held on the substrate is formed. Such a fixed abrasive 50a is spray-dried, for example, by mixing and dispersing a mixed liquid obtained by mixing and dispersing a slurry-like abrasive (a dispersion of abrasives in a liquid) and an emulsion resin. And heat-treated with pressure. As the abrasive, preferably, ceria (CeO) having an average particle diameter of 0.5 μm or less is used.₂) Or silica (SiO₂) Or barium carbonate (BaCO)₃) Or calcium carbonate (CaCO₃) Or zirconium oxide (ZrO). Further, the abrasive raw material may be either a powder raw material or a slurry raw material, but in order to produce a uniform fixed abrasive, it is desirable to use a slurry-like abrasive which is stably present as fine abrasive. More preferably, it is desirable to use abrasive grains having a particle size of 10 nm or more and 10 μm or less. Further, in order to obtain a polishing tool for semiconductor processing, it is desirable to minimize the amount of metal contained in the abrasive raw material as much as possible.
[0037]
Further, a thermoplastic resin or a thermosetting resin can be used as the binder. As the thermoplastic resin, in the case of addition polymerization, vinyl resins such as polyethylene resin, polypropylene resin, polybutadiene resin, polyvinyl chloride resin, polystyrene resin, polyvinylidene chloride resin, fluorine resin, acrylic resin, etc. Resins based on monomers can be exemplified, polycondensation systems include polyamide resins, polyester resins, polycarbonate resins, polyphenylene oxide resins, and the like, and polyaddition systems can include thermoplastic polyurethane resins. In the ring-opening polymerization system, a polyacetal resin can be exemplified. Examples of the thermosetting resin include PVA, polyester, and urethane.
[0038]
Fixed abrasive grains are composed of abrasive grains, a binder, and pores. As the binder, the thermoplastic resin of the present invention is mainly used. The composition ratio of fixed abrasive grains (ratio of abrasive grain rate (Vg), binder rate (Vb), and porosity (Vp): vol%) is, for example,
Abrasive grain ratio (Vg): binder ratio (Vb): porosity (Vp) = 35: 55: 10 (vol%)
It is. The composition ratio of fixed abrasive grains (ratio of abrasive rate (Vg), binder rate (Vb), and porosity (Vp): vol%) is generally
10% <Abrasive grain ratio (Vg) <50%,
0% <binder rate (Vb) <80%,
0% <porosity (Vp) <50%
And
Abrasive grain ratio (Vg)> 30%,
Binder ratio (Vb) <50%,
Porosity (Vp)> 10%
Is desirable.
[0039]
Next, the step of polishing a semiconductor wafer in the STI forming step using the polishing apparatus of the present invention will be described. For example, in the case of a low pattern density or a film quality (such as a BPSG film) that is easily shaved, dishing of the silicon oxide film in the trench portion easily progresses because the polishing reaches a protective film 10 (see FIG. 1) in a short time. In such a case, the following ex-situ dressing is employed.
[0040]
1) ex-situ dressing
While rotating the polishing table 50 and the dresser 54 respectively, the dresser 54 is pressed against the polishing table 50 to dress the fixed abrasive grains 50a. At this time, a mixed solution of DIW (deionized water (pure water)) and nitrogen gas is sprayed from the atomizer 53 toward the fixed abrasive grains 50a.
[0041]
2) Polishing
FIG. 3 is a schematic diagram showing a main part of the polishing apparatus shown in FIG. As shown in FIG. 3, the semiconductor wafer W is pressed against the polishing table 50 while rotating the polishing table 50 and the top ring 51 as indicated by arrows, until the silicon oxide film of the semiconductor wafer W reaches the protective film 10. Polish (see FIG. 1D). In this case, the abrasive grains of the fixed abrasive grains 50a on the polishing table 50 are ceria (CeO).₂) The case of particles is described. At this time, a polishing liquid containing an anionic surfactant and containing no abrasive is supplied from the polishing liquid supply nozzle 52 onto the fixed abrasive 50a. The concentration of the supplied anionic surfactant is preferably 0.001% to 5%, and the pH is preferably 5 to 10. The anionic surfactant is COO^―Group or SO₃ ^―It is preferable to include an organic compound having a hydrophilic group.
[0042]
As described above, by polishing while supplying a polishing liquid containing an anionic surfactant and containing no abrasive grains onto the fixed abrasive grains 50a, the anionic surfactant adheres to the surface of the ceria abrasive grains (ceria). The surface of the abrasive grains is positively charged, and also adheres to the surface of the protective film 10 (the surface of the nitride film is also positively charged), and both the ceria abrasive and the protective film are covered with an anionic surfactant. Since both surfaces have the same charge and repel each other, the ceria abrasive grains are less likely to approach the surface of the protective film. Therefore, the polishing rate of the protective film becomes extremely low, and as described above, the protective film 10 can function as a polishing stopper. Accordingly, the polishing rate of the protective film 10 can be reduced to obtain in-plane uniformity on the protective film 10 and to suppress dishing, thereby realizing polishing with less scratches and high flatness.
[0043]
3) Water polishing
After the polishing is completed, the semiconductor wafer is pressed against the polishing table 50 and water-polished while rotating the polishing table 50 and the top ring 51 respectively. At this time, the polishing liquid or DIW is supplied from the polishing liquid supply nozzle 52 onto the fixed abrasive grains 50a.
[0044]
As described above, the above-described ex-situ dressing is employed when polishing a wafer which is easy to be polished and has a high polishing rate. For this purpose, the in-situ dressing described below is employed. In the following description, portions overlapping with the above-described example will be omitted as appropriate.
[0045]
1) In-situ dressing polishing
The semiconductor wafer W is polished while dressing the fixed abrasive grains 50a while rotating the polishing table 50, the dresser 54, and the top ring 51, respectively. At this time, pure water or an alkaline liquid is supplied from the polishing liquid supply nozzle 52 onto the fixed abrasive grains 50a, and a mixed liquid of DIW and nitrogen gas is jetted from the atomizer 53 onto the fixed abrasive grains 50a. Thereafter, for example, when the thickness of the silicon oxide film on the protective film 10 becomes 1000 ° or less, the dressing by the dresser 54 is stopped, and the polishing of the semiconductor wafer is continued. At this time, a polishing liquid containing an anionic surfactant and containing no abrasive grains is supplied from the polishing liquid supply nozzle 52. That is, polishing (in-situ dressing) is performed while dressing is performed immediately before reaching the protective film 10 of the semiconductor wafer (the remaining film of the silicon oxide film on the protective film is about 1000 °), and then dressing is performed until reaching the protective film. Is stopped and polishing is continued. This allows the protective film to function as a polishing stopper, as described above. Therefore, the polishing rate of the protective film can be reduced to obtain in-plane uniformity on the protective film, and dishing can be suppressed, so that polishing with less scratches and high flatness can be realized.
[0046]
2) Water polishing
After the polishing is completed, the semiconductor wafer W is pressed against the polishing table 50 and water-polished while rotating the polishing table 50 and the top ring 51 respectively. At this time, the polishing liquid or DIW is supplied from the polishing liquid supply nozzle 52 onto the fixed abrasive grains 50a.
[0047]
In the above-described example, a case was described in which the protective film 10 was used as a polishing stopper by polishing while supplying a polishing liquid containing an anionic surfactant and containing no abrasive grains onto the fixed abrasive grains 50a. If the protective film needs to be shaved, a polishing liquid made of a cationic surfactant and containing no abrasive grains may be supplied onto the fixed abrasive grains 50a to continue the polishing. The cationic surfactant may include an organic compound having any of an aliphatic amine salt, an aliphatic quaternary ammonium salt, a benzalkonium salt, a benzethonium chloride, a pyridinium salt, and an imidazolinium salt. preferable.
[0048]
Although not shown in FIG. 2, the semiconductor wafer polished by the fixed abrasive grains 50a as described above is moved to a polishing table provided adjacent to the polishing table 50, where buff cleaning is performed. Be done. That is, the semiconductor wafer W after polishing held by the top ring 51 is pressed against a soft polishing cloth on the polishing table while independently rotating the top ring 51 and a polishing table installed adjacent to the top ring 51. At this time, a liquid not containing abrasive grains, for example, pure water or an alkaline liquid, preferably an alkaline liquid having a pH of 9 or more or an alkaline liquid containing TMAH (tetramethylammonium hydroxide) is supplied to the polishing cloth from a cleaning liquid supply nozzle (not shown). As a result, abrasive grains attached to the surface of the polished semiconductor wafer can be effectively removed.
[0049]
In addition, instead of the buff cleaning, DHF cleaning may be performed on the semiconductor wafer in a cleaning machine (not shown). After the buff cleaning and the DHF cleaning, the surface of the semiconductor wafer may be cleaned with a pencil-type sponge made of, for example, a PVF material or a PVA material. Further, after the polishing by the fixed abrasive grains 50a, the finish polishing of the semiconductor wafer may be performed. This finish polishing may be performed on the polishing table 50, or may be performed on a polishing table (not shown) installed adjacent to the polishing table 50. In any case, finish polishing is performed using a polishing liquid containing abrasive grains, and after the finish polishing, the above-described water polishing step and cleaning step (buff cleaning or DHF cleaning) are performed.
[0050]
Next, another embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
4A to 4G are schematic cross-sectional views showing an example of an STI forming and transistor manufacturing process using the semiconductor device manufacturing method according to the present invention. A first protection film 10 made of silicon carbide (SiC) is formed in an element formation region on the silicon substrate 1 by using a CVD method or the like (see FIG. 4A), and a CVD method is further formed on the first protection film 10. Is used to form a second protective film 11 made of a nitride film (see FIG. 4B). Then, using the second protective film 11 as a mask, the silicon substrate 1 is dry-etched (RIE) to form a shallow trench (shallow groove) 20, that is, an element isolation region (see FIG. 4C). The Si exposed in the trench is thermally oxidized to form SiO₂Form a thin film. Next, a silicon oxide film 30 as an insulating material is buried in the trench 20 by a CVD method (FIG. 4D).
[0051]
When the silicon oxide film 30 is buried in the trench 20, as shown in FIG. 4D, the extra silicon oxide film 30 remains on the outer peripheral surface of the trench. Then, the surface of the second protective film 11 is exposed (see FIG. 4E). Next, the second protective film 11 made of a nitride film and the first protective film 10 made of silicon carbide are removed by wet etching or the like to form a groove 30a of a silicon oxide film (see FIG. 4F). The transistor 40 is formed in the element forming region via the silicon oxide film groove 30a (see FIG. 4G). As the first protective film 10, a nitride film (Si₃N₄Any material may be used as long as it is harder than silicon carbide, and TiAlN, TiC, TiCN, DLC (diamond-like carbon), BN, or the like may be used instead of silicon carbide.
[0052]
As described above, the nitride film has a property of functioning as a stopper material when polishing by CMP. This function is caused by the effect of adsorbing the surfactant to the surface of the nitride film. Even if a hard material such as SiC is used, the function as the stopper material is of course exhibited, but the function as the stopper material appears more remarkably in the nitride film. As a method of protecting the semiconductor substrate while utilizing the characteristics of the nitride film, a two-layer structure shown in FIG. 4B is employed. That is, the second protective film 11 made of a nitride film is disposed as an upper layer, and the first protective film 10 made of a hard material (such as SiC, TiAlN, TiC, TiCN, DLC (diamond-like carbon), or BN) is disposed as a lower layer. is there. In order to make use of the stopper function of the nitride film, it is desirable to arrange the nitride film in an upper layer. It is desirable that the thickness of the nitride film is larger than the thickness of the hard film. A material harder than a nitride film is not easily removed by polishing or etching. Therefore, it is desirable that the protective film in the element formation region is mainly formed of a nitride film, and the lower hard film is as thin as possible. For example, the thickness of the lower hard film is preferably 50 nm or less. The polishing process by CMP in the embodiment shown in FIG. 4 is the same as that in the embodiment shown in FIG.
[0053]
In any of the polishing steps, management of the polishing end point is performed by the following method.
(1) Management by polishing time
(2) Light (single wavelength light or light having a spectral distribution) through an optical window embedded in a polishing table is incident on the surface to be polished, or light is incident on the surface to be polished by other means, Management of reflected light and interference light by data processing
(3) Management by changing the driving state of driving means such as a motor for driving a polishing table and a polishing belt (not shown).
(4) Management by changing the state of metals and conductive substances using an eddy current sensor mounted on a polishing table or top ring
It is also conceivable to control the polishing end point by the above (1) to (4) and the like, and to control the polishing by changing the polishing conditions (polishing pressure, top ring rotation speed, etc.) from the information of the end point and the remaining film. .
[0054]
【The invention's effect】
As described above, according to the present invention, a material harder than a nitride film, for example, SiC, TiAlN, TiC, TiCN, DLC (diamond-like carbon), or BN is used as a protective film in an element formation region for forming a transistor circuit. By using any of these methods, it is possible to realize polishing with high flatness without causing scratches or damage in the element formation region after CMP.
[Brief description of the drawings]
FIGS. 1A to 1F are schematic cross-sectional views showing an example of an STI formation and transistor manufacturing process using a semiconductor device manufacturing method according to the present invention.
FIG. 2 is a view showing a polishing apparatus used in a polishing step by CMP of the present invention, FIG. 2 (a) is a schematic elevation view of the polishing apparatus, and FIG. 2 (b) is an essential part of the polishing apparatus. It is a top view.
FIG. 3 is a schematic diagram showing a main part of the polishing apparatus shown in FIG. 2;
FIGS. 4A to 4G are schematic cross-sectional views showing another example of an STI forming and transistor manufacturing process using the semiconductor device manufacturing method according to the present invention.
FIGS. 5A to 5F are schematic diagrams showing an example of an STI forming process.
FIG. 6 is a schematic diagram illustrating dishing when a conventional polishing apparatus is used.
[Explanation of symbols]
1 Silicon substrate
10 Protective film (first protective film)
11 Second protective film
20 trench (shallow groove)
30 Silicon oxide film
30a Groove of silicon oxide film
40 transistors
50 polishing table
50a fixed abrasive
51 Top Ring
52 polishing liquid supply nozzle
53 Atomizer
54 Dresser
55 Top ring drive shaft
56 Top Ring Head
57,67 swing axis
65 Dresser drive shaft
66 Dresser head
W semiconductor wafer

Claims (13)

In forming a shallow groove serving as an element isolation region in a semiconductor substrate, in a step of protecting the element formation region with a thin protective film in advance, the protective film is made of a material harder than a nitride film (Si ₃ N ₄ ). A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the hard material is SiC. 2. The method according to claim 1, wherein the hard material is one of TiAlN, TiC, TiCN, DLC (diamond-like carbon), and BN. In forming a shallow groove serving as an element isolation region in a semiconductor substrate, in a step of protecting the element formation region with a thin protective film in advance, the protective film is a nitride film (Si ₃ N ₄ ) and harder than the nitride film. A method for manufacturing a semiconductor device, comprising a two-layer structure of a thin film made of a material. The method according to claim 4, wherein the hard material is SiC. 5. The method according to claim 4, wherein the hard material is one of TiAlN, TiC, TiCN, DLC (diamond-like carbon), and BN. 5. The method according to claim 4, wherein the nitride film (Si ₃ N ₄ ) is disposed in an upper layer, and a thin film made of a material harder than the nitride film is disposed in a lower layer. 5. The method according to claim 4, wherein a thickness of the nitride film is larger than a thickness of a thin film made of a material harder than the nitride film. In forming a shallow groove serving as an element isolation region in a semiconductor substrate, the element formation region is protected with a protective film in advance, and in the STI forming step of embedding an oxide film in the formed shallow groove, the protective film is formed over a nitride film. A method for polishing a semiconductor wafer, comprising a hard material, and polishing and removing an excess oxide film formed on the protective film with fixed abrasive grains. 10. The method according to claim 9, wherein the protective film comprises a thin film made of a material harder than the nitride film and a nitride film. The method for polishing a semiconductor wafer according to claim 9, wherein the hard material is any one of SiC, TiAlN, TiC, TiCN, DLC (diamond-like carbon), and BN. A polishing tool for use in the method for polishing a semiconductor wafer according to claim 9, wherein the fixed abrasive comprises an abrasive and a binder for fixing the abrasive, wherein the abrasive is protected. A polishing tool for a semiconductor wafer, comprising a material softer than a film. The abrasive _{grains CeO 2, SiO 2, BaCO 3} , CaCO 3, a semiconductor wafer polishing tool according to claim 12, wherein it is configured in one of ZrO _2.

Images