JP2004171787A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform write-in operation of a synchronous DRAM at a high speed. <P>SOLUTION: A semiconductor memory device fetching an address signal Addby responding to an external clock signal and fetching a data signal by responding to an external clock signal CLK succeeding the fetching timing of the address signal, has an address input circuit 62 fetching the address signal Add responding to the external clock signal, address decoding circuits 70, 78 decoding the address signal from an address input circuit 62, address driver circuits 74, 82 outputting the address signal from the address decoding circuits by responding to the delayed external clock signal, internal circuits 42, 44 writing the data signal in a memory cell corresponding to the address signal outputted from the address driver circuit. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a write operation such as a synchronous DRAM (Dynamic Random Access Memory) having a 2-bit prefetch function, and more particularly to a semiconductor memory device capable of shortening a write time.

  The synchronous DRAM receives an address, a control command, and the like from a system controlling the memory in synchronization with a clock, and performs internal read and write operations in synchronization with the clock. As a result, high-speed operation of the memory is enabled.

  Further, the synchronous DRAM has a burst mode function of accessing a column address given from the outside and a memory cell of a column address continuous with the column address. In this burst mode, reading or writing can be performed by accessing a memory cell having a continuous column address of 2, 4, or 8 bits corresponding to the burst length from a given column address.

  To perform this burst mode more efficiently, a 2-bit prefetch function is provided. The 2-bit prefetch function latches a given column address or a first internally generated column address, generates a second column address by adding one bit to the first column address, and generates a first and second column address. The memory cell is accessed with the column address of The memory cell array has an odd-numbered memory cell array, a corresponding column address decoder, and an output data holding circuit, and an even-numbered memory cell array, a corresponding column address decoder, and an output data holding circuit. When the first column address is an even number, the first column address is provided to the even-numbered column address decoder, and the second column address is provided to the odd-numbered column address decoder. If the first column address is an odd number, the first column address is provided to the odd-numbered column address decoder, and the second column address is provided to the even-numbered column address decoder. The odd-numbered data from the even-numbered data or the even-numbered data from the odd-numbered data is continuously output to the outside. Alternatively, in the case of writing, even-numbered data and odd-numbered data are written in order with even-numbered first column addresses, or odd-numbered data and even-numbered data are written in order with odd-numbered first column addresses.

  As described above, in a synchronous DRAM, a control signal and an address signal are generally supplied from the outside in synchronization with a clock, and various operations are performed internally in synchronization with the clock.

  However, it is necessary to externally supply write data to a data input / output terminal (DQ terminal) of the memory during a write operation. The data input / output terminal has a large load capacitance unlike the input terminal for the command signal and the address signal. The reason is that the input terminals of the command signal and the address signal are input-only terminals, so that the internal circuit is connected only to the input circuit. On the other hand, the data input / output terminal connects the output circuit together with the input circuit, and the load capacity thereof is increased.

  Therefore, the system can relatively easily apply the command signal and the address signal in synchronization with the clock. However, when a write data signal is applied to a data input / output terminal with a large load capacitance, the data signal may be rounded, so that the data signal is accurately transferred to the memory in synchronization with the rising edge or falling edge of the clock. It becomes difficult to give. In other words, a command signal or an address signal can be accurately given to a command signal or an address signal input terminal having a small input load capacitance by using a common clock as a strobe signal. However, it is difficult to provide a write data signal to the data input / output terminal having a larger input load capacity by using the same clock as the strobe signal. In addition, since the write data signal is supplied at high speed in synchronization with the rising edge and the falling edge of the clock, it becomes more difficult.

  Therefore, it has been proposed that the system side supplies a write data signal in synchronization with a data strobe signal that is asynchronous with a clock. This data strobe signal has the same frequency as the clock, but is not phase-synchronized with the clock.

  As described above, with the introduction of the data strobe signal asynchronous with the clock, it is necessary to solve the problem of how to control the internal write operation. It has not yet been proposed to perform an optimum write operation using an externally applied clock and a data strobe signal.

  Accordingly, an object of the present invention is to provide a semiconductor memory device capable of performing an optimum write operation using a clock and a data strobe signal asynchronous to the clock in order to solve the above-described conventional problem. .

  Still another object of the present invention is to provide a semiconductor memory device capable of performing the shortest write operation using a clock and a data strobe signal asynchronous to the clock.

  Another object of the present invention is to provide a semiconductor memory device capable of shortening a write operation in a memory to which a command, an address, and a write data signal are supplied in synchronization with a clock.

  In order to achieve the above object, the present invention provides a semiconductor memory device in which at least an address signal is supplied in synchronization with an external clock supplied from outside, a memory cell array having a plurality of memory cells for storing data, A data signal input circuit for holding a write data signal supplied in synchronization with an externally supplied external data strobe signal in response to an internal data strobe signal generated in response to the external data strobe signal; A write circuit that supplies a write data signal held by the data signal input circuit to the memory cell array in response to a write signal generated later than the internal data strobe signal in response to the external data strobe signal. It is characterized by.

  The above invention latches a write data signal provided in synchronization with an external data strobe signal internally in response to an internal data strobe signal generated in response to the external data strobe signal, and further comprises: In response to a write signal generated from the strobe signal, a write circuit such as a write amplifier supplies a write data signal to the memory cell array. On the other hand, the address signal is taken in by an external clock. Accordingly, since the driving of the data bus line and the like from the write amplifier to the memory cell array, which is the write operation inside the memory, is started according to the external data strobe signal, the write operation can be performed in the shortest time from the input of the write data signal. Can be finished.

  The above invention is particularly effective when the memory has a 2-bit prefetch function. That is, a 2-bit write data signal is supplied in time series in synchronization with the external data strobe signal. Since the internal write operation can be started after the input of the second write data signal, the shortest write operation can be performed.

  Further, as an internal write operation, a column address signal, a redundancy comparison result signal, and the like are provided to a corresponding column decoder of the memory cell array in response to a column selection signal generated in response to an external data strobe signal.

  In addition to the above-described invention, by causing an address signal provided in synchronization with an external clock to perform a comparison operation or the like in a redundant comparison circuit in response to an address latch signal generated in response to the external clock. In addition, the speed of the write operation can be further increased. In particular, when a 2-bit prefetch function is provided, it takes one clock period to capture a 2-bit write data signal. During that time, the comparison operation with the redundant address in the redundant comparison circuit is performed. Thus, at the point in time when the capture of the write data signal is completed, the preparation for supplying the redundant comparison result signal to the column decoder has already been completed.

  Another invention for achieving the above object is a semiconductor memory device to which at least a command signal and an address signal are supplied in synchronization with an external clock supplied from outside, wherein the semiconductor memory device is synchronized with a first clock of the external clock. The command signal and the address signal are supplied to the memory cell array having a plurality of memory cells for storing data, and a redundancy for comparing a defective address corresponding to a defective memory cell of the memory cell array with an externally applied address. A comparison circuit, and a data input for holding an externally applied write data signal in response to an internal data strobe signal generated in response to a second clock supplied after the first clock of the external clock A circuit, slower than the internal data strobe signal in response to the second clock. A write circuit that supplies a write data signal held by the data input circuit to the memory cell array in response to a write signal generated, and an address latch signal generated in response to the first clock. And an address latch circuit for supplying the address signal to the redundancy comparison circuit.

  In the above invention, in the memory to which the command, the address, and the write data signal are supplied in synchronization with the external clock, the command and the address are given in synchronization with the first clock, and the write data signal follows the first clock. When given in synchronization with the second clock, the redundancy comparison operation or the like in the redundancy comparison circuit is performed in response to the first clock. Thus, the redundant comparison operation can be performed before the input operation of the write data signal given in synchronization with the second clock is completed, and the write operation can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.

  FIG. 1 is a schematic diagram showing a relationship between a plurality of memories and a control unit that controls the memories. In this example, four SDRAMs 12, 14, 16, and 18 are connected to the control unit 10 on the system side. In this example, the command signal COMMAND and the address signal ADDRESS are applied in synchronization with the clock CLK. The write data signal is supplied to the data input / output terminal DQ in synchronization with the data strobe signal DS. By doing so, the strobe signal DS for the data input / output terminal DQ having a large load capacity can be asynchronous with the clock CLK which is the strobe signal for the command signal, the address signal, and the like, and the write data can be more reliably stored in the memory 12. ~ 18.

  FIG. 2 is a diagram showing a schematic timing chart of a write operation using the clock CLK and a data strobe signal DS asynchronous to the clock CLK. In this example, a write command is given to the command signal COMMAND and a column address is given to the address signal ADDRESS in synchronization with the clock clk1. On the other hand, the write data D0, D1, D2, and D3 are supplied to the data input / output terminal DQ in synchronization with the rising and falling edges of the data strobe signal DS.

  Although the data strobe signal DS is asynchronous with the clock CLK, it is specified by the standard that the frequency is within tDSS if the phase is advanced and within tDSH if the phase is delayed. Therefore, (a) in the figure shows the relationship between the data strobe signal DS and the write data of the data input / output terminal DQ when the phase of the data strobe signal DS is advanced by the maximum tDSS. FIG. 3B shows the relationship between the data strobe signal DS and the write data of the data input / output terminal DQ when the phase of the data strobe signal DS is delayed by a maximum of tDSH.

  In the case of (a) in the figure, the write data D0 given to the data input / output terminal DQ is fetched at the timing when a predetermined time has elapsed from the rising edge of the data strobe signal DS, and the next falling edge of the data strobe signal DS At a timing when a predetermined time has elapsed from the above, the write data D1 given to the data input / output terminal DQ is taken. Similarly, the write data D2 and D3 are also taken in synchronization with the data strobe signal DS. Therefore, the capture of the 2-bit write data D0 and D1 has already been completed at the timing of the clock clk1.5, and the input of the address has also been completed. Therefore, it is understood that the internal write operation can be started at any time.

  In the drawing, as an example, it is shown that the internal write operation starts at the timing of the clock clk2.

  On the other hand, in the case of (b) in FIG. 2, the data strobe signal DS rises at a timing delayed by the time tDSH from the timing of the clock clk1. Then, as in the case of the above (a), at a timing when a predetermined time has elapsed from the rising edge of the data strobe signal DS, the write data D0 given to the data input / output terminal DQ is taken in. The write data D1 applied to the data input / output terminal DQ is fetched at a timing when a predetermined time has elapsed from the falling edge of the data. Therefore, in this case, the input of both data D0 and D1 ends at a timing slightly earlier than the clock clk2.

  FIG. 3 is a schematic configuration diagram of the memory when the internal write operation is performed in synchronization with the clock CLK. In this example, the memory cell area includes an odd-numbered memory cell array 20 and an even-numbered memory cell array 21. Then, an odd-numbered sense amplifier 22, an even-numbered sense amplifier 23, an odd-numbered column decoder 24, and an even-numbered column decoder 25 are provided corresponding to the two memory cell arrays 20, 21, respectively.

  FIG. 3 shows a write data input circuit portion and a column address signal processing circuit portion of the peripheral circuit with respect to this memory cell array.

  FIG. 4 is a timing chart in the case where the phase of the data strobe signal DS is ahead of the reference clock by tDSS. FIG. 5 is a timing chart in the case where the phase of the data strobe signal DS is delayed from the reference clock by tDSH.

  First, the write data input circuit shown in FIG. 3 will be described. An input buffer 30 is connected to the data input / output terminal DQ, and given write data signals D0 and D1 are inputted using a reference level Vref given from outside. The capture of the write data signal is performed at the rising edge or the falling edge of the data strobe signal DS as described above. For this purpose, an externally applied data strobe signal DS is input to a buffer circuit 46, and the input internal data strobe signal int.DS is delayed by a delay circuit 48 for a predetermined time and a data strobe signal DDS. Become. Then, the delayed data strobe signal DDS is supplied to a rising edge (H-side edge) trigger circuit 50, and the rising edge trigger circuit 50 generates a first data strobe signal DSPZ that captures the first write data signal DQ. . As a result, at the timing of the first data strobe signal DSPZ, the write data signal D0 (internal write data signal int. DQ in the figure) is taken into the first data latch circuit 32.

  Further, a second data strobe signal DSPX synchronized with the falling edge of the data strobe signal DS is generated by the falling edge (L-side edge) trigger circuit 52, and the input second write data signal D1 is output by the second write strobe signal DSP1. At the timing of the second data strobe signal DSPX, it is taken into the second data latch circuit 36. At that time, the first write data signal D0 in the data latch circuit 32 is simultaneously latched by the data shift register 34. Up to this point, the operation is such that the write data signals D0 and D1 are taken in in synchronization with the data strobe signal DS.

  The first and second write data DQE1 and DQO1 latched by the data shift register 34 and the data latch circuit 36, respectively, are at the timing of the data transfer signal DQTZ synchronized with the clock generated by the transfer clock generation circuit 56, respectively. Are latched by the data transfer circuits 38 and 40 of the first embodiment. The transfer clock generation circuit 56 is supplied with a clock CLK (internal clock int.CLK in the figure) input from the buffer 54. Therefore, the data transfer signal DQTZ is generated at a timing after a predetermined time from the timing of the clock clk2 at which the capture of the two write data D0 and D1 is surely completed. As a result, the write data signal synchronized with the data strobe signal becomes a signal synchronized with the clock in the data transfer circuits 38 and 40. In this example, the first write data D0 is an example of even-numbered write data, and the second write data D1 is an example of odd-numbered write data.

  Then, at the timing of the write signal WRTZ generated by the write clock generation circuit 58, the even-numbered write amplifier 42 and the odd-numbered write amplifier 44 are activated, and a write data signal is output to the respective data buses 43 and 45.

  On the other hand, the processing part of the column address is as follows. The column address signal supplied to the column address terminal ADDRESS is taken in by the address buffer 62 at a timing synchronized with the rising edge of the clock clk1. Then, the column address signal CAxxZ (xx means an address number) fetched therein is transferred by the transfer clock generating circuit 56 to the timing control signal 65 generated at a timing delayed by a predetermined time from the timing of the clock clk1. At the timing, it is input to the internal column address latch / counter circuit 66.

  The internal column address latch / counter circuit 66 latches a given column address and generates a continuous column address by a counter function of adding +1 thereto. If the first column address is an even number, the column address is provided to an even-numbered predecoder and the like, and a second column address added by +1 is provided to an odd-numbered predecoder and the like.

  Then, the write clock generation circuit 58 generates the address generation signal ADLZ at the timing when a predetermined time has elapsed from the timing of the clock clk2, similarly to the write signal WRTZ. As a result, in response to the address generation signal ADLZ, the internal column address latch counter 66 supplies the odd-numbered column address CAxxZ1O and the even-numbered column address CAxxZ1E to the redundancy comparison circuits 68 and 78 and the predecoders 70 and 80, respectively. . Each circuit generates comparison result signals COMZO and COMZE and predecode signals PCAxxZO and PCAxxZE, respectively.

  In response to the timing signal CSZ generated by the write clock generation circuit 58, the column selection pulse generation circuit 60 generates a column selection signal CSELZ, and compares the column selection signal with the column decoders 24 and 25 at substantially the same timing as the write signal WRTZ. Drivers 72, 74, 82 and 84 are driven so as to supply result signals COMZ1O and COMZ1E and predecode signals PCAxxZ1O and PCAxxZ1E. That is, in synchronization with the timing of the clock clk2, the write signal WRT and the column selection signal CSELZ are generated, the output of the write data to the data buses 43 and 45, the predecode signal corresponding to the column address, and the redundancy comparison result. The timing of the output of the signal to the column decoder circuits 24 and 25 is adjusted.

  Therefore, in the memory shown in FIGS. 3 to 5, the write data signal is taken in synchronization with the data strobe signal DS, but the internal write operation is performed by the data transfer signal DQTZ generated in response to the timing of the clock clk2. Is controlled on the basis of

  However, as understood from the above description, it takes one cycle of the clock CLK to capture the first and second write data signals. This is because the first and second write data signals are captured at the rising edge and the falling edge of the data strobe signal DS. For this reason, it is appropriate to start the internal write operation at the timing of the clock clk2, which is one cycle after the clock clk1.

  However, as shown in FIG. 4, when the data strobe signal DS is input at an early timing, the capture of the write data D0 and D1 has already been completed at an intermediate timing between the clocks clk1.5 and clk2 in the figure. . Further, a column address is also given in synchronization with the clock clk1. In this case, waiting until the timing of the clock clk2 causes a longer write time.

  Further, generation of a column address, comparison with a redundant address, and pre-decoding are started in response to the address generation signal ADLZ, so that the column selection signal CSELZ is generated after the redundant comparison result signal and the pre-decode signal are generated. Will be delayed.

  FIG. 6 is a schematic configuration diagram of a memory in which an internal write operation is performed in synchronization with a data strobe signal according to an embodiment of the present invention. FIG. 7 is a timing chart in the case where the phase of the data strobe signal DS is ahead of the reference clock by tDSS in FIG. FIG. 8 is a timing chart in the case where the phase of the data strobe signal DS is delayed by tDSH from the reference clock in FIG.

  The memory illustrated in FIG. 6 includes a write data input circuit unit in the upper left half in the figure and a column address processing unit in the lower left half, as in the configuration of the memory in FIG. The memory cell array portion on the right side in the figure has the same configuration. Therefore, portions corresponding to those in FIG. 3 are denoted by the same reference numerals.

  In the example of the memory of FIG. 6, the write data signal DQ (D0, D1) is taken in in synchronization with the data strobe signal DS, and the internal write timing is also controlled based on the data strobe signal DS. . Specifically, the write data signals D0 and D1 from the data input / output terminal DQ are captured by the first data strobe signal DSPZ and the second data strobe signal DSPX. Further, based on the second data strobe signal DSPX, a write clock generation circuit 58 generates a write signal WRTZ for activating the write amplifiers 42 and 44, and a column selection pulse generation circuit 60 generates a column selection signal CSELZ. Is generated.

  Further, in the example of the memory of FIG. 6, the column address signal ADDRESS is taken into the inside at a timing synchronized with the clock CLK, generates an address increased by +1, and is output by the redundancy comparison circuits 68 and 78 and the predecoders 70 and 80. Is controlled.

  Therefore, as a general operation, at the timing of the clock clk1, fetching of a column address, a counter operation, a predecode operation, a redundancy comparison operation, and the like are performed. On the other hand, a write data signal is fetched at the rising edge and the falling edge of the data strobe signal DS, and an internal write operation is performed at a timing starting from the falling edge of the data strobe signal. In the internal write operation, a write data signal is output to the data bus line by activating the write amplifiers 42 and 44, and the redundant comparison result signal COMZ3 and the predecode signal PCAxxZ3 are converted into the column of the memory cell array by the column selection signal CSELZ. The data is supplied to decoders 24 and 25.

  In order to perform the above operation, in the memory shown in FIG. 6, unlike in FIG. 3, the write clock generation circuit 58 responds to the second data strobe signal DSPX generated from the data strobe signal DS in response to the write signal. Generate a WRT. Further, the column selection pulse generation circuit 60 generates a column selection signal CSELZ based on the signal CSZ generated by the write clock generation circuit 58. This is also different from FIG. Therefore, the data transfer circuits 38 and 40 in FIG. 3 do not exist in the example of FIG.

  Further, in the memory shown in FIG. 6, as compared with FIG. 3, the redundancy comparison circuits 68 and 78 and the predecoders 70 and 80 are ahead of the internal write operation at the timing of the clock timing clk1 of the clock CLK. Controlled. Therefore, the output timing of the column address CAxxZ1 by the internal column address latch / counter 66 is controlled by the address generation signal ADLZ generated by the internal clock generation circuit 90.

  The configuration and operation of FIG. 6 will be described below with reference to FIG. FIG. 7 shows a case where the data strobe signal DS has a phase earlier by the time tDDS than the clock clk1. The first write data D0 input from the data input / output terminal DQ is generated by the first data strobe signal DSPZ generated at the timing of the rising edge of the delayed data strobe signal DDS generated from the data strobe signal DS. The data is latched by the data latch circuit 32. Further, the second write data D1 is latched by the second data latch circuit 36 by the second data strobe signal DSPX generated at the timing of the subsequent falling edge of the delayed data strobe signal DDS. Then, at the timing of the second data strobe signal DSPX, the write data D0 simultaneously latched by the first data latch circuit 32 is held in the data shift register 34.

  After the timing of the second data strobe signal DSPX, the two write data signals D0 and D1 are completely latched, so that the write clock generation circuit 58 generates the write signal WRTZ in response to the signal DSPX. Further, based on signal CSZ generated by write clock generation circuit 58, column selection pulse generation circuit 60 generates column selection signal CSELZ.

  On the other hand, at the timing of the clock clk1, the address buffer 62 fetches the column address ADDRESS by the address buffer latch signal ABL generated by the internal clock generation circuit 90, and the internal column address CAxxZ is generated. Here, xx indicates that there are a plurality of column addresses.

  Further, the internal column address latch / counter circuit 66 generates a next column address increased by +1 from the given internal column address CAxxZ by a counter, for example, generates an even-numbered column address CAxxZ1E and an odd-numbered column address CAxxZ1O. I do. The even-numbered column address CAxxZ1E and the odd-numbered column address CAxxZ1O are supplied to the odd-numbered redundancy comparison circuit 68 and the predecoder 70 and to the even-numbered redundancy comparison circuit 78 and the predecoder 80 at the timing of the address generation signal ADLZ. Each given. Then, the address generation signal ADLZ is generated by the internal clock generation circuit 90 based on the clock clk1.

  Therefore, the generation of the increased address, the comparison with the redundant address, the predecoding operation, and the like for the column address signal ADDRESS are performed at an early timing at the timing based on the clock clk1 irrespective of the data strobe signal DS. Therefore, the output timing of the comparison result signals COMZO, COMZE and the predecode signals PCAxxZO, PCAxxZE by the drivers 72, 74, 76, 78 can be made earlier than in the case of FIG. The timing is the timing of the column selection signal CSELZ.

  As shown in FIG. 7, the internal write operation substantially starts at a timing t10 slightly delayed from the clock clk1.5. Therefore, as shown in the center of FIG. 7, the internal write operation can be started earlier by the time ΔT as compared with the case where the internal write operation is started from the clock clk2 in the case of FIG. In order to perform the internal write operation at such an early timing, as described above, it is necessary to start the processing of the column address early according to the timing of the clock clk1. In the example of FIG. 3, the processing of the column address is performed after the clock clk2.

  FIG. 8 is a timing chart in the case where the phase of the data strobe signal DS is delayed from the clock clk1 by the time tDSH. The operation of the configuration shown in FIG. 6 in this case is the same as in the case of FIG. As shown in FIG. 8, the processing of the column address is performed in advance according to the timing of the clock clk1. Then, the first write data signal D0 is latched at the rising edge (first data strobe signal DSPZ) of the data strobe signal DS which is given later by the time tDSH than the clock clk1, and the falling edge (second data strobe signal DSPX) , The second write data signal D1 is latched. Then, with the second data strobe signal DSPX as a starting point, an internal write operation is started from time t10.

  Therefore, in the case of FIG. 8, the internal write operation starts at the same time as in FIG. However, in the case of FIG. 3, as shown in FIGS. 4 and 5, after the internal write operation starts at time t10, the redundant comparison operation and the predecode operation are performed as shown at t20 in the figure. , And the comparison result signals COMZO and COMZE and the predecode signals PCAxxZO and PCAxxZE are generated thereafter. On the other hand, in the case of the memory of FIG. 6, as shown in FIG. 8, before the time t10 at which the internal write operation starts, the redundant comparison operation and the predecode operation are performed as shown by t20 in the drawing. Be done. Accordingly, the comparison result signals COMZO and COMZE and the predecode signals PCAxxZO and PCAxxZE generated by the column address signal processing are already generated before the internal writing operation start time t10. Therefore, as a whole, the time until the completion of writing is shortened.

  As described above, since the column address signal is taken in synchronization with the clock clk1, the redundant address and the predecode operation for the column address are preceded by the control timing synchronized with the clock clk1. The processing time of the internal write operation can be shortened.

  FIG. 9 is a diagram showing a circuit configuration of the drivers 72, 74, 76, and 78. The driver circuit shown in FIG. 6 is supplied with three control signals TCS1, TCS2, and CSELZ. However, the detailed configuration is not shown due to space limitations. Therefore, the detailed configuration and operation will be described with reference to FIG.

  As shown in FIG. 9, the three control signals TCS1, TCS2, and CSELZ control the gates at the preceding stage of the latch circuit 92, the latch circuit 94, and the final drive circuit 96. The timing control signal TCS1 generated by the internal clock generation circuit 90 is inverted by the inverter 102, and controls the N-type transistor 100 and the P-type transistor 101 constituting the CMOS transfer gate. That is, the comparison result signal COMZ from the redundancy comparison circuits 68 and 78 and the predecode signal PCAxxZ from the predecoders 70 and 80 are fetched by the timing control signal TCS1 and latched by the latch circuit 92. The latch circuit 92 includes two inverters 103 and 104. As a result, the results of the redundancy comparison operation and the predecode operation are latched in the driver circuit by the timing control signal TCS1 generated from the clock clk1. As a result, the latched result signal COMZ1 and the predecode signal PCAxxZ1 are held at the node n1.

  Next, the CMOS transfer gates 105 and 106 are opened by the second timing control signal TCS2 generated by the write clock generation circuit 58, and the signal at the node n1 is latched by the latch circuit 94. The second timing control signal TCS2 is a signal generated by the data strobe signal DS, and the comparison result signal and the predecode signal are latched by the latch circuit 94 in response to the start of internal writing. Therefore, the latch circuit 94 has the function of a transfer circuit for changing from control synchronized with the clock CLK to control synchronized with the data strobe signal. The latch circuit 94 includes a NAND gate 108 and an inverter 109. The node n2 holds the latched result signal COMZ2 and the predecode signal PCAxxZ2.

  Here, finally, the NAND gate 110 is opened by the column selection signal SELZ generated by the column selection pulse generation circuit 58, and the inverter 111 supplies the result signal COMZ3 and the predecode signal PCAxxZ3 to the column decoder provided in the memory cell array. 24, 25. That is, the result signal COMZ3 and the predecode signal PCAxxZ3 are output in accordance with the operations of the write amplifier circuits 42 and 44. Therefore, the internal write operation is controlled in synchronization with the data strobe signal DS.

  As described above, in the driver circuits 72, 74, 76, 78, the predecode signal PCAxxZ and the comparison result signal COMZ are held in the latch circuit 94 by the H level of the second timing control signal TCS2. Then, the predecode signal PCAxxZ2 and the comparison result signal COMZ2 held by the latch circuit 94 during the H level of the column selection signal CSELZ are given to the column decoders 24 and 25 as the predecode signal PCAxxZ3 and the comparison result signal COMZ3, respectively. . Therefore, the second timing control signal TCS2 and the column selection signal CSELZ enable the internal write operation at a control timing synchronized with the data strobe signal DS. Then, the first timing control signal TCS1 is controlled in synchronization with the clock clk1, and latches the previously performed redundant comparison result signal COMZ and the like in the latch circuit 92.

  When the read signal READ is at the H level, the NAND gates 112 and 108 are opened, and the predecode signal and the comparison result signal are supplied directly to the NAND gate 110. Therefore, at the time of reading, the timing control signals TCS1 and TCS2 are not used and are only output to the column decoder at the timing controlled by the column selection signal CSELZ.

  FIG. 10 is a diagram showing an example of a specific circuit of the first and second data latch circuits 32 and 36 and the data shift register circuit 34 shown in FIG. The first data latch circuit 32, which takes in the even-numbered write data D0 previously input by the first data strobe signal DSPZ, is configured by a master slice flip-flop circuit. The CMOS gates 120 and 121 are turned on by the H level of the first data strobe signal DSPZ, and the first write data signal D0 is latched by the slave latch circuit composed of the two inverters 123 and 124. Then, the CMOS gates 125 and 146 are turned on by the L level of the first data strobe signal DSPZ, and are held in the master side latch circuit composed of the two inverters 127 and 128.

  The configuration of the second data latch circuit 36 and the data shift register 34 is equivalent to that of the first data latch circuit 32. In response to the H level of the second data strobe signal DSPX synchronized with the falling edge of the data strobe signal DS, the second write data D1 is latched by the latch circuit including the inverters 143 and 144 of the second data latch circuit 36. You. At the same time, the data signal DQE held by the first data latch circuit 32 is also latched by the latch circuit including the inverters 133 and 134 of the data shift register 34. Then, according to the L level of the second data strobe signal DSPX, the respective write data D0 and D1 are stored in the latch circuit including the inverters 137 and 138 and the latch circuit including the inverters 147 and 148 in the respective circuits 34 and 36. Will be retained. As a result, the even-numbered write data signal DQE1 and the odd-numbered write data signal DQO1 are generated by the respective circuits 34 and 36.

  FIG. 11 is a diagram showing another example of a specific circuit of the data latch circuits 32 and 34. In this example, a latch circuit 176 at the preceding stage and a latch circuit 178 at the subsequent stage are provided. The pre-stage latch circuit 176 includes P-type transistors 150, 151, 158, 161 and N-type transistors 152, 153, 154, 159, 160, 162, 163. The latter-stage latch circuit 178 is constituted by two inverters 172 and 173.

  To briefly explain the operation, while the control signals DSPZ and DSPX are at the L level, the data latch circuit is in an inactive state and consumes no current. That is, the transistors 150 and 151 conduct, and the nodes n10 and n11 are both at the H level. As a result, the node n12 is at the L level by the inverter 166, and the node n13 is also at the L level by the inverter 167. Therefore, the transistors 168 to 171 are all non-conductive, and the nodes n14 and n15 are in a high impedance state. As a result, the latter-stage latch circuit 178 holds the previous state.

  Next, when the control signals DSPZ and DSPX go to the H level when the write data signals D0 and D1 are given to the internal input / output terminal int.DQ, the transistors 150 and 151 are turned off and the transistor 154 is turned on and the writing is performed. A differential amplifier composed of transistors 152 and 153 to which data D0 and D1 and an inverted signal thereof are supplied is activated. Now, assuming that the write data signal is at H level, the transistor 152 is turned on, the node n10 is at L level, and the node n11 is at H level. Therefore, the transistor 168 is turned on, the transistor 169 is turned off, and the node n14 becomes H level. On the other hand, transistor 171 conducts, and node n15 attains L level. The signals at these nodes n12 and n13 are fed back to the transistors 160 and 163 to facilitate the latch of the preceding latch circuit 176. Further, the subsequent-stage latch circuit 178 latches the data by the nodes n14 and n15.

  This data latch circuit can detect the write data signals D0 and D1 only at the rising edges of the control signals DSPZ and DSPX and latch them in the subsequent latch circuit 178. Accordingly, a higher-speed operation can be performed than a master-slave type circuit that latches at the rise and fall of the control signal shown in FIG. Moreover, it is an energy saving type that consumes current only while the control signal is at the H level.

  FIG. 12 is a diagram showing a schematic configuration of a memory according to the second embodiment of the present invention. In FIG. 12, parts corresponding to FIGS. 3 and 6 are denoted by the same reference numerals. FIG. 13 is a flowchart of the operation in FIG. Also in FIG. 13, the same reference numbers are given to portions corresponding to FIGS.

  The characteristic point of the circuit example of FIG. 12 is not the specification in which the write data signal is supplied in synchronization with the data strobe signal, but the specification in which the write data signal is supplied in synchronization with the external clock CLK.

  Generally, the column address signal ADDRESS is applied together with the write command signal in synchronization with the rising edge of the clock clk1. Therefore, in the memory shown in FIG. 12, by decoding the write command and recognizing the write mode, a write data signal is given to the input / output terminal DQ at the timing of the next clock clk2, The current consumption of the input buffer circuit 30 can be kept low. That is, after recognizing the write command, the input buffer circuit 30 may be activated by the enable signal EN and wait. Therefore, in this example, the write data signals D0 and D1 are supplied to the data input / output terminal DQ from the system in synchronization with the rising edge of the clock clk2 and the falling edge of the clock clk2.5.

  Therefore, the capture of the write data signal and the start of the internal write operation accompanying the write data signal are controlled by the timing of the internal control signal starting from the clock clk2. However, since the column address ADDRESS is input in synchronization with the rising edge of the clock clk1, the processing of the column address such as the redundant address comparison operation and the predecode operation is also performed in advance by the control signal starting from the clock clk1. As a result, the internal write operation can be started immediately from the point in time when the write data signals D0 and D1 subsequently input are latched.

  In order to enable the above operation, the first data strobe signal DSPZ and the second data strobe signal DSPX have rising edges in response to the internal clock int.CLK obtained by capturing the external clock CLK by the buffer circuit 46. It is generated by the trigger circuit 50 and the falling edge trigger circuit 56. The write clock generation circuit 58 that controls the internal write operation is controlled by the second data strobe signal DSPX generated from the clock int.CLK. The generation of the write signal WRT, the column selection signal CSELZ, and the like by the write clock generation circuit 58 is equivalent to the case of the circuit of FIG.

  Further, starting from the clock clk1 to which the column address ADDRESS is given, the internal clock generating circuit 90 generates the even-numbered and odd-numbered columns from the address buffer latch signal ABL, the first timing control signal TCS1, and the internal column address latch / counter circuit. An address latch signal ADLZ for outputting the addresses CAxxZ1O and CAxxZ1E is generated. With this configuration, starting from the clock clk1, it is possible to cause the redundancy comparison circuits 68 and 78 to perform the comparison operation of the redundant address and perform the predecoding operation by the predecoders 70 and 80 in advance.

  The operations of the drivers 72, 74, 76, and 78 are the same as those in FIGS. 6 and 9, and the first timing control signal TCS1 latches the redundant comparison result signals COMZO and COMZE and the predecode signals PCAxxZO and PCAxxZE. Then, the signal is further latched by the second timing control signal TCS1, and the signals COMZ3O, COMZ3E and PCAxxZ3O, PCAxxZ3E are output to the column decoders 24, 25 at the timing of the column selection signal CSELZ.

  As shown in the operation timing chart of FIG. 13, the column address signal is fetched at the timing of the clock clk1, and the operations of the redundancy comparison circuits 68 and 78 and the predecoders 70 and 80 precede at the time indicated by t20 in the figure. It is done. Then, at the timing of the clock clk2, the write data signals D0 and D1 are sequentially taken in, and the internal write operation is started from time t10. Specifically, write signal WRT is applied to write amplifiers 42 and 44, and column select signal CSELZ is applied to drivers 72, 74 and 82.84. Since the redundancy comparison operation and the like are performed in advance, the internal write operation can be started by the column selection signal CSELZ immediately after taking in the write data signal.

  FIG. 14 is a diagram showing a specific circuit of the input buffer circuit 30 connected to the data input / output terminal DQ. This input buffer circuit is a circuit that detects an H level or an L level of a write data signal based on externally applied write data signals D0 and D1 and a reference signal Vref, and converts it to a CMOS level. A current mirror circuit is formed by the P-type transistors 180 and 181, and a differential amplifier circuit is formed by the transistors 182 and 183 that use the current mirror circuit as a load. Then, the current source transistor 184 is turned on by the enable signal EN generated by the command decoder 189, and activates the differential amplifier circuit. Command decoder 189 is supplied with control signals / RAS, / CAS, / CS1 and / WE, and a write command is given by a combination of these control signals.

  When the command decoder 189 detects that the write command is given from the combination of the control signals, it sets the enable signal EN to the H level, activates the input buffer circuit 30, and stands by to receive the write data signal. Therefore, since the input buffer 30 is activated only at the time of writing, power consumption can be greatly reduced.

The internal write data signal int.DQ, which has been subjected to waveform shaping by the inverters 185, 186, and 187 and converted to a CMOS level, is generated.
FIG. 15 is a diagram showing an improved example of the second embodiment shown in FIG. In this example, a delayed lock loop circuit 194 is used to generate an internal clock int.CLK from an external clock CLK.

  The delayed lock loop circuit 194 is a circuit that generates an internal clock int.CLK synchronized with the clock CLK input from the input buffer 46 and having the same phase. The delayed locked loop circuit 194 includes a delay circuit 196, a delay control circuit 198 that controls the delay amount of the delay circuit 196, and a phase comparison circuit 199. Further, a buffer circuit 200 is further provided in a pseudo manner.

  Although the delayed lock loop circuit 194 is well known, the basic operation principle is that the phases of the external clock CLK and the internal clock int.CLK are compared by a phase comparison circuit, and the phases of both clocks match. Thus, the delay control circuit 198 controls the delay amount of the delay circuit 196. Since the pseudo buffer circuit 200 has a delay characteristic equivalent to that of the input buffer 46, for example, the internal clock int.CLK is a clock whose phase coincides with the external clock CLK by one cycle. Since the clock repeats the H level and the L level one after another, the external clock CLK and the internal clock int.CLK have apparently the same phase. That is, as shown by the broken line of the internal clock int.CLK in FIG. 13, the clock becomes the same as the external clock.

  When the data strobe signal DSPZ synchronized with the rising edge of the clock and the data strobe signal DSPX synchronized with the falling edge of the clock are generated using the internal clock, the latch timing in the data latch circuit 190 is changed as shown in FIG. It can be faster than if it were. Accordingly, in the example of FIG. 15, the data input / output terminal DQ is directly connected to the data latch circuits 190 and 192 instead of being connected to the data latch circuit via the input buffer 30 as in the example of FIG. Therefore, these latch circuits also have the function of an input buffer.

  The example of FIG. 15 is otherwise the same as that of FIG. 12, and corresponding circuits have the same reference numerals. That is, at the timing of the clock clk1, the column address is fetched and the operation up to the redundancy comparison operation is performed. On the other hand, the write data D0 and D1 are taken in from the data input / output terminal DQ at the timing of the clock clk2, and the internal write operation is performed.

  FIG. 16 is a diagram showing a circuit example of the data latch circuits 190 and 192 in FIG. This data latch circuit is also supplied with an external clock CLK and an external reference voltage Vref. Then, data strobe signals DSPZ and DSPX are given as control clocks. While the control clock is at the L level, P-type transistors 214 and 215 are conductive, and both nodes n20 and n21 are maintained at the H level. Thereby, the transistors 228 to 231 become non-conductive, and the nodes n22 and n23 enter a high impedance state.

  Therefore, when the control clocks DSPZ and DSPX go to the H level, the transistors 214 and 215 are turned off, the N-type transistors 218 and 219 are turned on, and the differential data composed of the transistors 216 and 217 writes the write data. A buffer operation is performed to determine whether the signals D0 and D1 are higher or lower than the reference voltage Vref. In response, one of nodes n20 and n21 falls from H level to L level. For example, when the write data signal is at H level, the transistor 216 is turned on and the node n20 is lowered to L level.

  Accordingly, transistor 228 conducts, node n22 attains H level, transistor 231 conducts, and node n23 attains L level. These node states are latched by a latch circuit including inverters 232 and 233.

  That is, the data latch circuit shown in FIG. 16 is controlled by the data strobe signals DSPZ and DSPX at an early timing generated from the internal clock having the same phase as the external clock CLK, and thus has a buffer function and a control clock DSPZ, It has a function to latch an input write data signal at high speed only by the rising edge of DSPX. Therefore, it is suitable as the data latch circuit in FIG.

  FIG. 17 is a diagram showing another improved example of the second embodiment shown in FIG. This example also uses the delayed lock loop circuit 194 to generate the internal clock int.CLK from the external clock CLK. Further, in this example, one data latch circuit 190 is provided for the data input / output terminal DQ, the write data signals D0 and D1 are fetched in a time series by the data strobe signals DSPZ and DSPX, and the even number And the write data signal DQO1 on the odd side.

  The data latch circuit 190 has the same configuration as the data latch circuit of FIG. The demultiplexer circuit 202 converts the data latched by the data latch circuit 190 into the even-numbered and odd-numbered write data DQE1 and DQO1 in response to the control signals DDSPZ and DDSPX obtained by delaying the data strobe signals DSPZ and DSPX, respectively. Distribute.

  FIG. 18 is a diagram showing an example of the demultiplexer circuit. This circuit has three latch circuits 250, 260, and 270. In this demultiplexer circuit, the internal data IDQ latched by the data latch circuit 190 is latched by a control signal DDSPZ obtained by delaying the first data strobe signal DSPZ in a latch section including inverters 255 and 256 in the latch circuit 250. Is done. Then, the CMOS gates 262, 263, and 272, and 274 are turned on by the control signal DDSPX obtained by delaying the second data strobe signal DSPX, and the second write data signal D1 is turned on by the inverters 275 and 276 in the latch circuit 270. The data DQE latched by the latch unit and latched by the latch circuit 250 is latched by the latch unit including the inverters 265 and 266 in the latch circuit 260.

  The memory shown in FIG. 17 has the same configuration as the memory in FIG. 15 except that the above-described demultiplexer circuit is provided. Therefore, corresponding parts are given the same reference numbers. The data latch circuit 190 and the demultiplexer circuit 202 shown in FIGS. 17 and 18 are not limited to the buffer circuit 30 of the first embodiment shown in FIG. , Can be applied instead of the data shift registers 34 and 36.

  Although the above embodiment has been described with reference to a synchronous DRAM as an example, the present invention is not limited to a synchronous DRAM but can be widely applied to a memory to which an address or the like is given in synchronization with an external clock.

As described above, according to the present invention, in a memory using an external clock and an external data strobe signal asynchronous with the external clock, the internal write operation is started immediately after the input of the write data signal in response to the external data strobe signal. The writing operation can be speeded up. Furthermore, by performing a redundancy comparison operation or the like without waiting for an internal write operation for an address signal given in synchronization with an external clock, the write operation can be further speeded up.
Further, in a memory in which an address and a command are supplied in synchronization with a first external clock and a write data signal is supplied in synchronization with a second external clock following the first external clock, Since the redundancy comparison operation and the like are performed after the address signal is input in synchronization, the time required for the internal write operation can be shortened.

FIG. 3 is a schematic diagram illustrating a relationship between a plurality of memories and a control unit that controls the memories. FIG. 9 is a diagram showing a schematic timing chart of a write operation using a clock CLK and a data strobe signal DS asynchronous to the clock CLK. FIG. 3 is a schematic configuration diagram of a memory when an internal write operation is performed in synchronization with a clock CLK. FIG. 9 is a timing chart in the case where the phase of the data strobe signal DS is ahead of the reference clock by tDSS. FIG. 9 is a timing chart when the data strobe signal DS has a phase delayed by tDSH from the reference clock. FIG. 3 is a schematic configuration diagram of a memory in which an internal write operation is performed in synchronization with a data strobe signal. FIG. 7 is a timing chart in the case where the phase of the data strobe signal DS is ahead of the reference clock by tDSS. FIG. 6 is a timing chart in the case where the phase of the data strobe signal DS is delayed by tDSH from the reference clock. FIG. 3 is a diagram illustrating a circuit configuration of a driver. FIG. 3 is a diagram illustrating an example of specific circuits of first and second data latch circuits and data shift register circuits. FIG. 9 is a diagram illustrating another example of a specific circuit of the data latch circuit. FIG. 7 is a diagram illustrating a schematic configuration of a memory according to a second embodiment of the present invention. FIG. 13 is a flowchart of the operation in FIG. 12. FIG. 3 is a diagram showing a specific circuit of an input buffer circuit connected to a data input / output terminal DQ. FIG. 13 is a diagram showing an improved example of the second embodiment shown in FIG. 12. FIG. 16 is a diagram illustrating a circuit example of data latch circuits 190 and 192 in FIG. 15. FIG. 13 is a diagram showing another improved example of the second embodiment shown in FIG. 12. FIG. 3 is a diagram illustrating an example of a demultiplexer circuit.

Explanation of reference numerals

CLK External clock SD External data strobe signal D0, D1 Write data signal DQ Data input / output terminal ADDRESS Address signal 20, 21 Memory cell array 24, 25 Column decoder 32, 34, 36 Write data signal input circuit 42, 44 Write circuit, write amplifier WRTZ write signal 72, 74, 82, 84 driver circuit CSELZ column select signal

Claims (7)

In a semiconductor memory device which takes in an address signal in response to an external clock signal and takes in a data signal in response to an external clock signal delayed from the timing of taking in the address signal,
An address input circuit that receives an address signal in response to the external clock signal;
An address decoding circuit for decoding an address signal from the address input circuit;
An address driver circuit for outputting an address signal from the address decode circuit in response to the delayed external clock signal;
A semiconductor memory device comprising: an internal circuit for writing the data signal into a memory cell corresponding to an address signal output from the address driver circuit.   2. The semiconductor memory device according to claim 1, wherein the data signal fetch timing is delayed by one clock cycle from the address signal fetch timing.   A data input buffer for receiving the data signal; fetching a command signal together with an address signal in response to the external clock signal; and selectively activating the data input buffer when the command signal is a write command. 3. The semiconductor memory device according to claim 1, wherein: A first data latch circuit that captures the data signal in response to a rise of the delayed external clock signal;
2. A data latch circuit according to claim 1, further comprising a second data latch circuit provided in parallel with said first data latch circuit and adapted to capture said data signal in response to a fall of said delayed external clock signal. 4. The semiconductor memory device according to any one of 3. In a semiconductor memory device which takes in an address signal in response to an external clock signal and takes in a data signal in response to a rise and fall of an external clock signal delayed from the timing of taking in the address signal,
A delayed lock loop circuit that receives the external clock and generates an internal clock synchronized in phase with the external clock;
An address input circuit for receiving an address signal in response to the internal clock signal;
An address decoding circuit for decoding an address signal from the address input circuit;
An address driver circuit that outputs an address signal from the address decode circuit in response to an internal clock corresponding to the delayed external clock signal;
A semiconductor memory device comprising: an internal circuit for writing the data signal into a memory cell corresponding to an address signal output from the address driver circuit.   6. The semiconductor memory device according to claim 5, further comprising a data input circuit directly connected to a data input terminal, wherein said data input circuit takes in said data signal in response to an internal clock signal corresponding to said delayed external clock signal.   A data latch circuit for sequentially taking in the data signal in response to the rise and fall of the internal clock signal corresponding to the delayed external clock signal; and a delay connected to the output of the data latch circuit for delaying the internal clock. 6. The semiconductor memory device according to claim 5, further comprising: a demultiplexer circuit that distributes and outputs said data signal to first and second data buses in response to an internal clock.

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