JP2004165452A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of further enhancing a security function of a semiconductor device than before by making prediction of a wiring arrangement communicating with an integrated circuit difficult. <P>SOLUTION: The method includes a process where an integrated circuit is formed in each of a plurality of chip regions separated from each other by a scribe region for dicing, a process where a first wiring layer which is electrically connected to the integrated circuit is formed, a process to form a second wiring layer connected to the first wiring layer through a conductive plug formed in the scribe region by penetrating an interlayer insulating film on the first wiring layer, a process for writing a prescribed data in the integrated circuit by utilizing a pad which is electrically connected to the second wiring layer and provided in the scribe region, and a process for dicing a semiconductor wafer along the scribe region for separating a plurality of chip regions of the semiconductor wafer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
In general, a semiconductor device forms an integrated circuit in each of a plurality of chip areas defined on a semiconductor wafer, performs dicing along a scribe area separating each chip area, and separates the individually separated integrated circuits. It is manufactured by mounting on a semiconductor package and providing necessary electric wiring.
[0003]
In this case, if all of the device patterns including the circuit pattern and the pad pattern are provided in the chip region, all of the device patterns exist in the semiconductor device as the final product. However, it is not preferable that all of the device patterns remain in the final product in a product application in which data falsification and leakage must be strictly restricted, such as an IC card. For example, if the wiring for the pad for writing data to the nonvolatile memory (ROM) of the IC card is left as it is, there is a concern that the wiring may be used improperly, and it is necessary to take protective measures for that. Problems such as complexity of the device and high cost may occur.
[0004]
In order to cope with such a problem, Japanese Patent Application Laid-Open No. 2001-135597 (Patent Document 1) discloses a semiconductor wafer having a chip area having a built-in storage area, a scribe area for cutting the semiconductor wafer, and a storage area. It discloses an invention in which a pad to which an electric signal is externally supplied for writing data is formed, a pad is formed in this scribe area, and after writing data through the pad, the semiconductor wafer is cut together with the pad. . This makes it impossible to access the storage area through the pad after dicing.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2001-135597
[Problems to be solved by the invention]
However, even if the pad is removed at the time of dicing, the wiring layer (cross section) appearing on the dicing surface surely leads to the storage area, so that the connection form of the wiring to the storage area of the integrated circuit can be easily predicted. It is feared that it will be done.
[0007]
An object of the present application is to provide a method of manufacturing a semiconductor device capable of strengthening a security function of the semiconductor device as compared with the related art by making it difficult to predict a wiring form leading to an integrated circuit.
[0008]
[Means for Solving the Problems]
According to the solution according to the invention,
Forming an integrated circuit in each of a plurality of chip areas separated by a scribe area for performing dicing;
Forming a first wiring layer electrically connected to the integrated circuit;
Forming a second wiring layer connected to the first wiring layer through a conductive plug formed in the scribe region, penetrating an interlayer insulating film on the first wiring layer;
Writing predetermined data into the integrated circuit using a pad electrically connected to the second wiring layer and provided in the scribe region;
A method of manufacturing a semiconductor device, comprising: dicing the semiconductor wafer along the scribe area to separate a plurality of chip areas of the semiconductor wafer.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
1 to 3 are sectional views showing main steps in a method of manufacturing a semiconductor device according to an embodiment of the present application. First, a plurality of chip regions are formed on a semiconductor wafer, and an integrated circuit having a storage element is formed in each of these chip regions. Each chip area is separated from each other by a scribe area for performing dicing. FIG. 1A shows a part (right side) of a chip area 12 where an integrated circuit is formed and a scribe area 14 (left side). FIG. 1A illustrates two transistors 20 and two capacitors 23 which are part of a ferroelectric memory (FeRAM); however, the present invention is not limited to such a mode, It is possible to target any integrated circuit with elements.
[0010]
The transistor 20 formed in the semiconductor device 10 is connected to the lower electrode 40 of the capacitor 23 by a conductive plug 30 penetrating through the interlayer insulating film 22. On the lower electrode 40, a ferroelectric film 50 and an upper electrode 60 are formed. The capacitor 23 is formed by etching the lower electrode 40, the ferroelectric film 50, and the upper electrode 60 thus stacked, and an insulating film 70 for protecting the capacitor 23 is formed. The insulating film 70 is formed of, for example, alumina (Al ₂ O ₃ ). The conductive plug 30 is connected to a conductive plug 90 that penetrates an interlayer insulating film 80 made of, for example, silicon oxide (SiO ₂ ).
[0011]
In the step shown in FIG. 1B, wiring layers 92 and 93 for the upper electrode 60 and the conductive plug 90 are formed on the interlayer insulating film 80. The wiring layer 92 is connected to a reference potential such as ground (GND), and the wiring layer 93 is connected to a bit line of the ferroelectric memory (the word line is connected to the gate electrode of the transistor 20).
[0012]
Unlike the related art, in the present embodiment, a dummy wiring layer 102 that is not electrically connected to the transistor 20 is formed on the interlayer insulating film 80. The dummy wiring layer 102 is formed so as to belong to both the chip region 12 and the scribe region 14. The dummy wiring layer 102 can be formed simultaneously with the other wiring layers 92 and 93 on the interlayer insulating film 80, or can be formed separately. At the same time, for example, after forming a conductive layer on the entire surface of the interlayer insulating film 80, it is possible to form each wiring layer by appropriately patterning the conductive layer, or conversely. Alternatively, it is also possible to form the resist by appropriately patterning a resist formed on the interlayer insulating film 80 and depositing a conductive material. An interlayer insulating film 104 is deposited on the wiring layers 92, 93, and 102, and is planarized to have a predetermined thickness by, for example, chemical mechanical polishing (CMP).
[0013]
In the step shown in FIG. 2C, a conductive plug 106 connected to the wiring layer 93 is formed in the interlayer insulating film 104. The conductive plug 106 is made of, for example, tungsten (W). Wiring layer 108 connected to conductive plug 106 is formed on interlayer insulating film 104. The wiring layer 108 is provided so as to extend at least from the position where the conductive plug 106 is located to the scribe region 14. An additional interlayer insulating film 110 is formed on the wiring layer 108 and the interlayer insulating film 104, and is planarized to a predetermined thickness. A conductive plug 112 is also provided on this interlayer insulating film 110. However, the conductive plug 112 is provided in the scribe region 14.
[0014]
In the step shown in FIG. 2D, a wiring layer 114 connected to the conductive plug 112 is formed on the interlayer insulating film 110. This wiring layer 114 is also formed so as to exist in both the chip region 12 and the scribe region 14. Then, an additional interlayer insulating film 116 is formed on the wiring layer 114 and the interlayer insulating film 110, and is planarized to have a predetermined thickness. A pad opening (pad) 118 is formed in a portion belonging to the scribe region 14 of the interlayer insulating film 116. Using these pads, predetermined data is written to (the storage area of) the integrated circuit formed in the chip area 12, and the characteristics of the integrated circuit are evaluated and inspected.
[0015]
In the step shown in FIG. 3E, the semiconductor wafer is diced along the scribe regions 14. The individually separated chip regions 12, that is, integrated circuits (IC chips) formed in the chip regions 12, are mounted on a semiconductor package, and after necessary wirings are provided, a semiconductor device is completed.
[0016]
In the illustrated example, for the sake of simplicity, all portions shown as scribe regions 14 are drawn so as to be cut by a dicing process. However, the scribe region 14 separating the plurality of chip regions 12 on the semiconductor wafer and the region cut in the dicing process are strictly different. For example, the part to be actually cut may be a part of the scribe area, or the entire scribe area may be cut.
[0017]
In any case, the semiconductor wafer is diced along the scribe region. What is important in this embodiment is that, as shown in FIG. 3E, (1) a part of the dummy wiring layer 102 is diced by dicing. The other portion remains in the chip region 12 while being removed, (2) the connection portion (conductive plug 112) between the multilayer wirings leading to the integrated circuit is removed by dicing, and (3) the integrated circuit A predetermined pad opening (pad) provided for access is also removed. Cross sections of the dummy wiring layer 102, the wiring layer 108, and the wiring layer 114 appear on the cut surface 120 formed by dicing, but it is not clear just by looking at these sections which wiring actually leads to the integrated circuit. The wirings other than the wiring layer 108 (the dummy wiring layer 102 and the wiring layer 114) are electrically insulated from the integrated circuit. Therefore, according to the present embodiment, it is more difficult to predict the connection form of the wiring than in the case where the wiring layer 108 exists alone.
[0018]
In the present embodiment, the multilayer wirings 108 and 114 leading to the integrated circuit are formed above the dummy wiring layer 102, but the present invention is not limited to such an embodiment. Dummy wiring layers 102 can be provided at desired locations above and below the multilayer wiring layers and between the multilayer wiring layers. Furthermore, it is also possible to provide a dummy wiring layer not only in the vertical direction (the direction in which wirings are stacked) with respect to the true wiring layer (wiring layer 108) but also in a position horizontally shifted from the true wiring layer. is there. This is because a dummy wiring layer electrically insulated from the integrated circuit may be formed so as to appear on the cut surface 120 by dicing. Further, it should be noted that the wiring layer 114 after dicing plays a role similar to that of the dummy wiring layer 102 because it is no longer connected to the integrated circuit. In other words, the conductive plug 112 for connecting the multilayer wirings is provided in the scribe region 14 so that the wiring layer 114 plays the role of a dummy wiring layer after dicing (the wiring layers 108 and 114 are connected to each other). From the viewpoint of electrical connection, the position of the conductive plug 112 may be in the chip region 12 or the scribe region 14.)
[0019]
FIG. 4 shows a state of a cut surface 120 when dummy wiring layers are provided at upper, lower, left, and right positions with respect to a true wiring layer 108 which is hatched. In this example, three dummy wiring layers 102 are provided on the interlayer insulating film 80, two dummy wiring layers 102 are provided on the left and right of the true wiring layer 108, and the multilayer wiring is connected to the true wiring layer 108. Two dummy wiring layers are also provided on the left and right sides of 114. As a result, the eight wiring layers 102 and 104 surrounding the true wiring layer 108 serve as dummy wiring layers. By providing a large number of dummy wiring layers above, below, right and left with respect to the true wiring layer in this way, it becomes difficult to specify a wiring layer that leads to the integrated circuit (estimate a connection relationship).
[0020]
From the viewpoint of making it difficult to predict the connection relationship, it is preferable that all of the true wiring layer and the dummy wiring layer have the same cross-sectional shape on the dicing cut surface. Further, it is also advantageous to change the location of the dummy wiring layer 102 every time a predetermined number of IC chips are manufactured, for example, for each lot. By doing so, even if the connection form of the wiring related to a certain IC chip is known, for example, the connection form of another IC chip of a different lot can still be kept secret.
[0021]
The dummy wiring layer 102 can be formed simultaneously with the true wiring layers 108 and 114 or can be formed separately. That is, the dummy wiring layer provided in the left-right direction of the true wiring layer can be simultaneously patterned when the true wiring layer is patterned. This makes it possible to form a dummy wiring layer without increasing the number of manufacturing steps.
[0022]
As described above, according to the embodiment of the present invention, an integrated circuit is formed in each of the plurality of chip areas 12 separated from each other by the scribe area 14 for dicing, and the first wiring layer 108 electrically connected to the integrated circuit is formed. To form a second wiring layer 114 that penetrates the interlayer insulating film 110 on the first wiring layer and is connected to the first wiring layer through the conductive plug 112 formed in the scribe region. Then, after predetermined data is written in the integrated circuit using a pad electrically connected to the second wiring layer and provided in the scribe region, the semiconductor wafer is diced along the scribe region. Although the cut surfaces of the first and second wiring layers appear on the dicing surface of the individually separated IC chip, they are not electrically connected (the conductive plug connecting them is removed by dicing). Has been). It is not clear which one leads to the integrated circuit only by looking at the cut surfaces of the first and second wiring layers. Therefore, according to the embodiment of the present application, it is possible to make the connection form of the wiring less predictable than in the related art. If more multilayer wiring structures are used instead of two-layer wirings, it is possible to make it even harder to determine.
[0023]
According to the embodiment of the present invention, since the pad for accessing the integrated circuit is cut by the dicing step, it is difficult to access the integrated circuit after dicing. Even if the wiring layer connected to the pad can be specified, it is not always connected to the integrated circuit after dicing, so it is not easy to predict the wiring connection form.
[0024]
According to the embodiment of the present application, a dummy wiring layer that is not electrically connected to the first and second wiring layers is formed in the scribe region and the chip region. Since the dummy wiring layer is formed not only in the scribe region but also in the chip region, a cut surface of the dummy wiring layer appears on the dicing surface. Since the cross section of the dummy wiring layer can be the same as the cross section of the first and second wiring layers, it is difficult to determine which is connected to the integrated circuit.
[0025]
【The invention's effect】
As described above, according to the present invention, it is possible to enhance the security function of a semiconductor device as compared with the related art.
[0026]
[Brief description of the drawings]
FIG. 1 is a sectional view (part 1) of a main step in a method for manufacturing a semiconductor device according to an embodiment of the present application;
FIG. 2 is a sectional view (part 2) of a main step in the method of manufacturing a semiconductor device according to the embodiment of the present application;
FIG. 3 is a sectional view (part 3) of a main step in the method for manufacturing a semiconductor device according to the embodiment of the present application;
FIG. 4 is a sectional view of an IC chip formed by the method of manufacturing a semiconductor device according to the embodiment of the present application.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 20 Transistor 22 Interlayer insulating film 23 Capacitor 30 Conductive plug 40 Lower electrode 50 Ferroelectric film 60 Upper electrode 70 Insulating film 80 Interlayer insulating film 90 Conductive plugs 92 and 93 Wiring layer 102 Dummy wiring layer 104 Interlayer insulating film 106 conductive plug 108 wiring layer 110 interlayer insulating film 112 conductive plug 114 wiring layer 116 interlayer insulating film 118 plug opening 120 dicing cut surface

Claims (5)

Forming an integrated circuit in each of a plurality of chip areas separated by a scribe area for performing dicing;
Forming a first wiring layer electrically connected to the integrated circuit;
Forming a second wiring layer connected to the first wiring layer through a conductive plug formed in the scribe region, penetrating an interlayer insulating film on the first wiring layer;
Writing predetermined data into the integrated circuit using a pad electrically connected to the second wiring layer and provided in the scribe region;
Dicing the semiconductor wafer along the scribe area to separate a plurality of chip areas of the semiconductor wafer. 2. The method according to claim 1, wherein the dicing step cuts the conductive plug or the pad. Further, before or after the formation of the first wiring layer, a step of forming a dummy wiring layer that is not electrically connected to the first wiring layer in the scribe region and the chip region. Item 3. A method for manufacturing a semiconductor device according to Item 2. Further, when forming the first or second wiring layer, a step of forming a dummy wiring layer that is not electrically connected to the first or second wiring layer in the scribe region and the chip region. The method for manufacturing a semiconductor device according to claim 1, wherein: 4. The method according to claim 3, wherein the dummy wiring layer is formed to have the same cross-sectional shape as the first wiring layer.

Images